Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_combo_key_combinations_obj::sysrst_ctrl_combo_key_combinations_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
96.34	96.34	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
sysrst_ctrl_combo_key_combinations_cg	96.34	1	100	1	64	64

---

Group Instance : sysrst_ctrl_combo_key_combinations_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.34	1	100	1	64	64

---

Summary for Group Instance sysrst_ctrl_combo_key_combinations_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	20	0	20	100.00
Crosses	62	3	59	95.16

Variables for Group Instance sysrst_ctrl_combo_key_combinations_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_ac_present_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key0_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key1_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_key2_in_sel	2	0	2	100.00	100	1	1	2
cp_precondition_pwrb_in_sel	2	0	2	100.00	100	1	1	2
cp_pwrb_in_sel	2	0	2	100.00	100	1	1	2

Crosses for Group Instance sysrst_ctrl_combo_key_combinations_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cross_key_combinations_combo_precondition_sel	31	3	28	90.32	100	1	1	0
cross_key_combinations_combo_detection_sel	31	0	31	100.00	100	1	1	0

Summary for Variable cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1994

1

T1

17

T19

12

T3

20

auto[1]

599

1

T1

5

T19

1

T3

12

---

Summary for Variable cp_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2009

1

T1

17

T19

13

T3

24

auto[1]

584

1

T1

5

T3

8

T13

3

---

Summary for Variable cp_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1991

1

T1

12

T19

12

T3

22

auto[1]

602

1

T1

10

T19

1

T3

10

---

Summary for Variable cp_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1947

1

T1

3

T19

12

T3

27

auto[1]

646

1

T1

19

T19

1

T3

5

---

Summary for Variable cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_ac_present_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2350

1

T1

22

T19

13

T3

27

auto[1]

243

1

T3

5

T8

8

T54

6

---

Summary for Variable cp_precondition_key0_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key0_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2291

1

T1

22

T19

13

T3

27

auto[1]

302

1

T3

5

T11

1

T36

5

---

Summary for Variable cp_precondition_key1_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key1_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2425

1

T1

22

T19

13

T3

25

auto[1]

168

1

T3

7

T8

4

T11

7

---

Summary for Variable cp_precondition_key2_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_key2_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2372

1

T1

22

T19

13

T3

25

auto[1]

221

1

T3

7

T36

1

T78

2

---

Summary for Variable cp_precondition_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_precondition_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

2425

1

T1

22

T19

13

T3

24

auto[1]

168

1

T3

8

T78

2

T79

2

---

Summary for Variable cp_pwrb_in_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pwrb_in_sel

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

1901

1

T1

17

T3

28

T8

8

auto[1]

692

1

T1

5

T19

13

T3

4

---

Summary for Cross cross_key_combinations_combo_precondition_sel

Samples crossed: cp_precondition_key0_in_sel cp_precondition_key1_in_sel cp_precondition_key2_in_sel cp_precondition_pwrb_in_sel cp_precondition_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	3	28	90.32	3
Automatically Generated Cross Bins	31	3	28	90.32	3
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_precondition_sel

Uncovered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	NUMBER	STATUS
[auto[0]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[0]]	[auto[1]]	[auto[1]]	0	1	1
[auto[1]]	[auto[1]]	[auto[1]]	[auto[1]]	[auto[0]]	0	1	1

Covered bins

cp_precondition_key0_in_sel	cp_precondition_key1_in_sel	cp_precondition_key2_in_sel	cp_precondition_pwrb_in_sel	cp_precondition_ac_present_sel	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
auto[0]	auto[0]	auto[0]	auto[0]	auto[0]	871	1			T1	22		T19	13		T13	2
auto[0]	auto[0]	auto[0]	auto[0]	auto[1]	74	1			T3	5		T8	4		T54	6
auto[0]	auto[0]	auto[0]	auto[1]	auto[0]	47	1			T79	2		T103	2		T366	4
auto[0]	auto[0]	auto[0]	auto[1]	auto[1]	15	1			T361	3		T384	3		T375	4
auto[0]	auto[0]	auto[1]	auto[0]	auto[0]	41	1			T233	3		T161	3		T385	1
auto[0]	auto[0]	auto[1]	auto[0]	auto[1]	27	1			T134	10		T386	10		T384	4
auto[0]	auto[0]	auto[1]	auto[1]	auto[0]	28	1			T367	2		T387	4		T388	3
auto[0]	auto[0]	auto[1]	auto[1]	auto[1]	6	1			T384	2		T245	4		-	-
auto[0]	auto[1]	auto[0]	auto[0]	auto[0]	35	1			T54	3		T361	6		T385	2
auto[0]	auto[1]	auto[0]	auto[0]	auto[1]	33	1			T8	4		T233	5		T366	2
auto[0]	auto[1]	auto[0]	auto[1]	auto[0]	6	1			T137	6		-	-		-	-
auto[0]	auto[1]	auto[0]	auto[1]	auto[1]	11	1			T243	3		T389	8		-	-
auto[0]	auto[1]	auto[1]	auto[0]	auto[0]	22	1			T3	4		T36	1		T102	3
auto[0]	auto[1]	auto[1]	auto[0]	auto[1]	8	1			T386	8		-	-		-	-
auto[0]	auto[1]	auto[1]	auto[1]	auto[0]	3	1			T3	3		-	-		-	-
auto[1]	auto[0]	auto[0]	auto[0]	auto[0]	138	1			T11	1		T36	3		T78	24
auto[1]	auto[0]	auto[0]	auto[0]	auto[1]	20	1			T120	2		T161	1		T332	4
auto[1]	auto[0]	auto[0]	auto[1]	auto[0]	16	1			T3	5		T390	2		T391	1
auto[1]	auto[0]	auto[0]	auto[1]	auto[1]	20	1			T392	1		T377	8		T381	5
auto[1]	auto[0]	auto[1]	auto[0]	auto[0]	37	1			T134	22		T364	2		T374	4
auto[1]	auto[0]	auto[1]	auto[0]	auto[1]	6	1			T245	6		-	-		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[0]	4	1			T137	1		T99	3		-	-
auto[1]	auto[0]	auto[1]	auto[1]	auto[1]	1	1			T78	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[0]	auto[0]	18	1			T36	2		T87	8		T390	2
auto[1]	auto[1]	auto[0]	auto[0]	auto[1]	1	1			T393	1		-	-		-	-
auto[1]	auto[1]	auto[0]	auto[1]	auto[0]	1	1			T243	1		-	-		-	-
auto[1]	auto[1]	auto[1]	auto[0]	auto[0]	5	1			T361	2		T375	1		T391	2
auto[1]	auto[1]	auto[1]	auto[0]	auto[1]	4	1			T79	3		T388	1		-	-

User Defined Cross Bins for cross_key_combinations_combo_precondition_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded

---

Summary for Cross cross_key_combinations_combo_detection_sel

Samples crossed: cp_key0_in_sel cp_key1_in_sel cp_key2_in_sel cp_pwrb_in_sel cp_ac_present_sel

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	31	0	31	100.00
Automatically Generated Cross Bins	31	0	31	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for cross_key_combinations_combo_detection_sel

Bins

cp_key0_in_sel

cp_key1_in_sel

cp_key2_in_sel

cp_pwrb_in_sel

cp_ac_present_sel

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

auto[0]

auto[0]

auto[0]

auto[1]

68

1

T37

9

T233

3

T244

4

auto[0]

auto[0]

auto[0]

auto[1]

auto[0]

179

1

T19

12

T8

4

T35

9

auto[0]

auto[0]

auto[0]

auto[1]

auto[1]

55

1

T3

4

T137

5

T361

6

auto[0]

auto[0]

auto[1]

auto[0]

auto[0]

104

1

T1

12

T36

2

T243

1

auto[0]

auto[0]

auto[1]

auto[0]

auto[1]

80

1

T104

5

T200

7

T89

3

auto[0]

auto[0]

auto[1]

auto[1]

auto[0]

61

1

T11

1

T35

7

T79

6

auto[0]

auto[0]

auto[1]

auto[1]

auto[1]

49

1

T36

3

T78

12

T200

3

auto[0]

auto[1]

auto[0]

auto[0]

auto[0]

101

1

T78

1

T137

1

T101

11

auto[0]

auto[1]

auto[0]

auto[0]

auto[1]

47

1

T3

5

T99

3

T385

1

auto[0]

auto[1]

auto[0]

auto[1]

auto[0]

43

1

T8

4

T332

4

T334

3

auto[0]

auto[1]

auto[0]

auto[1]

auto[1]

32

1

T37

2

T360

1

T359

3

auto[0]

auto[1]

auto[1]

auto[0]

auto[0]

45

1

T37

5

T264

8

T103

2

auto[0]

auto[1]

auto[1]

auto[0]

auto[1]

36

1

T1

5

T13

2

T104

1

auto[0]

auto[1]

auto[1]

auto[1]

auto[0]

47

1

T54

6

T137

6

T100

3

auto[0]

auto[1]

auto[1]

auto[1]

auto[1]

27

1

T19

1

T78

12

T200

1

auto[1]

auto[0]

auto[0]

auto[0]

auto[0]

124

1

T79

2

T243

3

T248

8

auto[1]

auto[0]

auto[0]

auto[0]

auto[1]

67

1

T3

3

T102

3

T366

4

auto[1]

auto[0]

auto[0]

auto[1]

auto[0]

46

1

T265

2

T366

2

T105

3

auto[1]

auto[0]

auto[0]

auto[1]

auto[1]

14

1

T54

3

T100

5

T394

2

auto[1]

auto[0]

auto[1]

auto[0]

auto[0]

40

1

T35

3

T137

6

T361

6

auto[1]

auto[0]

auto[1]

auto[0]

auto[1]

11

1

T259

1

T250

4

T108

5

auto[1]

auto[0]

auto[1]

auto[1]

auto[0]

35

1

T79

5

T104

2

T259

1

auto[1]

auto[0]

auto[1]

auto[1]

auto[1]

9

1

T359

2

T370

4

T217

2

auto[1]

auto[1]

auto[0]

auto[0]

auto[0]

62

1

T64

5

T161

3

T249

9

auto[1]

auto[1]

auto[0]

auto[0]

auto[1]

35

1

T249

3

T104

4

T259

3

auto[1]

auto[1]

auto[0]

auto[1]

auto[0]

22

1

T1

3

T36

2

T101

2

auto[1]

auto[1]

auto[0]

auto[1]

auto[1]

13

1

T358

4

T363

2

T378

2

auto[1]

auto[1]

auto[1]

auto[0]

auto[0]

23

1

T3

5

T264

5

T248

1

auto[1]

auto[1]

auto[1]

auto[0]

auto[1]

7

1

T264

3

T266

1

T363

2

auto[1]

auto[1]

auto[1]

auto[1]

auto[0]

12

1

T1

2

T64

1

T334

1

auto[1]

auto[1]

auto[1]

auto[1]

auto[1]

4

1

T358

2

T395

2

-

-

User Defined Cross Bins for cross_key_combinations_combo_detection_sel

Excluded/Illegal bins

NAME	COUNT	STATUS
detection_disable	0	Excluded