Unified Coverage Report :: Group :: sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

Group : sysrst_ctrl_env_pkg::sysrst_ctrl_pin_cfgs_obj::pin_cfg_cg

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_sysrst_ctrl_env_0.1/sysrst_ctrl_env_cov.sv

8 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg	100.00	1	100	1	64	64
tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg	100.00	1	100	1	64	64

---

Group Instance : tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[bat_disable].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[ec_rst_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[flash_wp_l].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key0_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key1_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[key2_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[pwrb_out].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

---

Group Instance : tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_en_override	2	0	2	100.00	100	1	1	2
cp_override_value	2	0	2	100.00	100	1	1	0
cp_pin_allowed_0	2	0	2	100.00	100	1	1	2
cp_pin_allowed_1	2	0	2	100.00	100	1	1	2

Crosses for Group Instance tb.me.obj.pin_cfg_cg[z3_wakeup].pin_cfg_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_pin_cross	16	0	16	100.00	100	1	1	0

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

551

1

T28

10

T74

5

T77

5

auto[1]

627

1

T28

10

T74

15

T77

15

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

281

1

T28

4

T74

5

T77

4

from_0to1

290

1

T28

4

T74

6

T77

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

582

1

T28

12

T74

8

T77

9

auto[1]

596

1

T28

8

T74

12

T77

11

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

625

1

T28

11

T74

13

T77

12

auto[1]

553

1

T28

9

T74

7

T77

8

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

40

1

T114

1

T198

2

T310

2

auto[0]

from_1to0

auto[0]

auto[1]

30

1

T28

2

T74

1

T114

2

auto[0]

from_1to0

auto[1]

auto[0]

30

1

T77

1

T195

1

T310

1

auto[0]

from_1to0

auto[1]

auto[1]

27

1

T28

1

T74

1

T114

1

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T28

1

T195

1

T335

1

auto[0]

from_0to1

auto[0]

auto[1]

25

1

T195

1

T198

1

T310

2

auto[0]

from_0to1

auto[1]

auto[0]

42

1

T28

1

T77

1

T198

1

auto[0]

from_0to1

auto[1]

auto[1]

32

1

T114

1

T310

1

T335

1

auto[1]

from_1to0

auto[0]

auto[0]

43

1

T114

1

T195

1

T198

1

auto[1]

from_1to0

auto[0]

auto[1]

39

1

T195

1

T125

1

T236

2

auto[1]

from_1to0

auto[1]

auto[0]

37

1

T28

1

T74

2

T77

2

auto[1]

from_1to0

auto[1]

auto[1]

35

1

T74

1

T77

1

T195

1

auto[1]

from_0to1

auto[0]

auto[0]

39

1

T28

1

T74

1

T77

1

auto[1]

from_0to1

auto[0]

auto[1]

42

1

T74

1

T77

1

T195

2

auto[1]

from_0to1

auto[1]

auto[0]

44

1

T74

3

T77

1

T114

3

auto[1]

from_0to1

auto[1]

auto[1]

33

1

T28

1

T74

1

T77

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

588

1

T28

11

T74

13

T77

11

auto[1]

590

1

T28

9

T74

7

T77

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

299

1

T28

3

T74

4

T77

7

from_0to1

297

1

T28

3

T74

4

T77

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

576

1

T28

11

T74

10

T77

10

auto[1]

602

1

T28

9

T74

10

T77

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

588

1

T28

10

T74

12

T77

10

auto[1]

590

1

T28

10

T74

8

T77

10

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

30

1

T77

2

T195

3

T310

1

auto[0]

from_1to0

auto[0]

auto[1]

36

1

T114

1

T195

1

T198

2

auto[0]

from_1to0

auto[1]

auto[0]

42

1

T28

1

T74

1

T77

1

auto[0]

from_1to0

auto[1]

auto[1]

55

1

T74

1

T195

1

T125

1

auto[0]

from_0to1

auto[0]

auto[0]

35

1

T28

1

T77

2

T195

1

auto[0]

from_0to1

auto[0]

auto[1]

34

1

T74

1

T114

1

T159

2

auto[0]

from_0to1

auto[1]

auto[0]

39

1

T28

1

T74

1

T77

1

auto[0]

from_0to1

auto[1]

auto[1]

36

1

T74

1

T77

1

T114

1

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T74

1

T77

1

T114

2

auto[1]

from_1to0

auto[0]

auto[1]

43

1

T28

2

T74

1

T77

1

auto[1]

from_1to0

auto[1]

auto[0]

29

1

T77

1

T195

1

T198

1

auto[1]

from_1to0

auto[1]

auto[1]

27

1

T77

1

T114

1

T195

1

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T74

1

T195

1

T310

2

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T28

1

T114

2

T198

1

auto[1]

from_0to1

auto[1]

auto[0]

36

1

T195

1

T198

1

T310

2

auto[1]

from_0to1

auto[1]

auto[1]

40

1

T77

3

T195

1

T335

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

605

1

T28

8

T74

11

T77

10

auto[1]

573

1

T28

12

T74

9

T77

10

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

282

1

T28

7

T74

6

T77

5

from_0to1

282

1

T28

7

T74

6

T77

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

603

1

T28

9

T74

13

T77

12

auto[1]

575

1

T28

11

T74

7

T77

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

614

1

T28

11

T74

8

T77

5

auto[1]

564

1

T28

9

T74

12

T77

15

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

37

1

T74

1

T114

1

T195

1

auto[0]

from_1to0

auto[0]

auto[1]

30

1

T74

1

T77

2

T195

1

auto[0]

from_1to0

auto[1]

auto[0]

31

1

T28

1

T74

2

T198

2

auto[0]

from_1to0

auto[1]

auto[1]

49

1

T74

1

T77

1

T114

1

auto[0]

from_0to1

auto[0]

auto[0]

46

1

T28

1

T74

1

T77

1

auto[0]

from_0to1

auto[0]

auto[1]

40

1

T28

2

T74

1

T195

1

auto[0]

from_0to1

auto[1]

auto[0]

43

1

T77

1

T114

1

T195

2

auto[0]

from_0to1

auto[1]

auto[1]

26

1

T74

1

T114

1

T335

1

auto[1]

from_1to0

auto[0]

auto[0]

36

1

T74

1

T198

2

T335

1

auto[1]

from_1to0

auto[0]

auto[1]

33

1

T28

1

T77

1

T114

2

auto[1]

from_1to0

auto[1]

auto[0]

34

1

T28

1

T77

1

T195

1

auto[1]

from_1to0

auto[1]

auto[1]

32

1

T28

4

T195

1

T198

1

auto[1]

from_0to1

auto[0]

auto[0]

33

1

T28

1

T335

1

T412

2

auto[1]

from_0to1

auto[0]

auto[1]

28

1

T28

1

T74

1

T77

1

auto[1]

from_0to1

auto[1]

auto[0]

39

1

T28

2

T77

1

T114

1

auto[1]

from_0to1

auto[1]

auto[1]

27

1

T74

2

T77

1

T198

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

598

1

T28

14

T74

10

T77

7

auto[1]

580

1

T28

6

T74

10

T77

13

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

281

1

T28

5

T74

5

T77

4

from_0to1

277

1

T28

4

T74

4

T77

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

595

1

T28

9

T74

12

T77

12

auto[1]

583

1

T28

11

T74

8

T77

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

619

1

T28

16

T74

4

T77

9

auto[1]

559

1

T28

4

T74

16

T77

11

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

34

1

T28

2

T74

2

T77

1

auto[0]

from_1to0

auto[0]

auto[1]

28

1

T28

1

T77

1

T198

1

auto[0]

from_1to0

auto[1]

auto[0]

40

1

T28

1

T77

1

T198

1

auto[0]

from_1to0

auto[1]

auto[1]

39

1

T195

1

T198

1

T310

2

auto[0]

from_0to1

auto[0]

auto[0]

44

1

T28

1

T198

1

T310

3

auto[0]

from_0to1

auto[0]

auto[1]

39

1

T28

1

T77

2

T195

2

auto[0]

from_0to1

auto[1]

auto[0]

33

1

T195

2

T198

1

T236

2

auto[0]

from_0to1

auto[1]

auto[1]

32

1

T74

1

T114

1

T198

1

auto[1]

from_1to0

auto[0]

auto[0]

37

1

T195

1

T125

3

T236

2

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T74

2

T77

1

T114

1

auto[1]

from_1to0

auto[1]

auto[0]

37

1

T28

1

T114

2

T195

1

auto[1]

from_1to0

auto[1]

auto[1]

30

1

T74

1

T114

1

T195

1

auto[1]

from_0to1

auto[0]

auto[0]

33

1

T114

1

T310

1

T335

1

auto[1]

from_0to1

auto[0]

auto[1]

36

1

T77

2

T114

1

T195

1

auto[1]

from_0to1

auto[1]

auto[0]

35

1

T28

2

T114

2

T310

1

auto[1]

from_0to1

auto[1]

auto[1]

25

1

T74

3

T125

1

T159

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

591

1

T28

11

T74

10

T77

12

auto[1]

587

1

T28

9

T74

10

T77

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

283

1

T28

4

T74

5

T77

7

from_0to1

284

1

T28

3

T74

6

T77

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

604

1

T28

9

T74

10

T77

8

auto[1]

574

1

T28

11

T74

10

T77

12

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

588

1

T28

10

T74

10

T77

11

auto[1]

590

1

T28

10

T74

10

T77

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T77

2

T195

1

T310

1

auto[0]

from_1to0

auto[0]

auto[1]

38

1

T28

1

T74

1

T198

1

auto[0]

from_1to0

auto[1]

auto[0]

33

1

T28

1

T77

2

T114

1

auto[0]

from_1to0

auto[1]

auto[1]

30

1

T74

1

T77

1

T114

2

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T74

1

T198

1

T335

1

auto[0]

from_0to1

auto[0]

auto[1]

34

1

T74

1

T77

1

T195

1

auto[0]

from_0to1

auto[1]

auto[0]

47

1

T74

3

T77

1

T114

1

auto[0]

from_0to1

auto[1]

auto[1]

28

1

T28

1

T77

1

T125

2

auto[1]

from_1to0

auto[0]

auto[0]

36

1

T77

1

T195

2

T335

1

auto[1]

from_1to0

auto[0]

auto[1]

35

1

T74

1

T125

3

T311

1

auto[1]

from_1to0

auto[1]

auto[0]

39

1

T28

2

T74

1

T198

2

auto[1]

from_1to0

auto[1]

auto[1]

34

1

T74

1

T77

1

T114

2

auto[1]

from_0to1

auto[0]

auto[0]

33

1

T74

1

T114

1

T195

1

auto[1]

from_0to1

auto[0]

auto[1]

44

1

T28

1

T77

1

T114

1

auto[1]

from_0to1

auto[1]

auto[0]

27

1

T28

1

T77

1

T114

1

auto[1]

from_0to1

auto[1]

auto[1]

38

1

T77

2

T114

2

T198

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

607

1

T28

11

T74

11

T77

11

auto[1]

571

1

T28

9

T74

9

T77

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

275

1

T28

4

T74

5

T77

4

from_0to1

275

1

T28

5

T74

5

T77

4

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

601

1

T28

9

T74

11

T77

12

auto[1]

577

1

T28

11

T74

9

T77

8

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

576

1

T28

11

T74

10

T77

11

auto[1]

602

1

T28

9

T74

10

T77

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T28

1

T74

1

T77

2

auto[0]

from_1to0

auto[0]

auto[1]

42

1

T28

1

T74

1

T77

1

auto[0]

from_1to0

auto[1]

auto[0]

35

1

T28

1

T74

1

T77

1

auto[0]

from_1to0

auto[1]

auto[1]

28

1

T74

1

T310

1

T164

1

auto[0]

from_0to1

auto[0]

auto[0]

40

1

T28

1

T74

1

T77

1

auto[0]

from_0to1

auto[0]

auto[1]

38

1

T74

2

T195

1

T236

1

auto[0]

from_0to1

auto[1]

auto[0]

35

1

T28

2

T195

1

T198

1

auto[0]

from_0to1

auto[1]

auto[1]

29

1

T198

2

T310

1

T335

1

auto[1]

from_1to0

auto[0]

auto[0]

32

1

T74

1

T198

1

T335

1

auto[1]

from_1to0

auto[0]

auto[1]

36

1

T114

1

T198

1

T335

2

auto[1]

from_1to0

auto[1]

auto[0]

30

1

T114

1

T195

1

T335

1

auto[1]

from_1to0

auto[1]

auto[1]

34

1

T28

1

T198

1

T125

2

auto[1]

from_0to1

auto[0]

auto[0]

36

1

T28

1

T114

4

T310

1

auto[1]

from_0to1

auto[0]

auto[1]

30

1

T28

1

T74

1

T77

2

auto[1]

from_0to1

auto[1]

auto[0]

32

1

T114

1

T195

1

T125

1

auto[1]

from_0to1

auto[1]

auto[1]

35

1

T74

1

T77

1

T195

1

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

575

1

T28

10

T74

12

T77

12

auto[1]

603

1

T28

10

T74

8

T77

8

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

279

1

T28

5

T74

5

T77

6

from_0to1

278

1

T28

5

T74

5

T77

7

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

590

1

T28

10

T74

11

T77

11

auto[1]

588

1

T28

10

T74

9

T77

9

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

596

1

T28

10

T74

8

T77

6

auto[1]

582

1

T28

10

T74

12

T77

14

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

35

1

T28

1

T74

3

T114

1

auto[0]

from_1to0

auto[0]

auto[1]

32

1

T77

1

T114

1

T198

1

auto[0]

from_1to0

auto[1]

auto[0]

26

1

T28

2

T195

1

T164

1

auto[0]

from_1to0

auto[1]

auto[1]

32

1

T77

3

T195

1

T198

2

auto[0]

from_0to1

auto[0]

auto[0]

35

1

T28

1

T74

1

T77

1

auto[0]

from_0to1

auto[0]

auto[1]

27

1

T74

2

T77

2

T114

1

auto[0]

from_0to1

auto[1]

auto[0]

37

1

T28

1

T77

1

T195

1

auto[0]

from_0to1

auto[1]

auto[1]

29

1

T28

1

T114

1

T310

2

auto[1]

from_1to0

auto[0]

auto[0]

32

1

T198

1

T125

1

T413

2

auto[1]

from_1to0

auto[0]

auto[1]

33

1

T28

1

T310

1

T335

1

auto[1]

from_1to0

auto[1]

auto[0]

44

1

T77

1

T114

2

T195

1

auto[1]

from_1to0

auto[1]

auto[1]

45

1

T28

1

T74

2

T77

1

auto[1]

from_0to1

auto[0]

auto[0]

38

1

T74

1

T77

1

T114

1

auto[1]

from_0to1

auto[0]

auto[1]

41

1

T28

1

T74

1

T77

1

auto[1]

from_0to1

auto[1]

auto[0]

26

1

T311

1

T326

1

T333

1

auto[1]

from_0to1

auto[1]

auto[1]

45

1

T28

1

T77

1

T114

2

Summary for Variable cp_en_override

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_en_override

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

563

1

T28

12

T74

14

T77

11

auto[1]

615

1

T28

8

T74

6

T77

9

---

Summary for Variable cp_override_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for cp_override_value

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

from_1to0

296

1

T28

4

T74

5

T77

6

from_0to1

283

1

T28

4

T74

4

T77

5

---

Summary for Variable cp_pin_allowed_0

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_0

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

603

1

T28

10

T74

9

T77

10

auto[1]

575

1

T28

10

T74

11

T77

10

---

Summary for Variable cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_pin_allowed_1

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

596

1

T28

5

T74

8

T77

11

auto[1]

582

1

T28

15

T74

12

T77

9

---

Summary for Cross cp_pin_cross

Samples crossed: cp_en_override cp_override_value cp_pin_allowed_0 cp_pin_allowed_1

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_pin_cross

Bins

cp_en_override

cp_override_value

cp_pin_allowed_0

cp_pin_allowed_1

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

from_1to0

auto[0]

auto[0]

38

1

T28

1

T74

1

T77

1

auto[0]

from_1to0

auto[0]

auto[1]

30

1

T74

1

T114

1

T236

1

auto[0]

from_1to0

auto[1]

auto[0]

33

1

T74

1

T195

1

T198

1

auto[0]

from_1to0

auto[1]

auto[1]

34

1

T28

1

T74

1

T77

2

auto[0]

from_0to1

auto[0]

auto[0]

33

1

T195

1

T198

1

T335

1

auto[0]

from_0to1

auto[0]

auto[1]

34

1

T28

1

T74

1

T195

1

auto[0]

from_0to1

auto[1]

auto[0]

31

1

T74

1

T77

2

T114

1

auto[0]

from_0to1

auto[1]

auto[1]

33

1

T74

1

T77

1

T114

1

auto[1]

from_1to0

auto[0]

auto[0]

42

1

T77

1

T114

1

T311

1

auto[1]

from_1to0

auto[0]

auto[1]

49

1

T28

2

T74

1

T77

1

auto[1]

from_1to0

auto[1]

auto[0]

30

1

T195

3

T198

1

T310

1

auto[1]

from_1to0

auto[1]

auto[1]

40

1

T77

1

T335

1

T125

1

auto[1]

from_0to1

auto[0]

auto[0]

47

1

T28

1

T77

2

T335

1

auto[1]

from_0to1

auto[0]

auto[1]

36

1

T28

1

T74

1

T310

1

auto[1]

from_0to1

auto[1]

auto[0]

34

1

T28

1

T125

1

T236

2

auto[1]

from_0to1

auto[1]

auto[1]

35

1

T114

2

T195

1

T310

2