Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_sysrst_ctrl_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	149766	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

119692

1

T4

23

T5

8

T6

6

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	141964	1			T4	2		T5	8		T6	9
values[0x0]	63337	1			T4	33		T5	5		T22	11
values[0x1]	64157	1			T4	27		T5	3		T6	3

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	121140	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

148318

1

T4

28

T5

9

T6

8

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	818	1			T1	2		T19	2		T3	3
valid_sources[0x01]	800	1			T22	4		T1	4		T19	6
valid_sources[0x02]	988	1			T1	2		T19	2		T8	11
valid_sources[0x03]	933	1			T1	7		T19	3		T21	2
valid_sources[0x04]	885	1			T8	4		T28	1		T13	3
valid_sources[0x05]	1627	1			T22	4		T1	2		T14	1
valid_sources[0x06]	819	1			T1	1		T19	7		T7	1
valid_sources[0x07]	1447	1			T19	3		T28	1		T51	4
valid_sources[0x08]	988	1			T22	7		T1	2		T9	3
valid_sources[0x09]	759	1			T1	2		T19	2		T10	1
valid_sources[0x0a]	1534	1			T19	2		T8	5		T10	1
valid_sources[0x0b]	1095	1			T22	5		T3	105		T8	1
valid_sources[0x0c]	1809	1			T22	7		T1	4		T19	3
valid_sources[0x0d]	848	1			T1	3		T19	14		T8	9
valid_sources[0x0e]	1295	1			T22	9		T1	2		T74	1
valid_sources[0x0f]	1387	1			T1	3		T19	4		T51	10
valid_sources[0x10]	780	1			T22	1		T1	8		T8	6
valid_sources[0x11]	930	1			T22	1		T1	9		T28	1
valid_sources[0x12]	792	1			T22	7		T19	1		T10	2
valid_sources[0x13]	719	1			T1	1		T19	2		T8	2
valid_sources[0x14]	832	1			T19	2		T8	6		T10	1
valid_sources[0x15]	830	1			T1	4		T19	9		T8	5
valid_sources[0x16]	1019	1			T1	6		T19	1		T21	1
valid_sources[0x17]	1048	1			T1	4		T2	1		T21	1
valid_sources[0x18]	776	1			T22	5		T1	4		T8	2
valid_sources[0x19]	1082	1			T19	3		T7	2		T8	8
valid_sources[0x1a]	2157	1			T22	3		T1	2		T21	1
valid_sources[0x1b]	941	1			T1	1		T14	4		T19	1
valid_sources[0x1c]	969	1			T1	2		T19	1		T21	1
valid_sources[0x1d]	952	1			T1	2		T2	1		T19	10
valid_sources[0x1e]	837	1			T1	3		T19	2		T13	3
valid_sources[0x1f]	790	1			T1	3		T2	1		T19	2
valid_sources[0x20]	814	1			T22	3		T3	15		T8	1
valid_sources[0x21]	1077	1			T1	3		T19	1		T8	2
valid_sources[0x22]	914	1			T1	3		T19	1		T8	1
valid_sources[0x23]	971	1			T22	2		T19	3		T3	54
valid_sources[0x24]	833	1			T1	1		T19	2		T13	4
valid_sources[0x25]	857	1			T1	3		T14	2		T8	15
valid_sources[0x26]	1880	1			T1	3		T16	19		T19	2
valid_sources[0x27]	1408	1			T1	3		T8	2		T76	1
valid_sources[0x28]	720	1			T22	2		T1	2		T18	4
valid_sources[0x29]	711	1			T1	4		T19	4		T8	1
valid_sources[0x2a]	854	1			T1	7		T14	3		T8	1
valid_sources[0x2b]	919	1			T1	4		T9	1		T10	2
valid_sources[0x2c]	797	1			T1	2		T2	1		T19	2
valid_sources[0x2d]	694	1			T1	9		T19	2		T60	4
valid_sources[0x2e]	840	1			T1	4		T10	1		T35	3
valid_sources[0x2f]	1773	1			T19	6		T28	1		T13	6
valid_sources[0x30]	929	1			T1	3		T19	10		T8	11
valid_sources[0x31]	986	1			T1	2		T19	1		T21	1
valid_sources[0x32]	1358	1			T1	3		T17	63		T19	6
valid_sources[0x33]	1125	1			T1	5		T8	3		T13	4
valid_sources[0x34]	792	1			T22	1		T1	2		T3	48
valid_sources[0x35]	940	1			T1	4		T8	1		T51	4
valid_sources[0x36]	835	1			T22	3		T1	1		T3	5
valid_sources[0x37]	1000	1			T1	2		T19	7		T7	1
valid_sources[0x38]	732	1			T1	1		T19	1		T8	10
valid_sources[0x39]	729	1			T1	4		T2	1		T19	3
valid_sources[0x3a]	796	1			T2	1		T19	3		T8	2
valid_sources[0x3b]	845	1			T22	6		T1	1		T19	6
valid_sources[0x3c]	787	1			T14	2		T19	1		T7	1
valid_sources[0x3d]	1227	1			T1	2		T19	2		T28	1
valid_sources[0x3e]	818	1			T22	2		T1	3		T19	3
valid_sources[0x3f]	1896	1			T1	3		T8	1		T13	2
valid_sources[0x40]	2002	1			T19	1		T7	1		T13	1
valid_sources[0x41]	2040	1			T22	3		T1	4		T19	6
valid_sources[0x42]	787	1			T1	1		T19	4		T8	7
valid_sources[0x43]	729	1			T1	2		T19	2		T28	1
valid_sources[0x44]	784	1			T22	3		T1	4		T13	1
valid_sources[0x45]	1376	1			T1	2		T19	2		T8	7
valid_sources[0x46]	1235	1			T1	2		T19	10		T28	1
valid_sources[0x47]	804	1			T22	1		T2	1		T10	2
valid_sources[0x48]	1005	1			T1	1		T19	4		T3	90
valid_sources[0x49]	753	1			T1	1		T28	1		T13	1
valid_sources[0x4a]	1040	1			T19	5		T76	3		T13	4
valid_sources[0x4b]	1156	1			T1	1		T18	6		T19	7
valid_sources[0x4c]	820	1			T1	2		T14	4		T21	1
valid_sources[0x4d]	796	1			T19	1		T8	6		T28	1
valid_sources[0x4e]	814	1			T22	4		T1	2		T19	2
valid_sources[0x4f]	1031	1			T1	1		T19	1		T8	3
valid_sources[0x50]	1005	1			T1	1		T28	1		T74	2
valid_sources[0x51]	1009	1			T22	4		T1	2		T2	1
valid_sources[0x52]	947	1			T1	4		T21	2		T7	1
valid_sources[0x53]	998	1			T1	1		T28	3		T73	3
valid_sources[0x54]	874	1			T21	1		T3	13		T8	4
valid_sources[0x55]	839	1			T22	3		T1	4		T2	1
valid_sources[0x56]	919	1			T1	5		T2	1		T19	2
valid_sources[0x57]	1712	1			T22	3		T1	3		T16	23
valid_sources[0x58]	1012	1			T1	3		T2	1		T21	2
valid_sources[0x59]	1194	1			T1	6		T19	2		T13	3
valid_sources[0x5a]	842	1			T1	1		T19	4		T28	1
valid_sources[0x5b]	3361	1			T22	2		T1	3		T8	10
valid_sources[0x5c]	888	1			T22	1		T1	1		T19	1
valid_sources[0x5d]	924	1			T1	2		T3	2		T8	2
valid_sources[0x5e]	1785	1			T1	3		T19	1		T28	1
valid_sources[0x5f]	716	1			T1	5		T2	1		T19	3
valid_sources[0x60]	1073	1			T19	3		T8	4		T28	1
valid_sources[0x61]	861	1			T1	2		T8	3		T28	1
valid_sources[0x62]	945	1			T22	3		T1	3		T19	10
valid_sources[0x63]	1358	1			T1	2		T129	1		T13	3
valid_sources[0x64]	796	1			T1	4		T19	1		T8	5
valid_sources[0x65]	829	1			T1	2		T19	7		T8	4
valid_sources[0x66]	1205	1			T8	13		T28	1		T74	1
valid_sources[0x67]	816	1			T1	4		T19	3		T8	4
valid_sources[0x68]	969	1			T1	4		T19	9		T51	7
valid_sources[0x69]	738	1			T1	3		T19	3		T8	2
valid_sources[0x6a]	1227	1			T1	1		T19	2		T21	2
valid_sources[0x6b]	837	1			T22	3		T1	6		T13	2
valid_sources[0x6c]	646	1			T19	2		T28	1		T77	2
valid_sources[0x6d]	1869	1			T21	1		T10	1		T11	842
valid_sources[0x6e]	711	1			T22	8		T19	9		T8	1
valid_sources[0x6f]	790	1			T1	4		T15	2		T8	13
valid_sources[0x70]	727	1			T1	1		T2	1		T19	6
valid_sources[0x71]	666	1			T1	1		T19	2		T8	3
valid_sources[0x72]	736	1			T1	5		T19	6		T129	1
valid_sources[0x73]	1060	1			T1	1		T19	4		T28	1
valid_sources[0x74]	2646	1			T4	62		T22	1		T1	2
valid_sources[0x75]	1355	1			T1	5		T19	3		T28	1
valid_sources[0x76]	805	1			T22	1		T1	4		T19	2
valid_sources[0x77]	879	1			T1	5		T14	2		T8	19
valid_sources[0x78]	1168	1			T1	1		T14	1		T19	3
valid_sources[0x79]	776	1			T22	1		T1	4		T19	6
valid_sources[0x7a]	1094	1			T5	16		T1	3		T19	4
valid_sources[0x7b]	1035	1			T22	10		T1	1		T2	1
valid_sources[0x7c]	1868	1			T1	6		T28	1		T13	2
valid_sources[0x7d]	1074	1			T1	2		T8	9		T74	2
valid_sources[0x7e]	2604	1			T1	5		T2	2		T21	1
valid_sources[0x7f]	1218	1			T1	4		T14	5		T19	1
valid_sources[0x80]	1010	1			T1	3		T19	11		T8	11

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

64662

1

T4

1

T5

3

T6

4

values[0x0]

all_enables

biggest_size

31910

1

T4

16

T5

5

T22

10

values[0x1]

all_enables

biggest_size

23120

1

T4

6

T6

2

T22

6