Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.17	93.48	85.71		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T26,T29

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T5,T26,T29

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T29,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T26,T29
1	0	Covered	T4,T5,T6
1	1	Covered	T5,T26,T29

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T29,T53
0	1	Covered	T84
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T29,T53
0	1	Covered	T5,T29,T53
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T29,T53
1	-	Covered	T5,T29,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T26,T29
DetectSt	168	Covered	T5,T29,T53
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T5,T29,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T29,T53
DebounceSt->IdleSt	163	Covered	T26,T55,T58
DetectSt->IdleSt	186	Covered	T84
DetectSt->StableSt	191	Covered	T5,T29,T53
IdleSt->DebounceSt	148	Covered	T5,T26,T29
StableSt->IdleSt	206	Covered	T5,T29,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T26,T29
0	1	Covered	T5,T26,T29
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T5,T29,T53
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T26,T29
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T29,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T55,T58,T131
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T26,T29
DetectSt	-	-	-	-	1	-	-	Covered	T84
DetectSt	-	-	-	-	0	1	-	Covered	T5,T29,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T5,T29,T53
StableSt	-	-	-	-	-	-	0	Covered	T5,T29,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	175	0	0
CntIncr_A	5590926	143694	0	0
CntNoWrap_A	5590926	5130833	0	0
DetectStDropOut_A	5590926	1	0	0
DetectedOut_A	5590926	549	0	0
DetectedPulseOut_A	5590926	78	0	0
DisabledIdleSt_A	5590926	4983342	0	0
DisabledNoDetection_A	5590926	4985280	0	0
EnterDebounceSt_A	5590926	96	0	0
EnterDetectSt_A	5590926	79	0	0
EnterStableSt_A	5590926	78	0	0
PulseIsPulse_A	5590926	78	0	0
StayInStableSt	5590926	471	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5590926	5532	0	0
gen_low_level_sva.LowLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	78	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	175	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T5	627	2	0	0
T6	888	0	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T22	1188	0	0	0
T26	0	1	0	0
T29	0	6	0	0
T53	0	4	0	0
T55	0	4	0	0
T56	0	4	0	0
T57	0	4	0	0
T58	0	3	0	0
T59	0	2	0	0
T84	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	143694	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T5	627	11	0	0
T6	888	0	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T22	1188	0	0	0
T26	0	10	0	0
T29	0	76	0	0
T53	0	150	0	0
T55	0	187	0	0
T56	0	26	0	0
T57	0	149	0	0
T58	0	133	0	0
T59	0	42	0	0
T84	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130833	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	224	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1	0	0
T84	611	1	0	0
T103	10830	0	0	0
T115	582	0	0	0
T116	422	0	0	0
T117	414	0	0	0
T118	429	0	0	0
T119	426	0	0	0
T120	7663	0	0	0
T121	1090	0	0	0
T122	850	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	549	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T5	627	4	0	0
T6	888	0	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T22	1188	0	0	0
T29	0	16	0	0
T53	0	20	0	0
T55	0	8	0	0
T56	0	18	0	0
T57	0	15	0	0
T58	0	5	0	0
T59	0	9	0	0
T115	0	3	0	0
T123	0	7	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	78	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T5	627	1	0	0
T6	888	0	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T22	1188	0	0	0
T29	0	3	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T115	0	1	0	0
T123	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4983342	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	166	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4985280	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	167	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	96	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T5	627	1	0	0
T6	888	0	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T22	1188	0	0	0
T26	0	1	0	0
T29	0	3	0	0
T53	0	2	0	0
T55	0	3	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	1	0	0
T84	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	79	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T5	627	1	0	0
T6	888	0	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T22	1188	0	0	0
T29	0	3	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T84	0	1	0	0
T115	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	78	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T5	627	1	0	0
T6	888	0	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T22	1188	0	0	0
T29	0	3	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T115	0	1	0	0
T123	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	78	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T5	627	1	0	0
T6	888	0	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T22	1188	0	0	0
T29	0	3	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T115	0	1	0	0
T123	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	471	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T5	627	3	0	0
T6	888	0	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T22	1188	0	0	0
T29	0	13	0	0
T53	0	18	0	0
T55	0	7	0	0
T56	0	16	0	0
T57	0	13	0	0
T58	0	4	0	0
T59	0	8	0	0
T115	0	2	0	0
T123	0	5	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5532	0	0
T1	33661	7	0	0
T2	1891	13	0	0
T4	526	5	0	0
T5	627	3	0	0
T6	888	3	0	0
T14	497	7	0	0
T15	430	3	0	0
T16	442	5	0	0
T17	524	3	0	0
T18	0	1	0	0
T22	1188	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	78	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T5	627	1	0	0
T6	888	0	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T22	1188	0	0	0
T29	0	3	0	0
T53	0	2	0	0
T55	0	1	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	1	0	0
T115	0	1	0	0
T123	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T9,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T9,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T10,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T9,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T63
0	1	Covered	T41,T94,T95
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T63
0	1	Unreachable
1	0	Covered	T2,T10,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T26
DetectSt	168	Covered	T2,T10,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T10,T63

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T41
DebounceSt->IdleSt	163	Covered	T9,T26,T82
DetectSt->IdleSt	186	Covered	T41,T94,T95
DetectSt->StableSt	191	Covered	T2,T10,T63
IdleSt->DebounceSt	148	Covered	T2,T9,T26
StableSt->IdleSt	206	Covered	T2,T10,T63

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T26
0	1	Covered	T2,T9,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T82,T92
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T26
DetectSt	-	-	-	-	1	-	-	Covered	T41,T94,T95
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T63
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	94	0	0
CntIncr_A	5590926	24680	0	0
CntNoWrap_A	5590926	5130914	0	0
DetectStDropOut_A	5590926	4	0	0
DetectedOut_A	5590926	55117	0	0
DetectedPulseOut_A	5590926	31	0	0
DisabledIdleSt_A	5590926	4811046	0	0
DisabledNoDetection_A	5590926	4813014	0	0
EnterDebounceSt_A	5590926	61	0	0
EnterDetectSt_A	5590926	35	0	0
EnterStableSt_A	5590926	31	0	0
PulseIsPulse_A	5590926	31	0	0
StayInStableSt	5590926	55086	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5590926	5532	0	0
gen_low_level_sva.LowLevelEvent_A	5590926	5132976	0	0
gen_sticky_sva.StableStDropOut_A	5590926	237125	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	94	0	0
T2	1891	2	0	0
T3	19016	0	0	0
T9	0	1	0	0
T10	0	4	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T41	0	2	0	0
T63	0	2	0	0
T65	0	2	0	0
T80	0	6	0	0
T81	0	2	0	0
T82	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	24680	0	0
T2	1891	57	0	0
T3	19016	0	0	0
T9	0	83	0	0
T10	0	188	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	74	0	0
T41	0	72	0	0
T63	0	86	0	0
T65	0	65	0	0
T80	0	204	0	0
T81	0	75	0	0
T82	0	168	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130914	0	0
T1	33661	33234	0	0
T2	1891	1488	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4	0	0
T37	31494	0	0	0
T41	2206	1	0	0
T55	692	0	0	0
T56	617	0	0	0
T63	1204	0	0	0
T64	19594	0	0	0
T78	22950	0	0	0
T79	16027	0	0	0
T94	0	1	0	0
T95	0	1	0	0
T132	0	1	0	0
T133	787	0	0	0
T134	18966	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	55117	0	0
T2	1891	230	0	0
T3	19016	0	0	0
T10	0	446	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T63	0	44	0	0
T65	0	277	0	0
T80	0	944	0	0
T81	0	12	0	0
T124	0	453	0	0
T125	0	540	0	0
T126	0	373	0	0
T127	0	49	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	31	0	0
T2	1891	1	0	0
T3	19016	0	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T63	0	1	0	0
T65	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4811046	0	0
T1	33661	33234	0	0
T2	1891	1019	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4813014	0	0
T1	33661	33248	0	0
T2	1891	1020	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	61	0	0
T2	1891	1	0	0
T3	19016	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	2	0	0
T41	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	35	0	0
T2	1891	1	0	0
T3	19016	0	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T41	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	31	0	0
T2	1891	1	0	0
T3	19016	0	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T63	0	1	0	0
T65	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	31	0	0
T2	1891	1	0	0
T3	19016	0	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T63	0	1	0	0
T65	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	55086	0	0
T2	1891	229	0	0
T3	19016	0	0	0
T10	0	444	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T63	0	43	0	0
T65	0	276	0	0
T80	0	941	0	0
T81	0	11	0	0
T124	0	452	0	0
T125	0	539	0	0
T126	0	372	0	0
T127	0	48	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5532	0	0
T1	33661	7	0	0
T2	1891	13	0	0
T4	526	5	0	0
T5	627	3	0	0
T6	888	3	0	0
T14	497	7	0	0
T15	430	3	0	0
T16	442	5	0	0
T17	524	3	0	0
T18	0	1	0	0
T22	1188	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	237125	0	0
T2	1891	160	0	0
T3	19016	0	0	0
T10	0	97	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T63	0	64	0	0
T65	0	89	0	0
T80	0	180	0	0
T81	0	51	0	0
T124	0	122849	0	0
T125	0	69	0	0
T126	0	172	0	0
T127	0	30	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T2
1	1	Covered	T4,T6,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T9,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T9,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T41,T65

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T26
1	0	Covered	T4,T6,T2
1	1	Covered	T2,T9,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T41,T65
0	1	Covered	T80,T92,T93
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T41,T65
0	1	Unreachable
1	0	Covered	T10,T41,T65

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T26
DetectSt	168	Covered	T10,T41,T65
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T41,T65

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T41,T65
DebounceSt->IdleSt	163	Covered	T2,T9,T26
DetectSt->IdleSt	186	Covered	T80,T92,T93
DetectSt->StableSt	191	Covered	T10,T41,T65
IdleSt->DebounceSt	148	Covered	T2,T9,T26
StableSt->IdleSt	206	Covered	T10,T41,T65

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T26
0	1	Covered	T2,T9,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T10,T41,T65
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T41,T65
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T9,T63
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T26
DetectSt	-	-	-	-	1	-	-	Covered	T80,T92,T93
DetectSt	-	-	-	-	0	1	-	Covered	T10,T41,T65
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T41,T65
StableSt	-	-	-	-	-	-	0	Covered	T10,T41,T65
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	109	0	0
CntIncr_A	5590926	60191	0	0
CntNoWrap_A	5590926	5130899	0	0
DetectStDropOut_A	5590926	10	0	0
DetectedOut_A	5590926	60176	0	0
DetectedPulseOut_A	5590926	30	0	0
DisabledIdleSt_A	5590926	4811046	0	0
DisabledNoDetection_A	5590926	4813014	0	0
EnterDebounceSt_A	5590926	71	0	0
EnterDetectSt_A	5590926	40	0	0
EnterStableSt_A	5590926	30	0	0
PulseIsPulse_A	5590926	30	0	0
StayInStableSt	5590926	60146	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_sticky_sva.StableStDropOut_A	5590926	196425	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	109	0	0
T2	1891	4	0	0
T3	19016	0	0	0
T9	0	1	0	0
T10	0	4	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T41	0	2	0	0
T63	0	1	0	0
T65	0	2	0	0
T80	0	16	0	0
T81	0	1	0	0
T82	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	60191	0	0
T2	1891	368	0	0
T3	19016	0	0	0
T9	0	32	0	0
T10	0	92	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	74	0	0
T41	0	55	0	0
T63	0	33	0	0
T65	0	44	0	0
T80	0	882	0	0
T81	0	32	0	0
T82	0	91	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130899	0	0
T1	33661	33234	0	0
T2	1891	1486	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	10	0	0
T38	2574	0	0	0
T44	1511	0	0	0
T57	40145	0	0	0
T80	1868	7	0	0
T92	0	1	0	0
T93	0	2	0	0
T97	5816	0	0	0
T135	402	0	0	0
T136	427	0	0	0
T137	14300	0	0	0
T138	527	0	0	0
T139	485	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	60176	0	0
T10	1596	98	0	0
T11	12099	0	0	0
T12	864	0	0	0
T41	0	1	0	0
T51	5272	0	0	0
T62	881	0	0	0
T65	0	186	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T82	0	424	0	0
T92	0	124	0	0
T124	0	448	0	0
T125	0	216	0	0
T126	0	428	0	0
T127	0	45	0	0
T128	0	31	0	0
T129	408	0	0	0
T130	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	30	0	0
T10	1596	2	0	0
T11	12099	0	0	0
T12	864	0	0	0
T41	0	1	0	0
T51	5272	0	0	0
T62	881	0	0	0
T65	0	1	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T82	0	1	0	0
T92	0	2	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	408	0	0	0
T130	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4811046	0	0
T1	33661	33234	0	0
T2	1891	1019	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4813014	0	0
T1	33661	33248	0	0
T2	1891	1020	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	71	0	0
T2	1891	4	0	0
T3	19016	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	2	0	0
T41	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T80	0	9	0	0
T81	0	1	0	0
T82	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	40	0	0
T10	1596	2	0	0
T11	12099	0	0	0
T12	864	0	0	0
T41	0	1	0	0
T51	5272	0	0	0
T62	881	0	0	0
T65	0	1	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T80	0	7	0	0
T82	0	1	0	0
T92	0	3	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T129	408	0	0	0
T130	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	30	0	0
T10	1596	2	0	0
T11	12099	0	0	0
T12	864	0	0	0
T41	0	1	0	0
T51	5272	0	0	0
T62	881	0	0	0
T65	0	1	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T82	0	1	0	0
T92	0	2	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	408	0	0	0
T130	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	30	0	0
T10	1596	2	0	0
T11	12099	0	0	0
T12	864	0	0	0
T41	0	1	0	0
T51	5272	0	0	0
T62	881	0	0	0
T65	0	1	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T82	0	1	0	0
T92	0	2	0	0
T124	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T127	0	1	0	0
T128	0	1	0	0
T129	408	0	0	0
T130	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	60146	0	0
T10	1596	96	0	0
T11	12099	0	0	0
T12	864	0	0	0
T51	5272	0	0	0
T62	881	0	0	0
T65	0	185	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T82	0	423	0	0
T92	0	122	0	0
T124	0	447	0	0
T125	0	215	0	0
T126	0	427	0	0
T127	0	44	0	0
T128	0	30	0	0
T129	408	0	0	0
T130	402	0	0	0
T140	0	177	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	196425	0	0
T10	1596	547	0	0
T11	12099	0	0	0
T12	864	0	0	0
T41	0	46	0	0
T51	5272	0	0	0
T62	881	0	0	0
T65	0	197	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T82	0	184	0	0
T92	0	279	0	0
T124	0	122843	0	0
T125	0	448	0	0
T126	0	99	0	0
T127	0	28	0	0
T128	0	69616	0	0
T129	408	0	0	0
T130	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T9,T26

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T9,T26

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T9,T26
1	0	Covered	T4,T6,T1
1	1	Covered	T2,T9,T26

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Covered	T90,T91
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T9,T10
0	1	Unreachable
1	0	Covered	T2,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T9,T26
DetectSt	168	Covered	T2,T9,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T9,T10
DebounceSt->IdleSt	163	Covered	T26,T82,T128
DetectSt->IdleSt	186	Covered	T90,T91
DetectSt->StableSt	191	Covered	T2,T9,T10
IdleSt->DebounceSt	148	Covered	T2,T9,T26
StableSt->IdleSt	206	Covered	T2,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T9,T26
0	1	Covered	T2,T9,T26
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T2,T9,T10
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T9,T26
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T82,T128,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T9,T26
DetectSt	-	-	-	-	1	-	-	Covered	T90,T91
DetectSt	-	-	-	-	0	1	-	Covered	T2,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T2,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	100	0	0
CntIncr_A	5590926	20978	0	0
CntNoWrap_A	5590926	5130908	0	0
DetectStDropOut_A	5590926	3	0	0
DetectedOut_A	5590926	109711	0	0
DetectedPulseOut_A	5590926	35	0	0
DisabledIdleSt_A	5590926	4811046	0	0
DisabledNoDetection_A	5590926	4813014	0	0
EnterDebounceSt_A	5590926	64	0	0
EnterDetectSt_A	5590926	38	0	0
EnterStableSt_A	5590926	35	0	0
PulseIsPulse_A	5590926	35	0	0
StayInStableSt	5590926	109676	0	0
gen_high_event_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_sticky_sva.StableStDropOut_A	5590926	61726	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	100	0	0
T2	1891	2	0	0
T3	19016	0	0	0
T9	0	2	0	0
T10	0	4	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T41	0	2	0	0
T63	0	2	0	0
T65	0	2	0	0
T80	0	6	0	0
T81	0	2	0	0
T82	0	3	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	20978	0	0
T2	1891	58	0	0
T3	19016	0	0	0
T9	0	19	0	0
T10	0	120	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	75	0	0
T41	0	59	0	0
T63	0	16	0	0
T65	0	82	0	0
T80	0	102	0	0
T81	0	44	0	0
T82	0	168	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130908	0	0
T1	33661	33234	0	0
T2	1891	1488	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	3	0	0
T90	145931	1	0	0
T91	0	2	0	0
T142	499	0	0	0
T143	437	0	0	0
T144	502	0	0	0
T145	705	0	0	0
T146	456	0	0	0
T147	403	0	0	0
T148	1015	0	0	0
T149	1864	0	0	0
T150	464	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	109711	0	0
T2	1891	187	0	0
T3	19016	0	0	0
T9	0	5	0	0
T10	0	252	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T41	0	14	0	0
T63	0	8	0	0
T65	0	322	0	0
T80	0	319	0	0
T81	0	28	0	0
T124	0	105225	0	0
T125	0	307	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	35	0	0
T2	1891	1	0	0
T3	19016	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T41	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4811046	0	0
T1	33661	33234	0	0
T2	1891	1019	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4813014	0	0
T1	33661	33248	0	0
T2	1891	1020	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	64	0	0
T2	1891	1	0	0
T3	19016	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	2	0	0
T41	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T82	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	38	0	0
T2	1891	1	0	0
T3	19016	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T41	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	35	0	0
T2	1891	1	0	0
T3	19016	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T41	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	35	0	0
T2	1891	1	0	0
T3	19016	0	0	0
T9	0	1	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T41	0	1	0	0
T63	0	1	0	0
T65	0	1	0	0
T80	0	3	0	0
T81	0	1	0	0
T124	0	1	0	0
T125	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	109676	0	0
T2	1891	186	0	0
T3	19016	0	0	0
T9	0	4	0	0
T10	0	250	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T41	0	13	0	0
T63	0	7	0	0
T65	0	321	0	0
T80	0	316	0	0
T81	0	27	0	0
T124	0	105224	0	0
T125	0	306	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	61726	0	0
T2	1891	219	0	0
T3	19016	0	0	0
T9	0	123	0	0
T10	0	380	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T41	0	45	0	0
T63	0	177	0	0
T65	0	40	0	0
T80	0	946	0	0
T81	0	82	0	0
T124	0	48	0	0
T125	0	352	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T47,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T47,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T47,T49,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T12,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T47,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T47,T49,T50
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T47,T49,T50
0	1	Covered	T47,T49,T151
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T47,T49,T50
1	-	Covered	T47,T49,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T47,T49
DetectSt	168	Covered	T47,T49,T50
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T47,T49,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T47,T49,T50
DebounceSt->IdleSt	163	Covered	T26,T152,T83
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T47,T49,T50
IdleSt->DebounceSt	148	Covered	T26,T47,T49
StableSt->IdleSt	206	Covered	T47,T49,T151

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T47,T49
0	1	Covered	T26,T47,T49
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T47,T49,T50
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T47,T49
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T47,T49,T50
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T47,T49
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T47,T49,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T47,T49,T151
StableSt	-	-	-	-	-	-	0	Covered	T47,T49,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	52	0	0
CntIncr_A	5590926	1497	0	0
CntNoWrap_A	5590926	5130956	0	0
DetectStDropOut_A	5590926	0	0	0
DetectedOut_A	5590926	1761	0	0
DetectedPulseOut_A	5590926	25	0	0
DisabledIdleSt_A	5590926	5118430	0	0
DisabledNoDetection_A	5590926	5120358	0	0
EnterDebounceSt_A	5590926	28	0	0
EnterDetectSt_A	5590926	25	0	0
EnterStableSt_A	5590926	25	0	0
PulseIsPulse_A	5590926	25	0	0
StayInStableSt	5590926	1721	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	52	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	4	0	0
T153	0	2	0	0
T154	0	2	0	0
T155	0	2	0	0
T156	0	2	0	0
T157	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1497	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	17	0	0
T29	616	0	0	0
T47	0	12	0	0
T49	0	82	0	0
T50	0	75	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	198	0	0
T152	0	33	0	0
T153	0	18	0	0
T154	0	55	0	0
T155	0	100	0	0
T156	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130956	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1761	0	0
T40	864	0	0	0
T47	558	56	0	0
T49	0	50	0	0
T50	0	59	0	0
T131	21334	0	0	0
T151	0	186	0	0
T153	0	42	0	0
T154	0	43	0	0
T155	0	45	0	0
T156	0	49	0	0
T157	0	4	0	0
T158	0	59	0	0
T159	502	0	0	0
T160	403	0	0	0
T161	10118	0	0	0
T162	635	0	0	0
T163	422	0	0	0
T164	503	0	0	0
T165	407	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T40	864	0	0	0
T47	558	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T131	21334	0	0	0
T151	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	502	0	0	0
T160	403	0	0	0
T161	10118	0	0	0
T162	635	0	0	0
T163	422	0	0	0
T164	503	0	0	0
T165	407	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5118430	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5120358	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	28	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T40	864	0	0	0
T47	558	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T131	21334	0	0	0
T151	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	502	0	0	0
T160	403	0	0	0
T161	10118	0	0	0
T162	635	0	0	0
T163	422	0	0	0
T164	503	0	0	0
T165	407	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T40	864	0	0	0
T47	558	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T131	21334	0	0	0
T151	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	502	0	0	0
T160	403	0	0	0
T161	10118	0	0	0
T162	635	0	0	0
T163	422	0	0	0
T164	503	0	0	0
T165	407	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T40	864	0	0	0
T47	558	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T131	21334	0	0	0
T151	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T156	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	502	0	0	0
T160	403	0	0	0
T161	10118	0	0	0
T162	635	0	0	0
T163	422	0	0	0
T164	503	0	0	0
T165	407	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1721	0	0
T40	864	0	0	0
T47	558	55	0	0
T49	0	49	0	0
T50	0	57	0	0
T131	21334	0	0	0
T151	0	183	0	0
T153	0	40	0	0
T154	0	42	0	0
T155	0	43	0	0
T156	0	47	0	0
T157	0	3	0	0
T158	0	58	0	0
T159	502	0	0	0
T160	403	0	0	0
T161	10118	0	0	0
T162	635	0	0	0
T163	422	0	0	0
T164	503	0	0	0
T165	407	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	10	0	0
T40	864	0	0	0
T47	558	1	0	0
T49	0	1	0	0
T131	21334	0	0	0
T148	0	1	0	0
T151	0	1	0	0
T154	0	1	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	502	0	0	0
T160	403	0	0	0
T161	10118	0	0	0
T162	635	0	0	0
T163	422	0	0	0
T164	503	0	0	0
T165	407	0	0	0
T166	0	1	0	0
T167	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T12,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T12,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T41,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T12,T41
1	0	Covered	T4,T22,T1
1	1	Covered	T26,T12,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T41,T43
0	1	Covered	T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T41,T43
0	1	Covered	T42,T168,T151
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T41,T43
1	-	Covered	T42,T168,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T12,T41
DetectSt	168	Covered	T12,T41,T43
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T41,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T41,T43
DebounceSt->IdleSt	163	Covered	T26,T157,T83
DetectSt->IdleSt	186	Covered	T86
DetectSt->StableSt	191	Covered	T12,T41,T43
IdleSt->DebounceSt	148	Covered	T26,T12,T41
StableSt->IdleSt	206	Covered	T41,T38,T42

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T12,T41
0	1	Covered	T26,T12,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T41,T43
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T12,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T41,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T157,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T12,T41
DetectSt	-	-	-	-	1	-	-	Covered	T86
DetectSt	-	-	-	-	0	1	-	Covered	T12,T41,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T168,T151
StableSt	-	-	-	-	-	-	0	Covered	T12,T41,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	80	0	0
CntIncr_A	5590926	10925	0	0
CntNoWrap_A	5590926	5130928	0	0
DetectStDropOut_A	5590926	1	0	0
DetectedOut_A	5590926	3913	0	0
DetectedPulseOut_A	5590926	37	0	0
DisabledIdleSt_A	5590926	5082968	0	0
DisabledNoDetection_A	5590926	5084903	0	0
EnterDebounceSt_A	5590926	42	0	0
EnterDetectSt_A	5590926	38	0	0
EnterStableSt_A	5590926	37	0	0
PulseIsPulse_A	5590926	37	0	0
StayInStableSt	5590926	3856	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5590926	1543	0	0
gen_low_level_sva.LowLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	80	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	2	0	0
T26	6185	1	0	0
T29	616	0	0	0
T38	0	2	0	0
T41	0	2	0	0
T42	0	4	0	0
T43	0	2	0	0
T49	0	2	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	4	0	0
T168	0	6	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	10925	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	79	0	0
T26	6185	17	0	0
T29	616	0	0	0
T38	0	36	0	0
T41	0	46	0	0
T42	0	156	0	0
T43	0	17	0	0
T49	0	17	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	198	0	0
T168	0	189	0	0
T170	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130928	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1	0	0
T86	37619	1	0	0
T171	490	0	0	0
T172	531	0	0	0
T173	1225	0	0	0
T174	445	0	0	0
T175	19976	0	0	0
T176	407	0	0	0
T177	524	0	0	0
T178	422	0	0	0
T179	1081	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	3913	0	0
T12	864	41	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	283	0	0
T41	0	190	0	0
T42	0	238	0	0
T43	0	155	0	0
T49	0	62	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	306	0	0
T168	0	362	0	0
T170	0	73	0	0
T180	0	68	0	0
T181	869	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	37	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T49	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	2	0	0
T168	0	3	0	0
T170	0	1	0	0
T180	0	1	0	0
T181	869	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5082968	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5084903	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	42	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	1	0	0
T26	6185	1	0	0
T29	616	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T49	0	1	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	2	0	0
T168	0	3	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	38	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T49	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	2	0	0
T168	0	3	0	0
T170	0	1	0	0
T180	0	1	0	0
T181	869	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	37	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T49	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	2	0	0
T168	0	3	0	0
T170	0	1	0	0
T180	0	1	0	0
T181	869	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	37	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	1	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T49	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	2	0	0
T168	0	3	0	0
T170	0	1	0	0
T180	0	1	0	0
T181	869	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	3856	0	0
T12	864	39	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	281	0	0
T41	0	188	0	0
T42	0	235	0	0
T43	0	153	0	0
T49	0	60	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	304	0	0
T168	0	358	0	0
T170	0	71	0	0
T180	0	66	0	0
T181	869	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1543	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T4	526	6	0	0
T5	627	0	0	0
T6	888	0	0	0
T7	0	1	0	0
T14	497	4	0	0
T15	430	3	0	0
T16	442	7	0	0
T17	524	4	0	0
T18	0	1	0	0
T20	0	2	0	0
T21	0	5	0	0
T22	1188	0	0	0
T60	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	17	0	0
T42	1086	1	0	0
T47	558	0	0	0
T131	21334	0	0	0
T148	0	1	0	0
T151	0	2	0	0
T156	0	1	0	0
T158	0	1	0	0
T159	502	0	0	0
T160	403	0	0	0
T161	10118	0	0	0
T162	635	0	0	0
T163	422	0	0	0
T164	503	0	0	0
T166	0	1	0	0
T168	0	2	0	0
T182	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T185	422	0	0	0