Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.69	95.65	85.71		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.61	95.65	85.71		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T43,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T43,T38

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T43,T38,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T26,T43
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T43,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T38,T44
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T38,T44
0	1	Covered	T38,T44,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T38,T44
1	-	Covered	T38,T44,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T43,T38
DetectSt	168	Covered	T43,T38,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T43,T38,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T38,T44
DebounceSt->IdleSt	163	Covered	T26,T182,T83
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T43,T38,T44
IdleSt->DebounceSt	148	Covered	T26,T43,T38
StableSt->IdleSt	206	Covered	T38,T44,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T43,T38
0	1	Covered	T26,T43,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T43,T38,T44
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T43,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T38,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T182
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T43,T38
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T43,T38,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T44,T40
StableSt	-	-	-	-	-	-	0	Covered	T43,T38,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	53	0	0
CntIncr_A	5590926	1206	0	0
CntNoWrap_A	5590926	5130955	0	0
DetectStDropOut_A	5590926	0	0	0
DetectedOut_A	5590926	1753	0	0
DetectedPulseOut_A	5590926	25	0	0
DisabledIdleSt_A	5590926	5083154	0	0
DisabledNoDetection_A	5590926	5085085	0	0
EnterDebounceSt_A	5590926	28	0	0
EnterDetectSt_A	5590926	25	0	0
EnterStableSt_A	5590926	25	0	0
PulseIsPulse_A	5590926	25	0	0
StayInStableSt	5590926	1716	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	53	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T38	0	4	0	0
T40	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T47	0	2	0	0
T49	0	2	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T180	0	4	0	0
T186	0	2	0	0
T187	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1206	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	16	0	0
T29	616	0	0	0
T38	0	72	0	0
T40	0	42	0	0
T43	0	17	0	0
T44	0	72	0	0
T47	0	12	0	0
T49	0	50	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T180	0	24	0	0
T186	0	72	0	0
T187	0	27	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130955	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1753	0	0
T38	0	85	0	0
T40	0	154	0	0
T43	582	47	0	0
T44	0	79	0	0
T47	0	54	0	0
T49	0	37	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T180	0	52	0	0
T186	0	132	0	0
T187	0	92	0	0
T188	0	121	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T38	0	2	0	0
T40	0	1	0	0
T43	582	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T180	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5083154	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5085085	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	28	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T38	0	2	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T180	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T38	0	2	0	0
T40	0	1	0	0
T43	582	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T180	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T38	0	2	0	0
T40	0	1	0	0
T43	582	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T180	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T38	0	2	0	0
T40	0	1	0	0
T43	582	1	0	0
T44	0	2	0	0
T47	0	1	0	0
T49	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T180	0	2	0	0
T186	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1716	0	0
T38	0	82	0	0
T40	0	153	0	0
T43	582	45	0	0
T44	0	76	0	0
T47	0	52	0	0
T49	0	36	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T180	0	49	0	0
T186	0	130	0	0
T187	0	91	0	0
T188	0	119	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	13	0	0
T38	2574	1	0	0
T40	0	1	0	0
T44	1511	1	0	0
T49	0	1	0	0
T98	5269	0	0	0
T138	527	0	0	0
T139	485	0	0	0
T180	0	1	0	0
T183	0	1	0	0
T187	0	1	0	0
T188	0	2	0	0
T192	0	1	0	0
T193	0	1	0	0
T194	655	0	0	0
T195	502	0	0	0
T196	526	0	0	0
T197	2104	0	0	0
T198	507	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T26,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T26,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T26,T12
1	0	Covered	T4,T22,T1
1	1	Covered	T7,T26,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T41
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T41
0	1	Covered	T12,T41,T46
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T12,T41
1	-	Covered	T12,T41,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T26,T12
DetectSt	168	Covered	T7,T12,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T12,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T12,T41
DebounceSt->IdleSt	163	Covered	T26,T44,T42
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T12,T41
IdleSt->DebounceSt	148	Covered	T7,T26,T12
StableSt->IdleSt	206	Covered	T12,T41,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T26,T12
0	1	Covered	T7,T26,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T26,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T12,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T44,T42,T199
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T26,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T12,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T41,T46
StableSt	-	-	-	-	-	-	0	Covered	T7,T12,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	93	0	0
CntIncr_A	5590926	2429	0	0
CntNoWrap_A	5590926	5130915	0	0
DetectStDropOut_A	5590926	0	0	0
DetectedOut_A	5590926	3280	0	0
DetectedPulseOut_A	5590926	43	0	0
DisabledIdleSt_A	5590926	5119822	0	0
DisabledNoDetection_A	5590926	5121755	0	0
EnterDebounceSt_A	5590926	50	0	0
EnterDetectSt_A	5590926	43	0	0
EnterStableSt_A	5590926	43	0	0
PulseIsPulse_A	5590926	43	0	0
StayInStableSt	5590926	3220	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5590926	1782	0	0
gen_low_level_sva.LowLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	93	0	0
T7	697	2	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	4	0	0
T26	6185	1	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T41	0	4	0	0
T42	0	5	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	2	0	0
T49	0	10	0	0
T60	416	0	0	0
T73	524	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	2429	0	0
T7	697	41	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	158	0	0
T26	6185	18	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T41	0	92	0	0
T42	0	234	0	0
T44	0	72	0	0
T45	0	63	0	0
T46	0	94	0	0
T48	0	71	0	0
T49	0	281	0	0
T60	416	0	0	0
T73	524	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130915	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	3280	0	0
T7	697	246	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	56	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T41	0	140	0	0
T42	0	87	0	0
T45	0	147	0	0
T46	0	397	0	0
T48	0	114	0	0
T49	0	320	0	0
T60	416	0	0	0
T73	524	0	0	0
T170	0	43	0	0
T200	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	43	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	2	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	5	0	0
T60	416	0	0	0
T73	524	0	0	0
T170	0	1	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5119822	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5121755	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	50	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	2	0	0
T26	6185	1	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T41	0	2	0	0
T42	0	3	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	5	0	0
T60	416	0	0	0
T73	524	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	43	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	2	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	5	0	0
T60	416	0	0	0
T73	524	0	0	0
T170	0	1	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	43	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	2	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	5	0	0
T60	416	0	0	0
T73	524	0	0	0
T170	0	1	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	43	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	2	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T41	0	2	0	0
T42	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	5	0	0
T60	416	0	0	0
T73	524	0	0	0
T170	0	1	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	3220	0	0
T7	697	244	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	54	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T41	0	137	0	0
T42	0	84	0	0
T45	0	145	0	0
T46	0	396	0	0
T48	0	112	0	0
T49	0	312	0	0
T60	416	0	0	0
T73	524	0	0	0
T170	0	41	0	0
T200	0	7	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1782	0	0
T1	33661	0	0	0
T2	1891	0	0	0
T4	526	6	0	0
T5	627	0	0	0
T6	888	0	0	0
T7	0	1	0	0
T14	497	4	0	0
T15	430	1	0	0
T16	442	3	0	0
T17	524	6	0	0
T18	0	2	0	0
T20	0	2	0	0
T21	0	2	0	0
T22	1188	0	0	0
T28	0	8	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	26	0	0
T12	864	2	0	0
T13	9956	0	0	0
T27	492	0	0	0
T41	0	1	0	0
T42	0	1	0	0
T46	0	1	0	0
T49	0	2	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T153	0	1	0	0
T180	0	2	0	0
T181	869	0	0	0
T186	0	1	0	0
T187	0	1	0	0
T200	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T41,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T41,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T41,T43,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T41,T43
1	0	Covered	T4,T6,T1
1	1	Covered	T26,T41,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T38,T48
0	1	Covered	T41
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T38,T48
0	1	Covered	T43,T46,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T38,T48
1	-	Covered	T43,T46,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T41,T43
DetectSt	168	Covered	T41,T43,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T43,T38,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T41,T43,T38
DebounceSt->IdleSt	163	Covered	T26,T83
DetectSt->IdleSt	186	Covered	T41
DetectSt->StableSt	191	Covered	T43,T38,T48
IdleSt->DebounceSt	148	Covered	T26,T41,T43
StableSt->IdleSt	206	Covered	T43,T38,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T41,T43
0	1	Covered	T26,T41,T43
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T41,T43,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T41,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T41,T43,T38
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T41,T43
DetectSt	-	-	-	-	1	-	-	Covered	T41
DetectSt	-	-	-	-	0	1	-	Covered	T43,T38,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T46,T39
StableSt	-	-	-	-	-	-	0	Covered	T43,T38,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	96	0	0
CntIncr_A	5590926	2760	0	0
CntNoWrap_A	5590926	5130912	0	0
DetectStDropOut_A	5590926	1	0	0
DetectedOut_A	5590926	4646	0	0
DetectedPulseOut_A	5590926	46	0	0
DisabledIdleSt_A	5590926	5117096	0	0
DisabledNoDetection_A	5590926	5119024	0	0
EnterDebounceSt_A	5590926	49	0	0
EnterDetectSt_A	5590926	47	0	0
EnterStableSt_A	5590926	46	0	0
PulseIsPulse_A	5590926	46	0	0
StayInStableSt	5590926	4582	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	28	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	96	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T38	0	2	0	0
T39	0	4	0	0
T40	0	4	0	0
T41	0	2	0	0
T42	0	2	0	0
T43	0	2	0	0
T46	0	4	0	0
T47	0	2	0	0
T48	0	2	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	2760	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	17	0	0
T29	616	0	0	0
T38	0	36	0	0
T39	0	98	0	0
T40	0	84	0	0
T41	0	46	0	0
T42	0	78	0	0
T43	0	17	0	0
T46	0	188	0	0
T47	0	12	0	0
T48	0	71	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130912	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1	0	0
T37	31494	0	0	0
T41	2206	1	0	0
T55	692	0	0	0
T56	617	0	0	0
T63	1204	0	0	0
T64	19594	0	0	0
T78	22950	0	0	0
T79	16027	0	0	0
T133	787	0	0	0
T134	18966	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4646	0	0
T38	0	42	0	0
T39	0	91	0	0
T40	0	210	0	0
T42	0	599	0	0
T43	582	92	0	0
T45	0	180	0	0
T46	0	208	0	0
T47	0	53	0	0
T48	0	42	0	0
T49	0	167	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	46	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	582	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	3	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5117096	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5119024	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	49	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	47	0	0
T37	31494	0	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T41	2206	1	0	0
T42	0	1	0	0
T43	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T55	692	0	0	0
T56	617	0	0	0
T63	1204	0	0	0
T64	19594	0	0	0
T78	22950	0	0	0
T79	16027	0	0	0
T133	787	0	0	0
T134	18966	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	46	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	582	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	3	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	46	0	0
T38	0	1	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	1	0	0
T43	582	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	3	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4582	0	0
T38	0	40	0	0
T39	0	88	0	0
T40	0	207	0	0
T42	0	597	0	0
T43	582	91	0	0
T45	0	177	0	0
T46	0	206	0	0
T47	0	52	0	0
T48	0	40	0	0
T49	0	163	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	28	0	0
T39	0	1	0	0
T40	0	1	0	0
T43	582	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T168	0	2	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T26,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T26,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T26,T12
1	0	Covered	T4,T6,T22
1	1	Covered	T7,T26,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T12,T41
0	1	Covered	T201
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T41,T39
0	1	Covered	T12,T39,T168
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T41,T39
1	-	Covered	T12,T39,T168

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T26,T12
DetectSt	168	Covered	T7,T12,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T12,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T12,T41
DebounceSt->IdleSt	163	Covered	T26,T182,T148
DetectSt->IdleSt	186	Covered	T201
DetectSt->StableSt	191	Covered	T7,T12,T41
IdleSt->DebounceSt	148	Covered	T7,T26,T12
StableSt->IdleSt	206	Covered	T12,T41,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T26,T12
0	1	Covered	T7,T26,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T26,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T12,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T182,T148
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T26,T12
DetectSt	-	-	-	-	1	-	-	Covered	T201
DetectSt	-	-	-	-	0	1	-	Covered	T7,T12,T41
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T12,T39,T168
StableSt	-	-	-	-	-	-	0	Covered	T7,T41,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	54	0	0
CntIncr_A	5590926	1473	0	0
CntNoWrap_A	5590926	5130954	0	0
DetectStDropOut_A	5590926	1	0	0
DetectedOut_A	5590926	1932	0	0
DetectedPulseOut_A	5590926	24	0	0
DisabledIdleSt_A	5590926	5080582	0	0
DisabledNoDetection_A	5590926	5082511	0	0
EnterDebounceSt_A	5590926	29	0	0
EnterDetectSt_A	5590926	25	0	0
EnterStableSt_A	5590926	24	0	0
PulseIsPulse_A	5590926	24	0	0
StayInStableSt	5590926	1894	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5590926	5349	0	0
gen_low_level_sva.LowLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	54	0	0
T7	697	2	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	2	0	0
T26	6185	1	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T39	0	2	0	0
T41	0	2	0	0
T60	416	0	0	0
T73	524	0	0	0
T151	0	2	0	0
T168	0	6	0	0
T180	0	4	0	0
T186	0	2	0	0
T188	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1473	0	0
T7	697	41	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	79	0	0
T26	6185	16	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T39	0	49	0	0
T41	0	46	0	0
T60	416	0	0	0
T73	524	0	0	0
T151	0	99	0	0
T168	0	189	0	0
T180	0	24	0	0
T186	0	72	0	0
T188	0	94	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130954	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1	0	0
T201	770	1	0	0
T202	503	0	0	0
T203	1001	0	0	0
T204	20014	0	0	0
T205	12972	0	0	0
T206	423	0	0	0
T207	402	0	0	0
T208	502	0	0	0
T209	445	0	0	0
T210	504	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1932	0	0
T7	697	42	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	1	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T39	0	40	0	0
T41	0	56	0	0
T60	416	0	0	0
T73	524	0	0	0
T151	0	141	0	0
T168	0	408	0	0
T180	0	53	0	0
T186	0	42	0	0
T188	0	44	0	0
T211	0	155	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	24	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	1	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T60	416	0	0	0
T73	524	0	0	0
T151	0	1	0	0
T168	0	3	0	0
T180	0	2	0	0
T186	0	1	0	0
T188	0	1	0	0
T211	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5080582	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5082511	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	29	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	1	0	0
T26	6185	1	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T60	416	0	0	0
T73	524	0	0	0
T151	0	1	0	0
T168	0	3	0	0
T180	0	2	0	0
T186	0	1	0	0
T188	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	1	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T60	416	0	0	0
T73	524	0	0	0
T151	0	1	0	0
T168	0	3	0	0
T180	0	2	0	0
T186	0	1	0	0
T188	0	1	0	0
T211	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	24	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	1	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T60	416	0	0	0
T73	524	0	0	0
T151	0	1	0	0
T168	0	3	0	0
T180	0	2	0	0
T186	0	1	0	0
T188	0	1	0	0
T211	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	24	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	1	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T39	0	1	0	0
T41	0	1	0	0
T60	416	0	0	0
T73	524	0	0	0
T151	0	1	0	0
T168	0	3	0	0
T180	0	2	0	0
T186	0	1	0	0
T188	0	1	0	0
T211	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1894	0	0
T7	697	40	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T39	0	39	0	0
T41	0	54	0	0
T60	416	0	0	0
T73	524	0	0	0
T151	0	140	0	0
T157	0	87	0	0
T168	0	404	0	0
T180	0	50	0	0
T186	0	40	0	0
T188	0	43	0	0
T211	0	153	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5349	0	0
T1	33661	13	0	0
T2	1891	13	0	0
T4	526	2	0	0
T5	627	0	0	0
T6	888	3	0	0
T14	497	5	0	0
T15	430	2	0	0
T16	442	4	0	0
T17	524	7	0	0
T18	0	1	0	0
T19	0	6	0	0
T22	1188	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	10	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	1	0	0
T157	0	1	0	0
T168	0	2	0	0
T180	0	1	0	0
T181	869	0	0	0
T188	0	1	0	0
T193	0	1	0	0
T212	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T14
1	1	Covered	T4,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T12,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T12,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T43,T44,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T12,T43
1	0	Covered	T4,T1,T14
1	1	Covered	T26,T12,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T47
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T47
0	1	Covered	T43,T44,T47
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T44,T47
1	-	Covered	T43,T44,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T12,T43
DetectSt	168	Covered	T43,T44,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T43,T44,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T44,T47
DebounceSt->IdleSt	163	Covered	T26,T12,T83
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T43,T44,T47
IdleSt->DebounceSt	148	Covered	T26,T12,T43
StableSt->IdleSt	206	Covered	T43,T44,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T12,T43
0	1	Covered	T26,T12,T43
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T43,T44,T47
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T12,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T44,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T12
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T12,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T43,T44,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T44,T47
StableSt	-	-	-	-	-	-	0	Covered	T43,T44,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	99	0	0
CntIncr_A	5590926	2397	0	0
CntNoWrap_A	5590926	5130909	0	0
DetectStDropOut_A	5590926	0	0	0
DetectedOut_A	5590926	4327	0	0
DetectedPulseOut_A	5590926	48	0	0
DisabledIdleSt_A	5590926	5118603	0	0
DisabledNoDetection_A	5590926	5120532	0	0
EnterDebounceSt_A	5590926	51	0	0
EnterDetectSt_A	5590926	48	0	0
EnterStableSt_A	5590926	48	0	0
PulseIsPulse_A	5590926	48	0	0
StayInStableSt	5590926	4256	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	99	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	1	0	0
T26	6185	1	0	0
T29	616	0	0	0
T40	0	4	0	0
T43	0	4	0	0
T44	0	2	0	0
T47	0	4	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	2	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	2397	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	79	0	0
T26	6185	17	0	0
T29	616	0	0	0
T40	0	84	0	0
T43	0	34	0	0
T44	0	36	0	0
T47	0	24	0	0
T49	0	132	0	0
T50	0	75	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	99	0	0
T200	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130909	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4327	0	0
T40	0	239	0	0
T43	582	90	0	0
T44	0	42	0	0
T47	0	106	0	0
T49	0	497	0	0
T50	0	60	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T151	0	141	0	0
T153	0	74	0	0
T186	0	146	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T200	0	61	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	48	0	0
T40	0	2	0	0
T43	582	2	0	0
T44	0	1	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T186	0	2	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T200	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5118603	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5120532	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	51	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	1	0	0
T26	6185	1	0	0
T29	616	0	0	0
T40	0	2	0	0
T43	0	2	0	0
T44	0	1	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	1	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	48	0	0
T40	0	2	0	0
T43	582	2	0	0
T44	0	1	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T186	0	2	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T200	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	48	0	0
T40	0	2	0	0
T43	582	2	0	0
T44	0	1	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T186	0	2	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T200	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	48	0	0
T40	0	2	0	0
T43	582	2	0	0
T44	0	1	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T186	0	2	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T200	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4256	0	0
T40	0	236	0	0
T43	582	87	0	0
T44	0	41	0	0
T47	0	103	0	0
T49	0	494	0	0
T50	0	58	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T151	0	140	0	0
T153	0	73	0	0
T186	0	143	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T200	0	59	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T40	0	1	0	0
T43	582	1	0	0
T44	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T154	0	1	0	0
T180	0	1	0	0
T186	0	1	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T14
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T14
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T12,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T12,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T43,T38

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T12,T43
1	0	Covered	T4,T22,T1
1	1	Covered	T26,T12,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T43,T38
0	1	Covered	T85,T184
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T38,T44
0	1	Covered	T43,T38,T40
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T38,T44
1	-	Covered	T43,T38,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T12,T43
DetectSt	168	Covered	T12,T43,T38
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T43,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T43,T38
DebounceSt->IdleSt	163	Covered	T26,T213,T83
DetectSt->IdleSt	186	Covered	T85,T184
DetectSt->StableSt	191	Covered	T12,T43,T38
IdleSt->DebounceSt	148	Covered	T26,T12,T43
StableSt->IdleSt	206	Covered	T43,T38,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T12,T43
0	1	Covered	T26,T12,T43
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T43,T38
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T12,T43
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T43,T38
DebounceSt	-	0	1	0	-	-	-	Covered	T213,T212
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T12,T43
DetectSt	-	-	-	-	1	-	-	Covered	T85,T184
DetectSt	-	-	-	-	0	1	-	Covered	T12,T43,T38
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T38,T40
StableSt	-	-	-	-	-	-	0	Covered	T12,T38,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	56	0	0
CntIncr_A	5590926	1389	0	0
CntNoWrap_A	5590926	5130952	0	0
DetectStDropOut_A	5590926	2	0	0
DetectedOut_A	5590926	1725	0	0
DetectedPulseOut_A	5590926	24	0	0
DisabledIdleSt_A	5590926	5118527	0	0
DisabledNoDetection_A	5590926	5120458	0	0
EnterDebounceSt_A	5590926	30	0	0
EnterDetectSt_A	5590926	26	0	0
EnterStableSt_A	5590926	24	0	0
PulseIsPulse_A	5590926	24	0	0
StayInStableSt	5590926	1689	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5590926	5074	0	0
gen_low_level_sva.LowLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	56	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	2	0	0
T26	6185	1	0	0
T29	616	0	0	0
T38	0	2	0	0
T40	0	2	0	0
T43	0	2	0	0
T44	0	2	0	0
T49	0	4	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	2	0	0
T168	0	2	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1389	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	79	0	0
T26	6185	18	0	0
T29	616	0	0	0
T38	0	36	0	0
T40	0	42	0	0
T43	0	17	0	0
T44	0	36	0	0
T49	0	67	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	99	0	0
T168	0	55	0	0
T170	0	24	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130952	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	2	0	0
T85	865	1	0	0
T182	774	0	0	0
T184	0	1	0	0
T193	598	0	0	0
T214	524	0	0	0
T215	502	0	0	0
T216	38388	0	0	0
T217	25227	0	0	0
T218	505	0	0	0
T219	526	0	0	0
T220	690	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1725	0	0
T12	864	41	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	104	0	0
T40	0	87	0	0
T43	0	1	0	0
T44	0	56	0	0
T49	0	91	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	381	0	0
T153	0	71	0	0
T168	0	42	0	0
T170	0	44	0	0
T181	869	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	24	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	0	2	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T181	869	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5118527	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5120458	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	30	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	1	0	0
T26	6185	1	0	0
T29	616	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	0	2	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	26	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	0	2	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T181	869	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	24	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	0	2	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T181	869	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	24	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	0	1	0	0
T44	0	1	0	0
T49	0	2	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T181	869	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1689	0	0
T12	864	39	0	0
T13	9956	0	0	0
T27	492	0	0	0
T38	0	103	0	0
T40	0	86	0	0
T44	0	54	0	0
T49	0	87	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T151	0	379	0	0
T153	0	69	0	0
T168	0	41	0	0
T170	0	42	0	0
T181	869	0	0	0
T187	0	87	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5074	0	0
T1	33661	13	0	0
T2	1891	0	0	0
T4	526	5	0	0
T5	627	0	0	0
T6	888	0	0	0
T14	497	8	0	0
T15	430	2	0	0
T16	442	5	0	0
T17	524	5	0	0
T18	0	1	0	0
T19	0	9	0	0
T20	0	1	0	0
T21	0	9	0	0
T22	1188	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	12	0	0
T38	0	1	0	0
T40	0	1	0	0
T43	582	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T148	0	2	0	0
T154	0	1	0	0
T168	0	1	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T211	0	1	0	0
T213	0	1	0	0
T221	0	1	0	0
T222	0	1	0	0