Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.26	93.48	85.71		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.10	100.00	90.48		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
96.66	97.83	90.48		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T14
1	1	Covered	T4,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T12,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T12,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T46,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T12,T48
1	0	Covered	T4,T1,T14
1	1	Covered	T26,T12,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T46,T39
0	1	Covered	T47,T40
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T46,T39
0	1	Covered	T42,T45,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T46,T39
1	-	Covered	T42,T45,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T12,T46
DetectSt	168	Covered	T12,T46,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T46,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T46,T39
DebounceSt->IdleSt	163	Covered	T26,T157,T83
DetectSt->IdleSt	186	Covered	T47,T40
DetectSt->StableSt	191	Covered	T12,T46,T39
IdleSt->DebounceSt	148	Covered	T26,T12,T46
StableSt->IdleSt	206	Covered	T42,T45,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T12,T46
0	1	Covered	T26,T12,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T46,T39
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T12,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T46,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T157,T108,T223
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T12,T46
DetectSt	-	-	-	-	1	-	-	Covered	T47,T40
DetectSt	-	-	-	-	0	1	-	Covered	T12,T46,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T45,T49
StableSt	-	-	-	-	-	-	0	Covered	T12,T46,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	108	0	0
CntIncr_A	5590926	2796	0	0
CntNoWrap_A	5590926	5130900	0	0
DetectStDropOut_A	5590926	2	0	0
DetectedOut_A	5590926	4891	0	0
DetectedPulseOut_A	5590926	49	0	0
DisabledIdleSt_A	5590926	5117368	0	0
DisabledNoDetection_A	5590926	5119293	0	0
EnterDebounceSt_A	5590926	57	0	0
EnterDetectSt_A	5590926	51	0	0
EnterStableSt_A	5590926	49	0	0
PulseIsPulse_A	5590926	49	0	0
StayInStableSt	5590926	4818	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	25	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	108	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	2	0	0
T26	6185	1	0	0
T29	616	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T42	0	4	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	4	0	0
T49	0	4	0	0
T50	0	2	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	2796	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	79	0	0
T26	6185	17	0	0
T29	616	0	0	0
T39	0	49	0	0
T40	0	84	0	0
T42	0	156	0	0
T45	0	126	0	0
T46	0	94	0	0
T47	0	24	0	0
T49	0	99	0	0
T50	0	75	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130900	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	2	0	0
T40	864	1	0	0
T47	558	1	0	0
T131	21334	0	0	0
T159	502	0	0	0
T160	403	0	0	0
T161	10118	0	0	0
T162	635	0	0	0
T163	422	0	0	0
T164	503	0	0	0
T165	407	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4891	0	0
T12	864	376	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	327	0	0
T40	0	54	0	0
T42	0	282	0	0
T45	0	181	0	0
T46	0	597	0	0
T47	0	71	0	0
T49	0	187	0	0
T50	0	59	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T168	0	341	0	0
T181	869	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	49	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T168	0	2	0	0
T181	869	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5117368	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5119293	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	57	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	1	0	0
T26	6185	1	0	0
T29	616	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	51	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T42	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T168	0	2	0	0
T181	869	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	49	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T168	0	2	0	0
T181	869	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	49	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	2	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T168	0	2	0	0
T181	869	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4818	0	0
T12	864	374	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	325	0	0
T40	0	52	0	0
T42	0	279	0	0
T45	0	178	0	0
T46	0	595	0	0
T47	0	69	0	0
T49	0	184	0	0
T50	0	57	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T168	0	338	0	0
T181	869	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T42	1086	1	0	0
T45	0	1	0	0
T47	558	0	0	0
T49	0	1	0	0
T131	21334	0	0	0
T151	0	2	0	0
T153	0	1	0	0
T154	0	1	0	0
T155	0	1	0	0
T159	502	0	0	0
T160	403	0	0	0
T161	10118	0	0	0
T162	635	0	0	0
T163	422	0	0	0
T164	503	0	0	0
T168	0	1	0	0
T185	422	0	0	0
T200	0	1	0	0
T213	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	0	1
187	0	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	18	85.71
Logical	21	18	85.71
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T14
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T14
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T43,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T43,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T43,T44,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T12,T43
1	0	Covered	T4,T22,T1
1	1	Covered	T26,T43,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T45,T49
0	1	Covered	T43,T45,T168
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T45,T49
1	-	Covered	T43,T45,T168

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T43,T44
DetectSt	168	Covered	T43,T44,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T43,T44,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T44,T45
DebounceSt->IdleSt	163	Covered	T26,T83
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T43,T44,T45
IdleSt->DebounceSt	148	Covered	T26,T43,T44
StableSt->IdleSt	206	Covered	T43,T44,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T43,T44
0	1	Covered	T26,T43,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T43,T44,T45
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T43,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T44,T45
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T43,T44
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T43,T44,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T45,T168
StableSt	-	-	-	-	-	-	0	Covered	T44,T45,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	52	0	0
CntIncr_A	5590926	1285	0	0
CntNoWrap_A	5590926	5130956	0	0
DetectStDropOut_A	5590926	0	0	0
DetectedOut_A	5590926	1482	0	0
DetectedPulseOut_A	5590926	25	0	0
DisabledIdleSt_A	5590926	5119998	0	0
DisabledNoDetection_A	5590926	5121929	0	0
EnterDebounceSt_A	5590926	27	0	0
EnterDetectSt_A	5590926	25	0	0
EnterStableSt_A	5590926	25	0	0
PulseIsPulse_A	5590926	25	0	0
StayInStableSt	5590926	1444	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5590926	5035	0	0
gen_low_level_sva.LowLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	52	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T43	0	2	0	0
T44	0	2	0	0
T45	0	2	0	0
T49	0	2	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T153	0	2	0	0
T154	0	2	0	0
T168	0	4	0	0
T188	0	2	0	0
T200	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1285	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	18	0	0
T29	616	0	0	0
T43	0	17	0	0
T44	0	36	0	0
T45	0	63	0	0
T49	0	82	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T153	0	18	0	0
T154	0	55	0	0
T168	0	134	0	0
T188	0	94	0	0
T200	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130956	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1482	0	0
T43	582	1	0	0
T44	0	56	0	0
T45	0	42	0	0
T49	0	176	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T153	0	42	0	0
T154	0	51	0	0
T168	0	86	0	0
T188	0	44	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T200	0	37	0	0
T211	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T43	582	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T49	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T153	0	1	0	0
T154	0	1	0	0
T168	0	2	0	0
T188	0	1	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T200	0	1	0	0
T211	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5119998	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5121929	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	27	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T43	0	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T49	0	1	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T153	0	1	0	0
T154	0	1	0	0
T168	0	2	0	0
T188	0	1	0	0
T200	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T43	582	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T49	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T153	0	1	0	0
T154	0	1	0	0
T168	0	2	0	0
T188	0	1	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T200	0	1	0	0
T211	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T43	582	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T49	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T153	0	1	0	0
T154	0	1	0	0
T168	0	2	0	0
T188	0	1	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T200	0	1	0	0
T211	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T43	582	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T49	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T153	0	1	0	0
T154	0	1	0	0
T168	0	2	0	0
T188	0	1	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T200	0	1	0	0
T211	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1444	0	0
T44	1511	54	0	0
T45	0	41	0	0
T49	0	174	0	0
T81	1470	0	0	0
T98	5269	0	0	0
T138	527	0	0	0
T139	485	0	0	0
T153	0	40	0	0
T154	0	49	0	0
T157	0	346	0	0
T168	0	84	0	0
T188	0	43	0	0
T194	655	0	0	0
T195	502	0	0	0
T196	526	0	0	0
T197	2104	0	0	0
T198	507	0	0	0
T200	0	35	0	0
T211	0	55	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5035	0	0
T1	33661	12	0	0
T2	1891	0	0	0
T4	526	3	0	0
T5	627	0	0	0
T6	888	0	0	0
T14	497	7	0	0
T15	430	3	0	0
T16	442	5	0	0
T17	524	5	0	0
T18	0	1	0	0
T19	0	12	0	0
T20	0	3	0	0
T21	0	6	0	0
T22	1188	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	12	0	0
T43	582	1	0	0
T45	0	1	0	0
T66	883	0	0	0
T69	494	0	0	0
T70	489	0	0	0
T80	1868	0	0	0
T85	0	1	0	0
T96	5266	0	0	0
T97	5816	0	0	0
T148	0	1	0	0
T157	0	1	0	0
T168	0	2	0	0
T188	0	1	0	0
T189	421	0	0	0
T190	409	0	0	0
T191	524	0	0	0
T211	0	2	0	0
T221	0	1	0	0
T223	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T1,T14

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T1,T14
1	1	Covered	T4,T1,T14

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T12,T41

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T12,T41

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T12,T41,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T12,T41
1	0	Covered	T4,T1,T14
1	1	Covered	T26,T12,T41

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T12,T41,T43
0	1	Covered	T155
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T12,T41,T43
0	1	Covered	T41,T44,T39
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T12,T41,T43
1	-	Covered	T41,T44,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T12,T41
DetectSt	168	Covered	T12,T41,T43
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T12,T41,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T12,T41,T43
DebounceSt->IdleSt	163	Covered	T26,T83,T184
DetectSt->IdleSt	186	Covered	T155
DetectSt->StableSt	191	Covered	T12,T41,T43
IdleSt->DebounceSt	148	Covered	T26,T12,T41
StableSt->IdleSt	206	Covered	T41,T44,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T12,T41
0	1	Covered	T26,T12,T41
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T12,T41,T43
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T12,T41
IdleSt	0	-	-	-	-	-	-	Covered	T4,T1,T14
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T12,T41,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T184,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T12,T41
DetectSt	-	-	-	-	1	-	-	Covered	T155
DetectSt	-	-	-	-	0	1	-	Covered	T12,T41,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T41,T44,T39
StableSt	-	-	-	-	-	-	0	Covered	T12,T41,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	96	0	0
CntIncr_A	5590926	20169	0	0
CntNoWrap_A	5590926	5130912	0	0
DetectStDropOut_A	5590926	1	0	0
DetectedOut_A	5590926	3336	0	0
DetectedPulseOut_A	5590926	45	0	0
DisabledIdleSt_A	5590926	5084243	0	0
DisabledNoDetection_A	5590926	5086177	0	0
EnterDebounceSt_A	5590926	50	0	0
EnterDetectSt_A	5590926	46	0	0
EnterStableSt_A	5590926	45	0	0
PulseIsPulse_A	5590926	45	0	0
StayInStableSt	5590926	3269	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	96	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	2	0	0
T26	6185	1	0	0
T29	616	0	0	0
T39	0	2	0	0
T40	0	4	0	0
T41	0	2	0	0
T43	0	2	0	0
T44	0	4	0	0
T45	0	2	0	0
T49	0	2	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T224	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	20169	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	79	0	0
T26	6185	17	0	0
T29	616	0	0	0
T39	0	49	0	0
T40	0	84	0	0
T41	0	46	0	0
T43	0	17	0	0
T44	0	72	0	0
T45	0	63	0	0
T49	0	17	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T224	0	29	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130912	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1	0	0
T152	3287	0	0	0
T155	900	1	0	0
T188	1090	0	0	0
T225	1250	0	0	0
T226	19964	0	0	0
T227	524	0	0	0
T228	506	0	0	0
T229	922	0	0	0
T230	430	0	0	0
T231	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	3336	0	0
T12	864	40	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	131	0	0
T40	0	227	0	0
T41	0	39	0	0
T43	0	67	0	0
T44	0	87	0	0
T45	0	245	0	0
T49	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T170	0	44	0	0
T181	869	0	0	0
T224	0	2	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	45	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T49	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T170	0	1	0	0
T181	869	0	0	0
T224	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5084243	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5086177	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	50	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	1	0	0
T26	6185	1	0	0
T29	616	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T49	0	1	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T224	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	46	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T49	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T170	0	1	0	0
T181	869	0	0	0
T224	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	45	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T49	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T170	0	1	0	0
T181	869	0	0	0
T224	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	45	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	1	0	0
T40	0	2	0	0
T41	0	1	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	1	0	0
T49	0	1	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T170	0	1	0	0
T181	869	0	0	0
T224	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	3269	0	0
T12	864	38	0	0
T13	9956	0	0	0
T27	492	0	0	0
T39	0	130	0	0
T40	0	224	0	0
T41	0	38	0	0
T43	0	65	0	0
T44	0	84	0	0
T45	0	244	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T153	0	69	0	0
T170	0	42	0	0
T181	869	0	0	0
T224	0	1	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	23	0	0
T37	31494	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T41	2206	1	0	0
T44	0	1	0	0
T45	0	1	0	0
T49	0	1	0	0
T55	692	0	0	0
T56	617	0	0	0
T63	1204	0	0	0
T64	19594	0	0	0
T78	22950	0	0	0
T79	16027	0	0	0
T133	787	0	0	0
T134	18966	0	0	0
T180	0	2	0	0
T188	0	1	0	0
T211	0	1	0	0
T224	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T14
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T14
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T39,T42

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T39,T42

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T39,T42,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T12,T43
1	0	Covered	T4,T22,T1
1	1	Covered	T26,T39,T42

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T39,T42,T40
0	1	Covered	T86
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T39,T42,T40
0	1	Covered	T42,T40,T49
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T39,T42,T40
1	-	Covered	T42,T40,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T39,T42
DetectSt	168	Covered	T39,T42,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T39,T42,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T39,T42,T40
DebounceSt->IdleSt	163	Covered	T26,T83
DetectSt->IdleSt	186	Covered	T86
DetectSt->StableSt	191	Covered	T39,T42,T40
IdleSt->DebounceSt	148	Covered	T26,T39,T42
StableSt->IdleSt	206	Covered	T42,T40,T224

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T39,T42
0	1	Covered	T26,T39,T42
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T39,T42,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T39,T42
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T39,T42,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T39,T42
DetectSt	-	-	-	-	1	-	-	Covered	T86
DetectSt	-	-	-	-	0	1	-	Covered	T39,T42,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T42,T40,T49
StableSt	-	-	-	-	-	-	0	Covered	T39,T42,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	48	0	0
CntIncr_A	5590926	10155	0	0
CntNoWrap_A	5590926	5130960	0	0
DetectStDropOut_A	5590926	1	0	0
DetectedOut_A	5590926	1794	0	0
DetectedPulseOut_A	5590926	22	0	0
DisabledIdleSt_A	5590926	5083549	0	0
DisabledNoDetection_A	5590926	5085484	0	0
EnterDebounceSt_A	5590926	25	0	0
EnterDetectSt_A	5590926	23	0	0
EnterStableSt_A	5590926	22	0	0
PulseIsPulse_A	5590926	22	0	0
StayInStableSt	5590926	1761	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5590926	5114	0	0
gen_low_level_sva.LowLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	48	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T39	0	2	0	0
T40	0	2	0	0
T42	0	2	0	0
T49	0	4	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	2	0	0
T154	0	2	0	0
T168	0	6	0	0
T187	0	2	0	0
T224	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	10155	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	18	0	0
T29	616	0	0	0
T39	0	49	0	0
T40	0	42	0	0
T42	0	78	0	0
T49	0	99	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	99	0	0
T154	0	55	0	0
T168	0	189	0	0
T187	0	27	0	0
T224	0	29	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130960	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1	0	0
T86	37619	1	0	0
T171	490	0	0	0
T172	531	0	0	0
T173	1225	0	0	0
T174	445	0	0	0
T175	19976	0	0	0
T176	407	0	0	0
T177	524	0	0	0
T178	422	0	0	0
T179	1081	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1794	0	0
T39	786	49	0	0
T40	0	25	0	0
T42	0	71	0	0
T49	0	87	0	0
T151	0	46	0	0
T154	0	151	0	0
T168	0	315	0	0
T187	0	22	0	0
T188	0	216	0	0
T224	0	14	0	0
T232	2059	0	0	0
T233	41844	0	0	0
T234	495	0	0	0
T235	180449	0	0	0
T236	507	0	0	0
T237	523	0	0	0
T238	489	0	0	0
T239	905	0	0	0
T240	421	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	22	0	0
T39	786	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T49	0	2	0	0
T151	0	1	0	0
T154	0	1	0	0
T168	0	3	0	0
T187	0	1	0	0
T188	0	1	0	0
T224	0	1	0	0
T232	2059	0	0	0
T233	41844	0	0	0
T234	495	0	0	0
T235	180449	0	0	0
T236	507	0	0	0
T237	523	0	0	0
T238	489	0	0	0
T239	905	0	0	0
T240	421	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5083549	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5085484	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	25	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T39	0	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T49	0	2	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	1	0	0
T154	0	1	0	0
T168	0	3	0	0
T187	0	1	0	0
T224	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	23	0	0
T39	786	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T49	0	2	0	0
T151	0	1	0	0
T154	0	1	0	0
T168	0	3	0	0
T187	0	1	0	0
T188	0	1	0	0
T224	0	1	0	0
T232	2059	0	0	0
T233	41844	0	0	0
T234	495	0	0	0
T235	180449	0	0	0
T236	507	0	0	0
T237	523	0	0	0
T238	489	0	0	0
T239	905	0	0	0
T240	421	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	22	0	0
T39	786	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T49	0	2	0	0
T151	0	1	0	0
T154	0	1	0	0
T168	0	3	0	0
T187	0	1	0	0
T188	0	1	0	0
T224	0	1	0	0
T232	2059	0	0	0
T233	41844	0	0	0
T234	495	0	0	0
T235	180449	0	0	0
T236	507	0	0	0
T237	523	0	0	0
T238	489	0	0	0
T239	905	0	0	0
T240	421	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	22	0	0
T39	786	1	0	0
T40	0	1	0	0
T42	0	1	0	0
T49	0	2	0	0
T151	0	1	0	0
T154	0	1	0	0
T168	0	3	0	0
T187	0	1	0	0
T188	0	1	0	0
T224	0	1	0	0
T232	2059	0	0	0
T233	41844	0	0	0
T234	495	0	0	0
T235	180449	0	0	0
T236	507	0	0	0
T237	523	0	0	0
T238	489	0	0	0
T239	905	0	0	0
T240	421	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1761	0	0
T39	786	47	0	0
T40	0	24	0	0
T42	0	70	0	0
T49	0	84	0	0
T151	0	44	0	0
T154	0	149	0	0
T168	0	311	0	0
T187	0	21	0	0
T188	0	215	0	0
T224	0	12	0	0
T232	2059	0	0	0
T233	41844	0	0	0
T234	495	0	0	0
T235	180449	0	0	0
T236	507	0	0	0
T237	523	0	0	0
T238	489	0	0	0
T239	905	0	0	0
T240	421	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5114	0	0
T1	33661	14	0	0
T2	1891	0	0	0
T4	526	5	0	0
T5	627	0	0	0
T6	888	0	0	0
T14	497	9	0	0
T15	430	2	0	0
T16	442	4	0	0
T17	524	3	0	0
T18	0	1	0	0
T19	0	9	0	0
T20	0	2	0	0
T21	0	6	0	0
T22	1188	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	11	0	0
T40	0	1	0	0
T42	1086	1	0	0
T47	558	0	0	0
T49	0	1	0	0
T131	21334	0	0	0
T148	0	1	0	0
T158	0	1	0	0
T159	502	0	0	0
T160	403	0	0	0
T161	10118	0	0	0
T162	635	0	0	0
T163	422	0	0	0
T164	503	0	0	0
T168	0	2	0	0
T182	0	1	0	0
T185	422	0	0	0
T187	0	1	0	0
T188	0	1	0	0
T199	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T26,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T26,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T12,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T26,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T26,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T41,T43
0	1	Covered	T12,T184
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T41,T43
0	1	Covered	T7,T43,T38
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T41,T43
1	-	Covered	T7,T43,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T26,T12
DetectSt	168	Covered	T7,T12,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T41,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T12,T41
DebounceSt->IdleSt	163	Covered	T26,T211,T83
DetectSt->IdleSt	186	Covered	T12,T184
DetectSt->StableSt	191	Covered	T7,T41,T43
IdleSt->DebounceSt	148	Covered	T7,T26,T12
StableSt->IdleSt	206	Covered	T7,T41,T43

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T26,T12
0	1	Covered	T7,T26,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T7,T12,T41
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T26,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T12,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T211,T184,T241
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T26,T12
DetectSt	-	-	-	-	1	-	-	Covered	T12,T184
DetectSt	-	-	-	-	0	1	-	Covered	T7,T41,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T43,T38
StableSt	-	-	-	-	-	-	0	Covered	T7,T41,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	89	0	0
CntIncr_A	5590926	20615	0	0
CntNoWrap_A	5590926	5130919	0	0
DetectStDropOut_A	5590926	2	0	0
DetectedOut_A	5590926	14205	0	0
DetectedPulseOut_A	5590926	40	0	0
DisabledIdleSt_A	5590926	5078800	0	0
DisabledNoDetection_A	5590926	5080729	0	0
EnterDebounceSt_A	5590926	47	0	0
EnterDetectSt_A	5590926	42	0	0
EnterStableSt_A	5590926	40	0	0
PulseIsPulse_A	5590926	40	0	0
StayInStableSt	5590926	14146	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	21	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	89	0	0
T7	697	2	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	2	0	0
T26	6185	1	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T38	0	4	0	0
T41	0	2	0	0
T42	0	4	0	0
T43	0	4	0	0
T45	0	2	0	0
T46	0	2	0	0
T49	0	2	0	0
T60	416	0	0	0
T73	524	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	20615	0	0
T7	697	41	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	79	0	0
T26	6185	17	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T38	0	72	0	0
T41	0	46	0	0
T42	0	156	0	0
T43	0	34	0	0
T45	0	63	0	0
T46	0	94	0	0
T49	0	50	0	0
T60	416	0	0	0
T73	524	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130919	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	2	0	0
T12	864	1	0	0
T13	9956	0	0	0
T27	492	0	0	0
T62	881	0	0	0
T74	502	0	0	0
T75	522	0	0	0
T76	522	0	0	0
T77	505	0	0	0
T130	402	0	0	0
T181	869	0	0	0
T184	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	14205	0	0
T7	697	164	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T38	0	64	0	0
T41	0	104	0	0
T42	0	112	0	0
T43	0	57	0	0
T45	0	41	0	0
T46	0	29	0	0
T49	0	292	0	0
T50	0	164	0	0
T60	416	0	0	0
T73	524	0	0	0
T168	0	189	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	40	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T60	416	0	0	0
T73	524	0	0	0
T168	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5078800	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5080729	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	47	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	1	0	0
T26	6185	1	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T60	416	0	0	0
T73	524	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	42	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T12	0	1	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T60	416	0	0	0
T73	524	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	40	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T60	416	0	0	0
T73	524	0	0	0
T168	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	40	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T38	0	2	0	0
T41	0	1	0	0
T42	0	2	0	0
T43	0	2	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T60	416	0	0	0
T73	524	0	0	0
T168	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	14146	0	0
T7	697	163	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T38	0	61	0	0
T41	0	102	0	0
T42	0	110	0	0
T43	0	54	0	0
T45	0	40	0	0
T46	0	28	0	0
T49	0	290	0	0
T50	0	162	0	0
T60	416	0	0	0
T73	524	0	0	0
T168	0	188	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	21	0	0
T7	697	1	0	0
T8	13824	0	0	0
T9	858	0	0	0
T10	1596	0	0	0
T26	6185	0	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T38	0	1	0	0
T42	0	2	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T60	416	0	0	0
T73	524	0	0	0
T151	0	2	0	0
T168	0	1	0	0
T180	0	1	0	0
T186	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	45	97.83
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	31	96.88
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
58	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	0	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			==> MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T26,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T26,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T38,T39,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T26,T38,T48
1	0	Covered	T4,T5,T6
1	1	Covered	T26,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Covered	T223
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T38,T39,T40
0	1	Covered	T38,T40,T151
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T38,T39,T40
1	-	Covered	T38,T40,T151

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T26,T38,T39
DetectSt	168	Covered	T38,T39,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T38,T39,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T38,T39,T40
DebounceSt->IdleSt	163	Covered	T26,T83
DetectSt->IdleSt	186	Covered	T223
DetectSt->StableSt	191	Covered	T38,T39,T40
IdleSt->DebounceSt	148	Covered	T26,T38,T39
StableSt->IdleSt	206	Covered	T38,T40,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T26,T38,T39
0	1	Covered	T26,T38,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T38,T39,T40
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T26,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T38,T39,T40
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T26,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T223
DetectSt	-	-	-	-	0	1	-	Covered	T38,T39,T40
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T38,T40,T151
StableSt	-	-	-	-	-	-	0	Covered	T38,T39,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	50	0	0
CntIncr_A	5590926	1284	0	0
CntNoWrap_A	5590926	5130958	0	0
DetectStDropOut_A	5590926	1	0	0
DetectedOut_A	5590926	1717	0	0
DetectedPulseOut_A	5590926	23	0	0
DisabledIdleSt_A	5590926	5117851	0	0
DisabledNoDetection_A	5590926	5119779	0	0
EnterDebounceSt_A	5590926	26	0	0
EnterDetectSt_A	5590926	24	0	0
EnterStableSt_A	5590926	23	0	0
PulseIsPulse_A	5590926	23	0	0
StayInStableSt	5590926	1680	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5590926	5532	0	0
gen_low_level_sva.LowLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	50	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T38	0	2	0	0
T39	0	2	0	0
T40	0	4	0	0
T45	0	2	0	0
T49	0	2	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	4	0	0
T153	0	2	0	0
T168	0	2	0	0
T186	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1284	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	16	0	0
T29	616	0	0	0
T38	0	36	0	0
T39	0	49	0	0
T40	0	84	0	0
T45	0	63	0	0
T49	0	82	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	198	0	0
T153	0	18	0	0
T168	0	79	0	0
T186	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130958	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1	0	0
T223	985	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1717	0	0
T38	2574	64	0	0
T39	0	48	0	0
T40	0	99	0	0
T44	1511	0	0	0
T45	0	42	0	0
T49	0	44	0	0
T98	5269	0	0	0
T138	527	0	0	0
T139	485	0	0	0
T151	0	187	0	0
T153	0	10	0	0
T168	0	321	0	0
T186	0	131	0	0
T188	0	165	0	0
T194	655	0	0	0
T195	502	0	0	0
T196	526	0	0	0
T197	2104	0	0	0
T198	507	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	23	0	0
T38	2574	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T44	1511	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T98	5269	0	0	0
T138	527	0	0	0
T139	485	0	0	0
T151	0	2	0	0
T153	0	1	0	0
T168	0	1	0	0
T186	0	1	0	0
T188	0	1	0	0
T194	655	0	0	0
T195	502	0	0	0
T196	526	0	0	0
T197	2104	0	0	0
T198	507	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5117851	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5119779	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	26	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T12	864	0	0	0
T26	6185	1	0	0
T29	616	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T45	0	1	0	0
T49	0	1	0	0
T51	5272	0	0	0
T73	524	0	0	0
T74	502	0	0	0
T129	408	0	0	0
T130	402	0	0	0
T151	0	2	0	0
T153	0	1	0	0
T168	0	1	0	0
T186	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	24	0	0
T38	2574	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T44	1511	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T98	5269	0	0	0
T138	527	0	0	0
T139	485	0	0	0
T151	0	2	0	0
T153	0	1	0	0
T168	0	1	0	0
T186	0	1	0	0
T188	0	1	0	0
T194	655	0	0	0
T195	502	0	0	0
T196	526	0	0	0
T197	2104	0	0	0
T198	507	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	23	0	0
T38	2574	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T44	1511	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T98	5269	0	0	0
T138	527	0	0	0
T139	485	0	0	0
T151	0	2	0	0
T153	0	1	0	0
T168	0	1	0	0
T186	0	1	0	0
T188	0	1	0	0
T194	655	0	0	0
T195	502	0	0	0
T196	526	0	0	0
T197	2104	0	0	0
T198	507	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	23	0	0
T38	2574	1	0	0
T39	0	1	0	0
T40	0	2	0	0
T44	1511	0	0	0
T45	0	1	0	0
T49	0	1	0	0
T98	5269	0	0	0
T138	527	0	0	0
T139	485	0	0	0
T151	0	2	0	0
T153	0	1	0	0
T168	0	1	0	0
T186	0	1	0	0
T188	0	1	0	0
T194	655	0	0	0
T195	502	0	0	0
T196	526	0	0	0
T197	2104	0	0	0
T198	507	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1680	0	0
T38	2574	63	0	0
T39	0	46	0	0
T40	0	96	0	0
T44	1511	0	0	0
T45	0	40	0	0
T49	0	42	0	0
T98	5269	0	0	0
T138	527	0	0	0
T139	485	0	0	0
T151	0	184	0	0
T153	0	9	0	0
T168	0	319	0	0
T186	0	130	0	0
T188	0	163	0	0
T194	655	0	0	0
T195	502	0	0	0
T196	526	0	0	0
T197	2104	0	0	0
T198	507	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5532	0	0
T1	33661	7	0	0
T2	1891	13	0	0
T4	526	5	0	0
T5	627	3	0	0
T6	888	3	0	0
T14	497	7	0	0
T15	430	3	0	0
T16	442	5	0	0
T17	524	3	0	0
T18	0	1	0	0
T22	1188	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	9	0	0
T38	2574	1	0	0
T40	0	1	0	0
T44	1511	0	0	0
T98	5269	0	0	0
T138	527	0	0	0
T139	485	0	0	0
T151	0	1	0	0
T153	0	1	0	0
T182	0	1	0	0
T184	0	1	0	0
T186	0	1	0	0
T194	655	0	0	0
T195	502	0	0	0
T196	526	0	0	0
T197	2104	0	0	0
T198	507	0	0	0
T211	0	1	0	0
T221	0	1	0	0