Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T8,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T30
1	0	Covered	T3,T8,T26
1	1	Covered	T3,T8,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T30
0	1	Covered	T30,T26,T51
1	0	Covered	T54,T99,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T26
0	1	Covered	T3,T8,T26
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T26
1	-	Covered	T3,T8,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T30
DetectSt	168	Covered	T3,T8,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T30
DebounceSt->IdleSt	163	Covered	T30,T26,T242
DetectSt->IdleSt	186	Covered	T30,T26,T51
DetectSt->StableSt	191	Covered	T3,T8,T26
IdleSt->DebounceSt	148	Covered	T3,T8,T30
StableSt->IdleSt	206	Covered	T3,T8,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T8,T30
0	1	Covered	T3,T8,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T30
IdleSt	0	-	-	-	-	-	-	Covered	T3,T8,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T26,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T26,T51
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T26
DetectSt	-	-	-	-	0	0	-	Covered	T3,T8,T30
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T26
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T26
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	3032	0	0
CntIncr_A	5590926	104913	0	0
CntNoWrap_A	5590926	5127976	0	0
DetectStDropOut_A	5590926	512	0	0
DetectedOut_A	5590926	70904	0	0
DetectedPulseOut_A	5590926	835	0	0
DisabledIdleSt_A	5590926	4651491	0	0
DisabledNoDetection_A	5590926	4653255	0	0
EnterDebounceSt_A	5590926	1529	0	0
EnterDetectSt_A	5590926	1504	0	0
EnterStableSt_A	5590926	835	0	0
PulseIsPulse_A	5590926	835	0	0
StayInStableSt	5590926	69957	0	0
gen_high_event_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	723	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	3032	0	0
T3	19016	18	0	0
T7	697	0	0	0
T8	13824	30	0	0
T9	858	0	0	0
T11	0	44	0	0
T26	6185	15	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	26	0	0
T36	0	54	0	0
T51	0	52	0	0
T54	0	48	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	6	0	0
T79	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	104913	0	0
T3	19016	378	0	0
T7	697	0	0	0
T8	13824	1335	0	0
T9	858	0	0	0
T11	0	1716	0	0
T26	6185	216	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	772	0	0
T36	0	1134	0	0
T51	0	1383	0	0
T54	0	1960	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	231	0	0
T79	0	177	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5127976	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	512	0	0
T9	858	0	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T26	6185	1	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	10	0	0
T51	5272	26	0	0
T54	0	4	0	0
T73	524	0	0	0
T96	0	10	0	0
T97	0	28	0	0
T98	0	12	0	0
T99	0	19	0	0
T102	0	14	0	0
T103	0	10	0	0
T129	408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	70904	0	0
T3	19016	284	0	0
T7	697	0	0	0
T8	13824	1211	0	0
T9	858	0	0	0
T11	0	981	0	0
T26	6185	250	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	977	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	134	0	0
T79	0	158	0	0
T134	0	1347	0	0
T137	0	2302	0	0
T243	0	419	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	835	0	0
T3	19016	9	0	0
T7	697	0	0	0
T8	13824	15	0	0
T9	858	0	0	0
T11	0	22	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	27	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	3	0	0
T79	0	3	0	0
T134	0	6	0	0
T137	0	23	0	0
T243	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4651491	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4653255	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1529	0	0
T3	19016	9	0	0
T7	697	0	0	0
T8	13824	15	0	0
T9	858	0	0	0
T11	0	22	0	0
T26	6185	9	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	16	0	0
T36	0	27	0	0
T51	0	26	0	0
T54	0	24	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	3	0	0
T79	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1504	0	0
T3	19016	9	0	0
T7	697	0	0	0
T8	13824	15	0	0
T9	858	0	0	0
T11	0	22	0	0
T26	6185	6	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	10	0	0
T36	0	27	0	0
T51	0	26	0	0
T54	0	24	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	3	0	0
T79	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	835	0	0
T3	19016	9	0	0
T7	697	0	0	0
T8	13824	15	0	0
T9	858	0	0	0
T11	0	22	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	27	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	3	0	0
T79	0	3	0	0
T134	0	6	0	0
T137	0	23	0	0
T243	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	835	0	0
T3	19016	9	0	0
T7	697	0	0	0
T8	13824	15	0	0
T9	858	0	0	0
T11	0	22	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	27	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	3	0	0
T79	0	3	0	0
T134	0	6	0	0
T137	0	23	0	0
T243	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	69957	0	0
T3	19016	273	0	0
T7	697	0	0	0
T8	13824	1194	0	0
T9	858	0	0	0
T11	0	958	0	0
T26	6185	245	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	950	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	130	0	0
T79	0	154	0	0
T134	0	1337	0	0
T137	0	2278	0	0
T243	0	413	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	723	0	0
T3	19016	7	0	0
T7	697	0	0	0
T8	13824	13	0	0
T9	858	0	0	0
T11	0	21	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	27	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	2	0	0
T79	0	2	0	0
T134	0	2	0	0
T137	0	22	0	0
T243	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T22,T1,T19
1	1	Covered	T1,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T3
0	1	Covered	T35,T104,T105
1	0	Covered	T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T3
0	1	Covered	T1,T19,T3
1	0	Covered	T26,T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T19,T3
1	-	Covered	T1,T19,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T3
DetectSt	168	Covered	T1,T19,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T19,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T19,T3
DebounceSt->IdleSt	163	Covered	T1,T26,T13
DetectSt->IdleSt	186	Covered	T35,T104,T105
DetectSt->StableSt	191	Covered	T1,T19,T3
IdleSt->DebounceSt	148	Covered	T1,T19,T3
StableSt->IdleSt	206	Covered	T1,T19,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T19,T3
0	1	Covered	T1,T19,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T19,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T13,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T35,T104,T105
DetectSt	-	-	-	-	0	1	-	Covered	T1,T19,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T19,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T19,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	847	0	0
CntIncr_A	5590926	45290	0	0
CntNoWrap_A	5590926	5130161	0	0
DetectStDropOut_A	5590926	28	0	0
DetectedOut_A	5590926	14844	0	0
DetectedPulseOut_A	5590926	366	0	0
DisabledIdleSt_A	5590926	4765116	0	0
DisabledNoDetection_A	5590926	4766374	0	0
EnterDebounceSt_A	5590926	452	0	0
EnterDetectSt_A	5590926	396	0	0
EnterStableSt_A	5590926	366	0	0
PulseIsPulse_A	5590926	366	0	0
StayInStableSt	5590926	14444	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	330	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	847	0	0
T1	33661	25	0	0
T2	1891	0	0	0
T3	0	4	0	0
T8	0	4	0	0
T11	0	2	0	0
T13	0	7	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	2	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	6	0	0
T34	0	2	0	0
T35	0	4	0	0
T36	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	45290	0	0
T1	33661	1419	0	0
T2	1891	0	0	0
T3	0	116	0	0
T8	0	156	0	0
T11	0	54	0	0
T13	0	592	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	158	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	83	0	0
T34	0	25	0	0
T35	0	156	0	0
T36	0	76	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130161	0	0
T1	33661	33209	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	28	0	0
T34	2313	0	0	0
T35	25031	2	0	0
T52	36575	0	0	0
T67	499	0	0	0
T90	0	1	0	0
T104	0	2	0	0
T105	0	10	0	0
T106	0	9	0	0
T107	0	1	0	0
T108	0	3	0	0
T109	716	0	0	0
T110	1793	0	0	0
T111	412	0	0	0
T112	522	0	0	0
T113	438	0	0	0
T114	509	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	14844	0	0
T1	33661	1179	0	0
T2	1891	0	0	0
T3	0	132	0	0
T8	0	155	0	0
T11	0	98	0	0
T13	0	17	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	8	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	99	0	0
T34	0	3	0	0
T36	0	46	0	0
T41	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	366	0	0
T1	33661	12	0	0
T2	1891	0	0	0
T3	0	2	0	0
T8	0	2	0	0
T11	0	1	0	0
T13	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	1	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T41	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4765116	0	0
T1	33661	28204	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4766374	0	0
T1	33661	28204	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	452	0	0
T1	33661	13	0	0
T2	1891	0	0	0
T3	0	2	0	0
T8	0	2	0	0
T11	0	1	0	0
T13	0	4	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	1	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	5	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	396	0	0
T1	33661	12	0	0
T2	1891	0	0	0
T3	0	2	0	0
T8	0	2	0	0
T11	0	1	0	0
T13	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	1	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T34	0	1	0	0
T35	0	2	0	0
T36	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	366	0	0
T1	33661	12	0	0
T2	1891	0	0	0
T3	0	2	0	0
T8	0	2	0	0
T11	0	1	0	0
T13	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	1	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T41	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	366	0	0
T1	33661	12	0	0
T2	1891	0	0	0
T3	0	2	0	0
T8	0	2	0	0
T11	0	1	0	0
T13	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	1	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T34	0	1	0	0
T36	0	2	0	0
T41	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	14444	0	0
T1	33661	1167	0	0
T2	1891	0	0	0
T3	0	129	0	0
T8	0	153	0	0
T11	0	97	0	0
T13	0	14	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	7	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	98	0	0
T34	0	2	0	0
T36	0	44	0	0
T41	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	330	0	0
T1	33661	12	0	0
T2	1891	0	0	0
T3	0	1	0	0
T8	0	2	0	0
T11	0	1	0	0
T13	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	1	0	0
T20	427	0	0	0
T21	492	0	0	0
T34	0	1	0	0
T36	0	2	0	0
T37	0	9	0	0
T41	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T8,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T30
1	0	Covered	T3,T8,T26
1	1	Covered	T3,T8,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T26
0	1	Covered	T30,T26,T51
1	0	Covered	T26,T243,T103

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T26
0	1	Covered	T3,T8,T26
1	0	Covered	T89,T244,T245

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T26
1	-	Covered	T3,T8,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T30
DetectSt	168	Covered	T3,T8,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T30
DebounceSt->IdleSt	163	Covered	T30,T26,T242
DetectSt->IdleSt	186	Covered	T30,T26,T51
DetectSt->StableSt	191	Covered	T3,T8,T26
IdleSt->DebounceSt	148	Covered	T3,T8,T30
StableSt->IdleSt	206	Covered	T3,T8,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T8,T30
0	1	Covered	T3,T8,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T30
IdleSt	0	-	-	-	-	-	-	Covered	T3,T8,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T26,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T26,T51
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T26
DetectSt	-	-	-	-	0	0	-	Covered	T3,T8,T26
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T26
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T26
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	3053	0	0
CntIncr_A	5590926	110220	0	0
CntNoWrap_A	5590926	5127955	0	0
DetectStDropOut_A	5590926	437	0	0
DetectedOut_A	5590926	82462	0	0
DetectedPulseOut_A	5590926	887	0	0
DisabledIdleSt_A	5590926	4644740	0	0
DisabledNoDetection_A	5590926	4646488	0	0
EnterDebounceSt_A	5590926	1537	0	0
EnterDetectSt_A	5590926	1517	0	0
EnterStableSt_A	5590926	887	0	0
PulseIsPulse_A	5590926	887	0	0
StayInStableSt	5590926	81447	0	0
gen_high_event_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	702	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	3053	0	0
T3	19016	32	0	0
T7	697	0	0	0
T8	13824	34	0	0
T9	858	0	0	0
T11	0	30	0	0
T26	6185	16	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	6	0	0
T36	0	30	0	0
T51	0	30	0	0
T54	0	56	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	62	0	0
T79	0	60	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	110220	0	0
T3	19016	448	0	0
T7	697	0	0	0
T8	13824	1088	0	0
T9	858	0	0	0
T11	0	1185	0	0
T26	6185	417	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	240	0	0
T36	0	840	0	0
T51	0	784	0	0
T54	0	1736	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	2201	0	0
T79	0	1560	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5127955	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	437	0	0
T9	858	0	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T26	6185	1	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	1	0	0
T51	5272	15	0	0
T73	524	0	0	0
T96	0	20	0	0
T97	0	16	0	0
T98	0	24	0	0
T129	408	0	0	0
T242	0	5	0	0
T243	0	4	0	0
T246	0	30	0	0
T247	0	24	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	82462	0	0
T3	19016	674	0	0
T7	697	0	0	0
T8	13824	704	0	0
T9	858	0	0	0
T11	0	531	0	0
T26	6185	277	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	109	0	0
T54	0	3256	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	2512	0	0
T79	0	1130	0	0
T134	0	2196	0	0
T137	0	1534	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	887	0	0
T3	19016	16	0	0
T7	697	0	0	0
T8	13824	17	0	0
T9	858	0	0	0
T11	0	15	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	15	0	0
T54	0	28	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	31	0	0
T79	0	30	0	0
T134	0	12	0	0
T137	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4644740	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4646488	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1537	0	0
T3	19016	16	0	0
T7	697	0	0	0
T8	13824	17	0	0
T9	858	0	0	0
T11	0	15	0	0
T26	6185	9	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	5	0	0
T36	0	15	0	0
T51	0	15	0	0
T54	0	28	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	31	0	0
T79	0	30	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1517	0	0
T3	19016	16	0	0
T7	697	0	0	0
T8	13824	17	0	0
T9	858	0	0	0
T11	0	15	0	0
T26	6185	7	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	1	0	0
T36	0	15	0	0
T51	0	15	0	0
T54	0	28	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	31	0	0
T79	0	30	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	887	0	0
T3	19016	16	0	0
T7	697	0	0	0
T8	13824	17	0	0
T9	858	0	0	0
T11	0	15	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	15	0	0
T54	0	28	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	31	0	0
T79	0	30	0	0
T134	0	12	0	0
T137	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	887	0	0
T3	19016	16	0	0
T7	697	0	0	0
T8	13824	17	0	0
T9	858	0	0	0
T11	0	15	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	15	0	0
T54	0	28	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	31	0	0
T79	0	30	0	0
T134	0	12	0	0
T137	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	81447	0	0
T3	19016	655	0	0
T7	697	0	0	0
T8	13824	687	0	0
T9	858	0	0	0
T11	0	516	0	0
T26	6185	272	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	93	0	0
T54	0	3222	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	2474	0	0
T79	0	1097	0	0
T134	0	2180	0	0
T137	0	1512	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	702	0	0
T3	19016	13	0	0
T7	697	0	0	0
T8	13824	17	0	0
T9	858	0	0	0
T11	0	15	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	14	0	0
T54	0	22	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	24	0	0
T79	0	27	0	0
T134	0	8	0	0
T137	0	18	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T22,T1,T19
1	1	Covered	T1,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T3
0	1	Covered	T64,T100,T101
1	0	Covered	T26,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T3
0	1	Covered	T1,T19,T3
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T19,T3
1	-	Covered	T1,T19,T3

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T3
DetectSt	168	Covered	T1,T19,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T19,T3

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T19,T3
DebounceSt->IdleSt	163	Covered	T19,T26,T13
DetectSt->IdleSt	186	Covered	T26,T64,T100
DetectSt->StableSt	191	Covered	T1,T19,T3
IdleSt->DebounceSt	148	Covered	T1,T19,T3
StableSt->IdleSt	206	Covered	T1,T19,T3

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T19,T3
0	1	Covered	T1,T19,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T19,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T13,T248
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T26,T64,T100
DetectSt	-	-	-	-	0	1	-	Covered	T1,T19,T3
DetectSt	-	-	-	-	0	0	-	Covered	T1,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T19,T3
StableSt	-	-	-	-	-	-	0	Covered	T1,T19,T3
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	894	0	0
CntIncr_A	5590926	51313	0	0
CntNoWrap_A	5590926	5130114	0	0
DetectStDropOut_A	5590926	64	0	0
DetectedOut_A	5590926	14468	0	0
DetectedPulseOut_A	5590926	355	0	0
DisabledIdleSt_A	5590926	4775260	0	0
DisabledNoDetection_A	5590926	4776554	0	0
EnterDebounceSt_A	5590926	472	0	0
EnterDetectSt_A	5590926	422	0	0
EnterStableSt_A	5590926	355	0	0
PulseIsPulse_A	5590926	355	0	0
StayInStableSt	5590926	14080	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	320	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	894	0	0
T1	33661	4	0	0
T2	1891	0	0	0
T3	0	4	0	0
T13	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	27	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	8	0	0
T35	0	6	0	0
T36	0	2	0	0
T54	0	8	0	0
T78	0	12	0	0
T79	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	51313	0	0
T1	33661	406	0	0
T2	1891	0	0	0
T3	0	140	0	0
T13	0	170	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	2130	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	110	0	0
T35	0	138	0	0
T36	0	28	0	0
T54	0	264	0	0
T78	0	306	0	0
T79	0	147	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130114	0	0
T1	33661	33230	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	64	0	0
T43	582	0	0	0
T56	617	0	0	0
T64	19594	4	0	0
T65	881	0	0	0
T68	494	0	0	0
T83	0	1	0	0
T100	0	6	0	0
T101	0	8	0	0
T134	18966	0	0	0
T249	0	5	0	0
T250	0	5	0	0
T251	0	1	0	0
T252	0	4	0	0
T253	0	2	0	0
T254	0	15	0	0
T255	403	0	0	0
T256	423	0	0	0
T257	631	0	0	0
T258	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	14468	0	0
T1	33661	8	0	0
T2	1891	0	0	0
T3	0	109	0	0
T13	0	83	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	135	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	100	0	0
T35	0	96	0	0
T36	0	33	0	0
T54	0	382	0	0
T78	0	441	0	0
T79	0	109	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	355	0	0
T1	33661	2	0	0
T2	1891	0	0	0
T3	0	2	0	0
T13	0	1	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	12	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T35	0	3	0	0
T36	0	1	0	0
T54	0	4	0	0
T78	0	6	0	0
T79	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4775260	0	0
T1	33661	28204	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4776554	0	0
T1	33661	28204	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	472	0	0
T1	33661	2	0	0
T2	1891	0	0	0
T3	0	2	0	0
T13	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	15	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	5	0	0
T35	0	3	0	0
T36	0	1	0	0
T54	0	4	0	0
T78	0	6	0	0
T79	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	422	0	0
T1	33661	2	0	0
T2	1891	0	0	0
T3	0	2	0	0
T13	0	1	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	12	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	3	0	0
T35	0	3	0	0
T36	0	1	0	0
T54	0	4	0	0
T78	0	6	0	0
T79	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	355	0	0
T1	33661	2	0	0
T2	1891	0	0	0
T3	0	2	0	0
T13	0	1	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	12	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T35	0	3	0	0
T36	0	1	0	0
T54	0	4	0	0
T78	0	6	0	0
T79	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	355	0	0
T1	33661	2	0	0
T2	1891	0	0	0
T3	0	2	0	0
T13	0	1	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	12	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T35	0	3	0	0
T36	0	1	0	0
T54	0	4	0	0
T78	0	6	0	0
T79	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	14080	0	0
T1	33661	6	0	0
T2	1891	0	0	0
T3	0	107	0	0
T13	0	82	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	122	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	99	0	0
T35	0	93	0	0
T36	0	32	0	0
T54	0	374	0	0
T78	0	435	0	0
T79	0	106	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	320	0	0
T1	33661	2	0	0
T2	1891	0	0	0
T3	0	2	0	0
T13	0	1	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	11	0	0
T20	427	0	0	0
T21	492	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T78	0	6	0	0
T79	0	3	0	0
T99	0	3	0	0
T137	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T8,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T30
1	0	Covered	T3,T8,T26
1	1	Covered	T3,T8,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T26
0	1	Covered	T30,T26,T51
1	0	Covered	T26,T54,T78

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T26
0	1	Covered	T3,T8,T26
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T26
1	-	Covered	T3,T8,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T30
DetectSt	168	Covered	T3,T8,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T30
DebounceSt->IdleSt	163	Covered	T30,T26,T242
DetectSt->IdleSt	186	Covered	T30,T26,T51
DetectSt->StableSt	191	Covered	T3,T8,T26
IdleSt->DebounceSt	148	Covered	T3,T8,T30
StableSt->IdleSt	206	Covered	T3,T8,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T8,T30
0	1	Covered	T3,T8,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T30
IdleSt	0	-	-	-	-	-	-	Covered	T3,T8,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T26,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T26,T51
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T26
DetectSt	-	-	-	-	0	0	-	Covered	T3,T8,T26
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T26
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T26
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	2978	0	0
CntIncr_A	5590926	109052	0	0
CntNoWrap_A	5590926	5128030	0	0
DetectStDropOut_A	5590926	471	0	0
DetectedOut_A	5590926	74140	0	0
DetectedPulseOut_A	5590926	769	0	0
DisabledIdleSt_A	5590926	4650162	0	0
DisabledNoDetection_A	5590926	4651925	0	0
EnterDebounceSt_A	5590926	1505	0	0
EnterDetectSt_A	5590926	1474	0	0
EnterStableSt_A	5590926	769	0	0
PulseIsPulse_A	5590926	769	0	0
StayInStableSt	5590926	73259	0	0
gen_high_event_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	656	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	2978	0	0
T3	19016	10	0	0
T7	697	0	0	0
T8	13824	62	0	0
T9	858	0	0	0
T11	0	52	0	0
T26	6185	16	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	8	0	0
T36	0	24	0	0
T51	0	6	0	0
T54	0	48	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	20	0	0
T79	0	48	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	109052	0	0
T3	19016	190	0	0
T7	697	0	0	0
T8	13824	2015	0	0
T9	858	0	0	0
T11	0	1508	0	0
T26	6185	389	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	288	0	0
T36	0	348	0	0
T51	0	156	0	0
T54	0	1960	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	777	0	0
T79	0	1680	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5128030	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	471	0	0
T9	858	0	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T26	6185	1	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	2	0	0
T51	5272	3	0	0
T54	0	4	0	0
T73	524	0	0	0
T78	0	6	0	0
T96	0	16	0	0
T97	0	24	0	0
T98	0	5	0	0
T99	0	3	0	0
T129	408	0	0	0
T243	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	74140	0	0
T3	19016	166	0	0
T7	697	0	0	0
T8	13824	3187	0	0
T9	858	0	0	0
T11	0	3031	0	0
T26	6185	303	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	500	0	0
T60	416	0	0	0
T73	524	0	0	0
T79	0	1336	0	0
T103	0	1383	0	0
T137	0	273	0	0
T161	0	304	0	0
T233	0	478	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	769	0	0
T3	19016	5	0	0
T7	697	0	0	0
T8	13824	31	0	0
T9	858	0	0	0
T11	0	26	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	12	0	0
T60	416	0	0	0
T73	524	0	0	0
T79	0	24	0	0
T103	0	25	0	0
T137	0	4	0	0
T161	0	11	0	0
T233	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4650162	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4651925	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1505	0	0
T3	19016	5	0	0
T7	697	0	0	0
T8	13824	31	0	0
T9	858	0	0	0
T11	0	26	0	0
T26	6185	9	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	6	0	0
T36	0	12	0	0
T51	0	3	0	0
T54	0	24	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	10	0	0
T79	0	24	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1474	0	0
T3	19016	5	0	0
T7	697	0	0	0
T8	13824	31	0	0
T9	858	0	0	0
T11	0	26	0	0
T26	6185	7	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	2	0	0
T36	0	12	0	0
T51	0	3	0	0
T54	0	24	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	10	0	0
T79	0	24	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	769	0	0
T3	19016	5	0	0
T7	697	0	0	0
T8	13824	31	0	0
T9	858	0	0	0
T11	0	26	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	12	0	0
T60	416	0	0	0
T73	524	0	0	0
T79	0	24	0	0
T103	0	25	0	0
T137	0	4	0	0
T161	0	11	0	0
T233	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	769	0	0
T3	19016	5	0	0
T7	697	0	0	0
T8	13824	31	0	0
T9	858	0	0	0
T11	0	26	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	12	0	0
T60	416	0	0	0
T73	524	0	0	0
T79	0	24	0	0
T103	0	25	0	0
T137	0	4	0	0
T161	0	11	0	0
T233	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	73259	0	0
T3	19016	160	0	0
T7	697	0	0	0
T8	13824	3154	0	0
T9	858	0	0	0
T11	0	3005	0	0
T26	6185	298	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	488	0	0
T60	416	0	0	0
T73	524	0	0	0
T79	0	1310	0	0
T103	0	1356	0	0
T137	0	269	0	0
T161	0	292	0	0
T233	0	475	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	656	0	0
T3	19016	4	0	0
T7	697	0	0	0
T8	13824	29	0	0
T9	858	0	0	0
T11	0	26	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	12	0	0
T60	416	0	0	0
T73	524	0	0	0
T79	0	22	0	0
T103	0	23	0	0
T137	0	4	0	0
T161	0	10	0	0
T233	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T22,T1,T19
1	1	Covered	T1,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T3
0	1	Covered	T19,T26,T101
1	0	Covered	T26,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T8
0	1	Covered	T1,T3,T8
1	0	Covered	T83

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T8
1	-	Covered	T1,T3,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T3
DetectSt	168	Covered	T1,T19,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T19,T3
DebounceSt->IdleSt	163	Covered	T1,T19,T26
DetectSt->IdleSt	186	Covered	T19,T26,T101
DetectSt->StableSt	191	Covered	T1,T3,T8
IdleSt->DebounceSt	148	Covered	T1,T19,T3
StableSt->IdleSt	206	Covered	T1,T3,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T19,T3
0	1	Covered	T1,T19,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T19,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T1,T19,T13
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T19,T26,T101
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	808	0	0
CntIncr_A	5590926	43734	0	0
CntNoWrap_A	5590926	5130200	0	0
DetectStDropOut_A	5590926	38	0	0
DetectedOut_A	5590926	14805	0	0
DetectedPulseOut_A	5590926	337	0	0
DisabledIdleSt_A	5590926	4780731	0	0
DisabledNoDetection_A	5590926	4782041	0	0
EnterDebounceSt_A	5590926	430	0	0
EnterDetectSt_A	5590926	379	0	0
EnterStableSt_A	5590926	337	0	0
PulseIsPulse_A	5590926	337	0	0
StayInStableSt	5590926	14431	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	297	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	808	0	0
T1	33661	11	0	0
T2	1891	0	0	0
T3	0	2	0	0
T8	0	4	0	0
T11	0	14	0	0
T13	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	5	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	8	0	0
T35	0	20	0	0
T36	0	4	0	0
T37	0	10	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	43734	0	0
T1	33661	1044	0	0
T2	1891	0	0	0
T3	0	42	0	0
T8	0	164	0	0
T11	0	686	0	0
T13	0	168	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	418	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	129	0	0
T35	0	490	0	0
T36	0	76	0	0
T37	0	555	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130200	0	0
T1	33661	33223	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	38	0	0
T3	19016	0	0	0
T7	697	0	0	0
T8	13824	0	0	0
T9	858	0	0	0
T19	30361	2	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T28	504	0	0	0
T30	5019	0	0	0
T60	416	0	0	0
T101	0	3	0	0
T156	0	2	0	0
T251	0	3	0	0
T259	0	2	0	0
T260	0	4	0	0
T261	0	1	0	0
T262	0	2	0	0
T263	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	14805	0	0
T1	33661	92	0	0
T2	1891	0	0	0
T3	0	83	0	0
T8	0	147	0	0
T11	0	376	0	0
T13	0	85	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	100	0	0
T35	0	241	0	0
T36	0	46	0	0
T37	0	287	0	0
T79	0	90	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	337	0	0
T1	33661	5	0	0
T2	1891	0	0	0
T3	0	1	0	0
T8	0	2	0	0
T11	0	7	0	0
T13	0	1	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T35	0	9	0	0
T36	0	2	0	0
T37	0	5	0	0
T79	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4780731	0	0
T1	33661	28204	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4782041	0	0
T1	33661	28204	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	430	0	0
T1	33661	6	0	0
T2	1891	0	0	0
T3	0	1	0	0
T8	0	2	0	0
T11	0	7	0	0
T13	0	2	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	3	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	5	0	0
T35	0	11	0	0
T36	0	2	0	0
T37	0	5	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	379	0	0
T1	33661	5	0	0
T2	1891	0	0	0
T3	0	1	0	0
T8	0	2	0	0
T11	0	7	0	0
T13	0	1	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	2	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	3	0	0
T35	0	9	0	0
T36	0	2	0	0
T37	0	5	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	337	0	0
T1	33661	5	0	0
T2	1891	0	0	0
T3	0	1	0	0
T8	0	2	0	0
T11	0	7	0	0
T13	0	1	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T35	0	9	0	0
T36	0	2	0	0
T37	0	5	0	0
T79	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	337	0	0
T1	33661	5	0	0
T2	1891	0	0	0
T3	0	1	0	0
T8	0	2	0	0
T11	0	7	0	0
T13	0	1	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T35	0	9	0	0
T36	0	2	0	0
T37	0	5	0	0
T79	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	14431	0	0
T1	33661	87	0	0
T2	1891	0	0	0
T3	0	82	0	0
T8	0	145	0	0
T11	0	369	0	0
T13	0	84	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	99	0	0
T35	0	232	0	0
T36	0	44	0	0
T37	0	282	0	0
T79	0	88	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	297	0	0
T1	33661	5	0	0
T2	1891	0	0	0
T3	0	1	0	0
T8	0	2	0	0
T11	0	7	0	0
T13	0	1	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T35	0	9	0	0
T36	0	2	0	0
T37	0	5	0	0
T64	0	5	0	0
T79	0	2	0	0