Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
79	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T3,T8,T30
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T8,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T30
1	0	Covered	T3,T8,T26
1	1	Covered	T3,T8,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T30
0	1	Covered	T30,T26,T51
1	0	Covered	T26,T99,T102

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T8,T26
0	1	Covered	T3,T8,T26
1	0	Covered	T87,T88

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T8,T26
1	-	Covered	T3,T8,T26

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T8,T30
DetectSt	168	Covered	T3,T8,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T8,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T8,T30
DebounceSt->IdleSt	163	Covered	T30,T26,T242
DetectSt->IdleSt	186	Covered	T30,T26,T51
DetectSt->StableSt	191	Covered	T3,T8,T26
IdleSt->DebounceSt	148	Covered	T3,T8,T30
StableSt->IdleSt	206	Covered	T3,T8,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T8,T30
0	1	Covered	T3,T8,T30
0	0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T3,T8,T30
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T3,T8,T30
IdleSt	0	-	-	-	-	-	-	Covered	T3,T8,T30
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T8,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T30,T26,T242
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T8,T30
DetectSt	-	-	-	-	1	-	-	Covered	T30,T26,T51
DetectSt	-	-	-	-	0	1	-	Covered	T3,T8,T26
DetectSt	-	-	-	-	0	0	-	Covered	T3,T8,T30
StableSt	-	-	-	-	-	-	1	Covered	T3,T8,T26
StableSt	-	-	-	-	-	-	0	Covered	T3,T8,T26
default	-	-	-	-	-	-	-	Not Covered

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	3189	0	0
CntIncr_A	5590926	117690	0	0
CntNoWrap_A	5590926	5127819	0	0
DetectStDropOut_A	5590926	454	0	0
DetectedOut_A	5590926	76748	0	0
DetectedPulseOut_A	5590926	952	0	0
DisabledIdleSt_A	5590926	4645922	0	0
DisabledNoDetection_A	5590926	4647685	0	0
EnterDebounceSt_A	5590926	1607	0	0
EnterDetectSt_A	5590926	1583	0	0
EnterStableSt_A	5590926	952	0	0
PulseIsPulse_A	5590926	952	0	0
StayInStableSt	5590926	75683	0	0
gen_high_event_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	816	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	3189	0	0
T3	19016	54	0	0
T7	697	0	0	0
T8	13824	12	0	0
T9	858	0	0	0
T11	0	16	0	0
T26	6185	16	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	26	0	0
T36	0	44	0	0
T51	0	36	0	0
T54	0	54	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	62	0	0
T79	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	117690	0	0
T3	19016	621	0	0
T7	697	0	0	0
T8	13824	474	0	0
T9	858	0	0	0
T11	0	544	0	0
T26	6185	390	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	865	0	0
T36	0	660	0	0
T51	0	950	0	0
T54	0	1944	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	2418	0	0
T79	0	1764	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5127819	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	454	0	0
T9	858	0	0	0
T10	1596	0	0	0
T11	12099	0	0	0
T26	6185	1	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	8	0	0
T51	5272	18	0	0
T73	524	0	0	0
T96	0	8	0	0
T97	0	8	0	0
T98	0	25	0	0
T99	0	19	0	0
T102	0	10	0	0
T129	408	0	0	0
T161	0	9	0	0
T246	0	4	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	76748	0	0
T3	19016	2531	0	0
T7	697	0	0	0
T8	13824	156	0	0
T9	858	0	0	0
T11	0	370	0	0
T26	6185	308	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	919	0	0
T54	0	805	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	2295	0	0
T79	0	670	0	0
T134	0	1872	0	0
T137	0	1507	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	952	0	0
T3	19016	27	0	0
T7	697	0	0	0
T8	13824	6	0	0
T9	858	0	0	0
T11	0	8	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	22	0	0
T54	0	27	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	31	0	0
T79	0	28	0	0
T134	0	12	0	0
T137	0	14	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4645922	0	0
T1	33661	33234	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4647685	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1607	0	0
T3	19016	27	0	0
T7	697	0	0	0
T8	13824	6	0	0
T9	858	0	0	0
T11	0	8	0	0
T26	6185	9	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	18	0	0
T36	0	22	0	0
T51	0	18	0	0
T54	0	27	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	31	0	0
T79	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	1583	0	0
T3	19016	27	0	0
T7	697	0	0	0
T8	13824	6	0	0
T9	858	0	0	0
T11	0	8	0	0
T26	6185	7	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	8	0	0
T36	0	22	0	0
T51	0	18	0	0
T54	0	27	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	31	0	0
T79	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	952	0	0
T3	19016	27	0	0
T7	697	0	0	0
T8	13824	6	0	0
T9	858	0	0	0
T11	0	8	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	22	0	0
T54	0	27	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	31	0	0
T79	0	28	0	0
T134	0	12	0	0
T137	0	14	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	952	0	0
T3	19016	27	0	0
T7	697	0	0	0
T8	13824	6	0	0
T9	858	0	0	0
T11	0	8	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	22	0	0
T54	0	27	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	31	0	0
T79	0	28	0	0
T134	0	12	0	0
T137	0	14	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	75683	0	0
T3	19016	2499	0	0
T7	697	0	0	0
T8	13824	150	0	0
T9	858	0	0	0
T11	0	362	0	0
T26	6185	303	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	897	0	0
T54	0	775	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	2257	0	0
T79	0	640	0	0
T134	0	1856	0	0
T137	0	1491	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	816	0	0
T3	19016	22	0	0
T7	697	0	0	0
T8	13824	6	0	0
T9	858	0	0	0
T11	0	8	0	0
T26	6185	5	0	0
T28	504	0	0	0
T29	616	0	0	0
T30	5019	0	0	0
T36	0	22	0	0
T54	0	24	0	0
T60	416	0	0	0
T73	524	0	0	0
T78	0	24	0	0
T79	0	26	0	0
T134	0	8	0	0
T137	0	12	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
60	1	1
69	1	1
70	1	1
72	1	1
76	1	1
92	1	1
99	1	1
101	1	1
104	1	1
105	1	1
107	1	1
125	1	1
128	1	1
129	1	1
132	1	1
133	1	1
138	1	1
140	1	1
147	1	1
148	1	1
149	1	1
			MISSING_ELSE
160	1	1
162	1	1
163	1	1
164	1	1
165	1	1
166	1	1
167	1	1
168	1	1
170	1	1
			MISSING_ELSE
181	1	1
182	1	1
185	1	1
186	1	1
187	1	1
190	1	1
191	1	1
192	1	1
193	1	1
194	1	1
			MISSING_ELSE
205	1	1
206	1	1
209	1	1
			Exclude Annotation: VC_COV_UNR
219	1	1
220	1	1
222	1	1

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T19,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T19,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T19,T3

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T19,T3
1	0	Covered	T22,T1,T19
1	1	Covered	T1,T19,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T19,T3
0	1	Covered	T19,T64,T264
1	0	Covered	T26,T83

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T26
0	1	Covered	T1,T3,T35
1	0	Covered	T26

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T26
1	-	Covered	T1,T3,T35

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T19,T3
DetectSt	168	Covered	T1,T19,T3
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T26

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T19,T3
DebounceSt->IdleSt	163	Covered	T19,T3,T26
DetectSt->IdleSt	186	Covered	T19,T26,T64
DetectSt->StableSt	191	Covered	T1,T3,T26
IdleSt->DebounceSt	148	Covered	T1,T19,T3
StableSt->IdleSt	206	Covered	T1,T3,T26

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv' or '../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_detect.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	92	(cnt_clr) ? 
-2-:	92	(cnt_en) ? 

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T19,T3
0	1	Covered	T1,T19,T3
0	0	Excluded	T4,T5,T6	VC_COV_UNR

	LineNo.	Expression
-1-:	99	(thresh_sel) ? 

Branches:

-1-	Status	Tests
1	Covered	T1,T19,T3
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	104	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	140	case (state_q)
-2-:	147	if ((trigger_event && cfg_enable_i))
-3-:	162	if ((!cfg_enable_i))
-4-:	165	if (cnt_done)
-5-:	167	if (trigger_active)
-6-:	185	if (((!cfg_enable_i) || (!trigger_active)))
-7-:	190	if (cnt_done)
-8-:	205	if (((!cfg_enable_i) || ((!trigger_active) && (!Sticky))))

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T19,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T26,T83
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T19,T3
DebounceSt	-	0	1	0	-	-	-	Covered	T19,T3,T37
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T19,T3
DetectSt	-	-	-	-	1	-	-	Covered	T19,T26,T64
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T26
DetectSt	-	-	-	-	0	0	-	Covered	T1,T19,T3
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T26
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T26
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

	LineNo.	Expression
-1-:	219	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

	LineNo.	Expression
-1-:	69	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5590926	852	0	0
CntIncr_A	5590926	48868	0	0
CntNoWrap_A	5590926	5130156	0	0
DetectStDropOut_A	5590926	77	0	0
DetectedOut_A	5590926	15038	0	0
DetectedPulseOut_A	5590926	321	0	0
DisabledIdleSt_A	5590926	4773818	0	0
DisabledNoDetection_A	5590926	4775118	0	0
EnterDebounceSt_A	5590926	450	0	0
EnterDetectSt_A	5590926	402	0	0
EnterStableSt_A	5590926	321	0	0
PulseIsPulse_A	5590926	321	0	0
StayInStableSt	5590926	14686	0	0
gen_high_level_sva.HighLevelEvent_A	5590926	5132976	0	0
gen_not_sticky_sva.StableStDropOut_A	5590926	288	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	852	0	0
T1	33661	6	0	0
T2	1891	0	0	0
T3	0	7	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	9	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	8	0	0
T35	0	14	0	0
T37	0	5	0	0
T54	0	4	0	0
T64	0	20	0	0
T78	0	12	0	0
T79	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	48868	0	0
T1	33661	438	0	0
T2	1891	0	0	0
T3	0	245	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	752	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	142	0	0
T35	0	462	0	0
T37	0	195	0	0
T54	0	218	0	0
T64	0	1442	0	0
T78	0	486	0	0
T79	0	42	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5130156	0	0
T1	33661	33228	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	77	0	0
T3	19016	0	0	0
T7	697	0	0	0
T8	13824	0	0	0
T9	858	0	0	0
T19	30361	4	0	0
T20	427	0	0	0
T21	492	0	0	0
T28	504	0	0	0
T30	5019	0	0	0
T60	416	0	0	0
T64	0	9	0	0
T105	0	1	0	0
T106	0	4	0	0
T200	0	8	0	0
T264	0	2	0	0
T265	0	1	0	0
T266	0	7	0	0
T267	0	14	0	0
T268	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	15038	0	0
T1	33661	183	0	0
T2	1891	0	0	0
T3	0	138	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	100	0	0
T35	0	85	0	0
T37	0	158	0	0
T54	0	104	0	0
T78	0	258	0	0
T79	0	43	0	0
T134	0	233	0	0
T137	0	170	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	321	0	0
T1	33661	3	0	0
T2	1891	0	0	0
T3	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T35	0	7	0	0
T37	0	2	0	0
T54	0	2	0	0
T78	0	6	0	0
T79	0	1	0	0
T134	0	4	0	0
T137	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4773818	0	0
T1	33661	28204	0	0
T2	1891	1490	0	0
T4	526	125	0	0
T5	627	226	0	0
T6	888	487	0	0
T14	497	96	0	0
T15	430	29	0	0
T16	442	41	0	0
T17	524	123	0	0
T22	1188	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	4775118	0	0
T1	33661	28204	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	450	0	0
T1	33661	3	0	0
T2	1891	0	0	0
T3	0	4	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	5	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	5	0	0
T35	0	7	0	0
T37	0	3	0	0
T54	0	2	0	0
T64	0	11	0	0
T78	0	6	0	0
T79	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	402	0	0
T1	33661	3	0	0
T2	1891	0	0	0
T3	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	4	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	3	0	0
T35	0	7	0	0
T37	0	2	0	0
T54	0	2	0	0
T64	0	9	0	0
T78	0	6	0	0
T79	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	321	0	0
T1	33661	3	0	0
T2	1891	0	0	0
T3	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T35	0	7	0	0
T37	0	2	0	0
T54	0	2	0	0
T78	0	6	0	0
T79	0	1	0	0
T134	0	4	0	0
T137	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	321	0	0
T1	33661	3	0	0
T2	1891	0	0	0
T3	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	1	0	0
T35	0	7	0	0
T37	0	2	0	0
T54	0	2	0	0
T78	0	6	0	0
T79	0	1	0	0
T134	0	4	0	0
T137	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	14686	0	0
T1	33661	180	0	0
T2	1891	0	0	0
T3	0	135	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T26	0	99	0	0
T35	0	78	0	0
T37	0	156	0	0
T54	0	100	0	0
T78	0	251	0	0
T79	0	42	0	0
T134	0	225	0	0
T137	0	168	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	5132976	0	0
T1	33661	33248	0	0
T2	1891	1491	0	0
T4	526	126	0	0
T5	627	227	0	0
T6	888	488	0	0
T14	497	97	0	0
T15	430	30	0	0
T16	442	42	0	0
T17	524	124	0	0
T22	1188	11	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5590926	288	0	0
T1	33661	3	0	0
T2	1891	0	0	0
T3	0	3	0	0
T14	497	0	0	0
T15	430	0	0	0
T16	442	0	0	0
T17	524	0	0	0
T18	415	0	0	0
T19	30361	0	0	0
T20	427	0	0	0
T21	492	0	0	0
T35	0	7	0	0
T37	0	2	0	0
T78	0	5	0	0
T79	0	1	0	0
T100	0	3	0	0
T101	0	11	0	0
T137	0	2	0	0
T243	0	2	0	0