Unified Coverage Report :: Module :: sysrst_ctrl_csr_assert_fpv

Module : sysrst_ctrl_csr_assert_fpv

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_fpv_sysrst_ctrl_csr_assert_0/sysrst_ctrl_csr_assert_fpv.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.sysrst_ctrl_csr_assert	100.00						100.00

---

Module Instance : tb.dut.sysrst_ctrl_csr_assert

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00						100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

---

Since this is the module's only instance, the coverage report is the same as for the module.

Assert Coverage for Module : sysrst_ctrl_csr_assert_fpv

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	36	36	100.00	36	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	36	36	100.00	36	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
TlulOOBAddrErr_A	1202938455	11523	0	0
auto_block_debounce_ctl_rd_A	1202938455	1496	0	0
auto_block_out_ctl_rd_A	1202938455	1968	0	0
com_det_ctl_0_rd_A	1202938455	3604	0	0
com_det_ctl_1_rd_A	1202938455	3783	0	0
com_det_ctl_2_rd_A	1202938455	3815	0	0
com_det_ctl_3_rd_A	1202938455	3870	0	0
com_out_ctl_0_rd_A	1202938455	4329	0	0
com_out_ctl_1_rd_A	1202938455	4248	0	0
com_out_ctl_2_rd_A	1202938455	4467	0	0
com_out_ctl_3_rd_A	1202938455	4390	0	0
com_pre_det_ctl_0_rd_A	1202938455	1177	0	0
com_pre_det_ctl_1_rd_A	1202938455	1183	0	0
com_pre_det_ctl_2_rd_A	1202938455	1076	0	0
com_pre_det_ctl_3_rd_A	1202938455	1358	0	0
com_pre_sel_ctl_0_rd_A	1202938455	4547	0	0
com_pre_sel_ctl_1_rd_A	1202938455	4413	0	0
com_pre_sel_ctl_2_rd_A	1202938455	4492	0	0
com_pre_sel_ctl_3_rd_A	1202938455	4572	0	0
com_sel_ctl_0_rd_A	1202938455	4596	0	0
com_sel_ctl_1_rd_A	1202938455	4774	0	0
com_sel_ctl_2_rd_A	1202938455	4660	0	0
com_sel_ctl_3_rd_A	1202938455	4509	0	0
ec_rst_ctl_rd_A	1202938455	2182	0	0
intr_enable_rd_A	1202938455	1561	0	0
key_intr_ctl_rd_A	1202938455	3696	0	0
key_intr_debounce_ctl_rd_A	1202938455	1211	0	0
key_invert_ctl_rd_A	1202938455	3942	0	0
pin_allowed_ctl_rd_A	1202938455	4242	0	0
pin_out_ctl_rd_A	1202938455	3147	0	0
pin_out_value_rd_A	1202938455	3313	0	0
regwen_rd_A	1202938455	1321	0	0
ulp_ac_debounce_ctl_rd_A	1202938455	1203	0	0
ulp_ctl_rd_A	1202938455	1280	0	0
ulp_lid_debounce_ctl_rd_A	1202938455	1234	0	0
ulp_pwrb_debounce_ctl_rd_A	1202938455	1328	0	0

TlulOOBAddrErr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	11523	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	2	0	0
T121	0	4	0	0
T194	0	9	0	0
T197	0	7	0	0
T224	0	20	0	0
T239	0	11	0	0
T294	0	5	0	0
T298	0	20	0	0
T299	0	15	0	0
T300	0	18	0	0

auto_block_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1496	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	21	0	0
T29	0	7	0	0
T58	0	8	0	0
T115	0	7	0	0
T127	0	55	0	0
T131	0	13	0	0
T239	0	16	0	0
T294	0	12	0	0
T301	0	50	0	0
T302	0	2	0	0

auto_block_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1968	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	10	0	0
T29	0	10	0	0
T58	0	9	0	0
T115	0	4	0	0
T127	0	41	0	0
T131	0	4	0	0
T239	0	4	0	0
T294	0	20	0	0
T301	0	34	0	0
T302	0	3	0	0

com_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	3604	0	0
T1	235634	46	0	0
T2	228606	0	0	0
T11	0	32	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	6	0	0
T37	0	74	0	0
T78	0	61	0	0
T79	0	39	0	0
T100	0	58	0	0
T137	0	33	0	0
T264	0	50	0	0
T294	0	11	0	0

com_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	3783	0	0
T1	235634	46	0	0
T2	228606	0	0	0
T11	0	42	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T21	236257	0	0	0
T37	0	87	0	0
T78	0	69	0	0
T79	0	37	0	0
T100	0	49	0	0
T137	0	57	0	0
T239	0	8	0	0
T264	0	70	0	0
T294	0	14	0	0

com_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	3815	0	0
T1	235634	67	0	0
T2	228606	0	0	0
T11	0	34	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	11	0	0
T37	0	54	0	0
T78	0	51	0	0
T79	0	47	0	0
T100	0	21	0	0
T137	0	52	0	0
T264	0	88	0	0
T294	0	13	0	0

com_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	3870	0	0
T1	235634	48	0	0
T2	228606	0	0	0
T11	0	31	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	24	0	0
T37	0	69	0	0
T78	0	57	0	0
T79	0	42	0	0
T100	0	48	0	0
T137	0	46	0	0
T264	0	60	0	0
T294	0	36	0	0

com_out_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4329	0	0
T1	235634	79	0	0
T2	228606	0	0	0
T11	0	37	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	5	0	0
T37	0	97	0	0
T78	0	41	0	0
T79	0	68	0	0
T100	0	37	0	0
T137	0	51	0	0
T264	0	84	0	0
T294	0	20	0	0

com_out_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4248	0	0
T1	235634	71	0	0
T2	228606	0	0	0
T11	0	27	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	11	0	0
T37	0	83	0	0
T78	0	60	0	0
T79	0	50	0	0
T100	0	42	0	0
T137	0	35	0	0
T264	0	71	0	0
T294	0	22	0	0

com_out_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4467	0	0
T1	235634	62	0	0
T2	228606	0	0	0
T11	0	29	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	19	0	0
T37	0	65	0	0
T78	0	68	0	0
T79	0	48	0	0
T100	0	47	0	0
T137	0	52	0	0
T264	0	69	0	0
T294	0	20	0	0

com_out_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4390	0	0
T1	235634	65	0	0
T2	228606	0	0	0
T11	0	42	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	24	0	0
T37	0	74	0	0
T78	0	61	0	0
T79	0	37	0	0
T100	0	62	0	0
T137	0	40	0	0
T264	0	92	0	0
T294	0	17	0	0

com_pre_det_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1177	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	8	0	0
T127	0	35	0	0
T229	0	44	0	0
T239	0	10	0	0
T294	0	21	0	0
T301	0	25	0	0
T303	0	21	0	0
T304	0	12	0	0
T305	0	20	0	0
T306	0	19	0	0

com_pre_det_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1183	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	6	0	0
T127	0	34	0	0
T229	0	60	0	0
T239	0	21	0	0
T294	0	10	0	0
T301	0	33	0	0
T303	0	18	0	0
T304	0	28	0	0
T305	0	12	0	0
T306	0	16	0	0

com_pre_det_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1076	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	12	0	0
T127	0	30	0	0
T229	0	36	0	0
T239	0	22	0	0
T294	0	11	0	0
T301	0	30	0	0
T303	0	26	0	0
T304	0	33	0	0
T305	0	23	0	0
T306	0	10	0	0

com_pre_det_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1358	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	18	0	0
T127	0	37	0	0
T229	0	42	0	0
T239	0	14	0	0
T294	0	23	0	0
T301	0	35	0	0
T303	0	19	0	0
T304	0	22	0	0
T305	0	17	0	0
T306	0	17	0	0

com_pre_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4547	0	0
T1	235634	76	0	0
T2	228606	0	0	0
T11	0	41	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	6	0	0
T37	0	68	0	0
T78	0	55	0	0
T79	0	32	0	0
T100	0	36	0	0
T137	0	43	0	0
T264	0	63	0	0
T294	0	14	0	0

com_pre_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4413	0	0
T1	235634	80	0	0
T2	228606	0	0	0
T11	0	29	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	16	0	0
T37	0	55	0	0
T78	0	45	0	0
T79	0	57	0	0
T100	0	29	0	0
T137	0	48	0	0
T264	0	55	0	0
T294	0	27	0	0

com_pre_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4492	0	0
T1	235634	59	0	0
T2	228606	0	0	0
T11	0	32	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	14	0	0
T37	0	67	0	0
T78	0	81	0	0
T79	0	46	0	0
T100	0	32	0	0
T137	0	57	0	0
T264	0	71	0	0
T294	0	17	0	0

com_pre_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4572	0	0
T1	235634	82	0	0
T2	228606	0	0	0
T11	0	44	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	14	0	0
T37	0	56	0	0
T78	0	31	0	0
T79	0	55	0	0
T100	0	44	0	0
T137	0	39	0	0
T264	0	75	0	0
T294	0	29	0	0

com_sel_ctl_0_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4596	0	0
T1	235634	75	0	0
T2	228606	0	0	0
T11	0	42	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	15	0	0
T37	0	63	0	0
T78	0	66	0	0
T79	0	56	0	0
T100	0	39	0	0
T137	0	39	0	0
T264	0	79	0	0
T294	0	9	0	0

com_sel_ctl_1_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4774	0	0
T1	235634	84	0	0
T2	228606	0	0	0
T11	0	32	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	6	0	0
T37	0	52	0	0
T78	0	69	0	0
T79	0	61	0	0
T100	0	56	0	0
T137	0	34	0	0
T264	0	67	0	0
T294	0	11	0	0

com_sel_ctl_2_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4660	0	0
T1	235634	93	0	0
T2	228606	0	0	0
T11	0	30	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	11	0	0
T37	0	65	0	0
T78	0	46	0	0
T79	0	58	0	0
T100	0	43	0	0
T137	0	50	0	0
T264	0	76	0	0
T294	0	24	0	0

com_sel_ctl_3_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4509	0	0
T1	235634	65	0	0
T2	228606	0	0	0
T11	0	26	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	11	0	0
T37	0	58	0	0
T78	0	62	0	0
T79	0	39	0	0
T100	0	27	0	0
T137	0	48	0	0
T264	0	71	0	0
T294	0	20	0	0

ec_rst_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	2182	0	0
T1	235634	52	0	0
T2	228606	0	0	0
T11	0	4	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	4	0	0
T26	0	1	0	0
T37	0	29	0	0
T51	0	2	0	0
T62	0	1	0	0
T78	0	20	0	0
T109	0	4	0	0
T294	0	17	0	0

intr_enable_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1561	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	14	0	0
T127	0	31	0	0
T229	0	32	0	0
T239	0	13	0	0
T266	0	21	0	0
T294	0	23	0	0
T301	0	34	0	0
T303	0	33	0	0
T304	0	15	0	0
T305	0	13	0	0

key_intr_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	3696	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T7	0	2	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	23	0	0
T26	0	109	0	0
T41	0	4	0	0
T127	0	45	0	0
T151	0	2	0	0
T239	0	31	0	0
T294	0	10	0	0
T301	0	28	0	0
T307	0	5	0	0

key_intr_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1211	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	8	0	0
T127	0	54	0	0
T229	0	50	0	0
T239	0	13	0	0
T294	0	32	0	0
T301	0	24	0	0
T303	0	15	0	0
T304	0	15	0	0
T305	0	17	0	0
T306	0	22	0	0

key_invert_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	3942	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	46	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T21	0	64	0	0
T22	285346	10	0	0
T69	0	82	0	0
T127	0	114	0	0
T239	0	8	0	0
T294	0	12	0	0
T301	0	35	0	0
T308	0	72	0	0
T309	0	47	0	0

pin_allowed_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	4242	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	14	0	0
T114	0	52	0	0
T127	0	55	0	0
T164	0	68	0	0
T195	0	56	0	0
T239	0	12	0	0
T294	0	11	0	0
T301	0	37	0	0
T310	0	69	0	0
T311	0	77	0	0

pin_out_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	3147	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	7	0	0
T114	0	31	0	0
T127	0	39	0	0
T164	0	76	0	0
T195	0	56	0	0
T239	0	10	0	0
T294	0	24	0	0
T301	0	31	0	0
T310	0	88	0	0
T311	0	85	0	0

pin_out_value_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	3313	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	3	0	0
T114	0	57	0	0
T127	0	36	0	0
T164	0	63	0	0
T195	0	85	0	0
T239	0	13	0	0
T294	0	24	0	0
T301	0	15	0	0
T310	0	67	0	0
T311	0	88	0	0

regwen_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1321	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	1	0	0
T127	0	52	0	0
T229	0	38	0	0
T239	0	7	0	0
T294	0	21	0	0
T301	0	39	0	0
T303	0	11	0	0
T304	0	12	0	0
T305	0	22	0	0
T306	0	25	0	0

ulp_ac_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1203	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	7	0	0
T65	0	2	0	0
T81	0	1	0	0
T82	0	10	0	0
T92	0	3	0	0
T127	0	35	0	0
T232	0	9	0	0
T239	0	15	0	0
T294	0	13	0	0
T301	0	36	0	0

ulp_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1280	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T6	49596	6	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T22	285346	18	0	0
T65	0	4	0	0
T81	0	3	0	0
T82	0	16	0	0
T92	0	11	0	0
T127	0	51	0	0
T232	0	14	0	0
T239	0	7	0	0
T294	0	21	0	0

ulp_lid_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1234	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T20	47035	0	0	0
T22	285346	6	0	0
T41	0	2	0	0
T65	0	7	0	0
T81	0	6	0	0
T82	0	10	0	0
T92	0	14	0	0
T232	0	9	0	0
T239	0	12	0	0
T294	0	15	0	0
T312	0	1	0	0

ulp_pwrb_debounce_ctl_rd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	1202938455	1328	0	0
T1	235634	0	0	0
T2	228606	0	0	0
T6	49596	10	0	0
T14	59730	0	0	0
T15	32285	0	0	0
T16	216613	0	0	0
T17	62937	0	0	0
T18	207629	0	0	0
T19	145730	0	0	0
T22	285346	25	0	0
T65	0	7	0	0
T81	0	3	0	0
T82	0	4	0	0
T92	0	5	0	0
T232	0	10	0	0
T239	0	5	0	0
T294	0	17	0	0
T312	0	2	0	0