Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.12	93.48	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T25 T45 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T25 T45 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T25 T45 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T25 T45 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T25 T45 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T25 T45 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T45 T55 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T45 T55 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T45 T55 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T45 T55 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T45 T55 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T45 T55 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T45 T55 
191        1/1                      state_d = StableSt;
           Tests:       T1 T45 T55 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T45 T55 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T45 T55 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T45 T55 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T45 T55 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T45 T55 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T45 T55 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T25,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T25,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T45,T55

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T54
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T25,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T45,T55
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T45,T55
0	1	Covered	T1,T55,T179
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T45,T55
1	-	Covered	T1,T55,T179

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T25,T45
DetectSt	168	Covered	T1,T45,T55
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T45,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T45,T55
DebounceSt->IdleSt	163	Covered	T25
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T45,T55
IdleSt->DebounceSt	148	Covered	T1,T25,T45
StableSt->IdleSt	206	Covered	T1,T45,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T25,T45
0	1	Covered	T1,T25,T45
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T45,T55
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T25,T45
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T45,T55
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T25,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T45,T55
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T45,T55
StableSt	-	-	-	-	-	-	0	Covered	T1,T45,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	43	0	0
CntIncr_A	7758203	60923	0	0
CntNoWrap_A	7758203	7283519	0	0
DetectStDropOut_A	7758203	0	0	0
DetectedOut_A	7758203	69193	0	0
DetectedPulseOut_A	7758203	21	0	0
DisabledIdleSt_A	7758203	6781546	0	0
DisabledNoDetection_A	7758203	6783426	0	0
EnterDebounceSt_A	7758203	22	0	0
EnterDetectSt_A	7758203	21	0	0
EnterStableSt_A	7758203	21	0	0
PulseIsPulse_A	7758203	21	0	0
StayInStableSt	7758203	69159	0	0
gen_high_level_sva.HighLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	43	0	0
T1	786	4	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	1	0	0
T45	0	2	0	0
T52	0	2	0	0
T55	0	2	0	0
T101	0	2	0	0
T146	0	2	0	0
T178	0	2	0	0
T179	0	2	0	0
T180	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	60923	0	0
T1	786	106	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	34	0	0
T45	0	21	0	0
T52	0	92	0	0
T55	0	57	0	0
T101	0	20	0	0
T146	0	99	0	0
T178	0	66	0	0
T179	0	31	0	0
T180	0	84	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283519	0	0
T1	786	381	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	69193	0	0
T1	786	85	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	6	0	0
T52	0	39	0	0
T55	0	42	0	0
T101	0	39	0	0
T146	0	12	0	0
T178	0	244	0	0
T179	0	19	0	0
T180	0	44	0	0
T181	0	95	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	21	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T101	0	1	0	0
T146	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6781546	0	0
T1	786	4	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6783426	0	0
T1	786	4	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	22	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	1	0	0
T45	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T101	0	1	0	0
T146	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	21	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T101	0	1	0	0
T146	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	21	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T101	0	1	0	0
T146	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	21	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T101	0	1	0	0
T146	0	1	0	0
T178	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T181	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	69159	0	0
T1	786	82	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	5	0	0
T52	0	37	0	0
T55	0	41	0	0
T101	0	37	0	0
T146	0	11	0	0
T178	0	242	0	0
T179	0	18	0	0
T180	0	42	0	0
T181	0	92	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T55	0	1	0	0
T146	0	1	0	0
T179	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T25 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T25 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T25 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T25 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T25 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T25 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T11 T54 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T11 T54 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T11 T54 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T126 T182 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T11 T54 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T11 T54 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T11 T54 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T11 T54 
191        1/1                      state_d = StableSt;
           Tests:       T1 T11 T54 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T11 T54 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T11 T54 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T11 T54 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T11 T54 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T50 T45 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T11 T54 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T25,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T25,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T11,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T11
1	0	Covered	T4,T6,T14
1	1	Covered	T1,T25,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T54
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T11,T54
0	1	Covered	T1,T50,T126
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T11,T54
1	-	Covered	T1,T50,T126

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T25,T11
DetectSt	168	Covered	T1,T11,T54
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T11,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T11,T54
DebounceSt->IdleSt	163	Covered	T25,T126,T182
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T11,T54
IdleSt->DebounceSt	148	Covered	T1,T25,T11
StableSt->IdleSt	206	Covered	T1,T50,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T25,T11
0	1	Covered	T1,T25,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T11,T54
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T25,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T11,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T126,T182
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T25,T11
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T11,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T50,T45
StableSt	-	-	-	-	-	-	0	Covered	T1,T11,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	73	0	0
CntIncr_A	7758203	25164	0	0
CntNoWrap_A	7758203	7283489	0	0
DetectStDropOut_A	7758203	0	0	0
DetectedOut_A	7758203	88087	0	0
DetectedPulseOut_A	7758203	35	0	0
DisabledIdleSt_A	7758203	7166706	0	0
DisabledNoDetection_A	7758203	7168589	0	0
EnterDebounceSt_A	7758203	38	0	0
EnterDetectSt_A	7758203	35	0	0
EnterStableSt_A	7758203	35	0	0
PulseIsPulse_A	7758203	35	0	0
StayInStableSt	7758203	88035	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7758203	1954	0	0
gen_low_level_sva.LowLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	73	0	0
T1	786	4	0	0
T2	510	0	0	0
T3	2489	0	0	0
T11	0	2	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	1	0	0
T45	0	2	0	0
T47	0	2	0	0
T50	0	4	0	0
T54	0	2	0	0
T126	0	3	0	0
T150	0	2	0	0
T166	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	25164	0	0
T1	786	106	0	0
T2	510	0	0	0
T3	2489	0	0	0
T11	0	40	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	33	0	0
T45	0	21	0	0
T47	0	32	0	0
T50	0	106	0	0
T54	0	31	0	0
T126	0	52	0	0
T150	0	42	0	0
T166	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283489	0	0
T1	786	381	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	88087	0	0
T1	786	76	0	0
T2	510	0	0	0
T3	2489	0	0	0
T11	0	78	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	7	0	0
T47	0	44	0	0
T48	0	214	0	0
T50	0	84	0	0
T54	0	253	0	0
T126	0	5	0	0
T150	0	42	0	0
T166	0	13	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	35	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T11	0	1	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	2	0	0
T54	0	1	0	0
T126	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7166706	0	0
T1	786	4	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7168589	0	0
T1	786	4	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	38	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T11	0	1	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T50	0	2	0	0
T54	0	1	0	0
T126	0	2	0	0
T150	0	1	0	0
T166	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	35	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T11	0	1	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	2	0	0
T54	0	1	0	0
T126	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	35	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T11	0	1	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	2	0	0
T54	0	1	0	0
T126	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	35	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T11	0	1	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T50	0	2	0	0
T54	0	1	0	0
T126	0	1	0	0
T150	0	1	0	0
T166	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	88035	0	0
T1	786	74	0	0
T2	510	0	0	0
T3	2489	0	0	0
T11	0	76	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	6	0	0
T47	0	42	0	0
T48	0	211	0	0
T50	0	81	0	0
T54	0	251	0	0
T126	0	4	0	0
T150	0	40	0	0
T166	0	12	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1954	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T4	425	3	0	0
T5	436	0	0	0
T6	528	7	0	0
T14	430	5	0	0
T15	506	5	0	0
T16	492	6	0	0
T17	407	0	0	0
T18	0	3	0	0
T19	0	4	0	0
T20	0	5	0	0
T63	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	17	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T48	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T126	0	1	0	0
T146	0	1	0	0
T161	0	2	0	0
T166	0	1	0	0
T177	0	1	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T6 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T6 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T25 T11 T53 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T6 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T6 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T6 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T6 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T6 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T6 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T6 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T6 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T25 T11 T53 
149        1/1                    cnt_en = 1'b1;
           Tests:       T25 T11 T53 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T25 T11 T53 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T25 T11 T53 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T25 T11 T53 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T53 T54 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T53 T54 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T53 T54 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T46 T185 T176 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T53 T54 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T53 T54 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T53 T54 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T53 T54 
191        1/1                      state_d = StableSt;
           Tests:       T11 T53 T54 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T53 T54 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T53 T54 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T53 T54 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T53 T54 
206        1/1                    state_d = IdleSt;
           Tests:       T53 T54 T45 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T53 T54 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T11,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T25,T11,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T53,T54

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T11,T53
1	0	Covered	T4,T6,T1
1	1	Covered	T25,T11,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T53,T54
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T53,T54
0	1	Covered	T53,T54,T51
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T53,T54
1	-	Covered	T53,T54,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T11,T53
DetectSt	168	Covered	T11,T53,T54
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T53,T54

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T53,T54
DebounceSt->IdleSt	163	Covered	T25,T46,T185
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T53,T54
IdleSt->DebounceSt	148	Covered	T25,T11,T53
StableSt->IdleSt	206	Covered	T53,T54,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T11,T53
0	1	Covered	T25,T11,T53
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T53,T54
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T11,T53
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T53,T54
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T185,T176
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T11,T53
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T53,T54
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T53,T54,T45
StableSt	-	-	-	-	-	-	0	Covered	T11,T53,T54
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	76	0	0
CntIncr_A	7758203	83370	0	0
CntNoWrap_A	7758203	7283486	0	0
DetectStDropOut_A	7758203	0	0	0
DetectedOut_A	7758203	13915	0	0
DetectedPulseOut_A	7758203	36	0	0
DisabledIdleSt_A	7758203	7106780	0	0
DisabledNoDetection_A	7758203	7108661	0	0
EnterDebounceSt_A	7758203	40	0	0
EnterDetectSt_A	7758203	36	0	0
EnterStableSt_A	7758203	36	0	0
PulseIsPulse_A	7758203	36	0	0
StayInStableSt	7758203	13863	0	0
gen_high_level_sva.HighLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	76	0	0
T10	478	0	0	0
T11	0	2	0	0
T25	7314	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	4	0	0
T51	0	4	0	0
T53	0	2	0	0
T54	0	6	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T149	0	2	0	0
T150	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	83370	0	0
T10	478	0	0	0
T11	0	40	0	0
T25	7314	33	0	0
T45	0	21	0	0
T46	0	89	0	0
T47	0	64	0	0
T51	0	170	0	0
T53	0	58	0	0
T54	0	93	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T149	0	32	0	0
T150	0	42	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283486	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	13915	0	0
T11	528	43	0	0
T12	7832	0	0	0
T13	505	0	0	0
T30	10288	0	0	0
T45	0	7	0	0
T47	0	105	0	0
T48	0	366	0	0
T51	0	2	0	0
T53	0	17	0	0
T54	0	95	0	0
T55	0	140	0	0
T76	495	0	0	0
T82	515	0	0	0
T149	0	41	0	0
T150	0	41	0	0
T186	425	0	0	0
T187	402	0	0	0
T188	406	0	0	0
T189	831	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	36	0	0
T11	528	1	0	0
T12	7832	0	0	0
T13	505	0	0	0
T30	10288	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	0	2	0	0
T76	495	0	0	0
T82	515	0	0	0
T149	0	1	0	0
T150	0	1	0	0
T186	425	0	0	0
T187	402	0	0	0
T188	406	0	0	0
T189	831	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7106780	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7108661	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	40	0	0
T10	478	0	0	0
T11	0	1	0	0
T25	7314	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	3	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T149	0	1	0	0
T150	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	36	0	0
T11	528	1	0	0
T12	7832	0	0	0
T13	505	0	0	0
T30	10288	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	0	2	0	0
T76	495	0	0	0
T82	515	0	0	0
T149	0	1	0	0
T150	0	1	0	0
T186	425	0	0	0
T187	402	0	0	0
T188	406	0	0	0
T189	831	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	36	0	0
T11	528	1	0	0
T12	7832	0	0	0
T13	505	0	0	0
T30	10288	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	0	2	0	0
T76	495	0	0	0
T82	515	0	0	0
T149	0	1	0	0
T150	0	1	0	0
T186	425	0	0	0
T187	402	0	0	0
T188	406	0	0	0
T189	831	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	36	0	0
T11	528	1	0	0
T12	7832	0	0	0
T13	505	0	0	0
T30	10288	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	3	0	0
T55	0	2	0	0
T76	495	0	0	0
T82	515	0	0	0
T149	0	1	0	0
T150	0	1	0	0
T186	425	0	0	0
T187	402	0	0	0
T188	406	0	0	0
T189	831	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	13863	0	0
T11	528	41	0	0
T12	7832	0	0	0
T13	505	0	0	0
T30	10288	0	0	0
T45	0	6	0	0
T47	0	102	0	0
T48	0	365	0	0
T53	0	16	0	0
T54	0	91	0	0
T55	0	137	0	0
T76	495	0	0	0
T82	515	0	0	0
T149	0	39	0	0
T150	0	39	0	0
T184	0	221	0	0
T186	425	0	0	0
T187	402	0	0	0
T188	406	0	0	0
T189	831	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	19	0	0
T43	8207	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	2	0	0
T53	585	1	0	0
T54	0	2	0	0
T55	0	1	0	0
T61	636	0	0	0
T85	523	0	0	0
T86	503	0	0	0
T127	478	0	0	0
T146	0	1	0	0
T179	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	727	0	0	0
T193	435	0	0	0
T194	502	0	0	0
T195	8510	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T6 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T25 T53 T49 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T25 T53 T49 
149        1/1                    cnt_en = 1'b1;
           Tests:       T25 T53 T49 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T25 T53 T49 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T25 T53 T49 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T25 T53 T49 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T53 T49 T45 
167        1/1                    if (trigger_active) begin
           Tests:       T53 T49 T45 
168        1/1                      state_d = DetectSt;
           Tests:       T53 T49 T45 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T196 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T53 T49 T45 
182        1/1                  cnt_en = 1'b1;
           Tests:       T53 T49 T45 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T53 T49 T45 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T53 T49 T45 
191        1/1                      state_d = StableSt;
           Tests:       T53 T49 T45 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T53 T49 T45 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T53 T49 T45 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T53 T49 T45 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T53 T49 T45 
206        1/1                    state_d = IdleSt;
           Tests:       T45 T55 T52 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T53 T49 T45 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T53,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T25,T53,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T53,T49,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T25,T11,T53
1	0	Covered	T4,T6,T1
1	1	Covered	T25,T53,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T53,T49,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T53,T49,T45
0	1	Covered	T55,T52,T181
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T53,T49,T45
1	-	Covered	T55,T52,T181

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T53,T49
DetectSt	168	Covered	T53,T49,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T53,T49,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T53,T49,T45
DebounceSt->IdleSt	163	Covered	T25,T196
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T53,T49,T45
IdleSt->DebounceSt	148	Covered	T25,T53,T49
StableSt->IdleSt	206	Covered	T49,T45,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T53,T49
0	1	Covered	T25,T53,T49
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T53,T49,T45
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T53,T49
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T53,T49,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T196
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T53,T49
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T53,T49,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T55,T52
StableSt	-	-	-	-	-	-	0	Covered	T53,T49,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	40	0	0
CntIncr_A	7758203	67303	0	0
CntNoWrap_A	7758203	7283522	0	0
DetectStDropOut_A	7758203	0	0	0
DetectedOut_A	7758203	58565	0	0
DetectedPulseOut_A	7758203	19	0	0
DisabledIdleSt_A	7758203	6836643	0	0
DisabledNoDetection_A	7758203	6838527	0	0
EnterDebounceSt_A	7758203	21	0	0
EnterDetectSt_A	7758203	19	0	0
EnterStableSt_A	7758203	19	0	0
PulseIsPulse_A	7758203	19	0	0
StayInStableSt	7758203	58536	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7758203	5426	0	0
gen_low_level_sva.LowLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	40	0	0
T10	478	0	0	0
T25	7314	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T55	0	2	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T165	0	4	0	0
T181	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	67303	0	0
T10	478	0	0	0
T25	7314	33	0	0
T45	0	21	0	0
T46	0	89	0	0
T48	0	79	0	0
T49	0	57	0	0
T52	0	92	0	0
T53	0	58	0	0
T55	0	57	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T165	0	48	0	0
T181	0	93	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283522	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	58565	0	0
T43	8207	0	0	0
T45	0	7	0	0
T46	0	416	0	0
T48	0	186	0	0
T49	0	45	0	0
T52	0	116	0	0
T53	585	42	0	0
T55	0	102	0	0
T61	636	0	0	0
T85	523	0	0	0
T86	503	0	0	0
T127	478	0	0	0
T165	0	87	0	0
T181	0	51	0	0
T182	0	41	0	0
T192	727	0	0	0
T193	435	0	0	0
T194	502	0	0	0
T195	8510	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	19	0	0
T43	8207	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	585	1	0	0
T55	0	1	0	0
T61	636	0	0	0
T85	523	0	0	0
T86	503	0	0	0
T127	478	0	0	0
T165	0	2	0	0
T181	0	1	0	0
T182	0	1	0	0
T192	727	0	0	0
T193	435	0	0	0
T194	502	0	0	0
T195	8510	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6836643	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6838527	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	21	0	0
T10	478	0	0	0
T25	7314	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T165	0	2	0	0
T181	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	19	0	0
T43	8207	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	585	1	0	0
T55	0	1	0	0
T61	636	0	0	0
T85	523	0	0	0
T86	503	0	0	0
T127	478	0	0	0
T165	0	2	0	0
T181	0	1	0	0
T182	0	1	0	0
T192	727	0	0	0
T193	435	0	0	0
T194	502	0	0	0
T195	8510	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	19	0	0
T43	8207	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	585	1	0	0
T55	0	1	0	0
T61	636	0	0	0
T85	523	0	0	0
T86	503	0	0	0
T127	478	0	0	0
T165	0	2	0	0
T181	0	1	0	0
T182	0	1	0	0
T192	727	0	0	0
T193	435	0	0	0
T194	502	0	0	0
T195	8510	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	19	0	0
T43	8207	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	585	1	0	0
T55	0	1	0	0
T61	636	0	0	0
T85	523	0	0	0
T86	503	0	0	0
T127	478	0	0	0
T165	0	2	0	0
T181	0	1	0	0
T182	0	1	0	0
T192	727	0	0	0
T193	435	0	0	0
T194	502	0	0	0
T195	8510	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	58536	0	0
T43	8207	0	0	0
T45	0	6	0	0
T46	0	414	0	0
T48	0	184	0	0
T49	0	43	0	0
T52	0	115	0	0
T53	585	40	0	0
T55	0	101	0	0
T61	636	0	0	0
T85	523	0	0	0
T86	503	0	0	0
T127	478	0	0	0
T165	0	85	0	0
T181	0	50	0	0
T182	0	39	0	0
T192	727	0	0	0
T193	435	0	0	0
T194	502	0	0	0
T195	8510	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	5426	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	11	0	0
T4	425	2	0	0
T5	436	0	0	0
T6	528	5	0	0
T14	430	2	0	0
T15	506	4	0	0
T16	492	4	0	0
T17	407	0	0	0
T19	0	10	0	0
T20	0	1	0	0
T63	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	8	0	0
T52	0	1	0	0
T55	933	1	0	0
T102	0	1	0	0
T104	5292	0	0	0
T154	0	1	0	0
T165	0	2	0	0
T181	0	1	0	0
T183	0	1	0	0
T185	3320	0	0	0
T197	428	0	0	0
T198	502	0	0	0
T199	499	0	0	0
T200	421	0	0	0
T201	749	0	0	0
T202	531	0	0	0
T203	505	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T9 T25 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T9 T25 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T9 T25 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T9 T25 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T9 T25 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T9 T25 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T11 T50 
167        1/1                    if (trigger_active) begin
           Tests:       T9 T11 T50 
168        1/1                      state_d = DetectSt;
           Tests:       T9 T11 T50 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T204 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T9 T11 T50 
182        1/1                  cnt_en = 1'b1;
           Tests:       T9 T11 T50 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T9 T11 T50 
186        1/1                    state_d = IdleSt;
           Tests:       T51 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T51 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T9 T11 T50 
191        1/1                      state_d = StableSt;
           Tests:       T9 T11 T50 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T9 T11 T50 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T9 T11 T50 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T9 T11 T50 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T9 T11 T50 
206        1/1                    state_d = IdleSt;
           Tests:       T9 T50 T45 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T9 T11 T50 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T25,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T25,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T11,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T25,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T25,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T50
0	1	Covered	T51
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T11,T50
0	1	Covered	T9,T50,T46
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T11,T50
1	-	Covered	T9,T50,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T25,T11
DetectSt	168	Covered	T9,T11,T50
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T11,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T11,T50
DebounceSt->IdleSt	163	Covered	T25,T204
DetectSt->IdleSt	186	Covered	T51
DetectSt->StableSt	191	Covered	T9,T11,T50
IdleSt->DebounceSt	148	Covered	T9,T25,T11
StableSt->IdleSt	206	Covered	T9,T50,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T25,T11
0	1	Covered	T9,T25,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T9,T11,T50
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T25,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T11,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T204
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T25,T11
DetectSt	-	-	-	-	1	-	-	Covered	T51
DetectSt	-	-	-	-	0	1	-	Covered	T9,T11,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T50,T45
StableSt	-	-	-	-	-	-	0	Covered	T9,T11,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	64	0	0
CntIncr_A	7758203	144591	0	0
CntNoWrap_A	7758203	7283498	0	0
DetectStDropOut_A	7758203	1	0	0
DetectedOut_A	7758203	103205	0	0
DetectedPulseOut_A	7758203	30	0	0
DisabledIdleSt_A	7758203	6783618	0	0
DisabledNoDetection_A	7758203	6785506	0	0
EnterDebounceSt_A	7758203	33	0	0
EnterDetectSt_A	7758203	31	0	0
EnterStableSt_A	7758203	30	0	0
PulseIsPulse_A	7758203	30	0	0
StayInStableSt	7758203	103165	0	0
gen_high_level_sva.HighLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	64	0	0
T9	744	2	0	0
T11	0	2	0	0
T25	7314	1	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	6	0	0
T50	0	4	0	0
T51	0	4	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T150	0	2	0	0
T205	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	144591	0	0
T9	744	31	0	0
T11	0	40	0	0
T25	7314	34	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	21	0	0
T46	0	89	0	0
T48	0	237	0	0
T50	0	106	0	0
T51	0	170	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T150	0	42	0	0
T205	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283498	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1	0	0
T44	35232	0	0	0
T51	8239	1	0	0
T56	37991	0	0	0
T57	8422	0	0	0
T71	906	0	0	0
T119	448	0	0	0
T206	743	0	0	0
T207	637	0	0	0
T208	426	0	0	0
T209	523	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	103205	0	0
T9	744	40	0	0
T11	0	79	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	7	0	0
T46	0	104	0	0
T48	0	90	0	0
T50	0	165	0	0
T51	0	137	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T150	0	113	0	0
T167	0	70	0	0
T205	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	30	0	0
T9	744	1	0	0
T11	0	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T50	0	2	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T150	0	1	0	0
T167	0	1	0	0
T205	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6783618	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6785506	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	33	0	0
T9	744	1	0	0
T11	0	1	0	0
T25	7314	1	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T50	0	2	0	0
T51	0	2	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T150	0	1	0	0
T205	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	31	0	0
T9	744	1	0	0
T11	0	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T50	0	2	0	0
T51	0	2	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T150	0	1	0	0
T167	0	1	0	0
T205	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	30	0	0
T9	744	1	0	0
T11	0	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T50	0	2	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T150	0	1	0	0
T167	0	1	0	0
T205	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	30	0	0
T9	744	1	0	0
T11	0	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	3	0	0
T50	0	2	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T150	0	1	0	0
T167	0	1	0	0
T205	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	103165	0	0
T9	744	39	0	0
T11	0	77	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	6	0	0
T46	0	103	0	0
T48	0	87	0	0
T50	0	162	0	0
T51	0	135	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T150	0	111	0	0
T167	0	68	0	0
T205	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	19	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T46	0	1	0	0
T48	0	3	0	0
T50	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T146	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0
T181	0	1	0	0
T183	0	2	0	0
T210	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T25 T53 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T25 T53 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T25 T53 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T25 T53 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T25 T53 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T25 T53 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T53 T45 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T53 T45 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T53 T45 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T165 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T53 T45 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T53 T45 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T53 T45 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T53 T45 
191        1/1                      state_d = StableSt;
           Tests:       T1 T53 T45 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T53 T45 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T53 T45 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T53 T45 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T53 T45 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T45 T47 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T53 T45 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T25,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T25,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T53,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T53
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T25,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T53,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T53,T45
0	1	Covered	T1,T47,T52
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T53,T45
1	-	Covered	T1,T47,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T25,T53
DetectSt	168	Covered	T1,T53,T45
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T53,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T53,T45
DebounceSt->IdleSt	163	Covered	T25,T165
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T53,T45
IdleSt->DebounceSt	148	Covered	T1,T25,T53
StableSt->IdleSt	206	Covered	T1,T45,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T25,T53
0	1	Covered	T1,T25,T53
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T53,T45
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T25,T53
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T53,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T165
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T25,T53
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T53,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T45,T47
StableSt	-	-	-	-	-	-	0	Covered	T1,T53,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	42	0	0
CntIncr_A	7758203	34694	0	0
CntNoWrap_A	7758203	7283520	0	0
DetectStDropOut_A	7758203	0	0	0
DetectedOut_A	7758203	28357	0	0
DetectedPulseOut_A	7758203	20	0	0
DisabledIdleSt_A	7758203	6998534	0	0
DisabledNoDetection_A	7758203	7000413	0	0
EnterDebounceSt_A	7758203	22	0	0
EnterDetectSt_A	7758203	20	0	0
EnterStableSt_A	7758203	20	0	0
PulseIsPulse_A	7758203	20	0	0
StayInStableSt	7758203	28323	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7758203	5047	0	0
gen_low_level_sva.LowLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	5	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	42	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T52	0	4	0	0
T53	0	2	0	0
T146	0	2	0	0
T161	0	2	0	0
T178	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	34694	0	0
T1	786	53	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	33	0	0
T45	0	21	0	0
T46	0	89	0	0
T47	0	32	0	0
T52	0	184	0	0
T53	0	58	0	0
T146	0	99	0	0
T161	0	15	0	0
T178	0	66	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283520	0	0
T1	786	383	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	28357	0	0
T1	786	43	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	6	0	0
T46	0	221	0	0
T47	0	43	0	0
T52	0	82	0	0
T53	0	41	0	0
T146	0	154	0	0
T161	0	126	0	0
T178	0	133	0	0
T204	0	165	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	20	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T146	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0
T204	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6998534	0	0
T1	786	4	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7000413	0	0
T1	786	4	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	22	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T146	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	20	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T146	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0
T204	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	20	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T146	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0
T204	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	20	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T146	0	1	0	0
T161	0	1	0	0
T178	0	1	0	0
T204	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	28323	0	0
T1	786	42	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	5	0	0
T46	0	219	0	0
T47	0	42	0	0
T52	0	79	0	0
T53	0	39	0	0
T146	0	152	0	0
T161	0	124	0	0
T178	0	131	0	0
T204	0	163	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	5047	0	0
T1	786	1	0	0
T2	510	1	0	0
T3	2489	0	0	0
T4	425	2	0	0
T5	436	1	0	0
T6	528	5	0	0
T14	430	4	0	0
T15	506	4	0	0
T16	492	8	0	0
T17	407	0	0	0
T19	0	9	0	0
T20	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	5	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T47	0	1	0	0
T52	0	1	0	0
T174	0	1	0	0
T211	0	1	0	0