Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T4 T5 T6
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T3 T28
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T5 T1 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T5 T1 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T1 T3 T28
149 1/1 cnt_en = 1'b1;
Tests: T1 T3 T28
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T3 T28
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T3 T28
163 1/1 state_d = IdleSt;
Tests: T25 T45
164 1/1 cnt_clr = 1'b1;
Tests: T25 T45
165 1/1 end else if (cnt_done) begin
Tests: T1 T3 T28
166 1/1 cnt_clr = 1'b1;
Tests: T1 T3 T28
167 1/1 if (trigger_active) begin
Tests: T1 T3 T28
168 1/1 state_d = DetectSt;
Tests: T1 T3 T28
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T29 T59 T69
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T3 T28
182 1/1 cnt_en = 1'b1;
Tests: T1 T3 T28
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T3 T28
186 1/1 state_d = IdleSt;
Tests: T68 T93 T72
187 1/1 cnt_clr = 1'b1;
Tests: T68 T93 T72
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T3 T28
191 1/1 state_d = StableSt;
Tests: T1 T3 T28
192 1/1 cnt_clr = 1'b1;
Tests: T1 T3 T28
193 1/1 event_detected_o = 1'b1;
Tests: T1 T3 T28
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T3 T28
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T3 T28
206 1/1 state_d = IdleSt;
Tests: T1 T3 T28
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T3 T28
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T6
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T3 T7
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T5 T1 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T5 T1 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T1 T3 T7
149 1/1 cnt_en = 1'b1;
Tests: T1 T3 T7
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T3 T7
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T3 T7
163 1/1 state_d = IdleSt;
Tests: T25 T45
164 1/1 cnt_clr = 1'b1;
Tests: T25 T45
165 1/1 end else if (cnt_done) begin
Tests: T1 T3 T7
166 1/1 cnt_clr = 1'b1;
Tests: T1 T3 T7
167 1/1 if (trigger_active) begin
Tests: T1 T3 T7
168 1/1 state_d = DetectSt;
Tests: T1 T3 T7
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T7 T9 T11
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T3 T7
182 1/1 cnt_en = 1'b1;
Tests: T1 T3 T7
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T3 T7
186 1/1 state_d = IdleSt;
Tests: T7 T51 T94
187 1/1 cnt_clr = 1'b1;
Tests: T7 T51 T94
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T3 T9
191 1/1 state_d = StableSt;
Tests: T1 T3 T9
192 1/1 cnt_clr = 1'b1;
Tests: T1 T3 T9
193 1/1 event_detected_o = 1'b1;
Tests: T1 T3 T9
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T3 T9
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T3 T9
206 1/1 state_d = IdleSt;
Tests: T1 T3 T38
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T3 T9
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 41 | 95.35 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 30 | 93.75 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T6 T1
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T4 T6 T1
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T3 T7 T25
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T3 T7 T25
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T3 T7 T25
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T6 T1
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T6 T1
129 1/1 cnt_en = 1'b0;
Tests: T4 T6 T1
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T6 T1
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T6 T1
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T6 T1
139
140 1/1 unique case (state_q)
Tests: T4 T6 T1
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T6 T1
148 1/1 state_d = DebounceSt;
Tests: T3 T7 T25
149 1/1 cnt_en = 1'b1;
Tests: T3 T7 T25
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T3 T7 T25
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T3 T7 T25
163 1/1 state_d = IdleSt;
Tests: T25 T45
164 1/1 cnt_clr = 1'b1;
Tests: T25 T45
165 1/1 end else if (cnt_done) begin
Tests: T3 T7 T25
166 1/1 cnt_clr = 1'b1;
Tests: T3 T7 T38
167 1/1 if (trigger_active) begin
Tests: T3 T7 T38
168 1/1 state_d = DetectSt;
Tests: T3 T7 T68
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T38 T95 T96
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T3 T7 T68
182 1/1 cnt_en = 1'b1;
Tests: T3 T7 T68
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T3 T7 T68
186 0/1 ==> state_d = IdleSt;
187 0/1 ==> cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T3 T7 T68
191 1/1 state_d = StableSt;
Tests: T3 T7 T68
192 1/1 cnt_clr = 1'b1;
Tests: T3 T7 T68
193 1/1 event_detected_o = 1'b1;
Tests: T3 T7 T68
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T3 T7 T68
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T3 T7 T68
206 1/1 state_d = IdleSt;
Tests: T3 T7 T68
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T3 T7 T68
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T25 T30 T31
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T25 T30 T31
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T8 T25
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T5 T1 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T5 T1 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T2 T8 T25
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T2 T8 T25
129 1/1 cnt_en = 1'b0;
Tests: T2 T8 T25
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T2 T8 T25
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T2 T8 T25
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T2 T8 T25
139
140 1/1 unique case (state_q)
Tests: T2 T8 T25
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T2 T8 T25
148 1/1 state_d = DebounceSt;
Tests: T2 T8 T25
149 1/1 cnt_en = 1'b1;
Tests: T2 T8 T25
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T8 T25
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T8 T25
163 1/1 state_d = IdleSt;
Tests: T25 T45
164 1/1 cnt_clr = 1'b1;
Tests: T25 T45
165 1/1 end else if (cnt_done) begin
Tests: T2 T8 T25
166 1/1 cnt_clr = 1'b1;
Tests: T2 T8 T25
167 1/1 if (trigger_active) begin
Tests: T2 T8 T25
168 1/1 state_d = DetectSt;
Tests: T2 T8 T25
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T25 T45 T97
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T8 T25
182 1/1 cnt_en = 1'b1;
Tests: T2 T8 T25
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T8 T25
186 1/1 state_d = IdleSt;
Tests: T25 T30 T31
187 1/1 cnt_clr = 1'b1;
Tests: T25 T30 T31
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T8 T25
191 1/1 state_d = StableSt;
Tests: T2 T8 T25
192 1/1 cnt_clr = 1'b1;
Tests: T2 T8 T25
193 1/1 event_detected_o = 1'b1;
Tests: T2 T8 T25
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T8 T25
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T8 T25
206 1/1 state_d = IdleSt;
Tests: T25 T30 T45
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T8 T25
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T5 T2 T32
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T5 T2 T32
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T5 T1 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T5 T1 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T5 T2 T32
149 1/1 cnt_en = 1'b1;
Tests: T5 T2 T32
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T5 T2 T32
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T5 T2 T32
163 1/1 state_d = IdleSt;
Tests: T25 T45
164 1/1 cnt_clr = 1'b1;
Tests: T25 T45
165 1/1 end else if (cnt_done) begin
Tests: T5 T2 T32
166 1/1 cnt_clr = 1'b1;
Tests: T5 T2 T32
167 1/1 if (trigger_active) begin
Tests: T5 T2 T32
168 1/1 state_d = DetectSt;
Tests: T2 T8 T25
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T5 T32 T58
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T8 T25
182 1/1 cnt_en = 1'b1;
Tests: T2 T8 T25
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T8 T25
186 1/1 state_d = IdleSt;
Tests: T25 T12 T45
187 1/1 cnt_clr = 1'b1;
Tests: T25 T12 T45
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T8 T25
191 1/1 state_d = StableSt;
Tests: T2 T8 T25
192 1/1 cnt_clr = 1'b1;
Tests: T2 T8 T25
193 1/1 event_detected_o = 1'b1;
Tests: T2 T8 T25
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T8 T25
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T8 T25
206 1/1 state_d = IdleSt;
Tests: T2 T8 T25
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T8 T25
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T2,T32 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T2,T32 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T2,T32 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T2,T32 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T8,T25 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T2,T32 |
| 1 | 0 | Covered | T66,T26,T70 |
| 1 | 1 | Covered | T5,T2,T32 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T8,T25 |
| 0 | 1 | Covered | T12,T45,T44 |
| 1 | 0 | Covered | T25,T45 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T8,T25 |
| 0 | 1 | Covered | T2,T8,T25 |
| 1 | 0 | Covered | T25,T45 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T2,T8,T25 |
| 1 | - | Covered | T2,T8,T25 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T28,T9 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T28,T9 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T28,T9 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T28,T9 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T1,T28,T9 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T28,T9 |
| 0 | 1 | Covered | T93,T98,T99 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T28,T9 |
| 0 | 1 | Covered | T1,T28,T9 |
| 1 | 0 | Covered | T45 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T28,T9 |
| 1 | - | Covered | T1,T28,T9 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T25,T30,T31 |
| 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T8,T25 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T8,T25 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T8,T25 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T25,T30,T31 |
| 1 | 0 | Covered | T25,T30,T45 |
| 1 | 1 | Covered | T2,T8,T25 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T8,T25 |
| 0 | 1 | Covered | T25,T30,T31 |
| 1 | 0 | Covered | T25,T30,T45 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T8,T25 |
| 0 | 1 | Covered | T25,T30,T45 |
| 1 | 0 | Covered | T25,T45,T100 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T2,T8,T25 |
| 1 | - | Covered | T25,T30,T45 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 14 | 87.50 |
| Logical | 16 | 14 | 87.50 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T6,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T7,T25 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T7,T25 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T7,T68 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T7,T25 |
| 1 | 0 | Covered | T4,T6,T1 |
| 1 | 1 | Covered | T3,T7,T25 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T7,T68 |
| 0 | 1 | Not Covered | |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T7,T68 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T7,T68 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T9,T25 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T9,T25 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T9,T11 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T9,T25 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T1,T9,T25 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T9,T11 |
| 0 | 1 | Covered | T51,T101,T102 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T9,T11 |
| 0 | 1 | Covered | T1,T9,T53 |
| 1 | 0 | Covered | T45 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T9,T11 |
| 1 | - | Covered | T1,T9,T53 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T6,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T6,T1 |
| 1 | 1 | Covered | T4,T6,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T7,T25 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T7,T25 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T7,T38 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T7,T25 |
| 1 | 0 | Covered | T4,T6,T1 |
| 1 | 1 | Covered | T3,T7,T25 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T38,T68 |
| 0 | 1 | Covered | T7,T94,T95 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T38,T68 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T38,T68 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T1 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T6,T1 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T7,T25 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T7,T25 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T7,T38 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T7,T25 |
| 1 | 0 | Covered | T4,T6,T14 |
| 1 | 1 | Covered | T3,T7,T25 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T7,T38 |
| 0 | 1 | Covered | T68,T72,T92 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T7,T38 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T7,T38 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DebounceSt |
148 |
Covered |
T1,T28,T9 |
| DetectSt |
168 |
Covered |
T1,T28,T9 |
| IdleSt |
163 |
Covered |
T4,T5,T6 |
| StableSt |
191 |
Covered |
T1,T28,T9 |
| transitions | Line No. | Covered | Tests |
| DebounceSt->DetectSt |
168 |
Covered |
T1,T28,T9 |
| DebounceSt->IdleSt |
163 |
Covered |
T29,T25,T59 |
| DetectSt->IdleSt |
186 |
Covered |
T7,T68,T51 |
| DetectSt->StableSt |
191 |
Covered |
T1,T28,T9 |
| IdleSt->DebounceSt |
148 |
Covered |
T1,T28,T9 |
| StableSt->IdleSt |
206 |
Covered |
T1,T28,T9 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T28,T9 |
| 0 |
1 |
Covered |
T1,T28,T9 |
| 0 |
0 |
Covered |
T4,T5,T6 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T28,T9 |
| 0 |
Covered |
T4,T5,T6 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T28,T9 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T25,T45 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T1,T28,T9 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T29,T59,T69 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T28,T9 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T7,T68,T51 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T1,T28,T9 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T2,T8,T25 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T28,T9 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T28,T9 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T2,T3,T8 |
| 0 |
1 |
Covered |
T2,T3,T8 |
| 0 |
0 |
Covered |
T4,T5,T6 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T2,T3,T8 |
| 0 |
Covered |
T4,T5,T6 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T2,T3,T8 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T6,T1 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T25,T45 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T2,T3,T8 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T25,T38,T45 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T2,T3,T8 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T25,T30,T31 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T2,T3,T8 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T2,T8,T25 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T3,T7,T25 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T2,T3,T8 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
16036 |
0 |
0 |
| T1 |
786 |
0 |
0 |
0 |
| T2 |
1020 |
4 |
0 |
0 |
| T3 |
4978 |
0 |
0 |
0 |
| T5 |
436 |
1 |
0 |
0 |
| T6 |
528 |
0 |
0 |
0 |
| T7 |
2664 |
0 |
0 |
0 |
| T8 |
505 |
4 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T13 |
0 |
4 |
0 |
0 |
| T14 |
430 |
0 |
0 |
0 |
| T15 |
1012 |
0 |
0 |
0 |
| T16 |
984 |
0 |
0 |
0 |
| T17 |
814 |
0 |
0 |
0 |
| T18 |
1228 |
0 |
0 |
0 |
| T19 |
496 |
0 |
0 |
0 |
| T25 |
0 |
25 |
0 |
0 |
| T27 |
509 |
0 |
0 |
0 |
| T28 |
1238 |
2 |
0 |
0 |
| T29 |
0 |
5 |
0 |
0 |
| T30 |
0 |
62 |
0 |
0 |
| T31 |
0 |
58 |
0 |
0 |
| T32 |
445 |
1 |
0 |
0 |
| T45 |
0 |
18 |
0 |
0 |
| T49 |
0 |
4 |
0 |
0 |
| T51 |
0 |
2 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T59 |
0 |
3 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T61 |
0 |
4 |
0 |
0 |
| T62 |
0 |
4 |
0 |
0 |
| T63 |
844 |
0 |
0 |
0 |
| T64 |
448 |
0 |
0 |
0 |
| T65 |
795 |
0 |
0 |
0 |
| T66 |
746 |
0 |
0 |
0 |
| T67 |
523 |
0 |
0 |
0 |
| T103 |
0 |
1 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
2265541 |
0 |
0 |
| T1 |
786 |
0 |
0 |
0 |
| T2 |
1020 |
46 |
0 |
0 |
| T3 |
4978 |
0 |
0 |
0 |
| T5 |
436 |
20 |
0 |
0 |
| T6 |
528 |
0 |
0 |
0 |
| T7 |
2664 |
0 |
0 |
0 |
| T8 |
505 |
46 |
0 |
0 |
| T10 |
0 |
25 |
0 |
0 |
| T12 |
0 |
88 |
0 |
0 |
| T13 |
0 |
46 |
0 |
0 |
| T14 |
430 |
0 |
0 |
0 |
| T15 |
1012 |
0 |
0 |
0 |
| T16 |
984 |
0 |
0 |
0 |
| T17 |
814 |
0 |
0 |
0 |
| T18 |
1228 |
0 |
0 |
0 |
| T19 |
496 |
0 |
0 |
0 |
| T25 |
0 |
840 |
0 |
0 |
| T27 |
509 |
0 |
0 |
0 |
| T28 |
1238 |
53 |
0 |
0 |
| T29 |
0 |
112 |
0 |
0 |
| T30 |
0 |
1375 |
0 |
0 |
| T31 |
0 |
1533 |
0 |
0 |
| T32 |
445 |
20 |
0 |
0 |
| T45 |
0 |
494 |
0 |
0 |
| T49 |
0 |
112 |
0 |
0 |
| T51 |
0 |
25 |
0 |
0 |
| T58 |
0 |
41 |
0 |
0 |
| T59 |
0 |
43 |
0 |
0 |
| T60 |
0 |
44 |
0 |
0 |
| T61 |
0 |
64 |
0 |
0 |
| T62 |
0 |
161 |
0 |
0 |
| T63 |
844 |
0 |
0 |
0 |
| T64 |
448 |
0 |
0 |
0 |
| T65 |
795 |
0 |
0 |
0 |
| T66 |
746 |
0 |
0 |
0 |
| T67 |
523 |
0 |
0 |
0 |
| T103 |
0 |
20 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
189356576 |
0 |
0 |
| T1 |
20436 |
9994 |
0 |
0 |
| T2 |
13260 |
2830 |
0 |
0 |
| T3 |
64714 |
54282 |
0 |
0 |
| T4 |
11050 |
624 |
0 |
0 |
| T5 |
11336 |
909 |
0 |
0 |
| T6 |
13728 |
3302 |
0 |
0 |
| T14 |
11180 |
754 |
0 |
0 |
| T15 |
13156 |
2730 |
0 |
0 |
| T16 |
12792 |
2366 |
0 |
0 |
| T17 |
10582 |
156 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
2173 |
0 |
0 |
| T25 |
7314 |
1 |
0 |
0 |
| T30 |
0 |
15 |
0 |
0 |
| T31 |
0 |
29 |
0 |
0 |
| T39 |
0 |
1 |
0 |
0 |
| T41 |
6177 |
0 |
0 |
0 |
| T44 |
0 |
10 |
0 |
0 |
| T45 |
6987 |
2 |
0 |
0 |
| T48 |
0 |
1 |
0 |
0 |
| T51 |
8239 |
0 |
0 |
0 |
| T57 |
0 |
4 |
0 |
0 |
| T72 |
880 |
0 |
0 |
0 |
| T78 |
494 |
0 |
0 |
0 |
| T79 |
493 |
0 |
0 |
0 |
| T93 |
646 |
1 |
0 |
0 |
| T98 |
0 |
1 |
0 |
0 |
| T99 |
0 |
1 |
0 |
0 |
| T104 |
0 |
9 |
0 |
0 |
| T105 |
0 |
3 |
0 |
0 |
| T106 |
0 |
5 |
0 |
0 |
| T107 |
0 |
7 |
0 |
0 |
| T108 |
0 |
2 |
0 |
0 |
| T109 |
0 |
2 |
0 |
0 |
| T110 |
0 |
2 |
0 |
0 |
| T111 |
0 |
1 |
0 |
0 |
| T112 |
0 |
1 |
0 |
0 |
| T113 |
0 |
1 |
0 |
0 |
| T114 |
1908 |
0 |
0 |
0 |
| T115 |
408 |
0 |
0 |
0 |
| T116 |
421 |
0 |
0 |
0 |
| T117 |
504 |
0 |
0 |
0 |
| T118 |
526 |
0 |
0 |
0 |
| T119 |
448 |
0 |
0 |
0 |
| T120 |
8402 |
0 |
0 |
0 |
| T121 |
1756 |
0 |
0 |
0 |
| T122 |
533 |
0 |
0 |
0 |
| T123 |
2656 |
0 |
0 |
0 |
| T124 |
500 |
0 |
0 |
0 |
| T125 |
438 |
0 |
0 |
0 |
| T126 |
587 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
1817829 |
0 |
0 |
| T2 |
1020 |
87 |
0 |
0 |
| T3 |
4978 |
0 |
0 |
0 |
| T7 |
2664 |
0 |
0 |
0 |
| T8 |
505 |
83 |
0 |
0 |
| T10 |
0 |
4 |
0 |
0 |
| T12 |
0 |
36 |
0 |
0 |
| T13 |
0 |
84 |
0 |
0 |
| T15 |
1012 |
0 |
0 |
0 |
| T16 |
984 |
0 |
0 |
0 |
| T17 |
814 |
0 |
0 |
0 |
| T18 |
1228 |
0 |
0 |
0 |
| T19 |
992 |
0 |
0 |
0 |
| T20 |
844 |
0 |
0 |
0 |
| T25 |
7314 |
402 |
0 |
0 |
| T27 |
509 |
0 |
0 |
0 |
| T28 |
1857 |
6 |
0 |
0 |
| T29 |
0 |
14 |
0 |
0 |
| T32 |
445 |
0 |
0 |
0 |
| T41 |
0 |
533 |
0 |
0 |
| T45 |
0 |
497 |
0 |
0 |
| T49 |
0 |
17 |
0 |
0 |
| T51 |
0 |
5 |
0 |
0 |
| T58 |
0 |
36 |
0 |
0 |
| T59 |
0 |
9 |
0 |
0 |
| T60 |
0 |
2 |
0 |
0 |
| T61 |
0 |
13 |
0 |
0 |
| T62 |
0 |
15 |
0 |
0 |
| T63 |
1266 |
0 |
0 |
0 |
| T64 |
448 |
0 |
0 |
0 |
| T65 |
795 |
0 |
0 |
0 |
| T66 |
746 |
0 |
0 |
0 |
| T67 |
523 |
0 |
0 |
0 |
| T80 |
513 |
0 |
0 |
0 |
| T86 |
0 |
80 |
0 |
0 |
| T90 |
447 |
0 |
0 |
0 |
| T93 |
0 |
2 |
0 |
0 |
| T127 |
0 |
4 |
0 |
0 |
| T128 |
0 |
9 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
4871 |
0 |
0 |
| T2 |
1020 |
2 |
0 |
0 |
| T3 |
4978 |
0 |
0 |
0 |
| T7 |
2664 |
0 |
0 |
0 |
| T8 |
505 |
2 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T15 |
1012 |
0 |
0 |
0 |
| T16 |
984 |
0 |
0 |
0 |
| T17 |
814 |
0 |
0 |
0 |
| T18 |
1228 |
0 |
0 |
0 |
| T19 |
992 |
0 |
0 |
0 |
| T20 |
844 |
0 |
0 |
0 |
| T25 |
7314 |
6 |
0 |
0 |
| T27 |
509 |
0 |
0 |
0 |
| T28 |
1857 |
1 |
0 |
0 |
| T29 |
0 |
2 |
0 |
0 |
| T32 |
445 |
0 |
0 |
0 |
| T41 |
0 |
10 |
0 |
0 |
| T45 |
0 |
6 |
0 |
0 |
| T49 |
0 |
2 |
0 |
0 |
| T51 |
0 |
1 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T59 |
0 |
1 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
2 |
0 |
0 |
| T63 |
1266 |
0 |
0 |
0 |
| T64 |
448 |
0 |
0 |
0 |
| T65 |
795 |
0 |
0 |
0 |
| T66 |
746 |
0 |
0 |
0 |
| T67 |
523 |
0 |
0 |
0 |
| T80 |
513 |
0 |
0 |
0 |
| T86 |
0 |
2 |
0 |
0 |
| T90 |
447 |
0 |
0 |
0 |
| T93 |
0 |
1 |
0 |
0 |
| T127 |
0 |
1 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
178308091 |
0 |
0 |
| T1 |
20436 |
7343 |
0 |
0 |
| T2 |
13260 |
2646 |
0 |
0 |
| T3 |
64714 |
51468 |
0 |
0 |
| T4 |
11050 |
624 |
0 |
0 |
| T5 |
11336 |
879 |
0 |
0 |
| T6 |
13728 |
3302 |
0 |
0 |
| T14 |
11180 |
754 |
0 |
0 |
| T15 |
13156 |
2730 |
0 |
0 |
| T16 |
12792 |
2366 |
0 |
0 |
| T17 |
10582 |
156 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
178354299 |
0 |
0 |
| T1 |
20436 |
7362 |
0 |
0 |
| T2 |
13260 |
2670 |
0 |
0 |
| T3 |
64714 |
51494 |
0 |
0 |
| T4 |
11050 |
650 |
0 |
0 |
| T5 |
11336 |
904 |
0 |
0 |
| T6 |
13728 |
3328 |
0 |
0 |
| T14 |
11180 |
780 |
0 |
0 |
| T15 |
13156 |
2756 |
0 |
0 |
| T16 |
12792 |
2392 |
0 |
0 |
| T17 |
10582 |
182 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
8251 |
0 |
0 |
| T1 |
786 |
0 |
0 |
0 |
| T2 |
1020 |
2 |
0 |
0 |
| T3 |
4978 |
0 |
0 |
0 |
| T5 |
436 |
1 |
0 |
0 |
| T6 |
528 |
0 |
0 |
0 |
| T7 |
2664 |
0 |
0 |
0 |
| T8 |
505 |
2 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T14 |
430 |
0 |
0 |
0 |
| T15 |
1012 |
0 |
0 |
0 |
| T16 |
984 |
0 |
0 |
0 |
| T17 |
814 |
0 |
0 |
0 |
| T18 |
1228 |
0 |
0 |
0 |
| T19 |
496 |
0 |
0 |
0 |
| T25 |
0 |
15 |
0 |
0 |
| T27 |
509 |
0 |
0 |
0 |
| T28 |
1238 |
1 |
0 |
0 |
| T29 |
0 |
3 |
0 |
0 |
| T30 |
0 |
31 |
0 |
0 |
| T31 |
0 |
29 |
0 |
0 |
| T32 |
445 |
1 |
0 |
0 |
| T45 |
0 |
11 |
0 |
0 |
| T49 |
0 |
2 |
0 |
0 |
| T51 |
0 |
1 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
2 |
0 |
0 |
| T63 |
844 |
0 |
0 |
0 |
| T64 |
448 |
0 |
0 |
0 |
| T65 |
795 |
0 |
0 |
0 |
| T66 |
746 |
0 |
0 |
0 |
| T67 |
523 |
0 |
0 |
0 |
| T103 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
7792 |
0 |
0 |
| T2 |
1020 |
2 |
0 |
0 |
| T3 |
4978 |
0 |
0 |
0 |
| T7 |
2664 |
0 |
0 |
0 |
| T8 |
505 |
2 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T15 |
1012 |
0 |
0 |
0 |
| T16 |
984 |
0 |
0 |
0 |
| T17 |
814 |
0 |
0 |
0 |
| T18 |
1228 |
0 |
0 |
0 |
| T19 |
992 |
0 |
0 |
0 |
| T20 |
844 |
0 |
0 |
0 |
| T25 |
7314 |
10 |
0 |
0 |
| T27 |
509 |
0 |
0 |
0 |
| T28 |
1857 |
1 |
0 |
0 |
| T29 |
0 |
2 |
0 |
0 |
| T32 |
445 |
0 |
0 |
0 |
| T41 |
0 |
10 |
0 |
0 |
| T45 |
0 |
10 |
0 |
0 |
| T49 |
0 |
2 |
0 |
0 |
| T51 |
0 |
1 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T59 |
0 |
1 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
2 |
0 |
0 |
| T63 |
1266 |
0 |
0 |
0 |
| T64 |
448 |
0 |
0 |
0 |
| T65 |
795 |
0 |
0 |
0 |
| T66 |
746 |
0 |
0 |
0 |
| T67 |
523 |
0 |
0 |
0 |
| T80 |
513 |
0 |
0 |
0 |
| T86 |
0 |
2 |
0 |
0 |
| T90 |
447 |
0 |
0 |
0 |
| T93 |
0 |
2 |
0 |
0 |
| T127 |
0 |
1 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
4871 |
0 |
0 |
| T2 |
1020 |
2 |
0 |
0 |
| T3 |
4978 |
0 |
0 |
0 |
| T7 |
2664 |
0 |
0 |
0 |
| T8 |
505 |
2 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T15 |
1012 |
0 |
0 |
0 |
| T16 |
984 |
0 |
0 |
0 |
| T17 |
814 |
0 |
0 |
0 |
| T18 |
1228 |
0 |
0 |
0 |
| T19 |
992 |
0 |
0 |
0 |
| T20 |
844 |
0 |
0 |
0 |
| T25 |
7314 |
6 |
0 |
0 |
| T27 |
509 |
0 |
0 |
0 |
| T28 |
1857 |
1 |
0 |
0 |
| T29 |
0 |
2 |
0 |
0 |
| T32 |
445 |
0 |
0 |
0 |
| T41 |
0 |
10 |
0 |
0 |
| T45 |
0 |
6 |
0 |
0 |
| T49 |
0 |
2 |
0 |
0 |
| T51 |
0 |
1 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T59 |
0 |
1 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
2 |
0 |
0 |
| T63 |
1266 |
0 |
0 |
0 |
| T64 |
448 |
0 |
0 |
0 |
| T65 |
795 |
0 |
0 |
0 |
| T66 |
746 |
0 |
0 |
0 |
| T67 |
523 |
0 |
0 |
0 |
| T80 |
513 |
0 |
0 |
0 |
| T86 |
0 |
2 |
0 |
0 |
| T90 |
447 |
0 |
0 |
0 |
| T93 |
0 |
1 |
0 |
0 |
| T127 |
0 |
1 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
4871 |
0 |
0 |
| T2 |
1020 |
2 |
0 |
0 |
| T3 |
4978 |
0 |
0 |
0 |
| T7 |
2664 |
0 |
0 |
0 |
| T8 |
505 |
2 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T15 |
1012 |
0 |
0 |
0 |
| T16 |
984 |
0 |
0 |
0 |
| T17 |
814 |
0 |
0 |
0 |
| T18 |
1228 |
0 |
0 |
0 |
| T19 |
992 |
0 |
0 |
0 |
| T20 |
844 |
0 |
0 |
0 |
| T25 |
7314 |
6 |
0 |
0 |
| T27 |
509 |
0 |
0 |
0 |
| T28 |
1857 |
1 |
0 |
0 |
| T29 |
0 |
2 |
0 |
0 |
| T32 |
445 |
0 |
0 |
0 |
| T41 |
0 |
10 |
0 |
0 |
| T45 |
0 |
6 |
0 |
0 |
| T49 |
0 |
2 |
0 |
0 |
| T51 |
0 |
1 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T59 |
0 |
1 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
2 |
0 |
0 |
| T63 |
1266 |
0 |
0 |
0 |
| T64 |
448 |
0 |
0 |
0 |
| T65 |
795 |
0 |
0 |
0 |
| T66 |
746 |
0 |
0 |
0 |
| T67 |
523 |
0 |
0 |
0 |
| T80 |
513 |
0 |
0 |
0 |
| T86 |
0 |
2 |
0 |
0 |
| T90 |
447 |
0 |
0 |
0 |
| T93 |
0 |
1 |
0 |
0 |
| T127 |
0 |
1 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
201713278 |
1812269 |
0 |
0 |
| T2 |
1020 |
84 |
0 |
0 |
| T3 |
4978 |
0 |
0 |
0 |
| T7 |
2664 |
0 |
0 |
0 |
| T8 |
505 |
80 |
0 |
0 |
| T10 |
0 |
3 |
0 |
0 |
| T12 |
0 |
35 |
0 |
0 |
| T13 |
0 |
81 |
0 |
0 |
| T15 |
1012 |
0 |
0 |
0 |
| T16 |
984 |
0 |
0 |
0 |
| T17 |
814 |
0 |
0 |
0 |
| T18 |
1228 |
0 |
0 |
0 |
| T19 |
992 |
0 |
0 |
0 |
| T20 |
844 |
0 |
0 |
0 |
| T25 |
7314 |
396 |
0 |
0 |
| T27 |
509 |
0 |
0 |
0 |
| T28 |
1857 |
5 |
0 |
0 |
| T29 |
0 |
12 |
0 |
0 |
| T32 |
445 |
0 |
0 |
0 |
| T41 |
0 |
523 |
0 |
0 |
| T45 |
0 |
491 |
0 |
0 |
| T49 |
0 |
15 |
0 |
0 |
| T51 |
0 |
4 |
0 |
0 |
| T58 |
0 |
34 |
0 |
0 |
| T59 |
0 |
8 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
11 |
0 |
0 |
| T62 |
0 |
13 |
0 |
0 |
| T63 |
1266 |
0 |
0 |
0 |
| T64 |
448 |
0 |
0 |
0 |
| T65 |
795 |
0 |
0 |
0 |
| T66 |
746 |
0 |
0 |
0 |
| T67 |
523 |
0 |
0 |
0 |
| T80 |
513 |
0 |
0 |
0 |
| T86 |
0 |
77 |
0 |
0 |
| T90 |
447 |
0 |
0 |
0 |
| T93 |
0 |
1 |
0 |
0 |
| T127 |
0 |
3 |
0 |
0 |
| T128 |
0 |
8 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
69823827 |
40476 |
0 |
0 |
| T1 |
7074 |
7 |
0 |
0 |
| T2 |
4590 |
3 |
0 |
0 |
| T3 |
22401 |
44 |
0 |
0 |
| T4 |
3825 |
23 |
0 |
0 |
| T5 |
3924 |
3 |
0 |
0 |
| T6 |
4752 |
45 |
0 |
0 |
| T14 |
3870 |
32 |
0 |
0 |
| T15 |
4554 |
40 |
0 |
0 |
| T16 |
4428 |
61 |
0 |
0 |
| T17 |
3663 |
0 |
0 |
0 |
| T18 |
0 |
3 |
0 |
0 |
| T19 |
0 |
69 |
0 |
0 |
| T20 |
0 |
22 |
0 |
0 |
| T28 |
0 |
9 |
0 |
0 |
| T63 |
0 |
15 |
0 |
0 |
| T64 |
0 |
7 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
38791015 |
36427375 |
0 |
0 |
| T1 |
3930 |
1930 |
0 |
0 |
| T2 |
2550 |
550 |
0 |
0 |
| T3 |
12445 |
10445 |
0 |
0 |
| T4 |
2125 |
125 |
0 |
0 |
| T5 |
2180 |
180 |
0 |
0 |
| T6 |
2640 |
640 |
0 |
0 |
| T14 |
2150 |
150 |
0 |
0 |
| T15 |
2530 |
530 |
0 |
0 |
| T16 |
2460 |
460 |
0 |
0 |
| T17 |
2035 |
35 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
131889451 |
123853075 |
0 |
0 |
| T1 |
13362 |
6562 |
0 |
0 |
| T2 |
8670 |
1870 |
0 |
0 |
| T3 |
42313 |
35513 |
0 |
0 |
| T4 |
7225 |
425 |
0 |
0 |
| T5 |
7412 |
612 |
0 |
0 |
| T6 |
8976 |
2176 |
0 |
0 |
| T14 |
7310 |
510 |
0 |
0 |
| T15 |
8602 |
1802 |
0 |
0 |
| T16 |
8364 |
1564 |
0 |
0 |
| T17 |
6919 |
119 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
69823827 |
65569275 |
0 |
0 |
| T1 |
7074 |
3474 |
0 |
0 |
| T2 |
4590 |
990 |
0 |
0 |
| T3 |
22401 |
18801 |
0 |
0 |
| T4 |
3825 |
225 |
0 |
0 |
| T5 |
3924 |
324 |
0 |
0 |
| T6 |
4752 |
1152 |
0 |
0 |
| T14 |
3870 |
270 |
0 |
0 |
| T15 |
4554 |
954 |
0 |
0 |
| T16 |
4428 |
828 |
0 |
0 |
| T17 |
3663 |
63 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
178438669 |
4035 |
0 |
0 |
| T2 |
510 |
1 |
0 |
0 |
| T3 |
2489 |
0 |
0 |
0 |
| T7 |
2664 |
0 |
0 |
0 |
| T8 |
505 |
1 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T15 |
506 |
0 |
0 |
0 |
| T16 |
492 |
0 |
0 |
0 |
| T17 |
407 |
0 |
0 |
0 |
| T18 |
614 |
0 |
0 |
0 |
| T19 |
496 |
0 |
0 |
0 |
| T20 |
422 |
0 |
0 |
0 |
| T25 |
7314 |
5 |
0 |
0 |
| T27 |
509 |
0 |
0 |
0 |
| T28 |
1238 |
1 |
0 |
0 |
| T29 |
0 |
2 |
0 |
0 |
| T32 |
445 |
0 |
0 |
0 |
| T41 |
0 |
10 |
0 |
0 |
| T45 |
0 |
5 |
0 |
0 |
| T49 |
0 |
2 |
0 |
0 |
| T51 |
0 |
1 |
0 |
0 |
| T59 |
0 |
1 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
2 |
0 |
0 |
| T63 |
844 |
0 |
0 |
0 |
| T64 |
448 |
0 |
0 |
0 |
| T65 |
795 |
0 |
0 |
0 |
| T66 |
746 |
0 |
0 |
0 |
| T67 |
523 |
0 |
0 |
0 |
| T80 |
513 |
0 |
0 |
0 |
| T86 |
0 |
1 |
0 |
0 |
| T87 |
0 |
12 |
0 |
0 |
| T90 |
447 |
0 |
0 |
0 |
| T93 |
0 |
1 |
0 |
0 |
| T127 |
0 |
1 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
23274609 |
1698424 |
0 |
0 |
| T3 |
7467 |
1560 |
0 |
0 |
| T7 |
0 |
650 |
0 |
0 |
| T16 |
1476 |
0 |
0 |
0 |
| T17 |
1221 |
0 |
0 |
0 |
| T18 |
1842 |
0 |
0 |
0 |
| T19 |
1488 |
0 |
0 |
0 |
| T20 |
1266 |
0 |
0 |
0 |
| T28 |
1857 |
0 |
0 |
0 |
| T32 |
1335 |
0 |
0 |
0 |
| T38 |
0 |
155 |
0 |
0 |
| T48 |
0 |
298833 |
0 |
0 |
| T63 |
1266 |
0 |
0 |
0 |
| T64 |
1344 |
0 |
0 |
0 |
| T68 |
0 |
100 |
0 |
0 |
| T69 |
0 |
1299 |
0 |
0 |
| T72 |
0 |
324 |
0 |
0 |
| T73 |
0 |
1497 |
0 |
0 |
| T92 |
0 |
351 |
0 |
0 |
| T94 |
0 |
875 |
0 |
0 |
| T95 |
0 |
64 |
0 |
0 |
| T96 |
0 |
228 |
0 |
0 |
| T129 |
0 |
300 |
0 |
0 |
| T130 |
0 |
41635 |
0 |
0 |
