Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T9 T25 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T9 T25 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T9 T25 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T9 T25 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T9 T25 T11 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T9 T25 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T11 T45 
167        1/1                    if (trigger_active) begin
           Tests:       T9 T11 T45 
168        1/1                      state_d = DetectSt;
           Tests:       T9 T45 T51 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T11 T46 T212 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T9 T45 T51 
182        1/1                  cnt_en = 1'b1;
           Tests:       T9 T45 T51 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T9 T45 T51 
186        1/1                    state_d = IdleSt;
           Tests:       T102 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T102 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T9 T45 T51 
191        1/1                      state_d = StableSt;
           Tests:       T9 T45 T51 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T9 T45 T51 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T9 T45 T51 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T9 T45 T51 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T9 T45 T51 
206        1/1                    state_d = IdleSt;
           Tests:       T9 T45 T51 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T9 T45 T51 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T25,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T25,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T45,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T25,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T25,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T45,T51
0	1	Covered	T102
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T45,T51
0	1	Covered	T9,T51,T46
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T45,T51
1	-	Covered	T9,T51,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T25,T11
DetectSt	168	Covered	T9,T45,T51
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T45,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T45,T51
DebounceSt->IdleSt	163	Covered	T25,T11,T46
DetectSt->IdleSt	186	Covered	T102
DetectSt->StableSt	191	Covered	T9,T45,T51
IdleSt->DebounceSt	148	Covered	T9,T25,T11
StableSt->IdleSt	206	Covered	T9,T45,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T25,T11
0	1	Covered	T9,T25,T11
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T9,T45,T51
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T25,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T45,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T46,T212
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T25,T11
DetectSt	-	-	-	-	1	-	-	Covered	T102
DetectSt	-	-	-	-	0	1	-	Covered	T9,T45,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T45,T51
StableSt	-	-	-	-	-	-	0	Covered	T9,T45,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	52	0	0
CntIncr_A	7758203	158275	0	0
CntNoWrap_A	7758203	7283510	0	0
DetectStDropOut_A	7758203	1	0	0
DetectedOut_A	7758203	16814	0	0
DetectedPulseOut_A	7758203	22	0	0
DisabledIdleSt_A	7758203	6837726	0	0
DisabledNoDetection_A	7758203	6839610	0	0
EnterDebounceSt_A	7758203	29	0	0
EnterDetectSt_A	7758203	23	0	0
EnterStableSt_A	7758203	22	0	0
PulseIsPulse_A	7758203	22	0	0
StayInStableSt	7758203	16784	0	0
gen_high_level_sva.HighLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	52	0	0
T9	744	2	0	0
T11	0	1	0	0
T25	7314	1	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	4	0	0
T48	0	2	0	0
T51	0	2	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T149	0	2	0	0
T167	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	158275	0	0
T9	744	31	0	0
T11	0	40	0	0
T25	7314	32	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	21	0	0
T46	0	178	0	0
T47	0	64	0	0
T48	0	79	0	0
T51	0	85	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T149	0	32	0	0
T167	0	14	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283510	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1	0	0
T102	696	1	0	0
T213	422	0	0	0
T214	493	0	0	0
T215	523	0	0	0
T216	503	0	0	0
T217	506	0	0	0
T218	1630	0	0	0
T219	22156	0	0	0
T220	20117	0	0	0
T221	553	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	16814	0	0
T9	744	43	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	6	0	0
T46	0	105	0	0
T47	0	141	0	0
T48	0	44	0	0
T51	0	126	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T149	0	42	0	0
T151	0	44	0	0
T167	0	85	0	0
T176	0	42	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	22	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T149	0	1	0	0
T151	0	1	0	0
T167	0	1	0	0
T176	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6837726	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6839610	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	29	0	0
T9	744	1	0	0
T11	0	1	0	0
T25	7314	1	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T149	0	1	0	0
T167	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	23	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T149	0	1	0	0
T151	0	1	0	0
T167	0	1	0	0
T176	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	22	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T149	0	1	0	0
T151	0	1	0	0
T167	0	1	0	0
T176	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	22	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T149	0	1	0	0
T151	0	1	0	0
T167	0	1	0	0
T176	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	16784	0	0
T9	744	42	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	5	0	0
T46	0	104	0	0
T47	0	138	0	0
T48	0	43	0	0
T51	0	125	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T149	0	40	0	0
T151	0	43	0	0
T167	0	83	0	0
T176	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	13	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T178	0	1	0	0
T181	0	1	0	0
T191	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T25 T49 T45 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T25 T45 T51 
149        1/1                    cnt_en = 1'b1;
           Tests:       T25 T45 T51 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T25 T45 T51 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T25 T45 T51 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T25 T45 T51 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T45 T51 T48 
167        1/1                    if (trigger_active) begin
           Tests:       T45 T51 T48 
168        1/1                      state_d = DetectSt;
           Tests:       T45 T51 T48 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T45 T51 T48 
182        1/1                  cnt_en = 1'b1;
           Tests:       T45 T51 T48 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T45 T51 T48 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T45 T51 T48 
191        1/1                      state_d = StableSt;
           Tests:       T45 T51 T48 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T45 T51 T48 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T45 T51 T48 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T45 T51 T48 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T45 T51 T48 
206        1/1                    state_d = IdleSt;
           Tests:       T45 T179 T101 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T45 T51 T48 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T45,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T25,T45,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T51,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T53
1	0	Covered	T4,T5,T6
1	1	Covered	T25,T45,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T51,T48
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T51,T48
0	1	Covered	T179,T101,T153
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T51,T48
1	-	Covered	T179,T101,T153

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T45,T51
DetectSt	168	Covered	T45,T51,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T45,T51,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T45,T51,T48
DebounceSt->IdleSt	163	Covered	T25
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T45,T51,T48
IdleSt->DebounceSt	148	Covered	T25,T45,T51
StableSt->IdleSt	206	Covered	T45,T51,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T45,T51
0	1	Covered	T25,T45,T51
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T45,T51,T48
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T45,T51
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T51,T48
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T45,T51
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T45,T51,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T179,T101
StableSt	-	-	-	-	-	-	0	Covered	T45,T51,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	33	0	0
CntIncr_A	7758203	855	0	0
CntNoWrap_A	7758203	7283529	0	0
DetectStDropOut_A	7758203	0	0	0
DetectedOut_A	7758203	1648	0	0
DetectedPulseOut_A	7758203	16	0	0
DisabledIdleSt_A	7758203	7275700	0	0
DisabledNoDetection_A	7758203	7277588	0	0
EnterDebounceSt_A	7758203	17	0	0
EnterDetectSt_A	7758203	16	0	0
EnterStableSt_A	7758203	16	0	0
PulseIsPulse_A	7758203	16	0	0
StayInStableSt	7758203	1620	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7758203	4933	0	0
gen_low_level_sva.LowLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	3	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	33	0	0
T10	478	0	0	0
T25	7314	1	0	0
T45	0	2	0	0
T48	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T101	0	2	0	0
T146	0	2	0	0
T161	0	2	0	0
T165	0	2	0	0
T179	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	855	0	0
T10	478	0	0	0
T25	7314	33	0	0
T45	0	21	0	0
T48	0	79	0	0
T51	0	85	0	0
T52	0	92	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T101	0	20	0	0
T146	0	99	0	0
T161	0	15	0	0
T165	0	24	0	0
T179	0	31	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283529	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1648	0	0
T41	6177	0	0	0
T45	6987	8	0	0
T48	0	401	0	0
T51	8239	52	0	0
T52	0	188	0	0
T78	494	0	0	0
T101	0	11	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	154	0	0
T161	0	139	0	0
T165	0	50	0	0
T179	0	39	0	0
T183	0	41	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	16	0	0
T41	6177	0	0	0
T45	6987	1	0	0
T48	0	1	0	0
T51	8239	1	0	0
T52	0	1	0	0
T78	494	0	0	0
T101	0	1	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	1	0	0
T161	0	1	0	0
T165	0	1	0	0
T179	0	1	0	0
T183	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7275700	0	0
T1	786	4	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7277588	0	0
T1	786	4	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	17	0	0
T10	478	0	0	0
T25	7314	1	0	0
T45	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T101	0	1	0	0
T146	0	1	0	0
T161	0	1	0	0
T165	0	1	0	0
T179	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	16	0	0
T41	6177	0	0	0
T45	6987	1	0	0
T48	0	1	0	0
T51	8239	1	0	0
T52	0	1	0	0
T78	494	0	0	0
T101	0	1	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	1	0	0
T161	0	1	0	0
T165	0	1	0	0
T179	0	1	0	0
T183	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	16	0	0
T41	6177	0	0	0
T45	6987	1	0	0
T48	0	1	0	0
T51	8239	1	0	0
T52	0	1	0	0
T78	494	0	0	0
T101	0	1	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	1	0	0
T161	0	1	0	0
T165	0	1	0	0
T179	0	1	0	0
T183	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	16	0	0
T41	6177	0	0	0
T45	6987	1	0	0
T48	0	1	0	0
T51	8239	1	0	0
T52	0	1	0	0
T78	494	0	0	0
T101	0	1	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	1	0	0
T161	0	1	0	0
T165	0	1	0	0
T179	0	1	0	0
T183	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1620	0	0
T41	6177	0	0	0
T45	6987	7	0	0
T48	0	399	0	0
T51	8239	50	0	0
T52	0	186	0	0
T78	494	0	0	0
T101	0	10	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	152	0	0
T161	0	137	0	0
T165	0	48	0	0
T179	0	38	0	0
T183	0	39	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	4933	0	0
T1	786	0	0	0
T2	510	1	0	0
T3	2489	0	0	0
T4	425	2	0	0
T5	436	1	0	0
T6	528	4	0	0
T14	430	4	0	0
T15	506	4	0	0
T16	492	7	0	0
T17	407	0	0	0
T19	0	11	0	0
T20	0	2	0	0
T63	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	3	0	0
T101	0	1	0	0
T146	2803	0	0	0
T153	0	1	0	0
T155	16450	0	0	0
T156	682	0	0	0
T157	418	0	0	0
T179	655	1	0	0
T222	403	0	0	0
T223	502	0	0	0
T224	493	0	0	0
T225	422	0	0	0
T226	2039	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T9 T25 T54 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T9 T25 T54 
149        1/1                    cnt_en = 1'b1;
           Tests:       T9 T25 T54 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T9 T25 T54 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T9 T25 T54 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T9 T25 T54 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T54 T49 
167        1/1                    if (trigger_active) begin
           Tests:       T9 T54 T49 
168        1/1                      state_d = DetectSt;
           Tests:       T9 T54 T49 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T54 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T9 T54 T49 
182        1/1                  cnt_en = 1'b1;
           Tests:       T9 T54 T49 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T9 T54 T49 
186        1/1                    state_d = IdleSt;
           Tests:       T101 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T101 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T9 T54 T49 
191        1/1                      state_d = StableSt;
           Tests:       T9 T54 T49 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T9 T54 T49 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T9 T54 T49 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T9 T54 T49 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T9 T54 T49 
206        1/1                    state_d = IdleSt;
           Tests:       T9 T54 T49 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T9 T54 T49 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T25,T54

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T25,T54

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T54,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T25,T54
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T25,T54

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T54,T49
0	1	Covered	T101
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T54,T49
0	1	Covered	T9,T54,T49
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T54,T49
1	-	Covered	T9,T54,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T25,T54
DetectSt	168	Covered	T9,T54,T49
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T54,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T54,T49
DebounceSt->IdleSt	163	Covered	T25,T54
DetectSt->IdleSt	186	Covered	T101
DetectSt->StableSt	191	Covered	T9,T54,T49
IdleSt->DebounceSt	148	Covered	T9,T25,T54
StableSt->IdleSt	206	Covered	T9,T54,T49

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T25,T54
0	1	Covered	T9,T25,T54
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T9,T54,T49
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T25,T54
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T54,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T54
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T25,T54
DetectSt	-	-	-	-	1	-	-	Covered	T101
DetectSt	-	-	-	-	0	1	-	Covered	T9,T54,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T54,T49
StableSt	-	-	-	-	-	-	0	Covered	T9,T54,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	78	0	0
CntIncr_A	7758203	87757	0	0
CntNoWrap_A	7758203	7283484	0	0
DetectStDropOut_A	7758203	1	0	0
DetectedOut_A	7758203	60384	0	0
DetectedPulseOut_A	7758203	37	0	0
DisabledIdleSt_A	7758203	6892846	0	0
DisabledNoDetection_A	7758203	6894727	0	0
EnterDebounceSt_A	7758203	40	0	0
EnterDetectSt_A	7758203	38	0	0
EnterStableSt_A	7758203	37	0	0
PulseIsPulse_A	7758203	37	0	0
StayInStableSt	7758203	60331	0	0
gen_high_level_sva.HighLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	78	0	0
T9	744	4	0	0
T25	7314	1	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	2	0	0
T47	0	4	0	0
T48	0	4	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T54	0	3	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T185	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	87757	0	0
T9	744	62	0	0
T25	7314	33	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	21	0	0
T47	0	64	0	0
T48	0	158	0	0
T49	0	57	0	0
T50	0	53	0	0
T51	0	85	0	0
T54	0	62	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T185	0	48	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283484	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1	0	0
T101	3926	1	0	0
T181	1282	0	0	0
T227	526	0	0	0
T228	1633	0	0	0
T229	421	0	0	0
T230	503	0	0	0
T231	1713	0	0	0
T232	11372	0	0	0
T233	411	0	0	0
T234	423	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	60384	0	0
T9	744	115	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	7	0	0
T47	0	87	0	0
T48	0	218	0	0
T49	0	54	0	0
T50	0	122	0	0
T51	0	40	0	0
T54	0	43	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T167	0	85	0	0
T185	0	57	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	37	0	0
T9	744	2	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T167	0	1	0	0
T185	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6892846	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6894727	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	40	0	0
T9	744	2	0	0
T25	7314	1	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	0	2	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T185	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	38	0	0
T9	744	2	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T167	0	1	0	0
T185	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	37	0	0
T9	744	2	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T167	0	1	0	0
T185	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	37	0	0
T9	744	2	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T167	0	1	0	0
T185	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	60331	0	0
T9	744	112	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	6	0	0
T47	0	84	0	0
T48	0	216	0	0
T49	0	53	0	0
T50	0	121	0	0
T51	0	39	0	0
T54	0	42	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T167	0	83	0	0
T185	0	55	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	20	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T47	0	1	0	0
T48	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T54	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T152	0	1	0	0
T178	0	1	0	0
T190	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T9 T25 T49 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T9 T25 T49 
149        1/1                    cnt_en = 1'b1;
           Tests:       T9 T25 T49 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T9 T25 T49 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T9 T25 T49 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T9 T25 T49 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T49 T50 
167        1/1                    if (trigger_active) begin
           Tests:       T9 T49 T50 
168        1/1                      state_d = DetectSt;
           Tests:       T9 T49 T50 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T46 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T9 T49 T50 
182        1/1                  cnt_en = 1'b1;
           Tests:       T9 T49 T50 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T9 T49 T50 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T9 T49 T50 
191        1/1                      state_d = StableSt;
           Tests:       T9 T49 T50 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T9 T49 T50 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T9 T49 T50 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T9 T49 T50 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T9 T49 T50 
206        1/1                    state_d = IdleSt;
           Tests:       T9 T45 T126 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T9 T49 T50 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T25,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T9,T25,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T49,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T9,T25,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T9,T25,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T49,T50
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T49,T50
0	1	Covered	T9,T126,T179
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T9,T49,T50
1	-	Covered	T9,T126,T179

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T25,T49
DetectSt	168	Covered	T9,T49,T50
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T49,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T49,T50
DebounceSt->IdleSt	163	Covered	T25,T46
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T9,T49,T50
IdleSt->DebounceSt	148	Covered	T9,T25,T49
StableSt->IdleSt	206	Covered	T9,T49,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T9,T25,T49
0	1	Covered	T9,T25,T49
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T9,T49,T50
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T25,T49
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T49,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T46
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T25,T49
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T9,T49,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T45,T126
StableSt	-	-	-	-	-	-	0	Covered	T9,T49,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	48	0	0
CntIncr_A	7758203	1346	0	0
CntNoWrap_A	7758203	7283514	0	0
DetectStDropOut_A	7758203	0	0	0
DetectedOut_A	7758203	1364	0	0
DetectedPulseOut_A	7758203	23	0	0
DisabledIdleSt_A	7758203	7219318	0	0
DisabledNoDetection_A	7758203	7221205	0	0
EnterDebounceSt_A	7758203	25	0	0
EnterDetectSt_A	7758203	23	0	0
EnterStableSt_A	7758203	23	0	0
PulseIsPulse_A	7758203	23	0	0
StayInStableSt	7758203	1326	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7758203	4985	0	0
gen_low_level_sva.LowLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	48	0	0
T9	744	2	0	0
T25	7314	1	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	2	0	0
T46	0	3	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T126	0	4	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T184	0	2	0	0
T190	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1346	0	0
T9	744	31	0	0
T25	7314	34	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	21	0	0
T46	0	178	0	0
T49	0	57	0	0
T50	0	53	0	0
T51	0	85	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T126	0	52	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T184	0	17	0	0
T190	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283514	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1364	0	0
T9	744	7	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	8	0	0
T46	0	87	0	0
T49	0	45	0	0
T50	0	147	0	0
T51	0	137	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T126	0	81	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T177	0	132	0	0
T184	0	49	0	0
T190	0	43	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	23	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T126	0	2	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T177	0	1	0	0
T184	0	1	0	0
T190	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7219318	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7221205	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	25	0	0
T9	744	1	0	0
T25	7314	1	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T126	0	2	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T184	0	1	0	0
T190	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	23	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T126	0	2	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T177	0	1	0	0
T184	0	1	0	0
T190	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	23	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T126	0	2	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T177	0	1	0	0
T184	0	1	0	0
T190	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	23	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T126	0	2	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T177	0	1	0	0
T184	0	1	0	0
T190	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1326	0	0
T9	744	6	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T45	0	7	0	0
T46	0	85	0	0
T49	0	43	0	0
T50	0	145	0	0
T51	0	135	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T126	0	78	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T177	0	130	0	0
T184	0	47	0	0
T190	0	41	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	4985	0	0
T1	786	1	0	0
T2	510	1	0	0
T3	2489	0	0	0
T4	425	2	0	0
T5	436	1	0	0
T6	528	4	0	0
T14	430	2	0	0
T15	506	6	0	0
T16	492	8	0	0
T17	407	0	0	0
T19	0	7	0	0
T20	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T101	0	1	0	0
T126	0	1	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T153	0	1	0	0
T165	0	1	0	0
T179	0	1	0	0
T204	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T6 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T6 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T9 T25 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T6 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T6 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T6 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T6 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T6 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T6 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T6 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T6 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T9 T25 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T9 T25 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T9 T25 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T9 T25 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T9 T25 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T9 T53 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T9 T53 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T9 T53 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T9 T184 T235 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T9 T53 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T9 T53 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T9 T53 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T9 T53 
191        1/1                      state_d = StableSt;
           Tests:       T1 T9 T53 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T9 T53 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T9 T53 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T9 T53 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T9 T53 
206        1/1                    state_d = IdleSt;
           Tests:       T9 T45 T46 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T9 T53 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T1
1	1	Covered	T4,T6,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T9,T25

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T9,T25

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T9,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T9,T25
1	0	Covered	T4,T6,T14
1	1	Covered	T1,T9,T25

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T53
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T53
0	1	Covered	T9,T46,T55
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T53
1	-	Covered	T9,T46,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T9,T25
DetectSt	168	Covered	T1,T9,T53
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T9,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T53
DebounceSt->IdleSt	163	Covered	T9,T25,T184
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T9,T53
IdleSt->DebounceSt	148	Covered	T1,T9,T25
StableSt->IdleSt	206	Covered	T9,T45,T51

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T9,T25
0	1	Covered	T1,T9,T25
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T53
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T9,T25
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T1
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T9,T184,T235
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T9,T25
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T45,T46
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	66	0	0
CntIncr_A	7758203	25211	0	0
CntNoWrap_A	7758203	7283496	0	0
DetectStDropOut_A	7758203	0	0	0
DetectedOut_A	7758203	48919	0	0
DetectedPulseOut_A	7758203	31	0	0
DisabledIdleSt_A	7758203	7110668	0	0
DisabledNoDetection_A	7758203	7112553	0	0
EnterDebounceSt_A	7758203	35	0	0
EnterDetectSt_A	7758203	31	0	0
EnterStableSt_A	7758203	31	0	0
PulseIsPulse_A	7758203	31	0	0
StayInStableSt	7758203	48872	0	0
gen_high_level_sva.HighLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	66	0	0
T1	786	2	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	5	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	1	0	0
T45	0	2	0	0
T46	0	4	0	0
T51	0	2	0	0
T53	0	2	0	0
T55	0	2	0	0
T149	0	2	0	0
T205	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	25211	0	0
T1	786	53	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	93	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	33	0	0
T45	0	21	0	0
T46	0	178	0	0
T51	0	85	0	0
T53	0	58	0	0
T55	0	57	0	0
T149	0	32	0	0
T205	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283496	0	0
T1	786	383	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	48919	0	0
T1	786	233	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	54	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	7	0	0
T46	0	85	0	0
T51	0	52	0	0
T53	0	118	0	0
T55	0	159	0	0
T149	0	41	0	0
T184	0	4	0	0
T205	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	31	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	2	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T149	0	1	0	0
T184	0	1	0	0
T205	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7110668	0	0
T1	786	4	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7112553	0	0
T1	786	4	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	35	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	3	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T25	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T149	0	1	0	0
T205	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	31	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	2	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T149	0	1	0	0
T184	0	1	0	0
T205	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	31	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	2	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T149	0	1	0	0
T184	0	1	0	0
T205	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	31	0	0
T1	786	1	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	2	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T51	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T149	0	1	0	0
T184	0	1	0	0
T205	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	48872	0	0
T1	786	231	0	0
T2	510	0	0	0
T3	2489	0	0	0
T9	0	51	0	0
T14	430	0	0	0
T15	506	0	0	0
T16	492	0	0	0
T17	407	0	0	0
T18	614	0	0	0
T19	496	0	0	0
T20	422	0	0	0
T45	0	6	0	0
T46	0	83	0	0
T51	0	50	0	0
T53	0	116	0	0
T55	0	158	0	0
T149	0	39	0	0
T184	0	3	0	0
T205	0	36	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	14	0	0
T9	744	1	0	0
T25	7314	0	0	0
T26	1308	0	0	0
T29	646	0	0	0
T46	0	2	0	0
T52	0	1	0	0
T55	0	1	0	0
T70	1774	0	0	0
T80	513	0	0	0
T90	447	0	0	0
T143	426	0	0	0
T144	4442	0	0	0
T145	402	0	0	0
T165	0	1	0	0
T167	0	1	0	0
T178	0	1	0	0
T182	0	1	0	0
T183	0	2	0	0
T184	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T6 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T25 T45 T46 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T25 T45 T46 
149        1/1                    cnt_en = 1'b1;
           Tests:       T25 T45 T46 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T25 T45 T46 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T25 T45 T46 
163        1/1                    state_d = IdleSt;
           Tests:       T25 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T25 
165        1/1                  end else if (cnt_done) begin
           Tests:       T25 T45 T46 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T45 T46 T47 
167        1/1                    if (trigger_active) begin
           Tests:       T45 T46 T47 
168        1/1                      state_d = DetectSt;
           Tests:       T45 T46 T47 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T46 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T45 T46 T47 
182        1/1                  cnt_en = 1'b1;
           Tests:       T45 T46 T47 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T45 T46 T47 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T45 T46 T47 
191        1/1                      state_d = StableSt;
           Tests:       T45 T46 T47 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T45 T46 T47 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T45 T46 T47 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T45 T46 T47 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T45 T46 T47 
206        1/1                    state_d = IdleSt;
           Tests:       T45 T48 T184 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T45 T46 T47 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T1
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T1
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T25,T45,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T25,T45,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T45,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T25,T53
1	0	Covered	T4,T6,T14
1	1	Covered	T25,T45,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T47
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T47
0	1	Covered	T48,T184,T52
1	0	Covered	T45

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T46,T47
1	-	Covered	T48,T184,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T25,T45,T46
DetectSt	168	Covered	T45,T46,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T45,T46,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T45,T46,T47
DebounceSt->IdleSt	163	Covered	T25,T46
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T45,T46,T47
IdleSt->DebounceSt	148	Covered	T25,T45,T46
StableSt->IdleSt	206	Covered	T45,T48,T184

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T25,T45,T46
0	1	Covered	T25,T45,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T45,T46,T47
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T25,T45,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T25
DebounceSt	-	0	1	1	-	-	-	Covered	T45,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T46
DebounceSt	-	0	0	-	-	-	-	Covered	T25,T45,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T45,T46,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T45,T48,T184
StableSt	-	-	-	-	-	-	0	Covered	T45,T46,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7758203	52	0	0
CntIncr_A	7758203	18267	0	0
CntNoWrap_A	7758203	7283510	0	0
DetectStDropOut_A	7758203	0	0	0
DetectedOut_A	7758203	1464	0	0
DetectedPulseOut_A	7758203	25	0	0
DisabledIdleSt_A	7758203	6997639	0	0
DisabledNoDetection_A	7758203	6999520	0	0
EnterDebounceSt_A	7758203	27	0	0
EnterDetectSt_A	7758203	25	0	0
EnterStableSt_A	7758203	25	0	0
PulseIsPulse_A	7758203	25	0	0
StayInStableSt	7758203	1424	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7758203	5501	0	0
gen_low_level_sva.LowLevelEvent_A	7758203	7285475	0	0
gen_not_sticky_sva.StableStDropOut_A	7758203	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	52	0	0
T10	478	0	0	0
T25	7314	1	0	0
T45	0	2	0	0
T46	0	3	0	0
T47	0	2	0	0
T48	0	4	0	0
T52	0	2	0	0
T55	0	2	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T167	0	2	0	0
T177	0	2	0	0
T184	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	18267	0	0
T10	478	0	0	0
T25	7314	32	0	0
T45	0	21	0	0
T46	0	178	0	0
T47	0	32	0	0
T48	0	158	0	0
T52	0	92	0	0
T55	0	57	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T167	0	14	0	0
T177	0	90	0	0
T184	0	34	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7283510	0	0
T1	786	385	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1464	0	0
T41	6177	0	0	0
T45	6987	8	0	0
T46	0	88	0	0
T47	0	44	0	0
T48	0	66	0	0
T51	8239	0	0	0
T52	0	56	0	0
T55	0	40	0	0
T78	494	0	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	84	0	0
T167	0	70	0	0
T177	0	38	0	0
T184	0	172	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	25	0	0
T41	6177	0	0	0
T45	6987	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T51	8239	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T78	494	0	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	2	0	0
T167	0	1	0	0
T177	0	1	0	0
T184	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6997639	0	0
T1	786	4	0	0
T2	510	109	0	0
T3	2489	2088	0	0
T4	425	24	0	0
T5	436	35	0	0
T6	528	127	0	0
T14	430	29	0	0
T15	506	105	0	0
T16	492	91	0	0
T17	407	6	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	6999520	0	0
T1	786	4	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	27	0	0
T10	478	0	0	0
T25	7314	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	2	0	0
T52	0	1	0	0
T55	0	1	0	0
T58	462	0	0	0
T59	639	0	0	0
T74	495	0	0	0
T75	491	0	0	0
T80	513	0	0	0
T81	524	0	0	0
T90	447	0	0	0
T91	4402	0	0	0
T167	0	1	0	0
T177	0	1	0	0
T184	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	25	0	0
T41	6177	0	0	0
T45	6987	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T51	8239	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T78	494	0	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	2	0	0
T167	0	1	0	0
T177	0	1	0	0
T184	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	25	0	0
T41	6177	0	0	0
T45	6987	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T51	8239	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T78	494	0	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	2	0	0
T167	0	1	0	0
T177	0	1	0	0
T184	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	25	0	0
T41	6177	0	0	0
T45	6987	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	2	0	0
T51	8239	0	0	0
T52	0	1	0	0
T55	0	1	0	0
T78	494	0	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	2	0	0
T167	0	1	0	0
T177	0	1	0	0
T184	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	1424	0	0
T41	6177	0	0	0
T45	6987	7	0	0
T46	0	86	0	0
T47	0	42	0	0
T48	0	63	0	0
T51	8239	0	0	0
T52	0	55	0	0
T55	0	38	0	0
T78	494	0	0	0
T114	1908	0	0	0
T115	408	0	0	0
T116	421	0	0	0
T117	504	0	0	0
T118	526	0	0	0
T119	448	0	0	0
T146	0	81	0	0
T167	0	68	0	0
T177	0	36	0	0
T184	0	169	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	5501	0	0
T1	786	0	0	0
T2	510	0	0	0
T3	2489	11	0	0
T4	425	3	0	0
T5	436	0	0	0
T6	528	5	0	0
T14	430	4	0	0
T15	506	4	0	0
T16	492	8	0	0
T17	407	0	0	0
T19	0	7	0	0
T20	0	3	0	0
T28	0	3	0	0
T63	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	7285475	0	0
T1	786	386	0	0
T2	510	110	0	0
T3	2489	2089	0	0
T4	425	25	0	0
T5	436	36	0	0
T6	528	128	0	0
T14	430	30	0	0
T15	506	106	0	0
T16	492	92	0	0
T17	407	7	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7758203	9	0	0
T48	310313	1	0	0
T52	0	1	0	0
T146	0	1	0	0
T165	0	1	0	0
T181	0	1	0	0
T183	0	1	0	0
T184	0	1	0	0
T211	0	1	0	0
T236	0	1	0	0
T237	500	0	0	0
T238	522	0	0	0
T239	3915	0	0	0
T240	7904	0	0	0
T241	1549	0	0	0
T242	538	0	0	0
T243	413	0	0	0
T244	422	0	0	0
T245	402	0	0	0