Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T5 T6 T23 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T6 T38 T39 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T6 T38 T39 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T6 T38 T39 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T6 T38 T39 
149        1/1                    cnt_en = 1'b1;
           Tests:       T6 T38 T39 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T6 T38 T39 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T6 T38 T39 
163        1/1                    state_d = IdleSt;
           Tests:       T34 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 
165        1/1                  end else if (cnt_done) begin
           Tests:       T6 T38 T39 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T6 T38 T39 
167        1/1                    if (trigger_active) begin
           Tests:       T6 T38 T39 
168        1/1                      state_d = DetectSt;
           Tests:       T6 T38 T39 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T67 T69 T72 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T6 T38 T39 
182        1/1                  cnt_en = 1'b1;
           Tests:       T6 T38 T39 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T6 T38 T39 
186        1/1                    state_d = IdleSt;
           Tests:       T129 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T129 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T6 T38 T39 
191        1/1                      state_d = StableSt;
           Tests:       T6 T38 T39 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T6 T38 T39 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T6 T38 T39 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T6 T38 T39 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T6 T38 T39 
206        1/1                    state_d = IdleSt;
           Tests:       T6 T38 T39 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T6 T38 T39 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T38,T39

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T6,T38,T39

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T6,T38,T39

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T38,T39
1	0	Covered	T5,T6,T23
1	1	Covered	T6,T38,T39

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T38,T39
0	1	Covered	T129
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T38,T39
0	1	Covered	T6,T38,T39
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T38,T39
1	-	Covered	T6,T38,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T38,T39
DetectSt	168	Covered	T6,T38,T39
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T6,T38,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T38,T39
DebounceSt->IdleSt	163	Covered	T67,T34,T69
DetectSt->IdleSt	186	Covered	T129
DetectSt->StableSt	191	Covered	T6,T38,T39
IdleSt->DebounceSt	148	Covered	T6,T38,T39
StableSt->IdleSt	206	Covered	T6,T38,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T38,T39
0	1	Covered	T6,T38,T39
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T38,T39
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T38,T39
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T38,T39
DebounceSt	-	0	1	0	-	-	-	Covered	T67,T69,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T38,T39
DetectSt	-	-	-	-	1	-	-	Covered	T129
DetectSt	-	-	-	-	0	1	-	Covered	T6,T38,T39
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T6,T38,T39
StableSt	-	-	-	-	-	-	0	Covered	T6,T38,T39
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	179	0	0
CntIncr_A	6456720	121697	0	0
CntNoWrap_A	6456720	5999934	0	0
DetectStDropOut_A	6456720	1	0	0
DetectedOut_A	6456720	556	0	0
DetectedPulseOut_A	6456720	79	0	0
DisabledIdleSt_A	6456720	5874286	0	0
DisabledNoDetection_A	6456720	5876131	0	0
EnterDebounceSt_A	6456720	102	0	0
EnterDetectSt_A	6456720	80	0	0
EnterStableSt_A	6456720	79	0	0
PulseIsPulse_A	6456720	79	0	0
StayInStableSt	6456720	477	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6456720	5453	0	0
gen_low_level_sva.LowLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	78	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	179	0	0
T1	506	0	0	0
T6	693	4	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T30	0	2	0	0
T34	0	1	0	0
T38	0	2	0	0
T39	0	2	0	0
T67	0	1	0	0
T69	0	3	0	0
T70	0	4	0	0
T71	0	6	0	0
T72	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	121697	0	0
T1	506	0	0	0
T6	693	54	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T30	0	26	0	0
T34	0	31	0	0
T38	0	53	0	0
T39	0	86	0	0
T67	0	10	0	0
T69	0	92	0	0
T70	0	63	0	0
T71	0	183	0	0
T72	0	160	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5999934	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	288	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	1	0	0
T129	694	1	0	0
T130	24386	0	0	0
T141	1907	0	0	0
T142	522	0	0	0
T143	409	0	0	0
T144	693	0	0	0
T145	17871	0	0	0
T146	92624	0	0	0
T147	423	0	0	0
T148	498	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	556	0	0
T1	506	0	0	0
T6	693	15	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T30	0	1	0	0
T38	0	9	0	0
T39	0	6	0	0
T69	0	4	0	0
T70	0	19	0	0
T71	0	27	0	0
T72	0	9	0	0
T149	0	21	0	0
T150	0	23	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	79	0	0
T1	506	0	0	0
T6	693	2	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T30	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	3	0	0
T72	0	2	0	0
T149	0	3	0	0
T150	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5874286	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	154	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5876131	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	155	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	102	0	0
T1	506	0	0	0
T6	693	2	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T30	0	1	0	0
T34	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T67	0	1	0	0
T69	0	2	0	0
T70	0	2	0	0
T71	0	3	0	0
T72	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	80	0	0
T1	506	0	0	0
T6	693	2	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T30	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	3	0	0
T72	0	2	0	0
T149	0	3	0	0
T150	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	79	0	0
T1	506	0	0	0
T6	693	2	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T30	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	3	0	0
T72	0	2	0	0
T149	0	3	0	0
T150	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	79	0	0
T1	506	0	0	0
T6	693	2	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T30	0	1	0	0
T38	0	1	0	0
T39	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	3	0	0
T72	0	2	0	0
T149	0	3	0	0
T150	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	477	0	0
T1	506	0	0	0
T6	693	13	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T38	0	8	0	0
T39	0	5	0	0
T69	0	3	0	0
T70	0	17	0	0
T71	0	24	0	0
T72	0	7	0	0
T149	0	18	0	0
T150	0	20	0	0
T151	0	19	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5453	0	0
T1	506	0	0	0
T2	0	4	0	0
T5	504	8	0	0
T6	693	3	0	0
T14	423	1	0	0
T15	424	3	0	0
T16	477	0	0	0
T17	0	4	0	0
T18	0	6	0	0
T23	423	4	0	0
T24	506	5	0	0
T25	560	0	0	0
T26	406	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	78	0	0
T1	506	0	0	0
T6	693	2	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T38	0	1	0	0
T39	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	3	0	0
T72	0	2	0	0
T149	0	3	0	0
T150	0	3	0	0
T151	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T5 T6 T23 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T34 T35 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T32 T33 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T32 T33 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T34 T35 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T34 T35 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T34 T35 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T34 T35 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T34 T35 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T35 T22 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T35 T22 
168        1/1                      state_d = DetectSt;
           Tests:       T103 T104 T105 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T2 T35 T22 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T103 T104 T105 
182        1/1                  cnt_en = 1'b1;
           Tests:       T103 T104 T105 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T103 T104 T105 
186        1/1                    state_d = IdleSt;
           Tests:       T107 T108 T118 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T107 T108 T118 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T103 T104 T105 
191        1/1                      state_d = StableSt;
           Tests:       T103 T104 T105 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T103 T104 T105 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T103 T104 T105 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T103 T104 T105 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T103 T104 T105 
206        1/1                    state_d = IdleSt;
           Tests:       T103 T104 T105 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T103 T104 T105 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T103,T104,T105

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T34,T35
1	0	Covered	T5,T6,T23
1	1	Covered	T2,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T103,T104,T105
0	1	Covered	T107,T108,T118
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T103,T104,T105
0	1	Unreachable
1	0	Covered	T103,T104,T105

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T34,T35
DetectSt	168	Covered	T103,T104,T105
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T103,T104,T105

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T103,T104,T105
DebounceSt->IdleSt	163	Covered	T2,T34,T35
DetectSt->IdleSt	186	Covered	T107,T108,T118
DetectSt->StableSt	191	Covered	T103,T104,T105
IdleSt->DebounceSt	148	Covered	T2,T34,T35
StableSt->IdleSt	206	Covered	T103,T104,T105

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T34,T35
0	1	Covered	T2,T34,T35
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T103,T104,T105
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T103,T104,T105
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T35,T22
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T107,T108,T118
DetectSt	-	-	-	-	0	1	-	Covered	T103,T104,T105
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T103,T104,T105
StableSt	-	-	-	-	-	-	0	Covered	T103,T104,T105
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	118	0	0
CntIncr_A	6456720	54600	0	0
CntNoWrap_A	6456720	5999995	0	0
DetectStDropOut_A	6456720	14	0	0
DetectedOut_A	6456720	46468	0	0
DetectedPulseOut_A	6456720	23	0	0
DisabledIdleSt_A	6456720	5256023	0	0
DisabledNoDetection_A	6456720	5257898	0	0
EnterDebounceSt_A	6456720	82	0	0
EnterDetectSt_A	6456720	37	0	0
EnterStableSt_A	6456720	23	0	0
PulseIsPulse_A	6456720	23	0	0
StayInStableSt	6456720	46445	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6456720	5453	0	0
gen_low_level_sva.LowLevelEvent_A	6456720	6001990	0	0
gen_sticky_sva.StableStDropOut_A	6456720	513973	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	118	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	5	0	0
T30	0	1	0	0
T32	714	0	0	0
T34	0	2	0	0
T35	0	5	0	0
T36	486	0	0	0
T45	0	2	0	0
T81	502	0	0	0
T103	0	2	0	0
T104	0	4	0	0
T105	0	2	0	0
T106	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	54600	0	0
T2	1083	99	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	100	0	0
T30	0	62	0	0
T32	714	0	0	0
T34	0	35	0	0
T35	0	260	0	0
T36	486	0	0	0
T45	0	198	0	0
T81	502	0	0	0
T103	0	73	0	0
T104	0	98	0	0
T105	0	14	0	0
T106	0	74	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5999995	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	14	0	0
T53	849	0	0	0
T107	2344	1	0	0
T108	0	2	0	0
T118	0	1	0	0
T119	0	1	0	0
T152	1376	0	0	0
T162	0	2	0	0
T163	0	6	0	0
T164	0	1	0	0
T165	656	0	0	0
T166	422	0	0	0
T167	417	0	0	0
T168	491	0	0	0
T169	772	0	0	0
T170	407	0	0	0
T171	22174	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46468	0	0
T64	538	0	0	0
T103	1190	478	0	0
T104	0	54	0	0
T105	0	56	0	0
T106	0	344	0	0
T108	0	1	0	0
T111	0	37	0	0
T113	0	399	0	0
T114	0	20	0	0
T118	0	37	0	0
T153	0	290	0	0
T154	873	0	0	0
T155	404	0	0	0
T156	27810	0	0	0
T157	15791	0	0	0
T158	422	0	0	0
T159	445	0	0	0
T160	508	0	0	0
T161	489	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	23	0	0
T64	538	0	0	0
T103	1190	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	2	0	0
T108	0	1	0	0
T111	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T118	0	1	0	0
T153	0	1	0	0
T154	873	0	0	0
T155	404	0	0	0
T156	27810	0	0	0
T157	15791	0	0	0
T158	422	0	0	0
T159	445	0	0	0
T160	508	0	0	0
T161	489	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5256023	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5257898	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	82	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	5	0	0
T30	0	2	0	0
T32	714	0	0	0
T34	0	2	0	0
T35	0	5	0	0
T36	486	0	0	0
T45	0	2	0	0
T81	502	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	37	0	0
T64	538	0	0	0
T103	1190	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	2	0	0
T107	0	1	0	0
T108	0	3	0	0
T113	0	1	0	0
T114	0	1	0	0
T118	0	2	0	0
T153	0	1	0	0
T154	873	0	0	0
T155	404	0	0	0
T156	27810	0	0	0
T157	15791	0	0	0
T158	422	0	0	0
T159	445	0	0	0
T160	508	0	0	0
T161	489	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	23	0	0
T64	538	0	0	0
T103	1190	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	2	0	0
T108	0	1	0	0
T111	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T118	0	1	0	0
T153	0	1	0	0
T154	873	0	0	0
T155	404	0	0	0
T156	27810	0	0	0
T157	15791	0	0	0
T158	422	0	0	0
T159	445	0	0	0
T160	508	0	0	0
T161	489	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	23	0	0
T64	538	0	0	0
T103	1190	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	2	0	0
T108	0	1	0	0
T111	0	1	0	0
T113	0	1	0	0
T114	0	1	0	0
T118	0	1	0	0
T153	0	1	0	0
T154	873	0	0	0
T155	404	0	0	0
T156	27810	0	0	0
T157	15791	0	0	0
T158	422	0	0	0
T159	445	0	0	0
T160	508	0	0	0
T161	489	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46445	0	0
T64	538	0	0	0
T103	1190	477	0	0
T104	0	52	0	0
T105	0	55	0	0
T106	0	342	0	0
T111	0	36	0	0
T113	0	398	0	0
T114	0	19	0	0
T118	0	36	0	0
T153	0	289	0	0
T154	873	0	0	0
T155	404	0	0	0
T156	27810	0	0	0
T157	15791	0	0	0
T158	422	0	0	0
T159	445	0	0	0
T160	508	0	0	0
T161	489	0	0	0
T172	0	266	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5453	0	0
T1	506	0	0	0
T2	0	4	0	0
T5	504	8	0	0
T6	693	3	0	0
T14	423	1	0	0
T15	424	3	0	0
T16	477	0	0	0
T17	0	4	0	0
T18	0	6	0	0
T23	423	4	0	0
T24	506	5	0	0
T25	560	0	0	0
T26	406	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	513973	0	0
T64	538	0	0	0
T103	1190	202	0	0
T104	0	122	0	0
T105	0	369	0	0
T106	0	561	0	0
T108	0	92	0	0
T111	0	283	0	0
T113	0	182988	0	0
T114	0	23	0	0
T118	0	99	0	0
T153	0	142	0	0
T154	873	0	0	0
T155	404	0	0	0
T156	27810	0	0	0
T157	15791	0	0	0
T158	422	0	0	0
T159	445	0	0	0
T160	508	0	0	0
T161	489	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T23 T24 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T5 T23 T24 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T34 T35 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T32 T33 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T32 T33 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T23 T24 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T23 T24 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T23 T24 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T23 T24 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T23 T24 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T23 T24 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T23 T24 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T23 T24 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T34 T35 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T34 T35 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T34 T35 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T34 T35 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T34 T35 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T35 T22 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T35 T22 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T22 T103 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T35 T45 T106 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T22 T103 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T22 T103 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T22 T103 
186        1/1                    state_d = IdleSt;
           Tests:       T113 T118 T119 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T113 T118 T119 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T22 T103 
191        1/1                      state_d = StableSt;
           Tests:       T2 T22 T103 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T22 T103 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T22 T103 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T22 T103 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T22 T103 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T22 T103 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T22 T103 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T23,T24

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T23,T24
1	1	Covered	T5,T23,T24

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T22,T103

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T34,T35
1	0	Covered	T5,T23,T24
1	1	Covered	T2,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T103
0	1	Covered	T113,T118,T119
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T103
0	1	Unreachable
1	0	Covered	T2,T22,T103

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T34,T35
DetectSt	168	Covered	T2,T22,T103
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T22,T103

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T22,T103
DebounceSt->IdleSt	163	Covered	T34,T35,T30
DetectSt->IdleSt	186	Covered	T113,T118,T119
DetectSt->StableSt	191	Covered	T2,T22,T103
IdleSt->DebounceSt	148	Covered	T2,T34,T35
StableSt->IdleSt	206	Covered	T2,T22,T103

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T34,T35
0	1	Covered	T2,T34,T35
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T22,T103
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T23,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T22,T103
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T45,T106
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T113,T118,T119
DetectSt	-	-	-	-	0	1	-	Covered	T2,T22,T103
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T22,T103
StableSt	-	-	-	-	-	-	0	Covered	T2,T22,T103
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	117	0	0
CntIncr_A	6456720	211841	0	0
CntNoWrap_A	6456720	5999996	0	0
DetectStDropOut_A	6456720	9	0	0
DetectedOut_A	6456720	103562	0	0
DetectedPulseOut_A	6456720	26	0	0
DisabledIdleSt_A	6456720	5256023	0	0
DisabledNoDetection_A	6456720	5257898	0	0
EnterDebounceSt_A	6456720	83	0	0
EnterDetectSt_A	6456720	35	0	0
EnterStableSt_A	6456720	26	0	0
PulseIsPulse_A	6456720	26	0	0
StayInStableSt	6456720	103536	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_sticky_sva.StableStDropOut_A	6456720	383348	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	117	0	0
T2	1083	2	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	2	0	0
T30	0	1	0	0
T32	714	0	0	0
T34	0	2	0	0
T35	0	5	0	0
T36	486	0	0	0
T45	0	2	0	0
T81	502	0	0	0
T103	0	2	0	0
T104	0	4	0	0
T105	0	2	0	0
T106	0	7	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	211841	0	0
T2	1083	51	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	55	0	0
T30	0	63	0	0
T32	714	0	0	0
T34	0	33	0	0
T35	0	135	0	0
T36	486	0	0	0
T45	0	90	0	0
T81	502	0	0	0
T103	0	20	0	0
T104	0	96	0	0
T105	0	42	0	0
T106	0	581	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5999996	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	9	0	0
T113	183928	2	0	0
T118	0	4	0	0
T119	0	1	0	0
T124	37477	0	0	0
T153	1288	0	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	526	0	0	0
T176	502	0	0	0
T177	767	0	0	0
T178	609	0	0	0
T179	10546	0	0	0
T180	425	0	0	0
T181	497	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	103562	0	0
T2	1083	19	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	265	0	0
T32	714	0	0	0
T36	486	0	0	0
T81	502	0	0	0
T103	0	134	0	0
T104	0	91	0	0
T105	0	171	0	0
T107	0	15	0	0
T108	0	482	0	0
T114	0	1	0	0
T152	0	55	0	0
T153	0	101	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	26	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	1	0	0
T32	714	0	0	0
T36	486	0	0	0
T81	502	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T114	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5256023	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5257898	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	83	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	1	0	0
T30	0	2	0	0
T32	714	0	0	0
T34	0	2	0	0
T35	0	5	0	0
T36	486	0	0	0
T45	0	2	0	0
T81	502	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	7	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	35	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	1	0	0
T32	714	0	0	0
T36	486	0	0	0
T81	502	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T113	0	2	0	0
T152	0	2	0	0
T153	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	26	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	1	0	0
T32	714	0	0	0
T36	486	0	0	0
T81	502	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T114	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	26	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	1	0	0
T32	714	0	0	0
T36	486	0	0	0
T81	502	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T107	0	1	0	0
T108	0	1	0	0
T114	0	1	0	0
T152	0	2	0	0
T153	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	103536	0	0
T2	1083	18	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	264	0	0
T32	714	0	0	0
T36	486	0	0	0
T81	502	0	0	0
T103	0	133	0	0
T104	0	89	0	0
T105	0	170	0	0
T107	0	14	0	0
T108	0	481	0	0
T152	0	53	0	0
T153	0	100	0	0
T182	0	129	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	383348	0	0
T2	1083	92	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	335	0	0
T32	714	0	0	0
T36	486	0	0	0
T81	502	0	0	0
T103	0	597	0	0
T104	0	64	0	0
T105	0	237	0	0
T107	0	138	0	0
T108	0	58	0	0
T114	0	43	0	0
T152	0	230	0	0
T153	0	130	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T23 T24 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T5 T23 T24 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T34 T35 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T32 T33 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T32 T33 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T23 T24 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T23 T24 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T23 T24 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T23 T24 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T23 T24 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T23 T24 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T23 T24 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T23 T24 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T34 T35 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T34 T35 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T34 T35 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T34 T35 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T34 T35 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T35 T22 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T35 T22 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T35 T22 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T35 T111 T112 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T35 T22 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T35 T22 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T35 T22 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T113 T114 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T113 T114 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T22 T45 
191        1/1                      state_d = StableSt;
           Tests:       T2 T22 T45 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T22 T45 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T22 T45 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T22 T45 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T22 T45 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T22 T45 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T22 T45 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T23,T24

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T34,T35

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T34,T35

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T35,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T34,T35
1	0	Covered	T5,T23,T24
1	1	Covered	T2,T34,T35

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T45
0	1	Covered	T35,T113,T114
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T22,T45
0	1	Unreachable
1	0	Covered	T2,T22,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T34,T35
DetectSt	168	Covered	T2,T35,T22
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T22,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T35,T22
DebounceSt->IdleSt	163	Covered	T34,T35,T30
DetectSt->IdleSt	186	Covered	T35,T113,T114
DetectSt->StableSt	191	Covered	T2,T22,T45
IdleSt->DebounceSt	148	Covered	T2,T34,T35
StableSt->IdleSt	206	Covered	T2,T22,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T34,T35
0	1	Covered	T2,T34,T35
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T35,T22
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T34,T35
IdleSt	0	-	-	-	-	-	-	Covered	T5,T23,T24
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T35,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T111,T112
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T34,T35
DetectSt	-	-	-	-	1	-	-	Covered	T35,T113,T114
DetectSt	-	-	-	-	0	1	-	Covered	T2,T22,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T22,T45
StableSt	-	-	-	-	-	-	0	Covered	T2,T22,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	106	0	0
CntIncr_A	6456720	65852	0	0
CntNoWrap_A	6456720	6000007	0	0
DetectStDropOut_A	6456720	10	0	0
DetectedOut_A	6456720	272041	0	0
DetectedPulseOut_A	6456720	32	0	0
DisabledIdleSt_A	6456720	5256023	0	0
DisabledNoDetection_A	6456720	5257898	0	0
EnterDebounceSt_A	6456720	65	0	0
EnterDetectSt_A	6456720	42	0	0
EnterStableSt_A	6456720	32	0	0
PulseIsPulse_A	6456720	32	0	0
StayInStableSt	6456720	272009	0	0
gen_high_event_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_sticky_sva.StableStDropOut_A	6456720	44598	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	106	0	0
T2	1083	2	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	2	0	0
T30	0	1	0	0
T32	714	0	0	0
T34	0	2	0	0
T35	0	8	0	0
T36	486	0	0	0
T45	0	2	0	0
T81	502	0	0	0
T103	0	2	0	0
T104	0	4	0	0
T105	0	2	0	0
T106	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	65852	0	0
T2	1083	75	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	71	0	0
T30	0	65	0	0
T32	714	0	0	0
T34	0	35	0	0
T35	0	345	0	0
T36	486	0	0	0
T45	0	45	0	0
T81	502	0	0	0
T103	0	90	0	0
T104	0	36	0	0
T105	0	77	0	0
T106	0	78	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6000007	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	10	0	0
T12	503	0	0	0
T35	1320	3	0	0
T41	5117	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T84	663	0	0	0
T102	4414	0	0	0
T113	0	3	0	0
T114	0	1	0	0
T120	445	0	0	0
T183	0	2	0	0
T184	0	1	0	0
T185	405	0	0	0
T186	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	272041	0	0
T2	1083	53	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	482	0	0
T32	714	0	0	0
T36	486	0	0	0
T45	0	90	0	0
T81	502	0	0	0
T103	0	617	0	0
T104	0	34	0	0
T105	0	340	0	0
T106	0	290	0	0
T107	0	73	0	0
T108	0	299	0	0
T152	0	122	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	32	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	1	0	0
T32	714	0	0	0
T36	486	0	0	0
T45	0	1	0	0
T81	502	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	2	0	0
T107	0	1	0	0
T108	0	1	0	0
T152	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5256023	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5257898	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	65	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	1	0	0
T30	0	2	0	0
T32	714	0	0	0
T34	0	2	0	0
T35	0	5	0	0
T36	486	0	0	0
T45	0	1	0	0
T81	502	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	42	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	1	0	0
T32	714	0	0	0
T35	0	3	0	0
T36	486	0	0	0
T45	0	1	0	0
T81	502	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	2	0	0
T107	0	1	0	0
T152	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	32	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	1	0	0
T32	714	0	0	0
T36	486	0	0	0
T45	0	1	0	0
T81	502	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	2	0	0
T107	0	1	0	0
T108	0	1	0	0
T152	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	32	0	0
T2	1083	1	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	1	0	0
T32	714	0	0	0
T36	486	0	0	0
T45	0	1	0	0
T81	502	0	0	0
T103	0	1	0	0
T104	0	2	0	0
T105	0	1	0	0
T106	0	2	0	0
T107	0	1	0	0
T108	0	1	0	0
T152	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	272009	0	0
T2	1083	52	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	481	0	0
T32	714	0	0	0
T36	486	0	0	0
T45	0	89	0	0
T81	502	0	0	0
T103	0	616	0	0
T104	0	32	0	0
T105	0	339	0	0
T106	0	288	0	0
T107	0	72	0	0
T108	0	298	0	0
T152	0	120	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	44598	0	0
T2	1083	46	0	0
T3	556	0	0	0
T7	731	0	0	0
T9	479	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T22	0	123	0	0
T32	714	0	0	0
T36	486	0	0	0
T45	0	222	0	0
T81	502	0	0	0
T103	0	48	0	0
T104	0	210	0	0
T105	0	43	0	0
T106	0	635	0	0
T107	0	31	0	0
T108	0	238	0	0
T152	0	92	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T13 T30 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T13 T30 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T13 T30 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T13 T30 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T13 T30 
163        1/1                    state_d = IdleSt;
           Tests:       T34 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T13 T30 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T30 T63 
167        1/1                    if (trigger_active) begin
           Tests:       T13 T30 T63 
168        1/1                      state_d = DetectSt;
           Tests:       T13 T30 T63 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T187 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T13 T30 T63 
182        1/1                  cnt_en = 1'b1;
           Tests:       T13 T30 T63 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T13 T30 T63 
186        1/1                    state_d = IdleSt;
           Tests:       T110 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T110 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T13 T30 T63 
191        1/1                      state_d = StableSt;
           Tests:       T13 T30 T63 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T13 T30 T63 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T13 T30 T63 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T13 T30 T63 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T13 T30 T63 
206        1/1                    state_d = IdleSt;
           Tests:       T13 T30 T63 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T13 T30 T63 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T13,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T34,T13,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T30,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T34,T13
1	0	Covered	T4,T5,T6
1	1	Covered	T34,T13,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T30,T63
0	1	Covered	T110
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T30,T63
0	1	Covered	T13,T63,T188
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T30,T63
1	-	Covered	T13,T63,T188

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T13,T30
DetectSt	168	Covered	T13,T30,T63
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T30,T63

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T30,T63
DebounceSt->IdleSt	163	Covered	T34,T187
DetectSt->IdleSt	186	Covered	T110
DetectSt->StableSt	191	Covered	T13,T30,T63
IdleSt->DebounceSt	148	Covered	T34,T13,T30
StableSt->IdleSt	206	Covered	T13,T30,T63

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T13,T30
0	1	Covered	T34,T13,T30
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T30,T63
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T13,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T30,T63
DebounceSt	-	0	1	0	-	-	-	Covered	T187
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T13,T30
DetectSt	-	-	-	-	1	-	-	Covered	T110
DetectSt	-	-	-	-	0	1	-	Covered	T13,T30,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T30,T63
StableSt	-	-	-	-	-	-	0	Covered	T13,T30,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	50	0	0
CntIncr_A	6456720	48969	0	0
CntNoWrap_A	6456720	6000063	0	0
DetectStDropOut_A	6456720	1	0	0
DetectedOut_A	6456720	3730	0	0
DetectedPulseOut_A	6456720	23	0	0
DisabledIdleSt_A	6456720	5706544	0	0
DisabledNoDetection_A	6456720	5708387	0	0
EnterDebounceSt_A	6456720	26	0	0
EnterDetectSt_A	6456720	24	0	0
EnterStableSt_A	6456720	23	0	0
PulseIsPulse_A	6456720	23	0	0
StayInStableSt	6456720	3699	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	14	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	50	0	0
T11	781	0	0	0
T13	0	4	0	0
T30	0	2	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T63	0	2	0	0
T64	0	2	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T102	4414	0	0	0
T110	0	4	0	0
T177	0	2	0	0
T188	0	4	0	0
T189	0	2	0	0
T190	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	48969	0	0
T11	781	0	0	0
T13	0	56	0	0
T30	0	28	0	0
T34	7688	39	0	0
T35	1320	0	0	0
T63	0	34	0	0
T64	0	42	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T102	4414	0	0	0
T110	0	170	0	0
T177	0	92	0	0
T188	0	22	0	0
T189	0	57	0	0
T190	0	188	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6000063	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	1	0	0
T110	1057	1	0	0
T191	497	0	0	0
T192	1276	0	0	0
T193	411	0	0	0
T194	649	0	0	0
T195	2311	0	0	0
T196	502	0	0	0
T197	522	0	0	0
T198	562	0	0	0
T199	764	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	3730	0	0
T13	768	148	0	0
T30	0	4	0	0
T63	0	42	0	0
T64	0	39	0	0
T69	647	0	0	0
T88	494	0	0	0
T110	0	195	0	0
T177	0	41	0	0
T188	0	82	0	0
T189	0	45	0	0
T190	0	178	0	0
T200	0	44	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	23	0	0
T13	768	2	0	0
T30	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T69	647	0	0	0
T88	494	0	0	0
T110	0	1	0	0
T177	0	1	0	0
T188	0	2	0	0
T189	0	1	0	0
T190	0	2	0	0
T200	0	1	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5706544	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5708387	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	26	0	0
T11	781	0	0	0
T13	0	2	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T63	0	1	0	0
T64	0	1	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T102	4414	0	0	0
T110	0	2	0	0
T177	0	1	0	0
T188	0	2	0	0
T189	0	1	0	0
T190	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	24	0	0
T13	768	2	0	0
T30	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T69	647	0	0	0
T88	494	0	0	0
T110	0	2	0	0
T177	0	1	0	0
T188	0	2	0	0
T189	0	1	0	0
T190	0	2	0	0
T200	0	1	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	23	0	0
T13	768	2	0	0
T30	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T69	647	0	0	0
T88	494	0	0	0
T110	0	1	0	0
T177	0	1	0	0
T188	0	2	0	0
T189	0	1	0	0
T190	0	2	0	0
T200	0	1	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	23	0	0
T13	768	2	0	0
T30	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0
T69	647	0	0	0
T88	494	0	0	0
T110	0	1	0	0
T177	0	1	0	0
T188	0	2	0	0
T189	0	1	0	0
T190	0	2	0	0
T200	0	1	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	3699	0	0
T13	768	145	0	0
T30	0	3	0	0
T63	0	41	0	0
T64	0	37	0	0
T69	647	0	0	0
T88	494	0	0	0
T110	0	194	0	0
T177	0	40	0	0
T188	0	79	0	0
T189	0	43	0	0
T190	0	175	0	0
T200	0	43	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	14	0	0
T13	768	1	0	0
T63	0	1	0	0
T69	647	0	0	0
T88	494	0	0	0
T110	0	1	0	0
T177	0	1	0	0
T188	0	1	0	0
T190	0	1	0	0
T200	0	1	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0
T208	0	1	0	0
T209	0	2	0	0
T210	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T7 T8 T34 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T7 T8 T34 
149        1/1                    cnt_en = 1'b1;
           Tests:       T7 T8 T34 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T7 T8 T34 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T7 T8 T34 
163        1/1                    state_d = IdleSt;
           Tests:       T34 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 
165        1/1                  end else if (cnt_done) begin
           Tests:       T7 T8 T34 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T7 T8 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T7 T8 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T7 T8 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T188 T110 T211 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T7 T8 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T7 T8 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T7 T8 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T57 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T57 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T7 T8 T11 
191        1/1                      state_d = StableSt;
           Tests:       T7 T8 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T7 T8 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T7 T8 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T7 T8 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T7 T8 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T30 T64 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T7 T8 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T7,T8,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T8
1	0	Covered	T5,T23,T24
1	1	Covered	T7,T8,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T11
0	1	Covered	T57
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T11
0	1	Covered	T8,T64,T188
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T11
1	-	Covered	T8,T64,T188

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T34
DetectSt	168	Covered	T7,T8,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T11
DebounceSt->IdleSt	163	Covered	T34,T188,T110
DetectSt->IdleSt	186	Covered	T57
DetectSt->StableSt	191	Covered	T7,T8,T11
IdleSt->DebounceSt	148	Covered	T7,T8,T34
StableSt->IdleSt	206	Covered	T8,T30,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T7,T8,T34
0	1	Covered	T7,T8,T34
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T11
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T188,T110,T211
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T34
DetectSt	-	-	-	-	1	-	-	Covered	T57
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T30,T64
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	100	0	0
CntIncr_A	6456720	3231	0	0
CntNoWrap_A	6456720	6000013	0	0
DetectStDropOut_A	6456720	1	0	0
DetectedOut_A	6456720	4457	0	0
DetectedPulseOut_A	6456720	46	0	0
DisabledIdleSt_A	6456720	5986221	0	0
DisabledNoDetection_A	6456720	5988062	0	0
EnterDebounceSt_A	6456720	54	0	0
EnterDetectSt_A	6456720	47	0	0
EnterStableSt_A	6456720	46	0	0
PulseIsPulse_A	6456720	46	0	0
StayInStableSt	6456720	4386	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6456720	1518	0	0
gen_low_level_sva.LowLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	100	0	0
T7	731	2	0	0
T8	0	2	0	0
T9	479	0	0	0
T11	0	2	0	0
T30	0	2	0	0
T32	714	0	0	0
T34	0	1	0	0
T37	492	0	0	0
T38	623	0	0	0
T57	0	4	0	0
T60	0	2	0	0
T64	0	2	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T188	0	3	0	0
T189	0	2	0	0
T212	446	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	3231	0	0
T7	731	97	0	0
T8	0	57	0	0
T9	479	0	0	0
T11	0	63	0	0
T30	0	28	0	0
T32	714	0	0	0
T34	0	39	0	0
T37	492	0	0	0
T38	623	0	0	0
T57	0	118	0	0
T60	0	46	0	0
T64	0	42	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T188	0	22	0	0
T189	0	57	0	0
T212	446	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6000013	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	1	0	0
T22	1281	0	0	0
T30	7514	0	0	0
T57	735	1	0	0
T90	492	0	0	0
T213	430	0	0	0
T214	522	0	0	0
T215	1934	0	0	0
T216	1850	0	0	0
T217	447	0	0	0
T218	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	4457	0	0
T7	731	224	0	0
T8	0	44	0	0
T9	479	0	0	0
T11	0	309	0	0
T30	0	6	0	0
T32	714	0	0	0
T37	492	0	0	0
T38	623	0	0	0
T57	0	107	0	0
T58	0	269	0	0
T60	0	114	0	0
T64	0	4	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T188	0	9	0	0
T189	0	301	0	0
T212	446	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46	0	0
T7	731	1	0	0
T8	0	1	0	0
T9	479	0	0	0
T11	0	1	0	0
T30	0	1	0	0
T32	714	0	0	0
T37	492	0	0	0
T38	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T64	0	1	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T188	0	1	0	0
T189	0	1	0	0
T212	446	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5986221	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5988062	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	54	0	0
T7	731	1	0	0
T8	0	1	0	0
T9	479	0	0	0
T11	0	1	0	0
T30	0	1	0	0
T32	714	0	0	0
T34	0	1	0	0
T37	492	0	0	0
T38	623	0	0	0
T57	0	2	0	0
T60	0	1	0	0
T64	0	1	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T188	0	2	0	0
T189	0	1	0	0
T212	446	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	47	0	0
T7	731	1	0	0
T8	0	1	0	0
T9	479	0	0	0
T11	0	1	0	0
T30	0	1	0	0
T32	714	0	0	0
T37	492	0	0	0
T38	623	0	0	0
T57	0	2	0	0
T58	0	1	0	0
T60	0	1	0	0
T64	0	1	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T188	0	1	0	0
T189	0	1	0	0
T212	446	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46	0	0
T7	731	1	0	0
T8	0	1	0	0
T9	479	0	0	0
T11	0	1	0	0
T30	0	1	0	0
T32	714	0	0	0
T37	492	0	0	0
T38	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T64	0	1	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T188	0	1	0	0
T189	0	1	0	0
T212	446	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46	0	0
T7	731	1	0	0
T8	0	1	0	0
T9	479	0	0	0
T11	0	1	0	0
T30	0	1	0	0
T32	714	0	0	0
T37	492	0	0	0
T38	623	0	0	0
T57	0	1	0	0
T58	0	1	0	0
T60	0	1	0	0
T64	0	1	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T188	0	1	0	0
T189	0	1	0	0
T212	446	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	4386	0	0
T7	731	222	0	0
T8	0	43	0	0
T9	479	0	0	0
T11	0	307	0	0
T30	0	5	0	0
T32	714	0	0	0
T37	492	0	0	0
T38	623	0	0	0
T57	0	105	0	0
T58	0	267	0	0
T60	0	112	0	0
T64	0	3	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T188	0	8	0	0
T189	0	300	0	0
T212	446	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	1518	0	0
T1	506	0	0	0
T5	504	3	0	0
T6	693	0	0	0
T7	0	1	0	0
T14	423	3	0	0
T15	424	2	0	0
T16	477	0	0	0
T17	0	4	0	0
T18	0	6	0	0
T23	423	2	0	0
T24	506	7	0	0
T25	560	0	0	0
T26	406	0	0	0
T36	0	4	0	0
T81	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	20	0	0
T8	978	1	0	0
T10	511	0	0	0
T53	0	1	0	0
T64	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T110	0	1	0	0
T187	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	2	0	0
T200	0	1	0	0
T219	0	1	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0