Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T4 T5 T6
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T6 T2 T7
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T4 T6 T1
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T4 T6 T1
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T6 T2 T7
149 1/1 cnt_en = 1'b1;
Tests: T6 T2 T7
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T6 T2 T7
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T6 T2 T7
163 1/1 state_d = IdleSt;
Tests: T34 T30
164 1/1 cnt_clr = 1'b1;
Tests: T34 T30
165 1/1 end else if (cnt_done) begin
Tests: T6 T2 T7
166 1/1 cnt_clr = 1'b1;
Tests: T6 T2 T7
167 1/1 if (trigger_active) begin
Tests: T6 T2 T7
168 1/1 state_d = DetectSt;
Tests: T6 T7 T38
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T2 T67 T35
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T6 T7 T38
182 1/1 cnt_en = 1'b1;
Tests: T6 T7 T38
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T6 T7 T38
186 1/1 state_d = IdleSt;
Tests: T57 T107 T108
187 1/1 cnt_clr = 1'b1;
Tests: T57 T107 T108
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T6 T7 T38
191 1/1 state_d = StableSt;
Tests: T6 T7 T38
192 1/1 cnt_clr = 1'b1;
Tests: T6 T7 T38
193 1/1 event_detected_o = 1'b1;
Tests: T6 T7 T38
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T6 T7 T38
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T6 T7 T38
206 1/1 state_d = IdleSt;
Tests: T6 T38 T39
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T6 T7 T38
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T6
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T3 T8
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T4 T1 T16
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T4 T1 T16
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T2 T3 T8
149 1/1 cnt_en = 1'b1;
Tests: T2 T3 T8
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T3 T8
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T3 T8
163 1/1 state_d = IdleSt;
Tests: T34 T30
164 1/1 cnt_clr = 1'b1;
Tests: T34 T30
165 1/1 end else if (cnt_done) begin
Tests: T2 T3 T8
166 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T35
167 1/1 if (trigger_active) begin
Tests: T2 T3 T35
168 1/1 state_d = DetectSt;
Tests: T2 T3 T13
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T35 T45 T106
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T3 T13
182 1/1 cnt_en = 1'b1;
Tests: T2 T3 T13
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T3 T13
186 1/1 state_d = IdleSt;
Tests: T13 T109 T110
187 1/1 cnt_clr = 1'b1;
Tests: T13 T109 T110
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T3 T13
191 1/1 state_d = StableSt;
Tests: T2 T3 T13
192 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T13
193 1/1 event_detected_o = 1'b1;
Tests: T2 T3 T13
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T3 T13
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T3 T13
206 1/1 state_d = IdleSt;
Tests: T2 T11 T13
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T3 T13
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T5 T23 T24
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T5 T23 T24
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T34 T35
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T2 T32 T33
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T2 T32 T33
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T5 T23 T24
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T5 T23 T24
129 1/1 cnt_en = 1'b0;
Tests: T5 T23 T24
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T5 T23 T24
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T5 T23 T24
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T5 T23 T24
139
140 1/1 unique case (state_q)
Tests: T5 T23 T24
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T5 T23 T24
148 1/1 state_d = DebounceSt;
Tests: T2 T34 T35
149 1/1 cnt_en = 1'b1;
Tests: T2 T34 T35
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T34 T35
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T34 T35
163 1/1 state_d = IdleSt;
Tests: T34 T30
164 1/1 cnt_clr = 1'b1;
Tests: T34 T30
165 1/1 end else if (cnt_done) begin
Tests: T2 T34 T35
166 1/1 cnt_clr = 1'b1;
Tests: T2 T35 T22
167 1/1 if (trigger_active) begin
Tests: T2 T35 T22
168 1/1 state_d = DetectSt;
Tests: T2 T35 T22
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T35 T111 T112
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T35 T22
182 1/1 cnt_en = 1'b1;
Tests: T2 T35 T22
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T35 T22
186 1/1 state_d = IdleSt;
Tests: T35 T113 T114
187 1/1 cnt_clr = 1'b1;
Tests: T35 T113 T114
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T22 T45
191 1/1 state_d = StableSt;
Tests: T2 T22 T45
192 1/1 cnt_clr = 1'b1;
Tests: T2 T22 T45
193 1/1 event_detected_o = 1'b1;
Tests: T2 T22 T45
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T22 T45
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T22 T45
206 1/1 state_d = IdleSt;
Tests: T2 T22 T45
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T22 T45
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T34 T41 T21
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T34 T41 T21
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T16 T40
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T4 T1 T16
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T4 T1 T16
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T16 T40
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T16 T40
129 1/1 cnt_en = 1'b0;
Tests: T1 T16 T40
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T16 T40
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T16 T40
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T16 T40
139
140 1/1 unique case (state_q)
Tests: T1 T16 T40
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T16 T40
148 1/1 state_d = DebounceSt;
Tests: T1 T16 T40
149 1/1 cnt_en = 1'b1;
Tests: T1 T16 T40
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T16 T40
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T16 T40
163 1/1 state_d = IdleSt;
Tests: T34 T30
164 1/1 cnt_clr = 1'b1;
Tests: T34 T30
165 1/1 end else if (cnt_done) begin
Tests: T1 T16 T40
166 1/1 cnt_clr = 1'b1;
Tests: T1 T16 T40
167 1/1 if (trigger_active) begin
Tests: T1 T16 T40
168 1/1 state_d = DetectSt;
Tests: T1 T16 T40
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T34 T30
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T16 T40
182 1/1 cnt_en = 1'b1;
Tests: T1 T16 T40
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T16 T40
186 1/1 state_d = IdleSt;
Tests: T34 T41 T21
187 1/1 cnt_clr = 1'b1;
Tests: T34 T41 T21
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T16 T40
191 1/1 state_d = StableSt;
Tests: T1 T16 T40
192 1/1 cnt_clr = 1'b1;
Tests: T1 T16 T40
193 1/1 event_detected_o = 1'b1;
Tests: T1 T16 T40
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T16 T40
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T16 T40
206 1/1 state_d = IdleSt;
Tests: T34 T21 T30
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T16 T40
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T1 T16
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T4 T1 T16
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T4 T1 T16
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T4 T1 T16
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T4 T1 T16
149 1/1 cnt_en = 1'b1;
Tests: T4 T1 T16
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T4 T1 T16
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T4 T1 T16
163 1/1 state_d = IdleSt;
Tests: T34 T30
164 1/1 cnt_clr = 1'b1;
Tests: T34 T30
165 1/1 end else if (cnt_done) begin
Tests: T4 T1 T16
166 1/1 cnt_clr = 1'b1;
Tests: T4 T1 T16
167 1/1 if (trigger_active) begin
Tests: T4 T1 T16
168 1/1 state_d = DetectSt;
Tests: T1 T9 T10
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T4 T16 T66
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T9 T10
182 1/1 cnt_en = 1'b1;
Tests: T1 T9 T10
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T9 T10
186 1/1 state_d = IdleSt;
Tests: T34 T30 T46
187 1/1 cnt_clr = 1'b1;
Tests: T34 T30 T46
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T9 T10
191 1/1 state_d = StableSt;
Tests: T1 T9 T10
192 1/1 cnt_clr = 1'b1;
Tests: T1 T9 T10
193 1/1 event_detected_o = 1'b1;
Tests: T1 T9 T10
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T9 T10
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T9 T10
206 1/1 state_d = IdleSt;
Tests: T1 T9 T10
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T9 T10
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T1,T16 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T1,T16 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T1,T16 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T1,T16 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T9,T10 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T1,T16 |
| 1 | 0 | Covered | T96,T92,T34 |
| 1 | 1 | Covered | T4,T1,T16 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T9,T10 |
| 0 | 1 | Covered | T34,T30,T46 |
| 1 | 0 | Covered | T34,T30 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T9,T10 |
| 0 | 1 | Covered | T1,T9,T10 |
| 1 | 0 | Covered | T34,T30,T115 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T9,T10 |
| 1 | - | Covered | T1,T9,T10 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T6,T7,T38 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T6,T7,T38 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T6,T7,T38 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T6,T3,T7 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T6,T7,T38 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T7,T38 |
| 0 | 1 | Covered | T57,T110,T116 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T6,T7,T38 |
| 0 | 1 | Covered | T6,T38,T39 |
| 1 | 0 | Covered | T30 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T6,T7,T38 |
| 1 | - | Covered | T6,T38,T39 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T34,T41,T21 |
| 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T16,T40 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T16,T40 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T16,T40 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T34,T41,T21 |
| 1 | 0 | Covered | T34,T21,T30 |
| 1 | 1 | Covered | T1,T16,T40 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T16,T40 |
| 0 | 1 | Covered | T34,T41,T21 |
| 1 | 0 | Covered | T34,T21,T30 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T16,T40 |
| 0 | 1 | Covered | T34,T21,T30 |
| 1 | 0 | Covered | T34,T30,T117 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T16,T40 |
| 1 | - | Covered | T34,T21,T30 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T23,T24 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T34,T35 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T34,T35 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T35,T22 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T34,T35 |
| 1 | 0 | Covered | T5,T23,T24 |
| 1 | 1 | Covered | T2,T34,T35 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T22,T45 |
| 0 | 1 | Covered | T35,T113,T114 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T22,T45 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T22,T45 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T8,T34 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T8,T34 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T8,T11 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T7,T8 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T3,T8,T34 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T8,T11 |
| 0 | 1 | Covered | T13,T109,T110 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T8,T11 |
| 0 | 1 | Covered | T11,T13,T55 |
| 1 | 0 | Covered | T30 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T3,T8,T11 |
| 1 | - | Covered | T11,T13,T55 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T23,T24 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T5,T23,T24 |
| 1 | 1 | Covered | T5,T23,T24 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T34,T35 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T34,T35 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T22,T103 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T34,T35 |
| 1 | 0 | Covered | T5,T23,T24 |
| 1 | 1 | Covered | T2,T34,T35 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T22,T103 |
| 0 | 1 | Covered | T113,T118,T119 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T22,T103 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T22,T103 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T6,T23 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T6,T23 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T34,T35 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T34,T35 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T103,T104,T105 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T34,T35 |
| 1 | 0 | Covered | T5,T6,T23 |
| 1 | 1 | Covered | T2,T34,T35 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T103,T104,T105 |
| 0 | 1 | Covered | T107,T108,T118 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T103,T104,T105 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T103,T104,T105 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DebounceSt |
148 |
Covered |
T6,T7,T38 |
| DetectSt |
168 |
Covered |
T6,T7,T38 |
| IdleSt |
163 |
Covered |
T4,T5,T6 |
| StableSt |
191 |
Covered |
T6,T7,T38 |
| transitions | Line No. | Covered | Tests |
| DebounceSt->DetectSt |
168 |
Covered |
T6,T7,T38 |
| DebounceSt->IdleSt |
163 |
Covered |
T2,T67,T34 |
| DetectSt->IdleSt |
186 |
Covered |
T35,T13,T57 |
| DetectSt->StableSt |
191 |
Covered |
T6,T7,T38 |
| IdleSt->DebounceSt |
148 |
Covered |
T6,T7,T38 |
| StableSt->IdleSt |
206 |
Covered |
T6,T38,T39 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T6,T7,T38 |
| 0 |
1 |
Covered |
T6,T7,T38 |
| 0 |
0 |
Covered |
T4,T5,T6 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T6,T7,T38 |
| 0 |
Covered |
T4,T5,T6 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T6,T7,T38 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T34,T30 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T6,T7,T38 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T2,T67,T35 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T6,T7,T38 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T34,T13,T57 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T6,T7,T38 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T9,T10 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T6,T38,T39 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T6,T7,T38 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T16,T2 |
| 0 |
1 |
Covered |
T1,T16,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T16,T2 |
| 0 |
Covered |
T4,T5,T6 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T16,T2 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T23,T24 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T34,T30 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T1,T16,T2 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T34,T35,T30 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T16,T2 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T34,T35,T41 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T1,T16,T2 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T16,T40 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T2,T34,T21 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T16,T2 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
16843 |
0 |
0 |
| T1 |
1518 |
4 |
0 |
0 |
| T2 |
1083 |
0 |
0 |
0 |
| T3 |
556 |
0 |
0 |
0 |
| T4 |
448 |
1 |
0 |
0 |
| T5 |
504 |
0 |
0 |
0 |
| T6 |
1386 |
4 |
0 |
0 |
| T9 |
0 |
2 |
0 |
0 |
| T10 |
0 |
4 |
0 |
0 |
| T11 |
781 |
0 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T14 |
1269 |
0 |
0 |
0 |
| T15 |
1272 |
0 |
0 |
0 |
| T16 |
954 |
3 |
0 |
0 |
| T17 |
1044 |
0 |
0 |
0 |
| T18 |
532 |
0 |
0 |
0 |
| T19 |
533 |
0 |
0 |
0 |
| T20 |
402 |
0 |
0 |
0 |
| T23 |
846 |
0 |
0 |
0 |
| T24 |
1012 |
0 |
0 |
0 |
| T25 |
1120 |
0 |
0 |
0 |
| T26 |
812 |
0 |
0 |
0 |
| T30 |
0 |
18 |
0 |
0 |
| T34 |
7688 |
25 |
0 |
0 |
| T38 |
0 |
2 |
0 |
0 |
| T39 |
0 |
2 |
0 |
0 |
| T40 |
0 |
3 |
0 |
0 |
| T41 |
0 |
28 |
0 |
0 |
| T66 |
0 |
1 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
0 |
3 |
0 |
0 |
| T70 |
0 |
4 |
0 |
0 |
| T71 |
0 |
6 |
0 |
0 |
| T72 |
0 |
5 |
0 |
0 |
| T74 |
1752 |
0 |
0 |
0 |
| T75 |
4411 |
0 |
0 |
0 |
| T120 |
0 |
1 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
1830410 |
0 |
0 |
| T1 |
1518 |
46 |
0 |
0 |
| T2 |
1083 |
0 |
0 |
0 |
| T3 |
556 |
0 |
0 |
0 |
| T4 |
448 |
20 |
0 |
0 |
| T5 |
504 |
0 |
0 |
0 |
| T6 |
1386 |
54 |
0 |
0 |
| T9 |
0 |
25 |
0 |
0 |
| T10 |
0 |
46 |
0 |
0 |
| T11 |
781 |
0 |
0 |
0 |
| T12 |
0 |
21 |
0 |
0 |
| T14 |
1269 |
0 |
0 |
0 |
| T15 |
1272 |
0 |
0 |
0 |
| T16 |
954 |
41 |
0 |
0 |
| T17 |
1044 |
0 |
0 |
0 |
| T18 |
532 |
0 |
0 |
0 |
| T19 |
533 |
0 |
0 |
0 |
| T20 |
402 |
0 |
0 |
0 |
| T23 |
846 |
0 |
0 |
0 |
| T24 |
1012 |
0 |
0 |
0 |
| T25 |
1120 |
0 |
0 |
0 |
| T26 |
812 |
0 |
0 |
0 |
| T30 |
0 |
612 |
0 |
0 |
| T34 |
7688 |
758 |
0 |
0 |
| T38 |
0 |
53 |
0 |
0 |
| T39 |
0 |
86 |
0 |
0 |
| T40 |
0 |
41 |
0 |
0 |
| T41 |
0 |
697 |
0 |
0 |
| T66 |
0 |
20 |
0 |
0 |
| T67 |
0 |
10 |
0 |
0 |
| T68 |
0 |
20 |
0 |
0 |
| T69 |
0 |
92 |
0 |
0 |
| T70 |
0 |
63 |
0 |
0 |
| T71 |
0 |
183 |
0 |
0 |
| T72 |
0 |
160 |
0 |
0 |
| T74 |
1752 |
0 |
0 |
0 |
| T75 |
4411 |
0 |
0 |
0 |
| T120 |
0 |
20 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
155986095 |
0 |
0 |
| T1 |
13156 |
2726 |
0 |
0 |
| T4 |
11648 |
1221 |
0 |
0 |
| T5 |
13104 |
2678 |
0 |
0 |
| T6 |
18018 |
7588 |
0 |
0 |
| T14 |
10998 |
572 |
0 |
0 |
| T15 |
11024 |
598 |
0 |
0 |
| T23 |
10998 |
572 |
0 |
0 |
| T24 |
13156 |
2730 |
0 |
0 |
| T25 |
14560 |
4134 |
0 |
0 |
| T26 |
10556 |
130 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
2239 |
0 |
0 |
| T21 |
0 |
4 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T34 |
7688 |
1 |
0 |
0 |
| T41 |
0 |
14 |
0 |
0 |
| T50 |
8908 |
21 |
0 |
0 |
| T73 |
0 |
28 |
0 |
0 |
| T97 |
0 |
13 |
0 |
0 |
| T98 |
0 |
14 |
0 |
0 |
| T101 |
0 |
10 |
0 |
0 |
| T117 |
0 |
12 |
0 |
0 |
| T121 |
0 |
12 |
0 |
0 |
| T122 |
0 |
24 |
0 |
0 |
| T123 |
0 |
19 |
0 |
0 |
| T124 |
0 |
12 |
0 |
0 |
| T125 |
0 |
2 |
0 |
0 |
| T126 |
0 |
10 |
0 |
0 |
| T127 |
0 |
3 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
| T129 |
694 |
1 |
0 |
0 |
| T130 |
24386 |
4 |
0 |
0 |
| T131 |
0 |
4 |
0 |
0 |
| T132 |
14826 |
0 |
0 |
0 |
| T133 |
1195 |
0 |
0 |
0 |
| T134 |
586 |
0 |
0 |
0 |
| T135 |
504 |
0 |
0 |
0 |
| T136 |
700 |
0 |
0 |
0 |
| T137 |
403 |
0 |
0 |
0 |
| T138 |
521 |
0 |
0 |
0 |
| T139 |
423 |
0 |
0 |
0 |
| T140 |
491 |
0 |
0 |
0 |
| T141 |
1907 |
0 |
0 |
0 |
| T142 |
522 |
0 |
0 |
0 |
| T143 |
409 |
0 |
0 |
0 |
| T144 |
693 |
0 |
0 |
0 |
| T145 |
17871 |
0 |
0 |
0 |
| T146 |
92624 |
0 |
0 |
0 |
| T147 |
423 |
0 |
0 |
0 |
| T148 |
498 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
1382321 |
0 |
0 |
| T1 |
1518 |
84 |
0 |
0 |
| T2 |
2166 |
0 |
0 |
0 |
| T3 |
1112 |
0 |
0 |
0 |
| T6 |
693 |
15 |
0 |
0 |
| T9 |
0 |
4 |
0 |
0 |
| T10 |
0 |
89 |
0 |
0 |
| T11 |
781 |
0 |
0 |
0 |
| T12 |
0 |
82 |
0 |
0 |
| T14 |
1269 |
0 |
0 |
0 |
| T15 |
1272 |
0 |
0 |
0 |
| T16 |
1431 |
52 |
0 |
0 |
| T17 |
1566 |
0 |
0 |
0 |
| T18 |
1064 |
0 |
0 |
0 |
| T19 |
1066 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T23 |
423 |
0 |
0 |
0 |
| T24 |
506 |
0 |
0 |
0 |
| T25 |
560 |
0 |
0 |
0 |
| T26 |
406 |
0 |
0 |
0 |
| T30 |
0 |
482 |
0 |
0 |
| T34 |
7688 |
543 |
0 |
0 |
| T38 |
0 |
9 |
0 |
0 |
| T39 |
0 |
6 |
0 |
0 |
| T40 |
0 |
26 |
0 |
0 |
| T45 |
0 |
3 |
0 |
0 |
| T46 |
0 |
108 |
0 |
0 |
| T49 |
0 |
19 |
0 |
0 |
| T65 |
0 |
40 |
0 |
0 |
| T69 |
0 |
4 |
0 |
0 |
| T70 |
0 |
19 |
0 |
0 |
| T71 |
0 |
27 |
0 |
0 |
| T72 |
0 |
9 |
0 |
0 |
| T74 |
1752 |
0 |
0 |
0 |
| T75 |
4411 |
0 |
0 |
0 |
| T76 |
406 |
0 |
0 |
0 |
| T77 |
507 |
0 |
0 |
0 |
| T149 |
0 |
21 |
0 |
0 |
| T150 |
0 |
23 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
5206 |
0 |
0 |
| T1 |
1518 |
2 |
0 |
0 |
| T2 |
2166 |
0 |
0 |
0 |
| T3 |
1112 |
0 |
0 |
0 |
| T6 |
693 |
2 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
781 |
0 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T14 |
1269 |
0 |
0 |
0 |
| T15 |
1272 |
0 |
0 |
0 |
| T16 |
1431 |
1 |
0 |
0 |
| T17 |
1566 |
0 |
0 |
0 |
| T18 |
1064 |
0 |
0 |
0 |
| T19 |
1066 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T23 |
423 |
0 |
0 |
0 |
| T24 |
506 |
0 |
0 |
0 |
| T25 |
560 |
0 |
0 |
0 |
| T26 |
406 |
0 |
0 |
0 |
| T30 |
0 |
7 |
0 |
0 |
| T34 |
7688 |
6 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T39 |
0 |
1 |
0 |
0 |
| T40 |
0 |
1 |
0 |
0 |
| T45 |
0 |
1 |
0 |
0 |
| T46 |
0 |
2 |
0 |
0 |
| T49 |
0 |
2 |
0 |
0 |
| T65 |
0 |
3 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
3 |
0 |
0 |
| T72 |
0 |
2 |
0 |
0 |
| T74 |
1752 |
0 |
0 |
0 |
| T75 |
4411 |
0 |
0 |
0 |
| T76 |
406 |
0 |
0 |
0 |
| T77 |
507 |
0 |
0 |
0 |
| T149 |
0 |
3 |
0 |
0 |
| T150 |
0 |
3 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
146870830 |
0 |
0 |
| T1 |
13156 |
2548 |
0 |
0 |
| T4 |
11648 |
1179 |
0 |
0 |
| T5 |
13104 |
2678 |
0 |
0 |
| T6 |
18018 |
7454 |
0 |
0 |
| T14 |
10998 |
572 |
0 |
0 |
| T15 |
11024 |
598 |
0 |
0 |
| T23 |
10998 |
572 |
0 |
0 |
| T24 |
13156 |
2730 |
0 |
0 |
| T25 |
14560 |
4134 |
0 |
0 |
| T26 |
10556 |
130 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
146915993 |
0 |
0 |
| T1 |
13156 |
2572 |
0 |
0 |
| T4 |
11648 |
1204 |
0 |
0 |
| T5 |
13104 |
2704 |
0 |
0 |
| T6 |
18018 |
7480 |
0 |
0 |
| T14 |
10998 |
598 |
0 |
0 |
| T15 |
11024 |
624 |
0 |
0 |
| T23 |
10998 |
598 |
0 |
0 |
| T24 |
13156 |
2756 |
0 |
0 |
| T25 |
14560 |
4160 |
0 |
0 |
| T26 |
10556 |
156 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
8626 |
0 |
0 |
| T1 |
1518 |
2 |
0 |
0 |
| T2 |
1083 |
0 |
0 |
0 |
| T3 |
556 |
0 |
0 |
0 |
| T4 |
448 |
1 |
0 |
0 |
| T5 |
504 |
0 |
0 |
0 |
| T6 |
1386 |
2 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
781 |
0 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T14 |
1269 |
0 |
0 |
0 |
| T15 |
1272 |
0 |
0 |
0 |
| T16 |
954 |
2 |
0 |
0 |
| T17 |
1044 |
0 |
0 |
0 |
| T18 |
532 |
0 |
0 |
0 |
| T19 |
533 |
0 |
0 |
0 |
| T20 |
402 |
0 |
0 |
0 |
| T23 |
846 |
0 |
0 |
0 |
| T24 |
1012 |
0 |
0 |
0 |
| T25 |
1120 |
0 |
0 |
0 |
| T26 |
812 |
0 |
0 |
0 |
| T30 |
0 |
10 |
0 |
0 |
| T34 |
7688 |
15 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T39 |
0 |
1 |
0 |
0 |
| T40 |
0 |
2 |
0 |
0 |
| T41 |
0 |
14 |
0 |
0 |
| T66 |
0 |
1 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
0 |
2 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
3 |
0 |
0 |
| T72 |
0 |
3 |
0 |
0 |
| T74 |
1752 |
0 |
0 |
0 |
| T75 |
4411 |
0 |
0 |
0 |
| T120 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
8229 |
0 |
0 |
| T1 |
1518 |
2 |
0 |
0 |
| T2 |
2166 |
0 |
0 |
0 |
| T3 |
1112 |
0 |
0 |
0 |
| T6 |
693 |
2 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
781 |
0 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T14 |
1269 |
0 |
0 |
0 |
| T15 |
1272 |
0 |
0 |
0 |
| T16 |
1431 |
1 |
0 |
0 |
| T17 |
1566 |
0 |
0 |
0 |
| T18 |
1064 |
0 |
0 |
0 |
| T19 |
1066 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T23 |
423 |
0 |
0 |
0 |
| T24 |
506 |
0 |
0 |
0 |
| T25 |
560 |
0 |
0 |
0 |
| T26 |
406 |
0 |
0 |
0 |
| T30 |
0 |
11 |
0 |
0 |
| T34 |
7688 |
10 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T39 |
0 |
1 |
0 |
0 |
| T40 |
0 |
1 |
0 |
0 |
| T45 |
0 |
1 |
0 |
0 |
| T46 |
0 |
2 |
0 |
0 |
| T49 |
0 |
2 |
0 |
0 |
| T65 |
0 |
3 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
3 |
0 |
0 |
| T72 |
0 |
2 |
0 |
0 |
| T74 |
1752 |
0 |
0 |
0 |
| T75 |
4411 |
0 |
0 |
0 |
| T76 |
406 |
0 |
0 |
0 |
| T77 |
507 |
0 |
0 |
0 |
| T149 |
0 |
3 |
0 |
0 |
| T150 |
0 |
3 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
5206 |
0 |
0 |
| T1 |
1518 |
2 |
0 |
0 |
| T2 |
2166 |
0 |
0 |
0 |
| T3 |
1112 |
0 |
0 |
0 |
| T6 |
693 |
2 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
781 |
0 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T14 |
1269 |
0 |
0 |
0 |
| T15 |
1272 |
0 |
0 |
0 |
| T16 |
1431 |
1 |
0 |
0 |
| T17 |
1566 |
0 |
0 |
0 |
| T18 |
1064 |
0 |
0 |
0 |
| T19 |
1066 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T23 |
423 |
0 |
0 |
0 |
| T24 |
506 |
0 |
0 |
0 |
| T25 |
560 |
0 |
0 |
0 |
| T26 |
406 |
0 |
0 |
0 |
| T30 |
0 |
7 |
0 |
0 |
| T34 |
7688 |
6 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T39 |
0 |
1 |
0 |
0 |
| T40 |
0 |
1 |
0 |
0 |
| T45 |
0 |
1 |
0 |
0 |
| T46 |
0 |
2 |
0 |
0 |
| T49 |
0 |
2 |
0 |
0 |
| T65 |
0 |
3 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
3 |
0 |
0 |
| T72 |
0 |
2 |
0 |
0 |
| T74 |
1752 |
0 |
0 |
0 |
| T75 |
4411 |
0 |
0 |
0 |
| T76 |
406 |
0 |
0 |
0 |
| T77 |
507 |
0 |
0 |
0 |
| T149 |
0 |
3 |
0 |
0 |
| T150 |
0 |
3 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
5206 |
0 |
0 |
| T1 |
1518 |
2 |
0 |
0 |
| T2 |
2166 |
0 |
0 |
0 |
| T3 |
1112 |
0 |
0 |
0 |
| T6 |
693 |
2 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
781 |
0 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T14 |
1269 |
0 |
0 |
0 |
| T15 |
1272 |
0 |
0 |
0 |
| T16 |
1431 |
1 |
0 |
0 |
| T17 |
1566 |
0 |
0 |
0 |
| T18 |
1064 |
0 |
0 |
0 |
| T19 |
1066 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T23 |
423 |
0 |
0 |
0 |
| T24 |
506 |
0 |
0 |
0 |
| T25 |
560 |
0 |
0 |
0 |
| T26 |
406 |
0 |
0 |
0 |
| T30 |
0 |
7 |
0 |
0 |
| T34 |
7688 |
6 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T39 |
0 |
1 |
0 |
0 |
| T40 |
0 |
1 |
0 |
0 |
| T45 |
0 |
1 |
0 |
0 |
| T46 |
0 |
2 |
0 |
0 |
| T49 |
0 |
2 |
0 |
0 |
| T65 |
0 |
3 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
3 |
0 |
0 |
| T72 |
0 |
2 |
0 |
0 |
| T74 |
1752 |
0 |
0 |
0 |
| T75 |
4411 |
0 |
0 |
0 |
| T76 |
406 |
0 |
0 |
0 |
| T77 |
507 |
0 |
0 |
0 |
| T149 |
0 |
3 |
0 |
0 |
| T150 |
0 |
3 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
167874720 |
1376341 |
0 |
0 |
| T1 |
1518 |
81 |
0 |
0 |
| T2 |
2166 |
0 |
0 |
0 |
| T3 |
1112 |
0 |
0 |
0 |
| T6 |
693 |
13 |
0 |
0 |
| T9 |
0 |
3 |
0 |
0 |
| T10 |
0 |
86 |
0 |
0 |
| T11 |
781 |
0 |
0 |
0 |
| T12 |
0 |
79 |
0 |
0 |
| T14 |
1269 |
0 |
0 |
0 |
| T15 |
1272 |
0 |
0 |
0 |
| T16 |
1431 |
50 |
0 |
0 |
| T17 |
1566 |
0 |
0 |
0 |
| T18 |
1064 |
0 |
0 |
0 |
| T19 |
1066 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T23 |
423 |
0 |
0 |
0 |
| T24 |
506 |
0 |
0 |
0 |
| T25 |
560 |
0 |
0 |
0 |
| T26 |
406 |
0 |
0 |
0 |
| T30 |
0 |
475 |
0 |
0 |
| T34 |
7688 |
537 |
0 |
0 |
| T38 |
0 |
8 |
0 |
0 |
| T39 |
0 |
5 |
0 |
0 |
| T45 |
0 |
2 |
0 |
0 |
| T46 |
0 |
106 |
0 |
0 |
| T49 |
0 |
17 |
0 |
0 |
| T65 |
0 |
37 |
0 |
0 |
| T69 |
0 |
3 |
0 |
0 |
| T70 |
0 |
17 |
0 |
0 |
| T71 |
0 |
24 |
0 |
0 |
| T72 |
0 |
7 |
0 |
0 |
| T74 |
1752 |
0 |
0 |
0 |
| T75 |
4411 |
0 |
0 |
0 |
| T76 |
406 |
0 |
0 |
0 |
| T77 |
507 |
0 |
0 |
0 |
| T149 |
0 |
18 |
0 |
0 |
| T150 |
0 |
20 |
0 |
0 |
| T151 |
0 |
19 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
58110480 |
39840 |
0 |
0 |
| T1 |
4554 |
3 |
0 |
0 |
| T2 |
0 |
16 |
0 |
0 |
| T4 |
1344 |
3 |
0 |
0 |
| T5 |
4536 |
59 |
0 |
0 |
| T6 |
6237 |
9 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T14 |
3807 |
14 |
0 |
0 |
| T15 |
3816 |
21 |
0 |
0 |
| T16 |
2862 |
3 |
0 |
0 |
| T17 |
0 |
36 |
0 |
0 |
| T18 |
0 |
50 |
0 |
0 |
| T19 |
0 |
3 |
0 |
0 |
| T23 |
3807 |
24 |
0 |
0 |
| T24 |
4554 |
46 |
0 |
0 |
| T25 |
5040 |
2 |
0 |
0 |
| T26 |
3654 |
5 |
0 |
0 |
| T36 |
0 |
14 |
0 |
0 |
| T81 |
0 |
11 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
32283600 |
30009950 |
0 |
0 |
| T1 |
2530 |
530 |
0 |
0 |
| T4 |
2240 |
240 |
0 |
0 |
| T5 |
2520 |
520 |
0 |
0 |
| T6 |
3465 |
1465 |
0 |
0 |
| T14 |
2115 |
115 |
0 |
0 |
| T15 |
2120 |
120 |
0 |
0 |
| T23 |
2115 |
115 |
0 |
0 |
| T24 |
2530 |
530 |
0 |
0 |
| T25 |
2800 |
800 |
0 |
0 |
| T26 |
2030 |
30 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
109764240 |
102033830 |
0 |
0 |
| T1 |
8602 |
1802 |
0 |
0 |
| T4 |
7616 |
816 |
0 |
0 |
| T5 |
8568 |
1768 |
0 |
0 |
| T6 |
11781 |
4981 |
0 |
0 |
| T14 |
7191 |
391 |
0 |
0 |
| T15 |
7208 |
408 |
0 |
0 |
| T23 |
7191 |
391 |
0 |
0 |
| T24 |
8602 |
1802 |
0 |
0 |
| T25 |
9520 |
2720 |
0 |
0 |
| T26 |
6902 |
102 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
58110480 |
54017910 |
0 |
0 |
| T1 |
4554 |
954 |
0 |
0 |
| T4 |
4032 |
432 |
0 |
0 |
| T5 |
4536 |
936 |
0 |
0 |
| T6 |
6237 |
2637 |
0 |
0 |
| T14 |
3807 |
207 |
0 |
0 |
| T15 |
3816 |
216 |
0 |
0 |
| T23 |
3807 |
207 |
0 |
0 |
| T24 |
4554 |
954 |
0 |
0 |
| T25 |
5040 |
1440 |
0 |
0 |
| T26 |
3654 |
54 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
148504560 |
4294 |
0 |
0 |
| T1 |
1012 |
1 |
0 |
0 |
| T2 |
1083 |
0 |
0 |
0 |
| T3 |
556 |
0 |
0 |
0 |
| T6 |
693 |
2 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T11 |
781 |
0 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T14 |
846 |
0 |
0 |
0 |
| T15 |
848 |
0 |
0 |
0 |
| T16 |
954 |
0 |
0 |
0 |
| T17 |
1044 |
0 |
0 |
0 |
| T18 |
532 |
0 |
0 |
0 |
| T19 |
533 |
0 |
0 |
0 |
| T20 |
402 |
0 |
0 |
0 |
| T23 |
423 |
0 |
0 |
0 |
| T24 |
506 |
0 |
0 |
0 |
| T25 |
560 |
0 |
0 |
0 |
| T26 |
406 |
0 |
0 |
0 |
| T34 |
7688 |
4 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T39 |
0 |
1 |
0 |
0 |
| T45 |
0 |
1 |
0 |
0 |
| T46 |
0 |
2 |
0 |
0 |
| T47 |
0 |
2 |
0 |
0 |
| T49 |
0 |
2 |
0 |
0 |
| T65 |
0 |
3 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
0 |
3 |
0 |
0 |
| T72 |
0 |
2 |
0 |
0 |
| T74 |
1752 |
0 |
0 |
0 |
| T75 |
4411 |
0 |
0 |
0 |
| T76 |
406 |
0 |
0 |
0 |
| T77 |
507 |
0 |
0 |
0 |
| T80 |
0 |
4 |
0 |
0 |
| T149 |
0 |
3 |
0 |
0 |
| T150 |
0 |
3 |
0 |
0 |
| T151 |
0 |
2 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
19370160 |
941919 |
0 |
0 |
| T2 |
2166 |
138 |
0 |
0 |
| T3 |
1112 |
0 |
0 |
0 |
| T7 |
1462 |
0 |
0 |
0 |
| T9 |
958 |
0 |
0 |
0 |
| T18 |
1064 |
0 |
0 |
0 |
| T19 |
1066 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T22 |
0 |
458 |
0 |
0 |
| T32 |
1428 |
0 |
0 |
0 |
| T36 |
972 |
0 |
0 |
0 |
| T45 |
0 |
222 |
0 |
0 |
| T64 |
538 |
0 |
0 |
0 |
| T81 |
1004 |
0 |
0 |
0 |
| T103 |
1190 |
847 |
0 |
0 |
| T104 |
0 |
396 |
0 |
0 |
| T105 |
0 |
649 |
0 |
0 |
| T106 |
0 |
1196 |
0 |
0 |
| T107 |
0 |
169 |
0 |
0 |
| T108 |
0 |
388 |
0 |
0 |
| T111 |
0 |
283 |
0 |
0 |
| T113 |
0 |
182988 |
0 |
0 |
| T114 |
0 |
66 |
0 |
0 |
| T118 |
0 |
99 |
0 |
0 |
| T152 |
0 |
322 |
0 |
0 |
| T153 |
0 |
272 |
0 |
0 |
| T154 |
873 |
0 |
0 |
0 |
| T155 |
404 |
0 |
0 |
0 |
| T156 |
27810 |
0 |
0 |
0 |
| T157 |
15791 |
0 |
0 |
0 |
| T158 |
422 |
0 |
0 |
0 |
| T159 |
445 |
0 |
0 |
0 |
| T160 |
508 |
0 |
0 |
0 |
| T161 |
489 |
0 |
0 |
0 |
