Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.64	95.65	90.48		83.33	95.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.21	93.48	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
91.56	95.65	90.48		83.33	95.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T23 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T23 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T34 T13 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T23 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T23 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T23 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T23 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T23 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T23 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T23 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T23 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T34 T13 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T34 T13 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T34 T13 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T34 T13 
163        1/1                    state_d = IdleSt;
           Tests:       T34 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T34 T13 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T13 T60 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T13 T60 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T13 T60 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T109 T110 T177 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T13 T60 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T13 T60 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T13 T60 
186        1/1                    state_d = IdleSt;
           Tests:       T239 T271 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T239 T271 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T13 T60 
191        1/1                      state_d = StableSt;
           Tests:       T8 T13 T60 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T13 T60 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T13 T60 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T13 T60 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T13 T60 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T13 T61 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T13 T60 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T23
1	1	Covered	T4,T5,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T34,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T34,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T34,T13
1	0	Covered	T4,T5,T23
1	1	Covered	T8,T34,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T60
0	1	Covered	T239,T271
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T60
0	1	Covered	T8,T13,T61
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T13,T60
1	-	Covered	T8,T13,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T34,T13
DetectSt	168	Covered	T8,T13,T60
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T13,T60

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T13,T60
DebounceSt->IdleSt	163	Covered	T34,T109,T110
DetectSt->IdleSt	186	Covered	T239,T271
DetectSt->StableSt	191	Covered	T8,T13,T60
IdleSt->DebounceSt	148	Covered	T8,T34,T13
StableSt->IdleSt	206	Covered	T8,T13,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T34,T13
0	1	Covered	T8,T34,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T60
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T34,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T13,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T109,T110,T177
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T34,T13
DetectSt	-	-	-	-	1	-	-	Covered	T239,T271
DetectSt	-	-	-	-	0	1	-	Covered	T8,T13,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T13,T61
StableSt	-	-	-	-	-	-	0	Covered	T8,T13,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	103	0	0
CntIncr_A	6456720	125692	0	0
CntNoWrap_A	6456720	6000010	0	0
DetectStDropOut_A	6456720	2	0	0
DetectedOut_A	6456720	154714	0	0
DetectedPulseOut_A	6456720	46	0	0
DisabledIdleSt_A	6456720	5511900	0	0
DisabledNoDetection_A	6456720	5513738	0	0
EnterDebounceSt_A	6456720	56	0	0
EnterDetectSt_A	6456720	48	0	0
EnterStableSt_A	6456720	46	0	0
PulseIsPulse_A	6456720	46	0	0
StayInStableSt	6456720	154646	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	103	0	0
T8	978	4	0	0
T10	511	0	0	0
T13	0	4	0	0
T30	0	2	0	0
T34	0	1	0	0
T56	0	2	0	0
T57	0	4	0	0
T60	0	2	0	0
T61	0	2	0	0
T62	0	2	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T242	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	125692	0	0
T8	978	114	0	0
T10	511	0	0	0
T13	0	56	0	0
T30	0	28	0	0
T34	0	39	0	0
T56	0	71	0	0
T57	0	118	0	0
T60	0	46	0	0
T61	0	52934	0	0
T62	0	57	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T242	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6000010	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	2	0	0
T239	914	1	0	0
T271	0	1	0	0
T272	24444	0	0	0
T273	429	0	0	0
T274	413	0	0	0
T275	1720	0	0	0
T276	493	0	0	0
T277	438	0	0	0
T278	134843	0	0	0
T279	3242	0	0	0
T280	502	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	154714	0	0
T8	978	196	0	0
T10	511	0	0	0
T13	0	97	0	0
T30	0	5	0	0
T56	0	41	0	0
T57	0	142	0	0
T60	0	45	0	0
T61	0	63173	0	0
T62	0	211	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T235	0	252	0	0
T242	0	20	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46	0	0
T8	978	2	0	0
T10	511	0	0	0
T13	0	2	0	0
T30	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T235	0	2	0	0
T242	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5511900	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5513738	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	56	0	0
T8	978	2	0	0
T10	511	0	0	0
T13	0	2	0	0
T30	0	1	0	0
T34	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T242	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	48	0	0
T8	978	2	0	0
T10	511	0	0	0
T13	0	2	0	0
T30	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T235	0	2	0	0
T242	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46	0	0
T8	978	2	0	0
T10	511	0	0	0
T13	0	2	0	0
T30	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T235	0	2	0	0
T242	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46	0	0
T8	978	2	0	0
T10	511	0	0	0
T13	0	2	0	0
T30	0	1	0	0
T56	0	1	0	0
T57	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T235	0	2	0	0
T242	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	154646	0	0
T8	978	193	0	0
T10	511	0	0	0
T13	0	94	0	0
T30	0	4	0	0
T56	0	40	0	0
T57	0	139	0	0
T60	0	43	0	0
T61	0	63172	0	0
T62	0	210	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T235	0	249	0	0
T242	0	19	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	23	0	0
T8	978	1	0	0
T10	511	0	0	0
T13	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T110	0	1	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T235	0	1	0	0
T242	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T23 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T34 T13 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T34 T13 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T34 T13 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T34 T13 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T34 T13 
163        1/1                    state_d = IdleSt;
           Tests:       T34 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T34 T13 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T13 T57 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T13 T57 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T13 T57 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T258 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T13 T57 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T13 T57 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T13 T57 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T13 T57 
191        1/1                      state_d = StableSt;
           Tests:       T8 T13 T57 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T13 T57 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T13 T57 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T13 T57 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T13 T57 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T13 T57 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T13 T57 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T34,T13

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T34,T13

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T13,T57

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T34,T13
1	0	Covered	T4,T5,T23
1	1	Covered	T8,T34,T13

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T57
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T13,T57
0	1	Covered	T8,T13,T57
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T13,T57
1	-	Covered	T8,T13,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T34,T13
DetectSt	168	Covered	T8,T13,T57
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T13,T57

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T13,T57
DebounceSt->IdleSt	163	Covered	T34,T258
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T13,T57
IdleSt->DebounceSt	148	Covered	T8,T34,T13
StableSt->IdleSt	206	Covered	T8,T13,T57

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T34,T13
0	1	Covered	T8,T34,T13
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T13,T57
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T34,T13
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T13,T57
DebounceSt	-	0	1	0	-	-	-	Covered	T258
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T34,T13
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T13,T57
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T13,T57
StableSt	-	-	-	-	-	-	0	Covered	T8,T13,T57
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	74	0	0
CntIncr_A	6456720	37134	0	0
CntNoWrap_A	6456720	6000039	0	0
DetectStDropOut_A	6456720	0	0	0
DetectedOut_A	6456720	2672	0	0
DetectedPulseOut_A	6456720	36	0	0
DisabledIdleSt_A	6456720	5704281	0	0
DisabledNoDetection_A	6456720	5706122	0	0
EnterDebounceSt_A	6456720	38	0	0
EnterDetectSt_A	6456720	36	0	0
EnterStableSt_A	6456720	36	0	0
PulseIsPulse_A	6456720	36	0	0
StayInStableSt	6456720	2618	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6456720	5035	0	0
gen_low_level_sva.LowLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	17	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	74	0	0
T8	978	2	0	0
T10	511	0	0	0
T13	0	2	0	0
T30	0	2	0	0
T34	0	1	0	0
T57	0	2	0	0
T58	0	2	0	0
T59	0	2	0	0
T62	0	2	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	2	0	0
T242	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	37134	0	0
T8	978	57	0	0
T10	511	0	0	0
T13	0	28	0	0
T30	0	28	0	0
T34	0	38	0	0
T57	0	59	0	0
T58	0	63	0	0
T59	0	61	0	0
T62	0	57	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	47	0	0
T242	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6000039	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	2672	0	0
T8	978	200	0	0
T10	511	0	0	0
T13	0	146	0	0
T30	0	6	0	0
T53	0	6	0	0
T57	0	4	0	0
T58	0	54	0	0
T59	0	89	0	0
T62	0	43	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	105	0	0
T242	0	167	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	36	0	0
T8	978	1	0	0
T10	511	0	0	0
T13	0	1	0	0
T30	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	1	0	0
T242	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5704281	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5706122	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	38	0	0
T8	978	1	0	0
T10	511	0	0	0
T13	0	1	0	0
T30	0	1	0	0
T34	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	1	0	0
T242	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	36	0	0
T8	978	1	0	0
T10	511	0	0	0
T13	0	1	0	0
T30	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	1	0	0
T242	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	36	0	0
T8	978	1	0	0
T10	511	0	0	0
T13	0	1	0	0
T30	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	1	0	0
T242	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	36	0	0
T8	978	1	0	0
T10	511	0	0	0
T13	0	1	0	0
T30	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T58	0	1	0	0
T59	0	1	0	0
T62	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	1	0	0
T242	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	2618	0	0
T8	978	199	0	0
T10	511	0	0	0
T13	0	145	0	0
T30	0	5	0	0
T53	0	5	0	0
T57	0	3	0	0
T58	0	52	0	0
T59	0	87	0	0
T62	0	41	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	103	0	0
T242	0	165	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5035	0	0
T1	506	1	0	0
T4	448	1	0	0
T5	504	7	0	0
T6	693	0	0	0
T14	423	1	0	0
T15	424	2	0	0
T16	0	1	0	0
T17	0	4	0	0
T18	0	6	0	0
T23	423	2	0	0
T24	506	5	0	0
T25	560	0	0	0
T26	406	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	17	0	0
T8	978	1	0	0
T10	511	0	0	0
T13	0	1	0	0
T53	0	1	0	0
T57	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T109	0	2	0	0
T190	0	1	0	0
T219	0	1	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T233	0	2	0	0
T234	0	1	0	0
T239	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T23 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T23 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T13 T55 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T23 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T23 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T23 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T23 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T23 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T23 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T23 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T23 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T13 T55 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T13 T55 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T13 T55 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T13 T55 
163        1/1                    state_d = IdleSt;
           Tests:       T34 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T13 T55 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T13 T55 T61 
167        1/1                    if (trigger_active) begin
           Tests:       T13 T55 T61 
168        1/1                      state_d = DetectSt;
           Tests:       T13 T55 T61 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T236 T239 T209 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T13 T55 T61 
182        1/1                  cnt_en = 1'b1;
           Tests:       T13 T55 T61 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T13 T55 T61 
186        1/1                    state_d = IdleSt;
           Tests:       T109 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T109 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T13 T55 T61 
191        1/1                      state_d = StableSt;
           Tests:       T13 T55 T61 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T13 T55 T61 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T13 T55 T61 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T13 T55 T61 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T13 T55 T61 
206        1/1                    state_d = IdleSt;
           Tests:       T13 T55 T61 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T13 T55 T61 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T23
1	1	Covered	T4,T5,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T13,T55

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T34,T13,T55

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T13,T55,T61

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T13,T55
1	0	Covered	T4,T5,T23
1	1	Covered	T34,T13,T55

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T13,T55,T61
0	1	Covered	T109
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T13,T55,T61
0	1	Covered	T13,T55,T61
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T13,T55,T61
1	-	Covered	T13,T55,T61

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T13,T55
DetectSt	168	Covered	T13,T55,T61
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T13,T55,T61

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T13,T55,T61
DebounceSt->IdleSt	163	Covered	T34,T236,T239
DetectSt->IdleSt	186	Covered	T109
DetectSt->StableSt	191	Covered	T13,T55,T61
IdleSt->DebounceSt	148	Covered	T34,T13,T55
StableSt->IdleSt	206	Covered	T13,T55,T61

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T13,T55
0	1	Covered	T34,T13,T55
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T13,T55,T61
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T13,T55
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T13,T55,T61
DebounceSt	-	0	1	0	-	-	-	Covered	T236,T239,T209
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T13,T55
DetectSt	-	-	-	-	1	-	-	Covered	T109
DetectSt	-	-	-	-	0	1	-	Covered	T13,T55,T61
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T13,T55,T61
StableSt	-	-	-	-	-	-	0	Covered	T13,T55,T61
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	81	0	0
CntIncr_A	6456720	190292	0	0
CntNoWrap_A	6456720	6000032	0	0
DetectStDropOut_A	6456720	2	0	0
DetectedOut_A	6456720	118103	0	0
DetectedPulseOut_A	6456720	36	0	0
DisabledIdleSt_A	6456720	5477099	0	0
DisabledNoDetection_A	6456720	5478947	0	0
EnterDebounceSt_A	6456720	43	0	0
EnterDetectSt_A	6456720	38	0	0
EnterStableSt_A	6456720	36	0	0
PulseIsPulse_A	6456720	36	0	0
StayInStableSt	6456720	118050	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	81	0	0
T11	781	0	0	0
T13	0	4	0	0
T30	0	2	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T55	0	4	0	0
T61	0	4	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T102	4414	0	0	0
T188	0	2	0	0
T189	0	4	0	0
T236	0	1	0	0
T242	0	2	0	0
T281	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	190292	0	0
T11	781	0	0	0
T13	0	56	0	0
T30	0	28	0	0
T34	7688	39	0	0
T35	1320	0	0	0
T55	0	96	0	0
T61	0	105868	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T102	4414	0	0	0
T188	0	11	0	0
T189	0	114	0	0
T236	0	26	0	0
T242	0	32	0	0
T281	0	100	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6000032	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	2	0	0
T109	2172	2	0	0
T219	28444	0	0	0
T258	1039	0	0	0
T282	526	0	0	0
T283	15336	0	0	0
T284	501	0	0	0
T285	700	0	0	0
T286	2598	0	0	0
T287	537	0	0	0
T288	415	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	118103	0	0
T13	768	116	0	0
T30	0	6	0	0
T53	0	92	0	0
T55	0	57	0	0
T59	0	309	0	0
T61	0	62721	0	0
T69	647	0	0	0
T88	494	0	0	0
T188	0	53	0	0
T189	0	181	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0
T242	0	38	0	0
T281	0	162	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	36	0	0
T13	768	2	0	0
T30	0	1	0	0
T53	0	3	0	0
T55	0	2	0	0
T59	0	1	0	0
T61	0	2	0	0
T69	647	0	0	0
T88	494	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0
T242	0	1	0	0
T281	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5477099	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5478947	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	43	0	0
T11	781	0	0	0
T13	0	2	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T55	0	2	0	0
T61	0	2	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T102	4414	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T236	0	1	0	0
T242	0	1	0	0
T281	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	38	0	0
T13	768	2	0	0
T30	0	1	0	0
T53	0	3	0	0
T55	0	2	0	0
T59	0	1	0	0
T61	0	2	0	0
T69	647	0	0	0
T88	494	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0
T242	0	1	0	0
T281	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	36	0	0
T13	768	2	0	0
T30	0	1	0	0
T53	0	3	0	0
T55	0	2	0	0
T59	0	1	0	0
T61	0	2	0	0
T69	647	0	0	0
T88	494	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0
T242	0	1	0	0
T281	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	36	0	0
T13	768	2	0	0
T30	0	1	0	0
T53	0	3	0	0
T55	0	2	0	0
T59	0	1	0	0
T61	0	2	0	0
T69	647	0	0	0
T88	494	0	0	0
T188	0	1	0	0
T189	0	2	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0
T242	0	1	0	0
T281	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	118050	0	0
T13	768	114	0	0
T30	0	5	0	0
T53	0	88	0	0
T55	0	54	0	0
T59	0	307	0	0
T61	0	62718	0	0
T69	647	0	0	0
T88	494	0	0	0
T188	0	52	0	0
T189	0	178	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0
T242	0	36	0	0
T281	0	160	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	18	0	0
T13	768	2	0	0
T53	0	2	0	0
T55	0	1	0	0
T61	0	1	0	0
T69	647	0	0	0
T88	494	0	0	0
T188	0	1	0	0
T189	0	1	0	0
T198	0	1	0	0
T201	502	0	0	0
T202	522	0	0	0
T203	434	0	0	0
T204	599	0	0	0
T205	402	0	0	0
T206	421	0	0	0
T207	519	0	0	0
T211	0	1	0	0
T219	0	1	0	0
T239	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T23 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T34 T55 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T34 T55 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T34 T55 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T34 T55 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T34 T55 
163        1/1                    state_d = IdleSt;
           Tests:       T34 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T34 T55 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T55 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T55 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T55 T30 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T55 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T55 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T55 T30 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T55 T30 
191        1/1                      state_d = StableSt;
           Tests:       T8 T55 T30 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T55 T30 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T55 T30 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T55 T30 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T55 T30 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T55 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T55 T30 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T34,T55

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T34,T55

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T55,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T34
1	0	Covered	T4,T5,T23
1	1	Covered	T8,T34,T55

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T55,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T55,T30
0	1	Covered	T8,T55,T62
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T55,T30
1	-	Covered	T8,T55,T62

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T34,T55
DetectSt	168	Covered	T8,T55,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T55,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T55,T30
DebounceSt->IdleSt	163	Covered	T34
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T55,T30
IdleSt->DebounceSt	148	Covered	T8,T34,T55
StableSt->IdleSt	206	Covered	T8,T55,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T34,T55
0	1	Covered	T8,T34,T55
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T55,T30
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T34,T55
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T55,T30
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T34,T55
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T55,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T55,T30
StableSt	-	-	-	-	-	-	0	Covered	T8,T55,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	51	0	0
CntIncr_A	6456720	7857	0	0
CntNoWrap_A	6456720	6000062	0	0
DetectStDropOut_A	6456720	0	0	0
DetectedOut_A	6456720	25703	0	0
DetectedPulseOut_A	6456720	25	0	0
DisabledIdleSt_A	6456720	5948844	0	0
DisabledNoDetection_A	6456720	5950685	0	0
EnterDebounceSt_A	6456720	26	0	0
EnterDetectSt_A	6456720	25	0	0
EnterStableSt_A	6456720	25	0	0
PulseIsPulse_A	6456720	25	0	0
StayInStableSt	6456720	25663	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6456720	5025	0	0
gen_low_level_sva.LowLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	51	0	0
T8	978	2	0	0
T10	511	0	0	0
T30	0	2	0	0
T34	0	1	0	0
T52	0	2	0	0
T55	0	2	0	0
T56	0	2	0	0
T62	0	4	0	0
T64	0	2	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T188	0	2	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	7857	0	0
T8	978	57	0	0
T10	511	0	0	0
T30	0	28	0	0
T34	0	39	0	0
T52	0	70	0	0
T55	0	48	0	0
T56	0	71	0	0
T62	0	114	0	0
T64	0	42	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T188	0	11	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	47	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6000062	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	25703	0	0
T8	978	143	0	0
T10	511	0	0	0
T30	0	6	0	0
T52	0	40	0	0
T55	0	40	0	0
T56	0	41	0	0
T62	0	85	0	0
T64	0	38	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T188	0	39	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	193	0	0
T258	0	67	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	25	0	0
T8	978	1	0	0
T10	511	0	0	0
T30	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T62	0	2	0	0
T64	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T188	0	1	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	1	0	0
T258	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5948844	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5950685	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	26	0	0
T8	978	1	0	0
T10	511	0	0	0
T30	0	1	0	0
T34	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T62	0	2	0	0
T64	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T188	0	1	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	25	0	0
T8	978	1	0	0
T10	511	0	0	0
T30	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T62	0	2	0	0
T64	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T188	0	1	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	1	0	0
T258	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	25	0	0
T8	978	1	0	0
T10	511	0	0	0
T30	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T62	0	2	0	0
T64	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T188	0	1	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	1	0	0
T258	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	25	0	0
T8	978	1	0	0
T10	511	0	0	0
T30	0	1	0	0
T52	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T62	0	2	0	0
T64	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T188	0	1	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	1	0	0
T258	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	25663	0	0
T8	978	142	0	0
T10	511	0	0	0
T30	0	5	0	0
T52	0	38	0	0
T55	0	39	0	0
T56	0	39	0	0
T62	0	82	0	0
T64	0	36	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T188	0	37	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T237	0	191	0	0
T258	0	65	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5025	0	0
T1	506	1	0	0
T4	448	1	0	0
T5	504	5	0	0
T6	693	0	0	0
T14	423	2	0	0
T15	424	1	0	0
T16	0	1	0	0
T17	0	4	0	0
T18	0	4	0	0
T23	423	2	0	0
T24	506	4	0	0
T25	560	0	0	0
T26	406	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	9	0	0
T8	978	1	0	0
T10	511	0	0	0
T55	0	1	0	0
T62	0	1	0	0
T67	586	0	0	0
T68	448	0	0	0
T87	495	0	0	0
T94	509	0	0	0
T95	527	0	0	0
T110	0	1	0	0
T177	0	1	0	0
T200	0	1	0	0
T209	0	1	0	0
T220	630	0	0	0
T221	422	0	0	0
T222	413	0	0	0
T232	0	1	0	0
T240	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T6 T23 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T5 T6 T23 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T7 T34 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T6 T23 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T6 T23 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T6 T23 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T6 T23 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T6 T23 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T6 T23 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T6 T23 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T6 T23 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T7 T34 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T7 T34 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T7 T34 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T7 T34 
163        1/1                    state_d = IdleSt;
           Tests:       T34 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T7 T34 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T7 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T7 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T7 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T109 T260 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T7 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T7 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T7 T11 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T7 T11 
191        1/1                      state_d = StableSt;
           Tests:       T3 T7 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T7 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T7 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T7 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T7 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T7 T13 T55 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T7 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T23

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T23
1	1	Covered	T5,T6,T23

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T3,T7,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T7,T34
1	0	Covered	T5,T6,T23
1	1	Covered	T3,T7,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T7,T11
0	1	Covered	T7,T13,T55
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T7,T11
1	-	Covered	T7,T13,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T7,T34
DetectSt	168	Covered	T3,T7,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T7,T11
DebounceSt->IdleSt	163	Covered	T34,T109,T289
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T7,T11
IdleSt->DebounceSt	148	Covered	T3,T7,T34
StableSt->IdleSt	206	Covered	T7,T13,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T7,T34
0	1	Covered	T3,T7,T34
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T7,T11
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T7,T34
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T23
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T109,T260
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T7,T34
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T7,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T13,T55
StableSt	-	-	-	-	-	-	0	Covered	T3,T7,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	96	0	0
CntIncr_A	6456720	2913	0	0
CntNoWrap_A	6456720	6000017	0	0
DetectStDropOut_A	6456720	0	0	0
DetectedOut_A	6456720	4583	0	0
DetectedPulseOut_A	6456720	46	0	0
DisabledIdleSt_A	6456720	5987351	0	0
DisabledNoDetection_A	6456720	5989191	0	0
EnterDebounceSt_A	6456720	51	0	0
EnterDetectSt_A	6456720	46	0	0
EnterStableSt_A	6456720	46	0	0
PulseIsPulse_A	6456720	46	0	0
StayInStableSt	6456720	4515	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	96	0	0
T3	556	2	0	0
T7	731	2	0	0
T9	479	0	0	0
T11	0	2	0	0
T13	0	4	0	0
T30	0	2	0	0
T32	714	0	0	0
T34	0	1	0	0
T36	486	0	0	0
T37	492	0	0	0
T55	0	4	0	0
T56	0	2	0	0
T57	0	2	0	0
T62	0	2	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	2913	0	0
T3	556	38	0	0
T7	731	97	0	0
T9	479	0	0	0
T11	0	63	0	0
T13	0	56	0	0
T30	0	28	0	0
T32	714	0	0	0
T34	0	39	0	0
T36	486	0	0	0
T37	492	0	0	0
T55	0	96	0	0
T56	0	71	0	0
T57	0	59	0	0
T62	0	57	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6000017	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	4583	0	0
T3	556	38	0	0
T7	731	82	0	0
T9	479	0	0	0
T11	0	223	0	0
T13	0	99	0	0
T30	0	5	0	0
T32	714	0	0	0
T36	486	0	0	0
T37	492	0	0	0
T55	0	48	0	0
T56	0	313	0	0
T57	0	207	0	0
T62	0	43	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T242	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46	0	0
T3	556	1	0	0
T7	731	1	0	0
T9	479	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T30	0	1	0	0
T32	714	0	0	0
T36	486	0	0	0
T37	492	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T62	0	1	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T242	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5987351	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5989191	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	51	0	0
T3	556	1	0	0
T7	731	1	0	0
T9	479	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T30	0	1	0	0
T32	714	0	0	0
T34	0	1	0	0
T36	486	0	0	0
T37	492	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T62	0	1	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46	0	0
T3	556	1	0	0
T7	731	1	0	0
T9	479	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T30	0	1	0	0
T32	714	0	0	0
T36	486	0	0	0
T37	492	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T62	0	1	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T242	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46	0	0
T3	556	1	0	0
T7	731	1	0	0
T9	479	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T30	0	1	0	0
T32	714	0	0	0
T36	486	0	0	0
T37	492	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T62	0	1	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T242	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	46	0	0
T3	556	1	0	0
T7	731	1	0	0
T9	479	0	0	0
T11	0	1	0	0
T13	0	2	0	0
T30	0	1	0	0
T32	714	0	0	0
T36	486	0	0	0
T37	492	0	0	0
T55	0	2	0	0
T56	0	1	0	0
T57	0	1	0	0
T62	0	1	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T242	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	4515	0	0
T3	556	36	0	0
T7	731	81	0	0
T9	479	0	0	0
T11	0	221	0	0
T13	0	96	0	0
T30	0	4	0	0
T32	714	0	0	0
T36	486	0	0	0
T37	492	0	0	0
T55	0	45	0	0
T56	0	312	0	0
T57	0	205	0	0
T62	0	41	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T242	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	23	0	0
T7	731	1	0	0
T9	479	0	0	0
T13	0	1	0	0
T32	714	0	0	0
T37	492	0	0	0
T38	623	0	0	0
T54	0	1	0	0
T55	0	1	0	0
T56	0	1	0	0
T66	445	0	0	0
T81	502	0	0	0
T91	511	0	0	0
T96	842	0	0	0
T109	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T212	446	0	0	0
T219	0	1	0	0
T237	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T5 T6 T23 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T30 T188 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T30 T188 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T30 T188 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T30 T188 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T30 T188 
163        1/1                    state_d = IdleSt;
           Tests:       T34 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T30 T188 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T30 T188 T52 
167        1/1                    if (trigger_active) begin
           Tests:       T30 T188 T52 
168        1/1                      state_d = DetectSt;
           Tests:       T30 T52 T53 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T188 T239 T210 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T30 T52 T53 
182        1/1                  cnt_en = 1'b1;
           Tests:       T30 T52 T53 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T30 T52 T53 
186        1/1                    state_d = IdleSt;
           Tests:       T241 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T241 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T30 T52 T53 
191        1/1                      state_d = StableSt;
           Tests:       T30 T52 T53 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T30 T52 T53 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T30 T52 T53 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T30 T52 T53 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T30 T52 T53 
206        1/1                    state_d = IdleSt;
           Tests:       T30 T53 T258 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T30 T52 T53 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T23
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T23
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T30,T188

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T34,T30,T188

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T30,T52,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T34,T57
1	0	Covered	T5,T6,T23
1	1	Covered	T34,T30,T188

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T30,T52,T53
0	1	Covered	T241
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T52,T53
0	1	Covered	T53,T258,T190
1	0	Covered	T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T52,T53
1	-	Covered	T53,T258,T190

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T30,T188
DetectSt	168	Covered	T30,T52,T53
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T30,T52,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T30,T52,T53
DebounceSt->IdleSt	163	Covered	T34,T188,T239
DetectSt->IdleSt	186	Covered	T241
DetectSt->StableSt	191	Covered	T30,T52,T53
IdleSt->DebounceSt	148	Covered	T34,T30,T188
StableSt->IdleSt	206	Covered	T30,T53,T258

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T30,T188
0	1	Covered	T34,T30,T188
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T30,T52,T53
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T30,T188
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34
DebounceSt	-	0	1	1	-	-	-	Covered	T30,T52,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T188,T239,T210
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T30,T188
DetectSt	-	-	-	-	1	-	-	Covered	T241
DetectSt	-	-	-	-	0	1	-	Covered	T30,T52,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T30,T53,T258
StableSt	-	-	-	-	-	-	0	Covered	T30,T52,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	44	0	0
CntIncr_A	6456720	14209	0	0
CntNoWrap_A	6456720	6000069	0	0
DetectStDropOut_A	6456720	1	0	0
DetectedOut_A	6456720	11979	0	0
DetectedPulseOut_A	6456720	19	0	0
DisabledIdleSt_A	6456720	5950485	0	0
DisabledNoDetection_A	6456720	5952332	0	0
EnterDebounceSt_A	6456720	24	0	0
EnterDetectSt_A	6456720	20	0	0
EnterStableSt_A	6456720	19	0	0
PulseIsPulse_A	6456720	19	0	0
StayInStableSt	6456720	11951	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6456720	5453	0	0
gen_low_level_sva.LowLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	9	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	44	0	0
T11	781	0	0	0
T30	0	2	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T52	0	2	0	0
T53	0	4	0	0
T54	0	2	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T102	4414	0	0	0
T188	0	1	0	0
T190	0	2	0	0
T232	0	2	0	0
T239	0	1	0	0
T258	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	14209	0	0
T11	781	0	0	0
T30	0	28	0	0
T34	7688	38	0	0
T35	1320	0	0	0
T52	0	70	0	0
T53	0	84	0	0
T54	0	82	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T102	4414	0	0	0
T188	0	11	0	0
T190	0	94	0	0
T232	0	66	0	0
T239	0	57	0	0
T258	0	77	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6000069	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	1	0	0
T241	856	1	0	0
T243	557	0	0	0
T244	439	0	0	0
T245	692	0	0	0
T246	16499	0	0	0
T247	1669	0	0	0
T248	426	0	0	0
T249	404	0	0	0
T250	435	0	0	0
T251	798	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	11979	0	0
T22	1281	0	0	0
T30	7514	6	0	0
T52	0	41	0	0
T53	0	86	0	0
T54	0	41	0	0
T90	492	0	0	0
T190	0	335	0	0
T208	0	50	0	0
T213	430	0	0	0
T214	522	0	0	0
T215	1934	0	0	0
T216	1850	0	0	0
T217	447	0	0	0
T218	524	0	0	0
T232	0	39	0	0
T233	0	261	0	0
T258	0	43	0	0
T290	0	41	0	0
T291	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	19	0	0
T22	1281	0	0	0
T30	7514	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T90	492	0	0	0
T190	0	1	0	0
T208	0	1	0	0
T213	430	0	0	0
T214	522	0	0	0
T215	1934	0	0	0
T216	1850	0	0	0
T217	447	0	0	0
T218	524	0	0	0
T232	0	1	0	0
T233	0	2	0	0
T258	0	1	0	0
T290	0	1	0	0
T291	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5950485	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5952332	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	24	0	0
T11	781	0	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T102	4414	0	0	0
T188	0	1	0	0
T190	0	1	0	0
T232	0	1	0	0
T239	0	1	0	0
T258	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	20	0	0
T22	1281	0	0	0
T30	7514	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T90	492	0	0	0
T190	0	1	0	0
T208	0	1	0	0
T213	430	0	0	0
T214	522	0	0	0
T215	1934	0	0	0
T216	1850	0	0	0
T217	447	0	0	0
T218	524	0	0	0
T232	0	1	0	0
T233	0	2	0	0
T258	0	1	0	0
T290	0	1	0	0
T291	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	19	0	0
T22	1281	0	0	0
T30	7514	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T90	492	0	0	0
T190	0	1	0	0
T208	0	1	0	0
T213	430	0	0	0
T214	522	0	0	0
T215	1934	0	0	0
T216	1850	0	0	0
T217	447	0	0	0
T218	524	0	0	0
T232	0	1	0	0
T233	0	2	0	0
T258	0	1	0	0
T290	0	1	0	0
T291	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	19	0	0
T22	1281	0	0	0
T30	7514	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T90	492	0	0	0
T190	0	1	0	0
T208	0	1	0	0
T213	430	0	0	0
T214	522	0	0	0
T215	1934	0	0	0
T216	1850	0	0	0
T217	447	0	0	0
T218	524	0	0	0
T232	0	1	0	0
T233	0	2	0	0
T258	0	1	0	0
T290	0	1	0	0
T291	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	11951	0	0
T22	1281	0	0	0
T30	7514	5	0	0
T52	0	39	0	0
T53	0	83	0	0
T54	0	39	0	0
T90	492	0	0	0
T190	0	334	0	0
T208	0	49	0	0
T213	430	0	0	0
T214	522	0	0	0
T215	1934	0	0	0
T216	1850	0	0	0
T217	447	0	0	0
T218	524	0	0	0
T232	0	38	0	0
T233	0	258	0	0
T258	0	42	0	0
T290	0	39	0	0
T291	402	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5453	0	0
T1	506	0	0	0
T2	0	4	0	0
T5	504	8	0	0
T6	693	3	0	0
T14	423	1	0	0
T15	424	3	0	0
T16	477	0	0	0
T17	0	4	0	0
T18	0	6	0	0
T23	423	4	0	0
T24	506	5	0	0
T25	560	0	0	0
T26	406	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	9	0	0
T53	849	1	0	0
T116	0	1	0	0
T171	22174	0	0	0
T190	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0
T232	0	1	0	0
T233	0	1	0	0
T258	0	1	0	0
T260	0	1	0	0
T292	425	0	0	0
T293	466	0	0	0
T294	527	0	0	0
T295	1429	0	0	0
T296	492	0	0	0
T297	794	0	0	0
T298	502	0	0	0
T299	629	0	0	0