Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.99	100.00	94.74		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T41 T21 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T41 T21 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T16 T40 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T16 T40 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T16 T40 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T16 T40 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T16 T40 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T16 T40 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T16 T40 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T16 T40 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T16 T40 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T16 T40 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T16 T40 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T16 T40 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T16 T40 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T16 T40 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T16 T40 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T16 T40 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T16 T40 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T30 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T16 T40 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T16 T40 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T16 T40 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T41 T21 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T41 T21 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T16 T40 
191        1/1                      state_d = StableSt;
           Tests:       T1 T16 T40 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T16 T40 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T16 T40 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T16 T40 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T16 T40 
206        1/1                    state_d = IdleSt;
           Tests:       T34 T30 T99 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T16 T40 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T41,T21
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T16,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T16,T40

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T16,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T41,T21
1	0	Covered	T34,T21,T30
1	1	Covered	T1,T16,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T40
0	1	Covered	T34,T41,T21
1	0	Covered	T34,T21,T30

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T40
0	1	Covered	T34,T30,T99
1	0	Covered	T34,T117

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T16,T40
1	-	Covered	T34,T30,T99

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T16,T40
DetectSt	168	Covered	T1,T16,T40
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T16,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T16,T40
DebounceSt->IdleSt	163	Covered	T34,T30
DetectSt->IdleSt	186	Covered	T34,T41,T21
DetectSt->StableSt	191	Covered	T1,T16,T40
IdleSt->DebounceSt	148	Covered	T1,T16,T40
StableSt->IdleSt	206	Covered	T34,T30,T99

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T16,T40
0	1	Covered	T1,T16,T40
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T40
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T16,T40
IdleSt	0	-	-	-	-	-	-	Covered	T34,T41,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T16,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T30
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T16,T40
DetectSt	-	-	-	-	1	-	-	Covered	T34,T41,T21
DetectSt	-	-	-	-	0	1	-	Covered	T1,T16,T40
DetectSt	-	-	-	-	0	0	-	Covered	T1,T16,T40
StableSt	-	-	-	-	-	-	1	Covered	T34,T30,T99
StableSt	-	-	-	-	-	-	0	Covered	T1,T16,T40
default	-	-	-	-	-	-	-	Not Covered

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	3278	0	0
CntIncr_A	6456720	110760	0	0
CntNoWrap_A	6456720	5996835	0	0
DetectStDropOut_A	6456720	543	0	0
DetectedOut_A	6456720	77924	0	0
DetectedPulseOut_A	6456720	907	0	0
DisabledIdleSt_A	6456720	5527866	0	0
DisabledNoDetection_A	6456720	5529521	0	0
EnterDebounceSt_A	6456720	1641	0	0
EnterDetectSt_A	6456720	1637	0	0
EnterStableSt_A	6456720	907	0	0
PulseIsPulse_A	6456720	907	0	0
StayInStableSt	6456720	76889	0	0
gen_high_event_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	773	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	3278	0	0
T1	506	2	0	0
T2	1083	0	0	0
T3	556	0	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	2	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T21	0	32	0	0
T30	0	16	0	0
T34	0	16	0	0
T40	0	2	0	0
T41	0	28	0	0
T73	0	56	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	110760	0	0
T1	506	21	0	0
T2	1083	0	0	0
T3	556	0	0	0
T10	0	21	0	0
T12	0	21	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	21	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T21	0	1541	0	0
T30	0	586	0	0
T34	0	468	0	0
T40	0	21	0	0
T41	0	697	0	0
T73	0	1653	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5996835	0	0
T1	506	103	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	543	0	0
T11	781	0	0	0
T21	0	4	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T41	0	14	0	0
T73	0	28	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T97	0	13	0	0
T98	0	14	0	0
T101	0	10	0	0
T102	4414	0	0	0
T117	0	12	0	0
T122	0	24	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	77924	0	0
T1	506	81	0	0
T2	1083	0	0	0
T3	556	0	0	0
T10	0	86	0	0
T12	0	78	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	52	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T30	0	368	0	0
T34	0	435	0	0
T40	0	26	0	0
T48	0	2825	0	0
T99	0	225	0	0
T100	0	3337	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	907	0	0
T1	506	1	0	0
T2	1083	0	0	0
T3	556	0	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	1	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T30	0	5	0	0
T34	0	5	0	0
T40	0	1	0	0
T48	0	23	0	0
T99	0	28	0	0
T100	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5527866	0	0
T1	506	3	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5529521	0	0
T1	506	3	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	1641	0	0
T1	506	1	0	0
T2	1083	0	0	0
T3	556	0	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	1	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T21	0	16	0	0
T30	0	9	0	0
T34	0	9	0	0
T40	0	1	0	0
T41	0	14	0	0
T73	0	28	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	1637	0	0
T1	506	1	0	0
T2	1083	0	0	0
T3	556	0	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	1	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T21	0	16	0	0
T30	0	7	0	0
T34	0	7	0	0
T40	0	1	0	0
T41	0	14	0	0
T73	0	28	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	907	0	0
T1	506	1	0	0
T2	1083	0	0	0
T3	556	0	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	1	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T30	0	5	0	0
T34	0	5	0	0
T40	0	1	0	0
T48	0	23	0	0
T99	0	28	0	0
T100	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	907	0	0
T1	506	1	0	0
T2	1083	0	0	0
T3	556	0	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	1	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T30	0	5	0	0
T34	0	5	0	0
T40	0	1	0	0
T48	0	23	0	0
T99	0	28	0	0
T100	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	76889	0	0
T1	506	79	0	0
T2	1083	0	0	0
T3	556	0	0	0
T10	0	84	0	0
T12	0	76	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	50	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T30	0	363	0	0
T34	0	430	0	0
T40	0	24	0	0
T48	0	2801	0	0
T99	0	197	0	0
T100	0	3314	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	773	0	0
T11	781	0	0	0
T30	0	5	0	0
T34	7688	4	0	0
T35	1320	0	0	0
T48	0	22	0	0
T51	0	6	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T99	0	28	0	0
T100	0	23	0	0
T102	4414	0	0	0
T115	0	3	0	0
T157	0	8	0	0
T300	0	16	0	0
T301	0	14	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T1 T16 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T4 T1 T16 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T4 T1 T16 
149        1/1                    cnt_en = 1'b1;
           Tests:       T4 T1 T16 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T4 T1 T16 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T4 T1 T16 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T4 T1 T16 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T4 T1 T16 
167        1/1                    if (trigger_active) begin
           Tests:       T4 T1 T16 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T9 T10 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T4 T16 T66 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T9 T10 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T9 T10 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T9 T10 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T30 T50 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 T50 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T9 T10 
191        1/1                      state_d = StableSt;
           Tests:       T1 T9 T10 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T9 T10 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T9 T10 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T9 T10 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T9 T10 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T9 T10 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T9 T10 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T1,T16
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T1,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T4,T1,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T4,T1,T16
1	0	Covered	T96,T92,T34
1	1	Covered	T4,T1,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T10
0	1	Covered	T50,T123,T124
1	0	Covered	T34,T30

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T9,T10
0	1	Covered	T1,T9,T10
1	0	Covered	T34,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T9,T10
1	-	Covered	T1,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T4,T1,T16
DetectSt	168	Covered	T1,T9,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T9,T10
DebounceSt->IdleSt	163	Covered	T4,T16,T66
DetectSt->IdleSt	186	Covered	T34,T30,T50
DetectSt->StableSt	191	Covered	T1,T9,T10
IdleSt->DebounceSt	148	Covered	T4,T1,T16
StableSt->IdleSt	206	Covered	T1,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T4,T1,T16
0	1	Covered	T4,T1,T16
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T9,T10
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T4,T1,T16
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T4,T16,T66
DebounceSt	-	0	0	-	-	-	-	Covered	T4,T1,T16
DetectSt	-	-	-	-	1	-	-	Covered	T34,T30,T50
DetectSt	-	-	-	-	0	1	-	Covered	T1,T9,T10
DetectSt	-	-	-	-	0	0	-	Covered	T1,T9,T10
StableSt	-	-	-	-	-	-	1	Covered	T1,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T1,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	796	0	0
CntIncr_A	6456720	37423	0	0
CntNoWrap_A	6456720	5999317	0	0
DetectStDropOut_A	6456720	41	0	0
DetectedOut_A	6456720	14768	0	0
DetectedPulseOut_A	6456720	326	0	0
DisabledIdleSt_A	6456720	5673773	0	0
DisabledNoDetection_A	6456720	5675023	0	0
EnterDebounceSt_A	6456720	426	0	0
EnterDetectSt_A	6456720	371	0	0
EnterStableSt_A	6456720	326	0	0
PulseIsPulse_A	6456720	326	0	0
StayInStableSt	6456720	14405	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	286	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	796	0	0
T1	506	2	0	0
T4	448	1	0	0
T5	504	0	0	0
T6	693	0	0	0
T9	0	2	0	0
T10	0	2	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	0	1	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T34	0	8	0	0
T40	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T120	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	37423	0	0
T1	506	25	0	0
T4	448	20	0	0
T5	504	0	0	0
T6	693	0	0	0
T9	0	25	0	0
T10	0	25	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	0	20	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T34	0	259	0	0
T40	0	20	0	0
T66	0	20	0	0
T68	0	20	0	0
T120	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5999317	0	0
T1	506	103	0	0
T4	448	46	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	41	0	0
T50	8908	8	0	0
T123	0	6	0	0
T124	0	12	0	0
T126	0	3	0	0
T127	0	3	0	0
T128	0	1	0	0
T130	0	4	0	0
T131	0	4	0	0
T132	14826	0	0	0
T133	1195	0	0	0
T134	586	0	0	0
T135	504	0	0	0
T136	700	0	0	0
T137	403	0	0	0
T138	521	0	0	0
T139	423	0	0	0
T140	491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	14768	0	0
T1	506	3	0	0
T2	1083	0	0	0
T3	556	0	0	0
T9	0	4	0	0
T10	0	3	0	0
T12	0	4	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T30	0	113	0	0
T34	0	108	0	0
T45	0	3	0	0
T46	0	108	0	0
T49	0	19	0	0
T65	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	326	0	0
T1	506	1	0	0
T2	1083	0	0	0
T3	556	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T30	0	1	0	0
T34	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T49	0	2	0	0
T65	0	3	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5673773	0	0
T1	506	25	0	0
T4	448	4	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5675023	0	0
T1	506	25	0	0
T4	448	4	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	426	0	0
T1	506	1	0	0
T4	448	1	0	0
T5	504	0	0	0
T6	693	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	0	1	0	0
T23	423	0	0	0
T24	506	0	0	0
T25	560	0	0	0
T26	406	0	0	0
T34	0	5	0	0
T40	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T120	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	371	0	0
T1	506	1	0	0
T2	1083	0	0	0
T3	556	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T30	0	3	0	0
T34	0	3	0	0
T45	0	1	0	0
T46	0	2	0	0
T49	0	2	0	0
T65	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	326	0	0
T1	506	1	0	0
T2	1083	0	0	0
T3	556	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T30	0	1	0	0
T34	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T49	0	2	0	0
T65	0	3	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	326	0	0
T1	506	1	0	0
T2	1083	0	0	0
T3	556	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T30	0	1	0	0
T34	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T49	0	2	0	0
T65	0	3	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	14405	0	0
T1	506	2	0	0
T2	1083	0	0	0
T3	556	0	0	0
T9	0	3	0	0
T10	0	2	0	0
T12	0	3	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T30	0	112	0	0
T34	0	107	0	0
T45	0	2	0	0
T46	0	106	0	0
T49	0	17	0	0
T65	0	37	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	286	0	0
T1	506	1	0	0
T2	1083	0	0	0
T3	556	0	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	423	0	0	0
T15	424	0	0	0
T16	477	0	0	0
T17	522	0	0	0
T18	532	0	0	0
T19	533	0	0	0
T20	402	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T49	0	2	0	0
T65	0	3	0	0
T80	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T41 T21 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T41 T21 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T41 T21 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T34 T41 T21 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T34 T41 T21 
129        1/1              cnt_en = 1'b0;
           Tests:       T34 T41 T21 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T34 T41 T21 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T34 T41 T21 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T34 T41 T21 
139                     
140        1/1              unique case (state_q)
           Tests:       T34 T41 T21 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T34 T41 T21 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T41 T21 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T41 T21 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T41 T21 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T41 T21 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T41 T21 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T41 T21 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T41 T21 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T41 T21 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T30 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T41 T21 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T41 T21 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T41 T21 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T41 T30 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T41 T30 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T41 T21 
191        1/1                      state_d = StableSt;
           Tests:       T34 T21 T30 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T34 T21 T30 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T34 T21 T30 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T34 T21 T30 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T34 T21 T30 
206        1/1                    state_d = IdleSt;
           Tests:       T34 T21 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T34 T21 T30 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T41,T21
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T41,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T41,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T41,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T41,T21
1	0	Covered	T34,T21,T30
1	1	Covered	T34,T41,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T41,T21
0	1	Covered	T34,T41,T30
1	0	Covered	T34,T30,T100

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T21,T30
0	1	Covered	T34,T21,T30
1	0	Covered	T34,T30,T302

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T21,T30
1	-	Covered	T34,T21,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T41,T21
DetectSt	168	Covered	T34,T41,T21
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T34,T21,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T41,T21
DebounceSt->IdleSt	163	Covered	T34,T30
DetectSt->IdleSt	186	Covered	T34,T41,T30
DetectSt->StableSt	191	Covered	T34,T21,T30
IdleSt->DebounceSt	148	Covered	T34,T41,T21
StableSt->IdleSt	206	Covered	T34,T21,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T41,T21
0	1	Covered	T34,T41,T21
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T41,T21
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T34,T41,T21
IdleSt	0	-	-	-	-	-	-	Covered	T34,T41,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T41,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T30
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T41,T21
DetectSt	-	-	-	-	1	-	-	Covered	T34,T41,T30
DetectSt	-	-	-	-	0	1	-	Covered	T34,T21,T30
DetectSt	-	-	-	-	0	0	-	Covered	T34,T41,T21
StableSt	-	-	-	-	-	-	1	Covered	T34,T21,T30
StableSt	-	-	-	-	-	-	0	Covered	T34,T21,T30
default	-	-	-	-	-	-	-	Not Covered

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	3027	0	0
CntIncr_A	6456720	100485	0	0
CntNoWrap_A	6456720	5997086	0	0
DetectStDropOut_A	6456720	496	0	0
DetectedOut_A	6456720	81771	0	0
DetectedPulseOut_A	6456720	870	0	0
DisabledIdleSt_A	6456720	5530174	0	0
DisabledNoDetection_A	6456720	5531852	0	0
EnterDebounceSt_A	6456720	1516	0	0
EnterDetectSt_A	6456720	1511	0	0
EnterStableSt_A	6456720	870	0	0
PulseIsPulse_A	6456720	870	0	0
StayInStableSt	6456720	80796	0	0
gen_high_event_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	761	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	3027	0	0
T11	781	0	0	0
T21	0	30	0	0
T30	0	17	0	0
T34	7688	16	0	0
T35	1320	0	0	0
T41	0	50	0	0
T73	0	24	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T97	0	62	0	0
T98	0	44	0	0
T99	0	56	0	0
T100	0	28	0	0
T101	0	14	0	0
T102	4414	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	100485	0	0
T11	781	0	0	0
T21	0	900	0	0
T30	0	384	0	0
T34	7688	517	0	0
T35	1320	0	0	0
T41	0	1247	0	0
T73	0	704	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T97	0	1670	0	0
T98	0	1100	0	0
T99	0	1932	0	0
T100	0	785	0	0
T101	0	352	0	0
T102	4414	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5997086	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	496	0	0
T11	781	0	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T41	0	25	0	0
T51	0	7	0	0
T73	0	12	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T97	0	31	0	0
T101	0	7	0	0
T102	4414	0	0	0
T122	0	5	0	0
T301	0	7	0	0
T303	0	16	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	81771	0	0
T11	781	0	0	0
T21	0	1670	0	0
T30	0	473	0	0
T34	7688	383	0	0
T35	1320	0	0	0
T48	0	3032	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T98	0	1491	0	0
T99	0	729	0	0
T102	4414	0	0	0
T115	0	2118	0	0
T117	0	1712	0	0
T157	0	1758	0	0
T300	0	1892	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	870	0	0
T11	781	0	0	0
T21	0	15	0	0
T30	0	5	0	0
T34	7688	5	0	0
T35	1320	0	0	0
T48	0	23	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T98	0	22	0	0
T99	0	28	0	0
T102	4414	0	0	0
T115	0	17	0	0
T117	0	10	0	0
T157	0	20	0	0
T300	0	20	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5530174	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5531852	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	1516	0	0
T11	781	0	0	0
T21	0	15	0	0
T30	0	10	0	0
T34	7688	9	0	0
T35	1320	0	0	0
T41	0	25	0	0
T73	0	12	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T97	0	31	0	0
T98	0	22	0	0
T99	0	28	0	0
T100	0	14	0	0
T101	0	7	0	0
T102	4414	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	1511	0	0
T11	781	0	0	0
T21	0	15	0	0
T30	0	7	0	0
T34	7688	7	0	0
T35	1320	0	0	0
T41	0	25	0	0
T73	0	12	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T97	0	31	0	0
T98	0	22	0	0
T99	0	28	0	0
T100	0	14	0	0
T101	0	7	0	0
T102	4414	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	870	0	0
T11	781	0	0	0
T21	0	15	0	0
T30	0	5	0	0
T34	7688	5	0	0
T35	1320	0	0	0
T48	0	23	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T98	0	22	0	0
T99	0	28	0	0
T102	4414	0	0	0
T115	0	17	0	0
T117	0	10	0	0
T157	0	20	0	0
T300	0	20	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	870	0	0
T11	781	0	0	0
T21	0	15	0	0
T30	0	5	0	0
T34	7688	5	0	0
T35	1320	0	0	0
T48	0	23	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T98	0	22	0	0
T99	0	28	0	0
T102	4414	0	0	0
T115	0	17	0	0
T117	0	10	0	0
T157	0	20	0	0
T300	0	20	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	80796	0	0
T11	781	0	0	0
T21	0	1653	0	0
T30	0	468	0	0
T34	7688	378	0	0
T35	1320	0	0	0
T48	0	3008	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T98	0	1469	0	0
T99	0	701	0	0
T102	4414	0	0	0
T115	0	2099	0	0
T117	0	1696	0	0
T157	0	1737	0	0
T300	0	1868	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	761	0	0
T11	781	0	0	0
T21	0	13	0	0
T30	0	4	0	0
T34	7688	4	0	0
T35	1320	0	0	0
T48	0	22	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T98	0	22	0	0
T99	0	28	0	0
T102	4414	0	0	0
T115	0	15	0	0
T117	0	4	0	0
T157	0	19	0	0
T300	0	16	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T41 T21 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T21 T30 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T21 T30 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T21 T30 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T21 T30 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T21 T30 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T21 T30 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T21 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T21 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T21 T30 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T65 T50 T47 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T21 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T21 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T21 T30 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T30 T50 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 T50 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T21 T30 
191        1/1                      state_d = StableSt;
           Tests:       T34 T21 T30 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T34 T21 T30 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T34 T21 T30 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T34 T21 T30 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T34 T21 T30 
206        1/1                    state_d = IdleSt;
           Tests:       T34 T30 T46 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T34 T21 T30 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T41,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T41,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T21,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T34,T21,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T21,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T21,T30
1	0	Covered	T96,T92,T34
1	1	Covered	T34,T21,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T21,T30
0	1	Covered	T30,T50,T121
1	0	Covered	T34,T30

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T21,T30
0	1	Covered	T46,T98,T65
1	0	Covered	T34,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T21,T30
1	-	Covered	T46,T98,T65

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T21,T30
DetectSt	168	Covered	T34,T21,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T34,T21,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T21,T30
DebounceSt->IdleSt	163	Covered	T34,T30,T65
DetectSt->IdleSt	186	Covered	T34,T30,T50
DetectSt->StableSt	191	Covered	T34,T21,T30
IdleSt->DebounceSt	148	Covered	T34,T21,T30
StableSt->IdleSt	206	Covered	T34,T21,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T21,T30
0	1	Covered	T34,T21,T30
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T21,T30
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T21,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T21,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T65,T50,T47
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T21,T30
DetectSt	-	-	-	-	1	-	-	Covered	T34,T30,T50
DetectSt	-	-	-	-	0	1	-	Covered	T34,T21,T30
DetectSt	-	-	-	-	0	0	-	Covered	T34,T21,T30
StableSt	-	-	-	-	-	-	1	Covered	T34,T30,T46
StableSt	-	-	-	-	-	-	0	Covered	T34,T21,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	785	0	0
CntIncr_A	6456720	39247	0	0
CntNoWrap_A	6456720	5999328	0	0
DetectStDropOut_A	6456720	80	0	0
DetectedOut_A	6456720	12685	0	0
DetectedPulseOut_A	6456720	285	0	0
DisabledIdleSt_A	6456720	5675985	0	0
DisabledNoDetection_A	6456720	5677297	0	0
EnterDebounceSt_A	6456720	417	0	0
EnterDetectSt_A	6456720	368	0	0
EnterStableSt_A	6456720	285	0	0
PulseIsPulse_A	6456720	285	0	0
StayInStableSt	6456720	12375	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	258	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	785	0	0
T11	781	0	0	0
T21	0	2	0	0
T30	0	8	0	0
T34	7688	8	0	0
T35	1320	0	0	0
T46	0	2	0	0
T47	0	3	0	0
T50	0	28	0	0
T65	0	13	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	10	0	0
T82	0	17	0	0
T98	0	8	0	0
T102	4414	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	39247	0	0
T11	781	0	0	0
T21	0	61	0	0
T30	0	286	0	0
T34	7688	208	0	0
T35	1320	0	0	0
T46	0	147	0	0
T47	0	187	0	0
T50	0	748	0	0
T65	0	865	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	310	0	0
T82	0	545	0	0
T98	0	208	0	0
T102	4414	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5999328	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	80	0	0
T22	1281	0	0	0
T30	7514	1	0	0
T50	0	13	0	0
T90	492	0	0	0
T121	0	12	0	0
T123	0	13	0	0
T125	0	2	0	0
T126	0	7	0	0
T213	430	0	0	0
T214	522	0	0	0
T215	1934	0	0	0
T216	1850	0	0	0
T217	447	0	0	0
T218	524	0	0	0
T291	402	0	0	0
T304	0	10	0	0
T305	0	7	0	0
T306	0	9	0	0
T307	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	12685	0	0
T11	781	0	0	0
T21	0	69	0	0
T30	0	115	0	0
T34	7688	107	0	0
T35	1320	0	0	0
T46	0	12	0	0
T47	0	24	0	0
T48	0	129	0	0
T65	0	27	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	202	0	0
T82	0	480	0	0
T98	0	320	0	0
T102	4414	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	285	0	0
T11	781	0	0	0
T21	0	1	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T65	0	6	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	5	0	0
T82	0	8	0	0
T98	0	4	0	0
T102	4414	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5675985	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5677297	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	417	0	0
T11	781	0	0	0
T21	0	1	0	0
T30	0	5	0	0
T34	7688	5	0	0
T35	1320	0	0	0
T46	0	1	0	0
T47	0	2	0	0
T50	0	15	0	0
T65	0	7	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	5	0	0
T82	0	9	0	0
T98	0	4	0	0
T102	4414	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	368	0	0
T11	781	0	0	0
T21	0	1	0	0
T30	0	3	0	0
T34	7688	3	0	0
T35	1320	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T50	0	13	0	0
T65	0	6	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	5	0	0
T82	0	8	0	0
T98	0	4	0	0
T102	4414	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	285	0	0
T11	781	0	0	0
T21	0	1	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T65	0	6	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	5	0	0
T82	0	8	0	0
T98	0	4	0	0
T102	4414	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	285	0	0
T11	781	0	0	0
T21	0	1	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T65	0	6	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	5	0	0
T82	0	8	0	0
T98	0	4	0	0
T102	4414	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	12375	0	0
T11	781	0	0	0
T21	0	67	0	0
T30	0	114	0	0
T34	7688	106	0	0
T35	1320	0	0	0
T46	0	11	0	0
T47	0	23	0	0
T48	0	126	0	0
T65	0	21	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	197	0	0
T82	0	472	0	0
T98	0	316	0	0
T102	4414	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	258	0	0
T46	10707	1	0	0
T47	0	1	0	0
T48	0	3	0	0
T56	907	0	0	0
T65	0	6	0	0
T80	0	5	0	0
T82	0	8	0	0
T97	5318	0	0	0
T98	6703	4	0	0
T156	0	5	0	0
T157	0	4	0	0
T264	2115	0	0	0
T265	425	0	0	0
T266	404	0	0	0
T267	430	0	0	0
T268	492	0	0	0
T269	503	0	0	0
T308	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T41 T21 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T41 T21 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T41 T21 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T34 T41 T21 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T34 T41 T21 
129        1/1              cnt_en = 1'b0;
           Tests:       T34 T41 T21 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T34 T41 T21 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T34 T41 T21 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T34 T41 T21 
139                     
140        1/1              unique case (state_q)
           Tests:       T34 T41 T21 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T34 T41 T21 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T41 T21 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T41 T21 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T41 T21 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T41 T21 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T41 T21 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T41 T21 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T41 T21 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T41 T21 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T30 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T41 T21 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T41 T21 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T41 T21 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T41 T30 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T41 T30 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T41 T21 
191        1/1                      state_d = StableSt;
           Tests:       T34 T21 T30 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T34 T21 T30 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T34 T21 T30 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T34 T21 T30 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T34 T21 T30 
206        1/1                    state_d = IdleSt;
           Tests:       T34 T21 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T34 T21 T30 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T41,T21
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T41,T21

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T41,T21

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T41,T21

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T41,T21
1	0	Covered	T34,T21,T30
1	1	Covered	T34,T41,T21

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T41,T21
0	1	Covered	T34,T41,T30
1	0	Covered	T34,T30,T98

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T21,T30
0	1	Covered	T34,T21,T30
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T21,T30
1	-	Covered	T34,T21,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T41,T21
DetectSt	168	Covered	T34,T41,T21
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T34,T21,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T41,T21
DebounceSt->IdleSt	163	Covered	T34,T30
DetectSt->IdleSt	186	Covered	T34,T41,T30
DetectSt->StableSt	191	Covered	T34,T21,T30
IdleSt->DebounceSt	148	Covered	T34,T41,T21
StableSt->IdleSt	206	Covered	T34,T21,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T41,T21
0	1	Covered	T34,T41,T21
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T41,T21
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T34,T41,T21
IdleSt	0	-	-	-	-	-	-	Covered	T34,T41,T21
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T41,T21
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T30
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T41,T21
DetectSt	-	-	-	-	1	-	-	Covered	T34,T41,T30
DetectSt	-	-	-	-	0	1	-	Covered	T34,T21,T30
DetectSt	-	-	-	-	0	0	-	Covered	T34,T41,T21
StableSt	-	-	-	-	-	-	1	Covered	T34,T21,T30
StableSt	-	-	-	-	-	-	0	Covered	T34,T21,T30
default	-	-	-	-	-	-	-	Not Covered

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	2962	0	0
CntIncr_A	6456720	102248	0	0
CntNoWrap_A	6456720	5997151	0	0
DetectStDropOut_A	6456720	438	0	0
DetectedOut_A	6456720	69445	0	0
DetectedPulseOut_A	6456720	789	0	0
DisabledIdleSt_A	6456720	5537901	0	0
DisabledNoDetection_A	6456720	5539583	0	0
EnterDebounceSt_A	6456720	1483	0	0
EnterDetectSt_A	6456720	1479	0	0
EnterStableSt_A	6456720	789	0	0
PulseIsPulse_A	6456720	789	0	0
StayInStableSt	6456720	68555	0	0
gen_high_event_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	688	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	2962	0	0
T11	781	0	0	0
T21	0	40	0	0
T30	0	16	0	0
T34	7688	16	0	0
T35	1320	0	0	0
T41	0	28	0	0
T73	0	18	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T97	0	34	0	0
T98	0	44	0	0
T99	0	54	0	0
T100	0	54	0	0
T101	0	40	0	0
T102	4414	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	102248	0	0
T11	781	0	0	0
T21	0	1200	0	0
T30	0	551	0	0
T34	7688	517	0	0
T35	1320	0	0	0
T41	0	692	0	0
T73	0	526	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T97	0	907	0	0
T98	0	1187	0	0
T99	0	1377	0	0
T100	0	1496	0	0
T101	0	1024	0	0
T102	4414	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5997151	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	438	0	0
T11	781	0	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T41	0	14	0	0
T73	0	9	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T97	0	17	0	0
T100	0	15	0	0
T101	0	20	0	0
T102	4414	0	0	0
T117	0	12	0	0
T122	0	13	0	0
T303	0	14	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	69445	0	0
T11	781	0	0	0
T21	0	1880	0	0
T30	0	469	0	0
T34	7688	406	0	0
T35	1320	0	0	0
T48	0	1168	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T99	0	2612	0	0
T102	4414	0	0	0
T115	0	2283	0	0
T157	0	788	0	0
T300	0	1892	0	0
T301	0	28	0	0
T309	0	1405	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	789	0	0
T11	781	0	0	0
T21	0	20	0	0
T30	0	5	0	0
T34	7688	5	0	0
T35	1320	0	0	0
T48	0	22	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T99	0	27	0	0
T102	4414	0	0	0
T115	0	22	0	0
T157	0	8	0	0
T300	0	20	0	0
T301	0	4	0	0
T309	0	28	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5537901	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5539583	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	1483	0	0
T11	781	0	0	0
T21	0	20	0	0
T30	0	9	0	0
T34	7688	9	0	0
T35	1320	0	0	0
T41	0	14	0	0
T73	0	9	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T97	0	17	0	0
T98	0	22	0	0
T99	0	27	0	0
T100	0	27	0	0
T101	0	20	0	0
T102	4414	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	1479	0	0
T11	781	0	0	0
T21	0	20	0	0
T30	0	7	0	0
T34	7688	7	0	0
T35	1320	0	0	0
T41	0	14	0	0
T73	0	9	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T97	0	17	0	0
T98	0	22	0	0
T99	0	27	0	0
T100	0	27	0	0
T101	0	20	0	0
T102	4414	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	789	0	0
T11	781	0	0	0
T21	0	20	0	0
T30	0	5	0	0
T34	7688	5	0	0
T35	1320	0	0	0
T48	0	22	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T99	0	27	0	0
T102	4414	0	0	0
T115	0	22	0	0
T157	0	8	0	0
T300	0	20	0	0
T301	0	4	0	0
T309	0	28	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	789	0	0
T11	781	0	0	0
T21	0	20	0	0
T30	0	5	0	0
T34	7688	5	0	0
T35	1320	0	0	0
T48	0	22	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T99	0	27	0	0
T102	4414	0	0	0
T115	0	22	0	0
T157	0	8	0	0
T300	0	20	0	0
T301	0	4	0	0
T309	0	28	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	68555	0	0
T11	781	0	0	0
T21	0	1856	0	0
T30	0	464	0	0
T34	7688	401	0	0
T35	1320	0	0	0
T48	0	1146	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T99	0	2585	0	0
T102	4414	0	0	0
T115	0	2259	0	0
T157	0	778	0	0
T300	0	1868	0	0
T301	0	24	0	0
T309	0	1376	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	688	0	0
T11	781	0	0	0
T21	0	16	0	0
T30	0	5	0	0
T34	7688	5	0	0
T35	1320	0	0	0
T48	0	22	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T99	0	27	0	0
T102	4414	0	0	0
T115	0	20	0	0
T157	0	6	0	0
T300	0	16	0	0
T301	0	4	0	0
T309	0	27	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T41 T21 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T21 T30 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T4 T1 T16 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T4 T1 T16 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T21 T30 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T21 T30 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T21 T30 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T21 T30 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T30 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T21 T30 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T21 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T21 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T21 T30 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T47 T82 T308 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T21 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T21 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T21 T30 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T30 T65 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T30 T65 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T21 T30 
191        1/1                      state_d = StableSt;
           Tests:       T34 T21 T30 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T34 T21 T30 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T34 T21 T30 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T34 T21 T30 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T34 T21 T30 
206        1/1                    state_d = IdleSt;
           Tests:       T34 T21 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T34 T21 T30 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T41,T21
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T41,T21
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T21,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T34,T21,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T21,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T21,T30
1	0	Covered	T96,T92,T34
1	1	Covered	T34,T21,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T21,T30
0	1	Covered	T65,T82,T310
1	0	Covered	T34,T30

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T21,T30
0	1	Covered	T21,T46,T99
1	0	Covered	T34,T115,T311

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T21,T30
1	-	Covered	T21,T30,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T21,T30
DetectSt	168	Covered	T34,T21,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T34,T21,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T21,T30
DebounceSt->IdleSt	163	Covered	T34,T30,T47
DetectSt->IdleSt	186	Covered	T34,T30,T65
DetectSt->StableSt	191	Covered	T34,T21,T30
IdleSt->DebounceSt	148	Covered	T34,T21,T30
StableSt->IdleSt	206	Covered	T34,T21,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T34,T21,T30
0	1	Covered	T34,T21,T30
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T21,T30
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T21,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T30
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T21,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T82,T308
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T21,T30
DetectSt	-	-	-	-	1	-	-	Covered	T34,T30,T65
DetectSt	-	-	-	-	0	1	-	Covered	T34,T21,T30
DetectSt	-	-	-	-	0	0	-	Covered	T34,T21,T30
StableSt	-	-	-	-	-	-	1	Covered	T34,T21,T30
StableSt	-	-	-	-	-	-	0	Covered	T34,T21,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6456720	756	0	0
CntIncr_A	6456720	38266	0	0
CntNoWrap_A	6456720	5999357	0	0
DetectStDropOut_A	6456720	23	0	0
DetectedOut_A	6456720	15380	0	0
DetectedPulseOut_A	6456720	329	0	0
DisabledIdleSt_A	6456720	5683376	0	0
DisabledNoDetection_A	6456720	5684689	0	0
EnterDebounceSt_A	6456720	400	0	0
EnterDetectSt_A	6456720	356	0	0
EnterStableSt_A	6456720	329	0	0
PulseIsPulse_A	6456720	329	0	0
StayInStableSt	6456720	15023	0	0
gen_high_level_sva.HighLevelEvent_A	6456720	6001990	0	0
gen_not_sticky_sva.StableStDropOut_A	6456720	297	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	756	0	0
T11	781	0	0	0
T21	0	6	0	0
T30	0	8	0	0
T34	7688	8	0	0
T35	1320	0	0	0
T46	0	6	0	0
T47	0	5	0	0
T49	0	12	0	0
T50	0	4	0	0
T65	0	4	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	2	0	0
T99	0	16	0	0
T102	4414	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	38266	0	0
T11	781	0	0	0
T21	0	225	0	0
T30	0	286	0	0
T34	7688	232	0	0
T35	1320	0	0	0
T46	0	411	0	0
T47	0	232	0	0
T49	0	474	0	0
T50	0	96	0	0
T65	0	272	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	53	0	0
T99	0	592	0	0
T102	4414	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5999357	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	23	0	0
T49	18394	0	0	0
T65	11994	2	0	0
T82	0	3	0	0
T99	8778	0	0	0
T123	0	2	0	0
T130	0	1	0	0
T150	14106	0	0	0
T305	0	7	0	0
T306	0	2	0	0
T310	0	4	0	0
T312	0	2	0	0
T313	422	0	0	0
T314	439	0	0	0
T315	884	0	0	0
T316	496	0	0	0
T317	502	0	0	0
T318	1166	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	15380	0	0
T11	781	0	0	0
T21	0	166	0	0
T30	0	113	0	0
T34	7688	107	0	0
T35	1320	0	0	0
T46	0	65	0	0
T47	0	132	0	0
T49	0	413	0	0
T50	0	11	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	49	0	0
T99	0	518	0	0
T102	4414	0	0	0
T156	0	174	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	329	0	0
T11	781	0	0	0
T21	0	3	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T46	0	3	0	0
T47	0	2	0	0
T49	0	6	0	0
T50	0	2	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	1	0	0
T99	0	8	0	0
T102	4414	0	0	0
T156	0	13	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5683376	0	0
T1	506	105	0	0
T4	448	47	0	0
T5	504	103	0	0
T6	693	292	0	0
T14	423	22	0	0
T15	424	23	0	0
T23	423	22	0	0
T24	506	105	0	0
T25	560	159	0	0
T26	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	5684689	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	400	0	0
T11	781	0	0	0
T21	0	3	0	0
T30	0	5	0	0
T34	7688	5	0	0
T35	1320	0	0	0
T46	0	3	0	0
T47	0	3	0	0
T49	0	6	0	0
T50	0	2	0	0
T65	0	2	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	1	0	0
T99	0	8	0	0
T102	4414	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	356	0	0
T11	781	0	0	0
T21	0	3	0	0
T30	0	3	0	0
T34	7688	3	0	0
T35	1320	0	0	0
T46	0	3	0	0
T47	0	2	0	0
T49	0	6	0	0
T50	0	2	0	0
T65	0	2	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	1	0	0
T99	0	8	0	0
T102	4414	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	329	0	0
T11	781	0	0	0
T21	0	3	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T46	0	3	0	0
T47	0	2	0	0
T49	0	6	0	0
T50	0	2	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	1	0	0
T99	0	8	0	0
T102	4414	0	0	0
T156	0	13	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	329	0	0
T11	781	0	0	0
T21	0	3	0	0
T30	0	1	0	0
T34	7688	1	0	0
T35	1320	0	0	0
T46	0	3	0	0
T47	0	2	0	0
T49	0	6	0	0
T50	0	2	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	1	0	0
T99	0	8	0	0
T102	4414	0	0	0
T156	0	13	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	15023	0	0
T11	781	0	0	0
T21	0	163	0	0
T30	0	112	0	0
T34	7688	106	0	0
T35	1320	0	0	0
T46	0	62	0	0
T47	0	130	0	0
T49	0	407	0	0
T50	0	9	0	0
T74	1752	0	0	0
T75	4411	0	0	0
T76	406	0	0	0
T77	507	0	0	0
T78	423	0	0	0
T79	1414	0	0	0
T80	0	48	0	0
T99	0	510	0	0
T102	4414	0	0	0
T156	0	161	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	6001990	0	0
T1	506	106	0	0
T4	448	48	0	0
T5	504	104	0	0
T6	693	293	0	0
T14	423	23	0	0
T15	424	24	0	0
T23	423	23	0	0
T24	506	106	0	0
T25	560	160	0	0
T26	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6456720	297	0	0
T21	19706	3	0	0
T46	0	3	0	0
T47	0	2	0	0
T49	0	6	0	0
T50	0	2	0	0
T61	233199	0	0	0
T71	719	0	0	0
T80	0	1	0	0
T85	976	0	0	0
T89	493	0	0	0
T99	0	8	0	0
T156	0	13	0	0
T157	0	2	0	0
T256	506	0	0	0
T257	2421	0	0	0
T261	410	0	0	0
T262	725	0	0	0
T308	0	8	0	0
T319	421	0	0	0