Unified Coverage Report :: Module :: sysrst_ctrl_ulp

Module : sysrst_ctrl_ulp

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_ulp.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_ulp	100.00	100.00	100.00

---

Module Instance : tb.dut.u_sysrst_ctrl_ulp

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.98	100.00	94.92		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sysrst_ctrl_detect_ac_present	98.67	100.00	93.33		100.00	100.00	100.00
u_sysrst_ctrl_detect_lid_open	98.89	100.00	94.44		100.00	100.00	100.00
u_sysrst_ctrl_detect_pwrb	98.89	100.00	94.44		100.00	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_ulp

	Line No.	Total	Covered	Percent
TOTAL		2	2	100.00
CONT_ASSIGN	89	1	1	100.00
CONT_ASSIGN	93	1	1	100.00

88                        // aggregate pulse and level signals
89         1/1            assign ulp_wakeup_pulse_o = pwrb_det_pulse     |
           Tests:       T2 T9 T36 
90                                                    lid_open_det_pulse |
91                                                    ac_present_det_pulse;
92                      
93         1/1            assign z3_wakeup_hw_o = pwrb_det |
           Tests:       T2 T9 T36 

---

Cond Coverage for Module : sysrst_ctrl_ulp

	Total	Covered	Percent
Conditions	8	8	100.00
Logical	8	8	100.00
Non-Logical	0	0
Event	0	0

 LINE       89
 EXPRESSION (pwrb_det_pulse | lid_open_det_pulse | ac_present_det_pulse)
             -------1------   ---------2--------   ----------3---------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T1
0	0	1	Covered	T2,T9,T36
0	1	0	Covered	T2,T36,T48
1	0	0	Covered	T2,T9,T36

 LINE       93
 EXPRESSION (pwrb_det | lid_open_det | ac_present_det)
             ----1---   ------2-----   -------3------

-1-	-2-	-3-	Status	Tests
0	0	0	Covered	T4,T5,T1
0	0	1	Covered	T48,T89,T90
0	1	0	Covered	T2,T36,T94
1	0	0	Covered	T9,T65,T157