Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T4 T5 T1
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T1
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T1
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T1
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T15 T3
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T15
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T15
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T1
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T1
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T1
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T1
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T1
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T1
139
140 1/1 unique case (state_q)
Tests: T4 T5 T1
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T1
148 1/1 state_d = DebounceSt;
Tests: T2 T15 T3
149 1/1 cnt_en = 1'b1;
Tests: T2 T15 T3
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T15 T3
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T15 T3
163 1/1 state_d = IdleSt;
Tests: T11 T30
164 1/1 cnt_clr = 1'b1;
Tests: T11 T30
165 1/1 end else if (cnt_done) begin
Tests: T2 T15 T3
166 1/1 cnt_clr = 1'b1;
Tests: T2 T15 T3
167 1/1 if (trigger_active) begin
Tests: T2 T15 T3
168 1/1 state_d = DetectSt;
Tests: T2 T15 T3
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T67 T60 T91
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T15 T3
182 1/1 cnt_en = 1'b1;
Tests: T2 T15 T3
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T15 T3
186 1/1 state_d = IdleSt;
Tests: T45 T92 T93
187 1/1 cnt_clr = 1'b1;
Tests: T45 T92 T93
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T15 T3
191 1/1 state_d = StableSt;
Tests: T2 T15 T3
192 1/1 cnt_clr = 1'b1;
Tests: T2 T15 T3
193 1/1 event_detected_o = 1'b1;
Tests: T2 T15 T3
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T15 T3
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T15 T3
206 1/1 state_d = IdleSt;
Tests: T2 T15 T3
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T15 T3
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T1
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T1
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T1
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T1
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T3 T9
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T18
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T18
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T1
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T1
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T1
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T1
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T1
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T1
139
140 1/1 unique case (state_q)
Tests: T4 T5 T1
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T1
148 1/1 state_d = DebounceSt;
Tests: T2 T3 T9
149 1/1 cnt_en = 1'b1;
Tests: T2 T3 T9
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T3 T9
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T3 T9
163 1/1 state_d = IdleSt;
Tests: T11 T30
164 1/1 cnt_clr = 1'b1;
Tests: T11 T30
165 1/1 end else if (cnt_done) begin
Tests: T2 T3 T9
166 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T9
167 1/1 if (trigger_active) begin
Tests: T2 T3 T9
168 1/1 state_d = DetectSt;
Tests: T2 T3 T11
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T3 T8 T9
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T3 T11
182 1/1 cnt_en = 1'b1;
Tests: T2 T3 T11
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T3 T11
186 1/1 state_d = IdleSt;
Tests: T67 T47 T90
187 1/1 cnt_clr = 1'b1;
Tests: T67 T47 T90
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T3 T11
191 1/1 state_d = StableSt;
Tests: T2 T3 T11
192 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T11
193 1/1 event_detected_o = 1'b1;
Tests: T2 T3 T11
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T3 T11
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T3 T11
206 1/1 state_d = IdleSt;
Tests: T2 T3 T11
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T3 T11
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T13
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T4 T5 T13
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T9 T11
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T2 T9 T25
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T2 T9 T25
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T13
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T13
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T13
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T13
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T13
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T13
139
140 1/1 unique case (state_q)
Tests: T4 T5 T13
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T13
148 1/1 state_d = DebounceSt;
Tests: T2 T9 T11
149 1/1 cnt_en = 1'b1;
Tests: T2 T9 T11
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T9 T11
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T9 T11
163 1/1 state_d = IdleSt;
Tests: T11 T30
164 1/1 cnt_clr = 1'b1;
Tests: T11 T30
165 1/1 end else if (cnt_done) begin
Tests: T2 T9 T11
166 1/1 cnt_clr = 1'b1;
Tests: T2 T9 T67
167 1/1 if (trigger_active) begin
Tests: T2 T9 T67
168 1/1 state_d = DetectSt;
Tests: T2 T9 T36
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T67 T65 T94
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T9 T36
182 1/1 cnt_en = 1'b1;
Tests: T2 T9 T36
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T9 T36
186 1/1 state_d = IdleSt;
Tests: T65 T95 T96
187 1/1 cnt_clr = 1'b1;
Tests: T65 T95 T96
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T9 T36
191 1/1 state_d = StableSt;
Tests: T2 T9 T36
192 1/1 cnt_clr = 1'b1;
Tests: T2 T9 T36
193 1/1 event_detected_o = 1'b1;
Tests: T2 T9 T36
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T9 T36
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T9 T36
206 1/1 state_d = IdleSt;
Tests: T2 T9 T36
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T9 T36
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T11 T30 T31
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T11 T30 T31
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T29 T10
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T18 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T18 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T29 T10
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T29 T10
129 1/1 cnt_en = 1'b0;
Tests: T1 T29 T10
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T29 T10
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T29 T10
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T29 T10
139
140 1/1 unique case (state_q)
Tests: T1 T29 T10
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T29 T10
148 1/1 state_d = DebounceSt;
Tests: T1 T29 T10
149 1/1 cnt_en = 1'b1;
Tests: T1 T29 T10
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T29 T10
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T29 T10
163 1/1 state_d = IdleSt;
Tests: T11 T30
164 1/1 cnt_clr = 1'b1;
Tests: T11 T30
165 1/1 end else if (cnt_done) begin
Tests: T1 T29 T10
166 1/1 cnt_clr = 1'b1;
Tests: T1 T29 T10
167 1/1 if (trigger_active) begin
Tests: T1 T29 T10
168 1/1 state_d = DetectSt;
Tests: T1 T29 T10
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T11 T30 T97
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T29 T10
182 1/1 cnt_en = 1'b1;
Tests: T1 T29 T10
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T29 T10
186 1/1 state_d = IdleSt;
Tests: T11 T30 T31
187 1/1 cnt_clr = 1'b1;
Tests: T11 T30 T31
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T29 T10
191 1/1 state_d = StableSt;
Tests: T1 T29 T10
192 1/1 cnt_clr = 1'b1;
Tests: T1 T29 T10
193 1/1 event_detected_o = 1'b1;
Tests: T1 T29 T10
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T29 T10
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T29 T10
206 1/1 state_d = IdleSt;
Tests: T11 T30 T31
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T29 T10
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T1 T18 T7
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T1
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T1
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T1
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T18 T7
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T18 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T18 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
105 1/1 cnt_q <= '0;
Tests: T4 T5 T1
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T1
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T1
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T1
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T1
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T1
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T1
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T1
139
140 1/1 unique case (state_q)
Tests: T4 T5 T1
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T1
148 1/1 state_d = DebounceSt;
Tests: T1 T18 T7
149 1/1 cnt_en = 1'b1;
Tests: T1 T18 T7
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T18 T7
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T18 T7
163 1/1 state_d = IdleSt;
Tests: T11 T30
164 1/1 cnt_clr = 1'b1;
Tests: T11 T30
165 1/1 end else if (cnt_done) begin
Tests: T1 T18 T7
166 1/1 cnt_clr = 1'b1;
Tests: T1 T18 T7
167 1/1 if (trigger_active) begin
Tests: T1 T18 T7
168 1/1 state_d = DetectSt;
Tests: T1 T7 T10
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T18 T29 T54
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T7 T10
182 1/1 cnt_en = 1'b1;
Tests: T1 T7 T10
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T7 T10
186 1/1 state_d = IdleSt;
Tests: T11 T30 T39
187 1/1 cnt_clr = 1'b1;
Tests: T11 T30 T39
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T7 T10
191 1/1 state_d = StableSt;
Tests: T1 T7 T10
192 1/1 cnt_clr = 1'b1;
Tests: T1 T7 T10
193 1/1 event_detected_o = 1'b1;
Tests: T1 T7 T10
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T7 T10
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T7 T10
206 1/1 state_d = IdleSt;
Tests: T1 T7 T10
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T7 T10
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T1
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T1
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T1
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T18,T7 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T18,T7 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T18,T7 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T18,T7 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T7,T10 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T18,T7 |
| 1 | 0 | Covered | T11,T51,T88 |
| 1 | 1 | Covered | T1,T18,T7 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T7,T10 |
| 0 | 1 | Covered | T39,T41,T98 |
| 1 | 0 | Covered | T11,T30 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T7,T10 |
| 0 | 1 | Covered | T1,T7,T10 |
| 1 | 0 | Covered | T11,T30,T99 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T7,T10 |
| 1 | - | Covered | T1,T7,T10 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T1 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T15,T3,T6 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T15,T3,T6 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T15,T3,T6 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T15,T3,T6 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T15,T3,T6 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T15,T3,T6 |
| 0 | 1 | Covered | T45,T92,T93 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T15,T3,T6 |
| 0 | 1 | Covered | T15,T3,T28 |
| 1 | 0 | Covered | T11,T30 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T15,T3,T6 |
| 1 | - | Covered | T15,T3,T28 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T11,T30,T31 |
| 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T29,T10 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T29,T10 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T1,T29,T10 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T30,T31 |
| 1 | 0 | Covered | T11,T30,T31 |
| 1 | 1 | Covered | T1,T29,T10 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T29,T10 |
| 0 | 1 | Covered | T11,T30,T31 |
| 1 | 0 | Covered | T11,T30,T31 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T29,T10 |
| 0 | 1 | Covered | T11,T30,T31 |
| 1 | 0 | Covered | T11,T30,T100 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T29,T10 |
| 1 | - | Covered | T11,T30,T31 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T13 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T9,T11 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T9,T11 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T9,T36 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T9,T11 |
| 1 | 0 | Covered | T4,T5,T13 |
| 1 | 1 | Covered | T2,T9,T11 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T9,T36 |
| 0 | 1 | Covered | T65,T95,T96 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T9,T36 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T9,T36 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T1 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T3,T6,T8 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T3,T6,T8 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T3,T6,T8 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T6,T8 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T3,T6,T8 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T6,T8 |
| 0 | 1 | Covered | T47,T101,T102 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T6,T8 |
| 0 | 1 | Covered | T3,T12,T46 |
| 1 | 0 | Covered | T11,T30 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T3,T6,T8 |
| 1 | - | Covered | T3,T12,T46 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T4,T5,T13 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T1 |
| 1 | 0 | Covered | T4,T5,T13 |
| 1 | 1 | Covered | T4,T5,T13 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T9,T11 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T9,T11 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T67,T36 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T9,T11 |
| 1 | 0 | Covered | T4,T5,T13 |
| 1 | 1 | Covered | T2,T9,T11 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T36,T48 |
| 0 | 1 | Covered | T67,T90,T103 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T36,T48 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T36,T48 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T13 |
| 1 | Covered | T4,T5,T1 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T13 |
| 1 | 0 | Covered | T4,T5,T1 |
| 1 | 1 | Covered | T4,T5,T1 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T9,T11 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T9,T11 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T1 |
| 1 | Covered | T2,T9,T36 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T9,T11 |
| 1 | 0 | Covered | T4,T5,T13 |
| 1 | 1 | Covered | T2,T9,T11 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T9,T36 |
| 0 | 1 | Covered | T104 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T9,T36 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T9,T36 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DebounceSt |
148 |
Covered |
T15,T3,T6 |
| DetectSt |
168 |
Covered |
T15,T3,T6 |
| IdleSt |
163 |
Covered |
T4,T5,T1 |
| StableSt |
191 |
Covered |
T15,T3,T6 |
| transitions | Line No. | Covered | Tests |
| DebounceSt->DetectSt |
168 |
Covered |
T15,T3,T6 |
| DebounceSt->IdleSt |
163 |
Covered |
T3,T11,T67 |
| DetectSt->IdleSt |
186 |
Covered |
T67,T45,T47 |
| DetectSt->StableSt |
191 |
Covered |
T15,T3,T6 |
| IdleSt->DebounceSt |
148 |
Covered |
T15,T3,T6 |
| StableSt->IdleSt |
206 |
Covered |
T15,T3,T11 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T15,T3,T6 |
| 0 |
1 |
Covered |
T15,T3,T6 |
| 0 |
0 |
Covered |
T4,T5,T1 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T15,T3,T6 |
| 0 |
Covered |
T4,T5,T1 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T15,T3,T6 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T1 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T11,T30 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T15,T3,T6 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T3,T67,T60 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T15,T3,T6 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T11,T67,T30 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T15,T3,T6 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T7,T10 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T15,T3,T11 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T15,T3,T6 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T2,T29 |
| 0 |
1 |
Covered |
T1,T2,T29 |
| 0 |
0 |
Covered |
T4,T5,T1 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T2,T29 |
| 0 |
Covered |
T4,T5,T1 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T2,T29 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T13 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T11,T30 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T1,T2,T29 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T11,T67,T30 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T2,T29 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T11,T30,T31 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T1,T2,T29 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T29,T10 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T2,T9,T11 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T2,T29 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T1 |
| 0 |
Covered |
T4,T5,T1 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
16497 |
0 |
0 |
| T1 |
1044 |
4 |
0 |
0 |
| T2 |
4450 |
0 |
0 |
0 |
| T3 |
813 |
0 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T10 |
0 |
4 |
0 |
0 |
| T11 |
7404 |
27 |
0 |
0 |
| T12 |
658 |
0 |
0 |
0 |
| T13 |
998 |
0 |
0 |
0 |
| T14 |
810 |
0 |
0 |
0 |
| T15 |
1956 |
4 |
0 |
0 |
| T16 |
1224 |
0 |
0 |
0 |
| T17 |
1572 |
0 |
0 |
0 |
| T18 |
1338 |
1 |
0 |
0 |
| T19 |
1578 |
0 |
0 |
0 |
| T20 |
1272 |
0 |
0 |
0 |
| T24 |
854 |
0 |
0 |
0 |
| T27 |
503 |
0 |
0 |
0 |
| T28 |
634 |
2 |
0 |
0 |
| T29 |
0 |
3 |
0 |
0 |
| T30 |
0 |
17 |
0 |
0 |
| T31 |
0 |
36 |
0 |
0 |
| T52 |
780 |
4 |
0 |
0 |
| T53 |
487 |
2 |
0 |
0 |
| T54 |
0 |
1 |
0 |
0 |
| T55 |
0 |
4 |
0 |
0 |
| T56 |
0 |
3 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T59 |
0 |
4 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
4 |
0 |
0 |
| T62 |
426 |
0 |
0 |
0 |
| T63 |
502 |
0 |
0 |
0 |
| T64 |
496 |
0 |
0 |
0 |
| T82 |
0 |
2 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
1994819 |
0 |
0 |
| T1 |
1044 |
46 |
0 |
0 |
| T2 |
4450 |
0 |
0 |
0 |
| T3 |
813 |
0 |
0 |
0 |
| T7 |
0 |
25 |
0 |
0 |
| T10 |
0 |
46 |
0 |
0 |
| T11 |
7404 |
770 |
0 |
0 |
| T12 |
658 |
0 |
0 |
0 |
| T13 |
998 |
0 |
0 |
0 |
| T14 |
810 |
0 |
0 |
0 |
| T15 |
1956 |
92 |
0 |
0 |
| T16 |
1224 |
0 |
0 |
0 |
| T17 |
1572 |
0 |
0 |
0 |
| T18 |
1338 |
20 |
0 |
0 |
| T19 |
1578 |
0 |
0 |
0 |
| T20 |
1272 |
0 |
0 |
0 |
| T24 |
854 |
0 |
0 |
0 |
| T27 |
503 |
0 |
0 |
0 |
| T28 |
634 |
20 |
0 |
0 |
| T29 |
0 |
41 |
0 |
0 |
| T30 |
0 |
689 |
0 |
0 |
| T31 |
0 |
1225 |
0 |
0 |
| T52 |
780 |
195 |
0 |
0 |
| T53 |
487 |
25 |
0 |
0 |
| T54 |
0 |
20 |
0 |
0 |
| T55 |
0 |
49 |
0 |
0 |
| T56 |
0 |
41 |
0 |
0 |
| T57 |
0 |
20 |
0 |
0 |
| T58 |
0 |
96 |
0 |
0 |
| T59 |
0 |
101 |
0 |
0 |
| T60 |
0 |
26 |
0 |
0 |
| T61 |
0 |
113 |
0 |
0 |
| T62 |
426 |
0 |
0 |
0 |
| T63 |
502 |
0 |
0 |
0 |
| T64 |
496 |
0 |
0 |
0 |
| T82 |
0 |
21 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
169251225 |
0 |
0 |
| T1 |
13572 |
3142 |
0 |
0 |
| T2 |
57850 |
47406 |
0 |
0 |
| T4 |
12896 |
2470 |
0 |
0 |
| T5 |
10998 |
572 |
0 |
0 |
| T13 |
12974 |
2548 |
0 |
0 |
| T14 |
10530 |
104 |
0 |
0 |
| T15 |
16952 |
6522 |
0 |
0 |
| T16 |
10608 |
182 |
0 |
0 |
| T17 |
13624 |
3198 |
0 |
0 |
| T18 |
11596 |
1169 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
1847 |
0 |
0 |
| T11 |
7404 |
1 |
0 |
0 |
| T30 |
0 |
1 |
0 |
0 |
| T31 |
0 |
10 |
0 |
0 |
| T44 |
10550 |
2 |
0 |
0 |
| T84 |
0 |
6 |
0 |
0 |
| T87 |
17941 |
16 |
0 |
0 |
| T92 |
2861 |
1 |
0 |
0 |
| T93 |
539 |
0 |
0 |
0 |
| T105 |
0 |
3 |
0 |
0 |
| T106 |
0 |
2 |
0 |
0 |
| T107 |
0 |
1 |
0 |
0 |
| T108 |
0 |
7 |
0 |
0 |
| T109 |
0 |
23 |
0 |
0 |
| T110 |
0 |
26 |
0 |
0 |
| T111 |
0 |
2 |
0 |
0 |
| T112 |
0 |
2 |
0 |
0 |
| T113 |
0 |
7 |
0 |
0 |
| T114 |
0 |
24 |
0 |
0 |
| T115 |
0 |
3 |
0 |
0 |
| T116 |
0 |
9 |
0 |
0 |
| T117 |
0 |
4 |
0 |
0 |
| T118 |
0 |
3 |
0 |
0 |
| T119 |
13413 |
0 |
0 |
0 |
| T120 |
519 |
0 |
0 |
0 |
| T121 |
726 |
0 |
0 |
0 |
| T122 |
8402 |
0 |
0 |
0 |
| T123 |
428 |
0 |
0 |
0 |
| T124 |
1052 |
0 |
0 |
0 |
| T125 |
437 |
0 |
0 |
0 |
| T126 |
426 |
0 |
0 |
0 |
| T127 |
501 |
0 |
0 |
0 |
| T128 |
559 |
0 |
0 |
0 |
| T129 |
433 |
0 |
0 |
0 |
| T130 |
618 |
0 |
0 |
0 |
| T131 |
429 |
0 |
0 |
0 |
| T132 |
494 |
0 |
0 |
0 |
| T133 |
522 |
0 |
0 |
0 |
| T134 |
504 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
1493218 |
0 |
0 |
| T1 |
1044 |
100 |
0 |
0 |
| T2 |
4450 |
0 |
0 |
0 |
| T3 |
813 |
0 |
0 |
0 |
| T7 |
0 |
3 |
0 |
0 |
| T10 |
0 |
78 |
0 |
0 |
| T11 |
7404 |
534 |
0 |
0 |
| T12 |
658 |
0 |
0 |
0 |
| T13 |
998 |
0 |
0 |
0 |
| T14 |
810 |
0 |
0 |
0 |
| T15 |
1956 |
12 |
0 |
0 |
| T16 |
1224 |
0 |
0 |
0 |
| T17 |
1572 |
0 |
0 |
0 |
| T18 |
1338 |
0 |
0 |
0 |
| T19 |
1578 |
0 |
0 |
0 |
| T20 |
1272 |
0 |
0 |
0 |
| T24 |
854 |
0 |
0 |
0 |
| T27 |
503 |
0 |
0 |
0 |
| T28 |
634 |
8 |
0 |
0 |
| T29 |
0 |
43 |
0 |
0 |
| T30 |
0 |
498 |
0 |
0 |
| T37 |
0 |
905 |
0 |
0 |
| T39 |
0 |
47 |
0 |
0 |
| T40 |
0 |
184 |
0 |
0 |
| T41 |
0 |
262 |
0 |
0 |
| T52 |
780 |
10 |
0 |
0 |
| T53 |
487 |
3 |
0 |
0 |
| T55 |
0 |
10 |
0 |
0 |
| T56 |
0 |
45 |
0 |
0 |
| T58 |
0 |
16 |
0 |
0 |
| T59 |
0 |
15 |
0 |
0 |
| T61 |
0 |
10 |
0 |
0 |
| T62 |
426 |
0 |
0 |
0 |
| T63 |
502 |
0 |
0 |
0 |
| T64 |
496 |
0 |
0 |
0 |
| T135 |
0 |
6 |
0 |
0 |
| T136 |
0 |
13 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
5473 |
0 |
0 |
| T1 |
1044 |
2 |
0 |
0 |
| T2 |
4450 |
0 |
0 |
0 |
| T3 |
813 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
7404 |
7 |
0 |
0 |
| T12 |
658 |
0 |
0 |
0 |
| T13 |
998 |
0 |
0 |
0 |
| T14 |
810 |
0 |
0 |
0 |
| T15 |
1956 |
2 |
0 |
0 |
| T16 |
1224 |
0 |
0 |
0 |
| T17 |
1572 |
0 |
0 |
0 |
| T18 |
1338 |
0 |
0 |
0 |
| T19 |
1578 |
0 |
0 |
0 |
| T20 |
1272 |
0 |
0 |
0 |
| T24 |
854 |
0 |
0 |
0 |
| T27 |
503 |
0 |
0 |
0 |
| T28 |
634 |
1 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
6 |
0 |
0 |
| T37 |
0 |
15 |
0 |
0 |
| T39 |
0 |
2 |
0 |
0 |
| T40 |
0 |
5 |
0 |
0 |
| T41 |
0 |
6 |
0 |
0 |
| T52 |
780 |
2 |
0 |
0 |
| T53 |
487 |
1 |
0 |
0 |
| T55 |
0 |
2 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
426 |
0 |
0 |
0 |
| T63 |
502 |
0 |
0 |
0 |
| T64 |
496 |
0 |
0 |
0 |
| T135 |
0 |
1 |
0 |
0 |
| T136 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
158777237 |
0 |
0 |
| T1 |
13572 |
2932 |
0 |
0 |
| T2 |
57850 |
42195 |
0 |
0 |
| T4 |
12896 |
2470 |
0 |
0 |
| T5 |
10998 |
572 |
0 |
0 |
| T13 |
12974 |
2548 |
0 |
0 |
| T14 |
10530 |
104 |
0 |
0 |
| T15 |
16952 |
6341 |
0 |
0 |
| T16 |
10608 |
182 |
0 |
0 |
| T17 |
13624 |
3198 |
0 |
0 |
| T18 |
11596 |
1128 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
158821243 |
0 |
0 |
| T1 |
13572 |
2956 |
0 |
0 |
| T2 |
57850 |
42221 |
0 |
0 |
| T4 |
12896 |
2496 |
0 |
0 |
| T5 |
10998 |
598 |
0 |
0 |
| T13 |
12974 |
2574 |
0 |
0 |
| T14 |
10530 |
130 |
0 |
0 |
| T15 |
16952 |
6366 |
0 |
0 |
| T16 |
10608 |
208 |
0 |
0 |
| T17 |
13624 |
3224 |
0 |
0 |
| T18 |
11596 |
1153 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
8423 |
0 |
0 |
| T1 |
1044 |
2 |
0 |
0 |
| T2 |
4450 |
0 |
0 |
0 |
| T3 |
813 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
7404 |
16 |
0 |
0 |
| T12 |
658 |
0 |
0 |
0 |
| T13 |
998 |
0 |
0 |
0 |
| T14 |
810 |
0 |
0 |
0 |
| T15 |
1956 |
2 |
0 |
0 |
| T16 |
1224 |
0 |
0 |
0 |
| T17 |
1572 |
0 |
0 |
0 |
| T18 |
1338 |
1 |
0 |
0 |
| T19 |
1578 |
0 |
0 |
0 |
| T20 |
1272 |
0 |
0 |
0 |
| T24 |
854 |
0 |
0 |
0 |
| T27 |
503 |
0 |
0 |
0 |
| T28 |
634 |
1 |
0 |
0 |
| T29 |
0 |
2 |
0 |
0 |
| T30 |
0 |
10 |
0 |
0 |
| T31 |
0 |
18 |
0 |
0 |
| T52 |
780 |
2 |
0 |
0 |
| T53 |
487 |
1 |
0 |
0 |
| T54 |
0 |
1 |
0 |
0 |
| T55 |
0 |
2 |
0 |
0 |
| T56 |
0 |
2 |
0 |
0 |
| T57 |
0 |
1 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
426 |
0 |
0 |
0 |
| T63 |
502 |
0 |
0 |
0 |
| T64 |
496 |
0 |
0 |
0 |
| T82 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
8079 |
0 |
0 |
| T1 |
1044 |
2 |
0 |
0 |
| T2 |
4450 |
0 |
0 |
0 |
| T3 |
813 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
7404 |
11 |
0 |
0 |
| T12 |
658 |
0 |
0 |
0 |
| T13 |
998 |
0 |
0 |
0 |
| T14 |
810 |
0 |
0 |
0 |
| T15 |
1956 |
2 |
0 |
0 |
| T16 |
1224 |
0 |
0 |
0 |
| T17 |
1572 |
0 |
0 |
0 |
| T18 |
1338 |
0 |
0 |
0 |
| T19 |
1578 |
0 |
0 |
0 |
| T20 |
1272 |
0 |
0 |
0 |
| T24 |
854 |
0 |
0 |
0 |
| T27 |
503 |
0 |
0 |
0 |
| T28 |
634 |
1 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
10 |
0 |
0 |
| T37 |
0 |
15 |
0 |
0 |
| T39 |
0 |
2 |
0 |
0 |
| T40 |
0 |
5 |
0 |
0 |
| T41 |
0 |
6 |
0 |
0 |
| T52 |
780 |
2 |
0 |
0 |
| T53 |
487 |
1 |
0 |
0 |
| T55 |
0 |
2 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
426 |
0 |
0 |
0 |
| T63 |
502 |
0 |
0 |
0 |
| T64 |
496 |
0 |
0 |
0 |
| T135 |
0 |
1 |
0 |
0 |
| T136 |
0 |
1 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
5473 |
0 |
0 |
| T1 |
1044 |
2 |
0 |
0 |
| T2 |
4450 |
0 |
0 |
0 |
| T3 |
813 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
7404 |
7 |
0 |
0 |
| T12 |
658 |
0 |
0 |
0 |
| T13 |
998 |
0 |
0 |
0 |
| T14 |
810 |
0 |
0 |
0 |
| T15 |
1956 |
2 |
0 |
0 |
| T16 |
1224 |
0 |
0 |
0 |
| T17 |
1572 |
0 |
0 |
0 |
| T18 |
1338 |
0 |
0 |
0 |
| T19 |
1578 |
0 |
0 |
0 |
| T20 |
1272 |
0 |
0 |
0 |
| T24 |
854 |
0 |
0 |
0 |
| T27 |
503 |
0 |
0 |
0 |
| T28 |
634 |
1 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
6 |
0 |
0 |
| T37 |
0 |
15 |
0 |
0 |
| T39 |
0 |
2 |
0 |
0 |
| T40 |
0 |
5 |
0 |
0 |
| T41 |
0 |
6 |
0 |
0 |
| T52 |
780 |
2 |
0 |
0 |
| T53 |
487 |
1 |
0 |
0 |
| T55 |
0 |
2 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
426 |
0 |
0 |
0 |
| T63 |
502 |
0 |
0 |
0 |
| T64 |
496 |
0 |
0 |
0 |
| T135 |
0 |
1 |
0 |
0 |
| T136 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
5473 |
0 |
0 |
| T1 |
1044 |
2 |
0 |
0 |
| T2 |
4450 |
0 |
0 |
0 |
| T3 |
813 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
7404 |
7 |
0 |
0 |
| T12 |
658 |
0 |
0 |
0 |
| T13 |
998 |
0 |
0 |
0 |
| T14 |
810 |
0 |
0 |
0 |
| T15 |
1956 |
2 |
0 |
0 |
| T16 |
1224 |
0 |
0 |
0 |
| T17 |
1572 |
0 |
0 |
0 |
| T18 |
1338 |
0 |
0 |
0 |
| T19 |
1578 |
0 |
0 |
0 |
| T20 |
1272 |
0 |
0 |
0 |
| T24 |
854 |
0 |
0 |
0 |
| T27 |
503 |
0 |
0 |
0 |
| T28 |
634 |
1 |
0 |
0 |
| T29 |
0 |
1 |
0 |
0 |
| T30 |
0 |
6 |
0 |
0 |
| T37 |
0 |
15 |
0 |
0 |
| T39 |
0 |
2 |
0 |
0 |
| T40 |
0 |
5 |
0 |
0 |
| T41 |
0 |
6 |
0 |
0 |
| T52 |
780 |
2 |
0 |
0 |
| T53 |
487 |
1 |
0 |
0 |
| T55 |
0 |
2 |
0 |
0 |
| T56 |
0 |
1 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
426 |
0 |
0 |
0 |
| T63 |
502 |
0 |
0 |
0 |
| T64 |
496 |
0 |
0 |
0 |
| T135 |
0 |
1 |
0 |
0 |
| T136 |
0 |
1 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
181188306 |
1486941 |
0 |
0 |
| T1 |
1044 |
97 |
0 |
0 |
| T2 |
4450 |
0 |
0 |
0 |
| T3 |
813 |
0 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T10 |
0 |
75 |
0 |
0 |
| T11 |
7404 |
527 |
0 |
0 |
| T12 |
658 |
0 |
0 |
0 |
| T13 |
998 |
0 |
0 |
0 |
| T14 |
810 |
0 |
0 |
0 |
| T15 |
1956 |
10 |
0 |
0 |
| T16 |
1224 |
0 |
0 |
0 |
| T17 |
1572 |
0 |
0 |
0 |
| T18 |
1338 |
0 |
0 |
0 |
| T19 |
1578 |
0 |
0 |
0 |
| T20 |
1272 |
0 |
0 |
0 |
| T24 |
854 |
0 |
0 |
0 |
| T27 |
503 |
0 |
0 |
0 |
| T28 |
634 |
7 |
0 |
0 |
| T29 |
0 |
41 |
0 |
0 |
| T30 |
0 |
492 |
0 |
0 |
| T37 |
0 |
889 |
0 |
0 |
| T39 |
0 |
45 |
0 |
0 |
| T40 |
0 |
179 |
0 |
0 |
| T41 |
0 |
256 |
0 |
0 |
| T52 |
780 |
8 |
0 |
0 |
| T53 |
487 |
2 |
0 |
0 |
| T55 |
0 |
8 |
0 |
0 |
| T56 |
0 |
43 |
0 |
0 |
| T58 |
0 |
14 |
0 |
0 |
| T59 |
0 |
13 |
0 |
0 |
| T61 |
0 |
8 |
0 |
0 |
| T62 |
426 |
0 |
0 |
0 |
| T63 |
502 |
0 |
0 |
0 |
| T64 |
496 |
0 |
0 |
0 |
| T135 |
0 |
5 |
0 |
0 |
| T136 |
0 |
12 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
62719029 |
38882 |
0 |
0 |
| T1 |
4698 |
3 |
0 |
0 |
| T2 |
20025 |
40 |
0 |
0 |
| T3 |
0 |
15 |
0 |
0 |
| T4 |
4464 |
66 |
0 |
0 |
| T5 |
3807 |
19 |
0 |
0 |
| T6 |
0 |
2 |
0 |
0 |
| T13 |
4491 |
61 |
0 |
0 |
| T14 |
3645 |
0 |
0 |
0 |
| T15 |
5868 |
9 |
0 |
0 |
| T16 |
3672 |
0 |
0 |
0 |
| T17 |
4716 |
44 |
0 |
0 |
| T18 |
4014 |
3 |
0 |
0 |
| T19 |
0 |
31 |
0 |
0 |
| T20 |
0 |
22 |
0 |
0 |
| T24 |
0 |
3 |
0 |
0 |
| T27 |
0 |
43 |
0 |
0 |
| T62 |
0 |
11 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
34843905 |
32560640 |
0 |
0 |
| T1 |
2610 |
610 |
0 |
0 |
| T2 |
11125 |
9125 |
0 |
0 |
| T4 |
2480 |
480 |
0 |
0 |
| T5 |
2115 |
115 |
0 |
0 |
| T13 |
2495 |
495 |
0 |
0 |
| T14 |
2025 |
25 |
0 |
0 |
| T15 |
3260 |
1260 |
0 |
0 |
| T16 |
2040 |
40 |
0 |
0 |
| T17 |
2620 |
620 |
0 |
0 |
| T18 |
2230 |
230 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
118469277 |
110706176 |
0 |
0 |
| T1 |
8874 |
2074 |
0 |
0 |
| T2 |
37825 |
31025 |
0 |
0 |
| T4 |
8432 |
1632 |
0 |
0 |
| T5 |
7191 |
391 |
0 |
0 |
| T13 |
8483 |
1683 |
0 |
0 |
| T14 |
6885 |
85 |
0 |
0 |
| T15 |
11084 |
4284 |
0 |
0 |
| T16 |
6936 |
136 |
0 |
0 |
| T17 |
8908 |
2108 |
0 |
0 |
| T18 |
7582 |
782 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
62719029 |
58609152 |
0 |
0 |
| T1 |
4698 |
1098 |
0 |
0 |
| T2 |
20025 |
16425 |
0 |
0 |
| T4 |
4464 |
864 |
0 |
0 |
| T5 |
3807 |
207 |
0 |
0 |
| T13 |
4491 |
891 |
0 |
0 |
| T14 |
3645 |
45 |
0 |
0 |
| T15 |
5868 |
2268 |
0 |
0 |
| T16 |
3672 |
72 |
0 |
0 |
| T17 |
4716 |
1116 |
0 |
0 |
| T18 |
4014 |
414 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
160281963 |
4496 |
0 |
0 |
| T1 |
522 |
1 |
0 |
0 |
| T2 |
2225 |
0 |
0 |
0 |
| T3 |
813 |
0 |
0 |
0 |
| T7 |
0 |
1 |
0 |
0 |
| T10 |
0 |
1 |
0 |
0 |
| T11 |
7404 |
5 |
0 |
0 |
| T12 |
658 |
0 |
0 |
0 |
| T13 |
499 |
0 |
0 |
0 |
| T14 |
405 |
0 |
0 |
0 |
| T15 |
1304 |
2 |
0 |
0 |
| T16 |
816 |
0 |
0 |
0 |
| T17 |
1048 |
0 |
0 |
0 |
| T18 |
892 |
0 |
0 |
0 |
| T19 |
1052 |
0 |
0 |
0 |
| T20 |
848 |
0 |
0 |
0 |
| T24 |
854 |
0 |
0 |
0 |
| T27 |
503 |
0 |
0 |
0 |
| T28 |
634 |
1 |
0 |
0 |
| T30 |
0 |
4 |
0 |
0 |
| T37 |
0 |
14 |
0 |
0 |
| T39 |
0 |
2 |
0 |
0 |
| T40 |
0 |
5 |
0 |
0 |
| T41 |
0 |
6 |
0 |
0 |
| T52 |
780 |
2 |
0 |
0 |
| T53 |
487 |
1 |
0 |
0 |
| T55 |
0 |
2 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T59 |
0 |
2 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
426 |
0 |
0 |
0 |
| T63 |
502 |
0 |
0 |
0 |
| T64 |
496 |
0 |
0 |
0 |
| T135 |
0 |
1 |
0 |
0 |
| T136 |
0 |
1 |
0 |
0 |
| T137 |
0 |
1 |
0 |
0 |
| T138 |
0 |
1 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
20906343 |
2094559 |
0 |
0 |
| T2 |
6675 |
1785 |
0 |
0 |
| T3 |
2439 |
0 |
0 |
0 |
| T9 |
0 |
1412 |
0 |
0 |
| T15 |
1956 |
0 |
0 |
0 |
| T16 |
1224 |
0 |
0 |
0 |
| T17 |
1572 |
0 |
0 |
0 |
| T18 |
1338 |
0 |
0 |
0 |
| T19 |
1578 |
0 |
0 |
0 |
| T20 |
1272 |
0 |
0 |
0 |
| T27 |
1509 |
0 |
0 |
0 |
| T36 |
0 |
1062 |
0 |
0 |
| T48 |
0 |
787 |
0 |
0 |
| T62 |
1278 |
0 |
0 |
0 |
| T65 |
0 |
156 |
0 |
0 |
| T89 |
0 |
420 |
0 |
0 |
| T90 |
0 |
308 |
0 |
0 |
| T92 |
0 |
196 |
0 |
0 |
| T94 |
0 |
169 |
0 |
0 |
| T101 |
0 |
105 |
0 |
0 |
| T103 |
0 |
196 |
0 |
0 |
| T139 |
0 |
531 |
0 |
0 |
| T140 |
0 |
538 |
0 |
0 |
| T141 |
0 |
1012 |
0 |
0 |
| T142 |
0 |
470623 |
0 |
0 |
| T143 |
0 |
126 |
0 |
0 |
