Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.34	89.13	90.48		83.33	85.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
88.34	89.13	90.48		83.33	85.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T11 T12 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T11 T12 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T11 T12 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T11 T12 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T11 T12 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T11 T12 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T11 T12 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T11 T12 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T11 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T3 T174 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T11 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T11 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T11 T12 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T11 T12 
191        1/1                      state_d = StableSt;
           Tests:       T3 T11 T12 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T11 T12 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T11 T12 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T11 T12 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T11 T12 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T11 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T11 T12 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T3,T47,T182
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T12
1	-	Covered	T3,T47,T182

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T12
DetectSt	168	Covered	T3,T11,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T12
DebounceSt->IdleSt	163	Covered	T3,T174
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T11,T12
IdleSt->DebounceSt	148	Covered	T3,T11,T12
StableSt->IdleSt	206	Covered	T3,T11,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T12
0	1	Covered	T3,T11,T12
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T174
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T30
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	40	0	0
CntIncr_A	6968781	1099	0	0
CntNoWrap_A	6968781	6510257	0	0
DetectStDropOut_A	6968781	0	0	0
DetectedOut_A	6968781	1063	0	0
DetectedPulseOut_A	6968781	19	0	0
DisabledIdleSt_A	6968781	6278880	0	0
DisabledNoDetection_A	6968781	6280684	0	0
EnterDebounceSt_A	6968781	21	0	0
EnterDetectSt_A	6968781	19	0	0
EnterStableSt_A	6968781	19	0	0
PulseIsPulse_A	6968781	19	0	0
StayInStableSt	6968781	1034	0	0
gen_high_level_sva.HighLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	40	0	0
T3	813	3	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	2	0	0
T45	0	2	0	0
T47	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	2	0	0
T182	0	2	0	0
T189	0	2	0	0
T190	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1099	0	0
T3	813	84	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	19	0	0
T12	0	20	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	26	0	0
T45	0	37	0	0
T47	0	30	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	50	0	0
T182	0	30	0	0
T189	0	75	0	0
T190	0	88	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510257	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1063	0	0
T3	813	17	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	14	0	0
T12	0	62	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	9	0	0
T45	0	45	0	0
T47	0	40	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	40	0	0
T182	0	40	0	0
T189	0	171	0	0
T190	0	55	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	19	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T182	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6278880	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6280684	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	21	0	0
T3	813	2	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T182	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	19	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T182	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	19	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T182	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	19	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T182	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1034	0	0
T3	813	16	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	13	0	0
T12	0	60	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	8	0	0
T45	0	43	0	0
T47	0	39	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	38	0	0
T182	0	39	0	0
T189	0	169	0	0
T190	0	54	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	7	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T47	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T182	0	1	0	0
T187	0	1	0	0
T190	0	1	0	0
T191	0	1	0	0
T192	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T6 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T6 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T6 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T6 T11 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T6 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T6 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T6 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T6 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T181 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T6 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T6 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T45 T193 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T45 T193 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T6 T11 
191        1/1                      state_d = StableSt;
           Tests:       T3 T6 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T6 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T6 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T6 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T6 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T11 T46 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T6 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T6,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T11
1	0	Covered	T4,T5,T13
1	1	Covered	T3,T6,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T45,T193
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T3,T46,T182
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T11
1	-	Covered	T3,T46,T182

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T11
DetectSt	168	Covered	T3,T6,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T11
DebounceSt->IdleSt	163	Covered	T181
DetectSt->IdleSt	186	Covered	T45,T193
DetectSt->StableSt	191	Covered	T3,T6,T11
IdleSt->DebounceSt	148	Covered	T3,T6,T11
StableSt->IdleSt	206	Covered	T3,T11,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T11
0	1	Covered	T3,T6,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T11
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T181
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T11
DetectSt	-	-	-	-	1	-	-	Covered	T45,T193
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T46
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	101	0	0
CntIncr_A	6968781	62180	0	0
CntNoWrap_A	6968781	6510196	0	0
DetectStDropOut_A	6968781	2	0	0
DetectedOut_A	6968781	5324	0	0
DetectedPulseOut_A	6968781	48	0	0
DisabledIdleSt_A	6968781	6213316	0	0
DisabledNoDetection_A	6968781	6215108	0	0
EnterDebounceSt_A	6968781	51	0	0
EnterDetectSt_A	6968781	50	0	0
EnterStableSt_A	6968781	48	0	0
PulseIsPulse_A	6968781	48	0	0
StayInStableSt	6968781	5253	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6968781	1746	0	0
gen_low_level_sva.LowLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	101	0	0
T3	813	6	0	0
T6	848	2	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	2	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	2	0	0
T45	0	2	0	0
T46	0	4	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T166	0	4	0	0
T182	0	4	0	0
T189	0	2	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	62180	0	0
T3	813	126	0	0
T6	848	83	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	19	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	26	0	0
T45	0	37	0	0
T46	0	92	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T166	0	154	0	0
T182	0	60	0	0
T189	0	75	0	0
T194	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510196	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	2	0	0
T45	1584	1	0	0
T48	3509	0	0	0
T60	690	0	0	0
T74	491	0	0	0
T75	2775	0	0	0
T193	0	1	0	0
T195	422	0	0	0
T196	402	0	0	0
T197	8421	0	0	0
T198	523	0	0	0
T199	754	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5324	0	0
T3	813	192	0	0
T6	848	355	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	16	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	9	0	0
T46	0	110	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T120	0	50	0	0
T166	0	426	0	0
T182	0	247	0	0
T189	0	43	0	0
T194	0	197	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	48	0	0
T3	813	3	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T120	0	1	0	0
T166	0	2	0	0
T182	0	2	0	0
T189	0	1	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6213316	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6215108	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	51	0	0
T3	813	3	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T166	0	2	0	0
T182	0	2	0	0
T189	0	1	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	50	0	0
T3	813	3	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T166	0	2	0	0
T182	0	2	0	0
T189	0	1	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	48	0	0
T3	813	3	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T120	0	1	0	0
T166	0	2	0	0
T182	0	2	0	0
T189	0	1	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	48	0	0
T3	813	3	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T120	0	1	0	0
T166	0	2	0	0
T182	0	2	0	0
T189	0	1	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5253	0	0
T3	813	188	0	0
T6	848	353	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	15	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	8	0	0
T46	0	107	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T120	0	48	0	0
T166	0	423	0	0
T182	0	244	0	0
T189	0	42	0	0
T194	0	195	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1746	0	0
T1	522	0	0	0
T2	2225	0	0	0
T3	0	3	0	0
T4	496	5	0	0
T5	423	1	0	0
T13	499	4	0	0
T14	405	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	5	0	0
T18	446	0	0	0
T19	0	6	0	0
T20	0	1	0	0
T24	0	3	0	0
T27	0	5	0	0
T62	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	23	0	0
T3	813	2	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T46	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T166	0	1	0	0
T173	0	2	0	0
T182	0	1	0	0
T186	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T200	0	1	0	0
T201	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T13 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T11 T12 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T11 T12 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T11 T12 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T11 T12 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T11 T12 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T11 T12 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T11 T12 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T11 T12 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T11 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T46 T45 T190 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T11 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T11 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T11 T12 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T11 T12 
191        1/1                      state_d = StableSt;
           Tests:       T8 T11 T12 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T11 T12 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T11 T12 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T11 T12 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T11 T12 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T12 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T11 T12 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T13
1	1	Covered	T4,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T12
1	0	Covered	T4,T5,T13
1	1	Covered	T8,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T12
0	1	Covered	T12,T45,T48
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T12
1	-	Covered	T12,T45,T48

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T12
DetectSt	168	Covered	T8,T11,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T12
DebounceSt->IdleSt	163	Covered	T46,T45,T190
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T11,T12
IdleSt->DebounceSt	148	Covered	T8,T11,T12
StableSt->IdleSt	206	Covered	T11,T12,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T12
0	1	Covered	T8,T11,T12
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T12
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T45,T190
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T12,T30
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	80	0	0
CntIncr_A	6968781	19526	0	0
CntNoWrap_A	6968781	6510217	0	0
DetectStDropOut_A	6968781	0	0	0
DetectedOut_A	6968781	4899	0	0
DetectedPulseOut_A	6968781	37	0	0
DisabledIdleSt_A	6968781	6430538	0	0
DisabledNoDetection_A	6968781	6432333	0	0
EnterDebounceSt_A	6968781	43	0	0
EnterDetectSt_A	6968781	37	0	0
EnterStableSt_A	6968781	37	0	0
PulseIsPulse_A	6968781	37	0	0
StayInStableSt	6968781	4846	0	0
gen_high_level_sva.HighLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	80	0	0
T8	548	2	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	2	0	0
T12	0	4	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	2	0	0
T45	0	3	0	0
T46	0	3	0	0
T48	0	2	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T168	0	2	0	0
T169	0	4	0	0
T182	0	4	0	0
T202	409	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	19526	0	0
T8	548	94	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	19	0	0
T12	0	40	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	26	0	0
T45	0	74	0	0
T46	0	92	0	0
T48	0	30	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T168	0	70	0	0
T169	0	100	0	0
T182	0	60	0	0
T202	409	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510217	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	4899	0	0
T8	548	43	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	15	0	0
T12	0	124	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	8	0	0
T45	0	1	0	0
T46	0	106	0	0
T48	0	40	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T168	0	150	0	0
T169	0	94	0	0
T182	0	82	0	0
T202	409	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	37	0	0
T8	548	1	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T168	0	1	0	0
T169	0	2	0	0
T182	0	2	0	0
T202	409	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6430538	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6432333	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	43	0	0
T8	548	1	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	1	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T168	0	1	0	0
T169	0	2	0	0
T182	0	2	0	0
T202	409	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	37	0	0
T8	548	1	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T168	0	1	0	0
T169	0	2	0	0
T182	0	2	0	0
T202	409	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	37	0	0
T8	548	1	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T168	0	1	0	0
T169	0	2	0	0
T182	0	2	0	0
T202	409	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	37	0	0
T8	548	1	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	1	0	0
T12	0	2	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T168	0	1	0	0
T169	0	2	0	0
T182	0	2	0	0
T202	409	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	4846	0	0
T8	548	41	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	14	0	0
T12	0	121	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	7	0	0
T46	0	104	0	0
T48	0	39	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T168	0	148	0	0
T169	0	91	0	0
T182	0	80	0	0
T189	0	166	0	0
T202	409	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	19	0	0
T12	658	1	0	0
T28	634	0	0	0
T45	0	1	0	0
T48	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T169	0	1	0	0
T182	0	2	0	0
T188	0	1	0	0
T189	0	1	0	0
T203	0	2	0	0
T204	0	1	0	0
T205	0	1	0	0
T206	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T13 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T12 T46 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T12 T46 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T12 T46 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T12 T46 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T12 T46 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T12 T46 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T12 T46 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T12 T46 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T12 T46 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T171 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T12 T46 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T12 T46 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T12 T46 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T12 T46 
191        1/1                      state_d = StableSt;
           Tests:       T11 T12 T46 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T12 T46 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T12 T46 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T12 T46 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T12 T46 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T12 T46 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T12 T46 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T12,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T11,T12,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T12,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T12,T50
1	0	Covered	T4,T5,T13
1	1	Covered	T11,T12,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T12,T46
0	1	Covered	T12,T46,T45
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T12,T46
1	-	Covered	T12,T46,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T12,T46
DetectSt	168	Covered	T11,T12,T46
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T12,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T12,T46
DebounceSt->IdleSt	163	Covered	T171
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T12,T46
IdleSt->DebounceSt	148	Covered	T11,T12,T46
StableSt->IdleSt	206	Covered	T11,T12,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T12,T46
0	1	Covered	T11,T12,T46
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T12,T46
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T12,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T12,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T171
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T12,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T12,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T12,T46
StableSt	-	-	-	-	-	-	0	Covered	T11,T12,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	63	0	0
CntIncr_A	6968781	1833	0	0
CntNoWrap_A	6968781	6510234	0	0
DetectStDropOut_A	6968781	0	0	0
DetectedOut_A	6968781	2939	0	0
DetectedPulseOut_A	6968781	31	0	0
DisabledIdleSt_A	6968781	6495977	0	0
DisabledNoDetection_A	6968781	6497770	0	0
EnterDebounceSt_A	6968781	32	0	0
EnterDetectSt_A	6968781	31	0	0
EnterStableSt_A	6968781	31	0	0
PulseIsPulse_A	6968781	31	0	0
StayInStableSt	6968781	2894	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6968781	5176	0	0
gen_low_level_sva.LowLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	63	0	0
T11	7404	2	0	0
T12	658	2	0	0
T28	634	0	0	0
T30	0	2	0	0
T45	0	4	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	2	0	0
T182	0	4	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1833	0	0
T11	7404	19	0	0
T12	658	20	0	0
T28	634	0	0	0
T30	0	26	0	0
T45	0	74	0	0
T46	0	46	0	0
T47	0	30	0	0
T48	0	30	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	90	0	0
T182	0	60	0	0
T194	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510234	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	2939	0	0
T11	7404	14	0	0
T12	658	62	0	0
T28	634	0	0	0
T30	0	10	0	0
T45	0	84	0	0
T46	0	40	0	0
T47	0	55	0	0
T48	0	194	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	227	0	0
T182	0	115	0	0
T194	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	31	0	0
T11	7404	1	0	0
T12	658	1	0	0
T28	634	0	0	0
T30	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	1	0	0
T182	0	2	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6495977	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6497770	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	32	0	0
T11	7404	1	0	0
T12	658	1	0	0
T28	634	0	0	0
T30	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	1	0	0
T182	0	2	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	31	0	0
T11	7404	1	0	0
T12	658	1	0	0
T28	634	0	0	0
T30	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	1	0	0
T182	0	2	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	31	0	0
T11	7404	1	0	0
T12	658	1	0	0
T28	634	0	0	0
T30	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	1	0	0
T182	0	2	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	31	0	0
T11	7404	1	0	0
T12	658	1	0	0
T28	634	0	0	0
T30	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	1	0	0
T182	0	2	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	2894	0	0
T11	7404	13	0	0
T12	658	61	0	0
T28	634	0	0	0
T30	0	9	0	0
T45	0	81	0	0
T46	0	39	0	0
T47	0	54	0	0
T48	0	192	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	225	0	0
T182	0	112	0	0
T194	0	38	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5176	0	0
T1	522	0	0	0
T2	2225	10	0	0
T3	0	1	0	0
T4	496	8	0	0
T5	423	3	0	0
T13	499	7	0	0
T14	405	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	6	0	0
T18	446	0	0	0
T19	0	3	0	0
T20	0	5	0	0
T27	0	5	0	0
T62	0	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	15	0	0
T12	658	1	0	0
T28	634	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T167	0	1	0	0
T169	0	1	0	0
T182	0	1	0	0
T186	0	1	0	0
T190	0	1	0	0
T203	0	1	0	0
T206	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T6 T8 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T6 T8 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T6 T8 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T8 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T6 T8 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T6 T8 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T6 T8 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T6 T8 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T6 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T8 T45 T102 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T6 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T6 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T101 T102 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T101 T102 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T6 T11 
191        1/1                      state_d = StableSt;
           Tests:       T3 T6 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T6 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T6 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T6 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T6 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T6 T11 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T6 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T101,T102
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T3,T6,T46
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T11
1	-	Covered	T3,T6,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T8
DetectSt	168	Covered	T3,T6,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T11
DebounceSt->IdleSt	163	Covered	T8,T45,T102
DetectSt->IdleSt	186	Covered	T101,T102
DetectSt->StableSt	191	Covered	T3,T6,T11
IdleSt->DebounceSt	148	Covered	T3,T6,T8
StableSt->IdleSt	206	Covered	T3,T6,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T11
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T45,T102
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T101,T102
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	80	0	0
CntIncr_A	6968781	180016	0	0
CntNoWrap_A	6968781	6510217	0	0
DetectStDropOut_A	6968781	2	0	0
DetectedOut_A	6968781	3013	0	0
DetectedPulseOut_A	6968781	36	0	0
DisabledIdleSt_A	6968781	6148135	0	0
DisabledNoDetection_A	6968781	6149935	0	0
EnterDebounceSt_A	6968781	42	0	0
EnterDetectSt_A	6968781	38	0	0
EnterStableSt_A	6968781	36	0	0
PulseIsPulse_A	6968781	36	0	0
StayInStableSt	6968781	2962	0	0
gen_high_level_sva.HighLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	19	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	80	0	0
T3	813	4	0	0
T6	848	2	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	2	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	2	0	0
T45	0	3	0	0
T46	0	2	0	0
T49	0	2	0	0
T51	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	180016	0	0
T3	813	84	0	0
T6	848	83	0	0
T7	480	0	0	0
T8	548	94	0	0
T11	0	19	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	26	0	0
T45	0	74	0	0
T46	0	46	0	0
T49	0	70	0	0
T51	0	26	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510217	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	2	0	0
T101	5154	1	0	0
T102	0	1	0	0
T142	472933	0	0	0
T171	770	0	0	0
T207	493	0	0	0
T208	869	0	0	0
T209	524	0	0	0
T210	1272	0	0	0
T211	405	0	0	0
T212	407	0	0	0
T213	425	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	3013	0	0
T3	813	146	0	0
T6	848	227	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	15	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	8	0	0
T45	0	82	0	0
T46	0	59	0	0
T49	0	170	0	0
T51	0	45	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	40	0	0
T194	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	36	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6148135	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6149935	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	42	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	38	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	36	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	36	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	2962	0	0
T3	813	143	0	0
T6	848	226	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	14	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	7	0	0
T45	0	80	0	0
T46	0	58	0	0
T49	0	168	0	0
T51	0	43	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	38	0	0
T194	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	19	0	0
T3	813	1	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T46	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T166	0	2	0	0
T173	0	2	0	0
T190	0	1	0	0
T200	0	1	0	0
T203	0	2	0	0
T210	0	1	0	0
T214	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T6 T11 T30 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T6 T11 T30 
149        1/1                    cnt_en = 1'b1;
           Tests:       T6 T11 T30 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T6 T11 T30 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T6 T11 T30 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T6 T11 T30 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T6 T11 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T6 T11 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T6 T11 T30 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T6 T11 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T6 T11 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T6 T11 T30 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T6 T11 T30 
191        1/1                      state_d = StableSt;
           Tests:       T6 T11 T30 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T6 T11 T30 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T6 T11 T30 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T6 T11 T30 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T6 T11 T30 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T30 T45 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T6 T11 T30 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T11,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T6,T11,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T11,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T51
1	0	Covered	T4,T5,T1
1	1	Covered	T6,T11,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T30
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T11,T30
0	1	Covered	T45,T47,T215
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T11,T30
1	-	Covered	T45,T47,T215

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T11,T30
DetectSt	168	Covered	T6,T11,T30
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T11,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T11,T30
DebounceSt->IdleSt	163	Covered	T215
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T11,T30
IdleSt->DebounceSt	148	Covered	T6,T11,T30
StableSt->IdleSt	206	Covered	T11,T30,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	17	85.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T6,T11,T30
0	1	Covered	T6,T11,T30
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T11,T30
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T11,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T11,T30
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T11,T30
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T11,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T30,T45
StableSt	-	-	-	-	-	-	0	Covered	T6,T11,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	44	0	0
CntIncr_A	6968781	3584	0	0
CntNoWrap_A	6968781	6510253	0	0
DetectStDropOut_A	6968781	0	0	0
DetectedOut_A	6968781	1311	0	0
DetectedPulseOut_A	6968781	22	0	0
DisabledIdleSt_A	6968781	6266587	0	0
DisabledNoDetection_A	6968781	6268383	0	0
EnterDebounceSt_A	6968781	23	0	0
EnterDetectSt_A	6968781	22	0	0
EnterStableSt_A	6968781	22	0	0
PulseIsPulse_A	6968781	22	0	0
StayInStableSt	6968781	1277	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6968781	4814	0	0
gen_low_level_sva.LowLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	8	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	44	0	0
T6	848	2	0	0
T7	480	0	0	0
T8	548	0	0	0
T9	2031	0	0	0
T11	0	2	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	2	0	0
T45	0	2	0	0
T47	0	2	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T170	0	2	0	0
T182	0	2	0	0
T190	0	2	0	0
T202	409	0	0	0
T203	0	4	0	0
T215	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	3584	0	0
T6	848	83	0	0
T7	480	0	0	0
T8	548	0	0	0
T9	2031	0	0	0
T11	0	19	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	26	0	0
T45	0	37	0	0
T47	0	30	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T170	0	48	0	0
T182	0	30	0	0
T190	0	88	0	0
T202	409	0	0	0
T203	0	104	0	0
T215	0	2476	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510253	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1311	0	0
T6	848	45	0	0
T7	480	0	0	0
T8	548	0	0	0
T9	2031	0	0	0
T11	0	15	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	9	0	0
T45	0	40	0	0
T47	0	40	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T170	0	39	0	0
T182	0	43	0	0
T190	0	41	0	0
T202	409	0	0	0
T203	0	90	0	0
T215	0	165	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	22	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T9	2031	0	0	0
T11	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T170	0	1	0	0
T182	0	1	0	0
T190	0	1	0	0
T202	409	0	0	0
T203	0	2	0	0
T215	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6266587	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6268383	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	23	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T9	2031	0	0	0
T11	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T170	0	1	0	0
T182	0	1	0	0
T190	0	1	0	0
T202	409	0	0	0
T203	0	2	0	0
T215	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	22	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T9	2031	0	0	0
T11	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T170	0	1	0	0
T182	0	1	0	0
T190	0	1	0	0
T202	409	0	0	0
T203	0	2	0	0
T215	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	22	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T9	2031	0	0	0
T11	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T170	0	1	0	0
T182	0	1	0	0
T190	0	1	0	0
T202	409	0	0	0
T203	0	2	0	0
T215	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	22	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T9	2031	0	0	0
T11	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T170	0	1	0	0
T182	0	1	0	0
T190	0	1	0	0
T202	409	0	0	0
T203	0	2	0	0
T215	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1277	0	0
T6	848	43	0	0
T7	480	0	0	0
T8	548	0	0	0
T9	2031	0	0	0
T11	0	14	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	8	0	0
T45	0	39	0	0
T47	0	39	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T170	0	37	0	0
T182	0	41	0	0
T190	0	39	0	0
T202	409	0	0	0
T203	0	87	0	0
T215	0	164	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	4814	0	0
T1	522	1	0	0
T2	2225	0	0	0
T3	0	1	0	0
T4	496	8	0	0
T5	423	3	0	0
T13	499	7	0	0
T14	405	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	6	0	0
T18	446	1	0	0
T19	0	2	0	0
T20	0	4	0	0
T27	0	5	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	8	0	0
T45	1584	1	0	0
T47	0	1	0	0
T48	3509	0	0	0
T60	690	0	0	0
T74	491	0	0	0
T75	2775	0	0	0
T171	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T195	422	0	0	0
T196	402	0	0	0
T197	8421	0	0	0
T198	523	0	0	0
T199	754	0	0	0
T203	0	1	0	0
T210	0	1	0	0
T215	0	1	0	0