Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T6 T8 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T6 T8 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T6 T8 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T8 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T6 T8 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T6 T8 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T6 T8 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T6 T8 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T6 T8 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T48 T47 T204 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T6 T8 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T8 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T6 T8 
186        1/1                    state_d = IdleSt;
           Tests:       T47 T181 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T47 T181 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T6 T8 
191        1/1                      state_d = StableSt;
           Tests:       T3 T6 T8 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T6 T8 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T6 T8 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T6 T8 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T6 T8 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T6 T11 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T6 T8 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T47,T181
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T8
0	1	Covered	T3,T6,T46
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T8
1	-	Covered	T3,T6,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T8
DetectSt	168	Covered	T3,T6,T8
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T6,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T8
DebounceSt->IdleSt	163	Covered	T48,T47,T204
DetectSt->IdleSt	186	Covered	T47,T181
DetectSt->StableSt	191	Covered	T3,T6,T8
IdleSt->DebounceSt	148	Covered	T3,T6,T8
StableSt->IdleSt	206	Covered	T3,T6,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T8
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T47,T204
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T8
DetectSt	-	-	-	-	1	-	-	Covered	T47,T181
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T8
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T6,T11
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	104	0	0
CntIncr_A	6968781	22454	0	0
CntNoWrap_A	6968781	6510193	0	0
DetectStDropOut_A	6968781	2	0	0
DetectedOut_A	6968781	4289	0	0
DetectedPulseOut_A	6968781	47	0	0
DisabledIdleSt_A	6968781	6452885	0	0
DisabledNoDetection_A	6968781	6454678	0	0
EnterDebounceSt_A	6968781	55	0	0
EnterDetectSt_A	6968781	49	0	0
EnterStableSt_A	6968781	47	0	0
PulseIsPulse_A	6968781	47	0	0
StayInStableSt	6968781	4223	0	0
gen_high_level_sva.HighLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	26	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	104	0	0
T3	813	4	0	0
T6	848	2	0	0
T7	480	0	0	0
T8	548	2	0	0
T11	0	2	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	2	0	0
T46	0	2	0	0
T47	0	5	0	0
T48	0	3	0	0
T49	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	22454	0	0
T3	813	84	0	0
T6	848	83	0	0
T7	480	0	0	0
T8	548	94	0	0
T11	0	19	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	26	0	0
T46	0	46	0	0
T47	0	90	0	0
T48	0	60	0	0
T49	0	70	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510193	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	2	0	0
T31	8960	0	0	0
T47	712	1	0	0
T135	717	0	0	0
T168	630	0	0	0
T181	0	1	0	0
T216	872	0	0	0
T217	501	0	0	0
T218	405	0	0	0
T219	917	0	0	0
T220	494	0	0	0
T221	418	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	4289	0	0
T3	813	65	0	0
T6	848	227	0	0
T7	480	0	0	0
T8	548	44	0	0
T11	0	14	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	9	0	0
T46	0	6	0	0
T47	0	14	0	0
T48	0	18	0	0
T49	0	50	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	47	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6452885	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6454678	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	55	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	3	0	0
T48	0	2	0	0
T49	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	49	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	47	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	47	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	4223	0	0
T3	813	63	0	0
T6	848	226	0	0
T7	480	0	0	0
T8	548	42	0	0
T11	0	13	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	8	0	0
T46	0	5	0	0
T47	0	13	0	0
T48	0	17	0	0
T49	0	49	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T194	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	26	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T166	0	1	0	0
T167	0	2	0	0
T182	0	1	0	0
T189	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T6 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T6 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T6 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T6 T11 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T6 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T6 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T6 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T6 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T201 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T6 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T6 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T222 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T222 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T6 T11 
191        1/1                      state_d = StableSt;
           Tests:       T3 T6 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T6 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T6 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T6 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T6 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T11 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T6 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T6,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T11
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T222
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T6,T11
0	1	Covered	T3,T47,T167
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T6,T11
1	-	Covered	T3,T47,T167

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T11
DetectSt	168	Covered	T3,T6,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T6,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T6,T11
DebounceSt->IdleSt	163	Covered	T201
DetectSt->IdleSt	186	Covered	T222
DetectSt->StableSt	191	Covered	T3,T6,T11
IdleSt->DebounceSt	148	Covered	T3,T6,T11
StableSt->IdleSt	206	Covered	T3,T11,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T11
0	1	Covered	T3,T6,T11
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T6,T11
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T11
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T6,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T201
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T11
DetectSt	-	-	-	-	1	-	-	Covered	T222
DetectSt	-	-	-	-	0	1	-	Covered	T3,T6,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T30
StableSt	-	-	-	-	-	-	0	Covered	T3,T6,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	59	0	0
CntIncr_A	6968781	120191	0	0
CntNoWrap_A	6968781	6510238	0	0
DetectStDropOut_A	6968781	1	0	0
DetectedOut_A	6968781	10216	0	0
DetectedPulseOut_A	6968781	28	0	0
DisabledIdleSt_A	6968781	6170613	0	0
DisabledNoDetection_A	6968781	6172410	0	0
EnterDebounceSt_A	6968781	30	0	0
EnterDetectSt_A	6968781	29	0	0
EnterStableSt_A	6968781	28	0	0
PulseIsPulse_A	6968781	28	0	0
StayInStableSt	6968781	10172	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6968781	4867	0	0
gen_low_level_sva.LowLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	59	0	0
T3	813	4	0	0
T6	848	2	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	2	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	2	0	0
T46	0	2	0	0
T47	0	6	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T167	0	4	0	0
T169	0	2	0	0
T203	0	2	0	0
T210	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	120191	0	0
T3	813	84	0	0
T6	848	83	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	19	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	26	0	0
T46	0	46	0	0
T47	0	90	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T167	0	166	0	0
T169	0	50	0	0
T203	0	52	0	0
T210	0	190	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510238	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1	0	0
T222	565	1	0	0
T223	499	0	0	0
T224	711	0	0	0
T225	534	0	0	0
T226	506	0	0	0
T227	6940	0	0	0
T228	421	0	0	0
T229	9519	0	0	0
T230	404	0	0	0
T231	879	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	10216	0	0
T3	813	167	0	0
T6	848	45	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	15	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	8	0	0
T46	0	53	0	0
T47	0	121	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T167	0	86	0	0
T169	0	182	0	0
T203	0	47	0	0
T210	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	28	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	3	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T167	0	2	0	0
T169	0	1	0	0
T203	0	1	0	0
T210	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6170613	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6172410	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	30	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	3	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T167	0	2	0	0
T169	0	1	0	0
T203	0	1	0	0
T210	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	29	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	3	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T167	0	2	0	0
T169	0	1	0	0
T203	0	1	0	0
T210	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	28	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	3	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T167	0	2	0	0
T169	0	1	0	0
T203	0	1	0	0
T210	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	28	0	0
T3	813	2	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	3	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T167	0	2	0	0
T169	0	1	0	0
T203	0	1	0	0
T210	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	10172	0	0
T3	813	164	0	0
T6	848	43	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	14	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	7	0	0
T46	0	51	0	0
T47	0	117	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T167	0	83	0	0
T169	0	180	0	0
T203	0	45	0	0
T210	0	84	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	4867	0	0
T1	522	1	0	0
T2	2225	0	0	0
T3	0	2	0	0
T4	496	8	0	0
T5	423	3	0	0
T13	499	11	0	0
T14	405	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	4	0	0
T18	446	1	0	0
T19	0	5	0	0
T20	0	2	0	0
T27	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	10	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T47	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T167	0	1	0	0
T171	0	1	0	0
T176	0	1	0	0
T204	0	1	0	0
T205	0	1	0	0
T210	0	1	0	0
T232	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T1 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T50 T49 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T50 T49 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T50 T49 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T50 T49 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T50 T49 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T50 T49 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T50 T49 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T50 T49 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T50 T49 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T47 T166 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T50 T49 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T50 T49 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T50 T49 
186        1/1                    state_d = IdleSt;
           Tests:       T175 T233 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T175 T233 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T50 T49 
191        1/1                      state_d = StableSt;
           Tests:       T11 T50 T49 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T50 T49 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T50 T49 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T50 T49 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T50 T49 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T30 T48 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T50 T49 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T50,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T11,T50,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T11,T50,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T50,T49
1	0	Covered	T4,T5,T1
1	1	Covered	T11,T50,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T50,T49
0	1	Covered	T175,T233
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T50,T49
0	1	Covered	T48,T194,T182
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T50,T49
1	-	Covered	T48,T194,T182

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T50,T49
DetectSt	168	Covered	T11,T50,T49
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T11,T50,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T50,T49
DebounceSt->IdleSt	163	Covered	T47,T166
DetectSt->IdleSt	186	Covered	T175,T233
DetectSt->StableSt	191	Covered	T11,T50,T49
IdleSt->DebounceSt	148	Covered	T11,T50,T49
StableSt->IdleSt	206	Covered	T11,T30,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T11,T50,T49
0	1	Covered	T11,T50,T49
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T50,T49
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T50,T49
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T50,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T166
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T50,T49
DetectSt	-	-	-	-	1	-	-	Covered	T175,T233
DetectSt	-	-	-	-	0	1	-	Covered	T11,T50,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T30,T48
StableSt	-	-	-	-	-	-	0	Covered	T11,T50,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	78	0	0
CntIncr_A	6968781	56141	0	0
CntNoWrap_A	6968781	6510219	0	0
DetectStDropOut_A	6968781	2	0	0
DetectedOut_A	6968781	61729	0	0
DetectedPulseOut_A	6968781	36	0	0
DisabledIdleSt_A	6968781	6301300	0	0
DisabledNoDetection_A	6968781	6303098	0	0
EnterDebounceSt_A	6968781	40	0	0
EnterDetectSt_A	6968781	38	0	0
EnterStableSt_A	6968781	36	0	0
PulseIsPulse_A	6968781	36	0	0
StayInStableSt	6968781	61677	0	0
gen_high_level_sva.HighLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	78	0	0
T11	7404	2	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	2	0	0
T47	0	3	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	2	0	0
T167	0	4	0	0
T182	0	2	0	0
T194	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	56141	0	0
T11	7404	19	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	26	0	0
T47	0	60	0	0
T48	0	30	0	0
T49	0	70	0	0
T50	0	98	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	90	0	0
T167	0	166	0	0
T182	0	30	0	0
T194	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510219	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	2	0	0
T175	761	1	0	0
T191	2757	0	0	0
T233	0	1	0	0
T234	14950	0	0	0
T235	522	0	0	0
T236	424	0	0	0
T237	497	0	0	0
T238	1510	0	0	0
T239	2171	0	0	0
T240	1028	0	0	0
T241	645	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	61729	0	0
T11	7404	14	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	10	0	0
T47	0	40	0	0
T48	0	91	0	0
T49	0	169	0	0
T50	0	40	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	93	0	0
T167	0	342	0	0
T182	0	92	0	0
T194	0	59	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	36	0	0
T11	7404	1	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	1	0	0
T167	0	2	0	0
T182	0	1	0	0
T194	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6301300	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6303098	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	40	0	0
T11	7404	1	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	1	0	0
T167	0	2	0	0
T182	0	1	0	0
T194	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	38	0	0
T11	7404	1	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	1	0	0
T167	0	2	0	0
T182	0	1	0	0
T194	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	36	0	0
T11	7404	1	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	1	0	0
T167	0	2	0	0
T182	0	1	0	0
T194	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	36	0	0
T11	7404	1	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	1	0	0
T167	0	2	0	0
T182	0	1	0	0
T194	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	61677	0	0
T11	7404	13	0	0
T12	658	0	0	0
T28	634	0	0	0
T30	0	9	0	0
T47	0	38	0	0
T48	0	90	0	0
T49	0	167	0	0
T50	0	38	0	0
T51	3934	0	0	0
T52	780	0	0	0
T53	487	0	0	0
T54	443	0	0	0
T63	502	0	0	0
T64	496	0	0	0
T88	1867	0	0	0
T159	0	91	0	0
T167	0	339	0	0
T182	0	91	0	0
T194	0	58	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	18	0	0
T48	3509	1	0	0
T167	0	1	0	0
T170	0	1	0	0
T173	0	1	0	0
T182	0	1	0	0
T186	0	2	0	0
T194	705	1	0	0
T215	0	1	0	0
T242	0	1	0	0
T243	0	1	0	0
T244	548	0	0	0
T245	507	0	0	0
T246	424	0	0	0
T247	566	0	0	0
T248	1341	0	0	0
T249	491	0	0	0
T250	751	0	0	0
T251	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T1 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T6 T8 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T6 T8 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T6 T8 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T6 T8 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T6 T8 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T6 T8 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T6 T8 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T6 T8 
168        1/1                      state_d = DetectSt;
           Tests:       T6 T8 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T3 T243 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T6 T8 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T6 T8 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T6 T8 T11 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T6 T8 T11 
191        1/1                      state_d = StableSt;
           Tests:       T6 T8 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T6 T8 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T6 T8 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T6 T8 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T6 T8 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T30 T47 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T6 T8 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T6,T8

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T6,T8

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T6,T8,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T8
1	0	Covered	T4,T5,T1
1	1	Covered	T3,T6,T8

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T8,T11
0	1	Covered	T47,T189,T190
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T8,T11
1	-	Covered	T47,T189,T190

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T6,T8
DetectSt	168	Covered	T6,T8,T11
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T6,T8,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T8,T11
DebounceSt->IdleSt	163	Covered	T3,T243
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T6,T8,T11
IdleSt->DebounceSt	148	Covered	T3,T6,T8
StableSt->IdleSt	206	Covered	T11,T51,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T6,T8
0	1	Covered	T3,T6,T8
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T8,T11
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T6,T8
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T8,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T243
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T6,T8
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T6,T8,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T30,T47
StableSt	-	-	-	-	-	-	0	Covered	T6,T8,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	60	0	0
CntIncr_A	6968781	61084	0	0
CntNoWrap_A	6968781	6510237	0	0
DetectStDropOut_A	6968781	0	0	0
DetectedOut_A	6968781	71284	0	0
DetectedPulseOut_A	6968781	29	0	0
DisabledIdleSt_A	6968781	6178740	0	0
DisabledNoDetection_A	6968781	6180530	0	0
EnterDebounceSt_A	6968781	31	0	0
EnterDetectSt_A	6968781	29	0	0
EnterStableSt_A	6968781	29	0	0
PulseIsPulse_A	6968781	29	0	0
StayInStableSt	6968781	71240	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6968781	4785	0	0
gen_low_level_sva.LowLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	60	0	0
T3	813	1	0	0
T6	848	2	0	0
T7	480	0	0	0
T8	548	2	0	0
T11	0	2	0	0
T12	0	2	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	2	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T51	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	61084	0	0
T3	813	42	0	0
T6	848	83	0	0
T7	480	0	0	0
T8	548	94	0	0
T11	0	19	0	0
T12	0	20	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	26	0	0
T46	0	46	0	0
T47	0	30	0	0
T48	0	30	0	0
T51	0	26	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510237	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	71284	0	0
T6	848	46	0	0
T7	480	0	0	0
T8	548	42	0	0
T9	2031	0	0	0
T11	0	16	0	0
T12	0	43	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	9	0	0
T46	0	192	0	0
T47	0	71	0	0
T48	0	143	0	0
T51	0	45	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	40	0	0
T202	409	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	29	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	1	0	0
T9	2031	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T202	409	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6178740	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6180530	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	31	0	0
T3	813	1	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	1	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	29	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	1	0	0
T9	2031	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T202	409	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	29	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	1	0	0
T9	2031	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T202	409	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	29	0	0
T6	848	1	0	0
T7	480	0	0	0
T8	548	1	0	0
T9	2031	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T46	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	1	0	0
T202	409	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	71240	0	0
T6	848	44	0	0
T7	480	0	0	0
T8	548	40	0	0
T9	2031	0	0	0
T11	0	15	0	0
T12	0	41	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	8	0	0
T46	0	190	0	0
T47	0	70	0	0
T48	0	141	0	0
T51	0	43	0	0
T66	620	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T169	0	38	0	0
T202	409	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	4785	0	0
T1	522	1	0	0
T2	2225	0	0	0
T3	0	1	0	0
T4	496	10	0	0
T5	423	1	0	0
T13	499	10	0	0
T14	405	0	0	0
T15	652	0	0	0
T16	408	0	0	0
T17	524	4	0	0
T18	446	1	0	0
T19	0	3	0	0
T20	0	2	0	0
T27	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	12	0	0
T31	8960	0	0	0
T47	712	1	0	0
T101	0	1	0	0
T135	717	0	0	0
T168	630	0	0	0
T175	0	1	0	0
T188	0	1	0	0
T189	0	1	0	0
T190	0	1	0	0
T203	0	1	0	0
T204	0	2	0	0
T210	0	1	0	0
T216	872	0	0	0
T217	501	0	0	0
T218	405	0	0	0
T219	917	0	0	0
T220	494	0	0	0
T221	418	0	0	0
T252	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T13 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T13 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T11 T51 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T13 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T13 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T13 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T13 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T13 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T13 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T13 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T13 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T11 T51 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T11 T51 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T11 T51 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T11 T51 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T11 T51 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T11 T51 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T11 T51 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T11 T49 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T51 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T11 T49 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T11 T49 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T11 T49 
186        1/1                    state_d = IdleSt;
           Tests:       T180 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T180 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T11 T49 
191        1/1                      state_d = StableSt;
           Tests:       T8 T11 T49 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T11 T49 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T11 T49 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T11 T49 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T11 T49 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T30 T48 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T11 T49 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T4,T5,T13

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T1
1	0	Covered	T4,T5,T13
1	1	Covered	T4,T5,T13

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T51

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T8,T11,T51

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T8,T11,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T11,T51
1	0	Covered	T4,T5,T13
1	1	Covered	T8,T11,T51

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T49
0	1	Covered	T180
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T11,T49
0	1	Covered	T48,T47,T182
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T11,T49
1	-	Covered	T48,T47,T182

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T11,T51
DetectSt	168	Covered	T8,T11,T49
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T8,T11,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T11,T49
DebounceSt->IdleSt	163	Covered	T51,T101
DetectSt->IdleSt	186	Covered	T180
DetectSt->StableSt	191	Covered	T8,T11,T49
IdleSt->DebounceSt	148	Covered	T8,T11,T51
StableSt->IdleSt	206	Covered	T11,T30,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T11,T51
0	1	Covered	T8,T11,T51
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T11,T49
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T11,T51
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T13
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T11,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T51
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T11,T51
DetectSt	-	-	-	-	1	-	-	Covered	T180
DetectSt	-	-	-	-	0	1	-	Covered	T8,T11,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T30,T48
StableSt	-	-	-	-	-	-	0	Covered	T8,T11,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	69	0	0
CntIncr_A	6968781	181573	0	0
CntNoWrap_A	6968781	6510228	0	0
DetectStDropOut_A	6968781	1	0	0
DetectedOut_A	6968781	164303	0	0
DetectedPulseOut_A	6968781	33	0	0
DisabledIdleSt_A	6968781	5993459	0	0
DisabledNoDetection_A	6968781	5995254	0	0
EnterDebounceSt_A	6968781	36	0	0
EnterDetectSt_A	6968781	34	0	0
EnterStableSt_A	6968781	33	0	0
PulseIsPulse_A	6968781	33	0	0
StayInStableSt	6968781	164254	0	0
gen_high_level_sva.HighLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	69	0	0
T8	548	2	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	2	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	2	0	0
T47	0	4	0	0
T48	0	2	0	0
T49	0	2	0	0
T51	0	1	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T167	0	2	0	0
T182	0	2	0	0
T194	0	2	0	0
T202	409	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	181573	0	0
T8	548	94	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	19	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	26	0	0
T47	0	60	0	0
T48	0	30	0	0
T49	0	70	0	0
T51	0	26	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T167	0	83	0	0
T182	0	30	0	0
T194	0	98	0	0
T202	409	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510228	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1	0	0
T114	5470	0	0	0
T180	471	1	0	0
T192	2933	0	0	0
T253	23868	0	0	0
T254	25794	0	0	0
T255	1487	0	0	0
T256	689	0	0	0
T257	13215	0	0	0
T258	433	0	0	0
T259	1453	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	164303	0	0
T8	548	44	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	14	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	9	0	0
T47	0	111	0	0
T48	0	18	0	0
T49	0	170	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T167	0	41	0	0
T169	0	182	0	0
T182	0	99	0	0
T194	0	39	0	0
T202	409	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	33	0	0
T8	548	1	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T167	0	1	0	0
T169	0	1	0	0
T182	0	1	0	0
T194	0	1	0	0
T202	409	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5993459	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5995254	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	36	0	0
T8	548	1	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T167	0	1	0	0
T182	0	1	0	0
T194	0	1	0	0
T202	409	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	34	0	0
T8	548	1	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T167	0	1	0	0
T169	0	1	0	0
T182	0	1	0	0
T194	0	1	0	0
T202	409	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	33	0	0
T8	548	1	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T167	0	1	0	0
T169	0	1	0	0
T182	0	1	0	0
T194	0	1	0	0
T202	409	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	33	0	0
T8	548	1	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	1	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0
T49	0	1	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T167	0	1	0	0
T169	0	1	0	0
T182	0	1	0	0
T194	0	1	0	0
T202	409	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	164254	0	0
T8	548	42	0	0
T9	2031	0	0	0
T10	501	0	0	0
T11	0	13	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	8	0	0
T47	0	108	0	0
T48	0	17	0	0
T49	0	168	0	0
T66	620	0	0	0
T76	502	0	0	0
T77	522	0	0	0
T81	403	0	0	0
T167	0	39	0	0
T169	0	180	0	0
T182	0	98	0	0
T194	0	37	0	0
T202	409	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	15	0	0
T47	0	1	0	0
T48	3509	1	0	0
T166	0	1	0	0
T176	0	1	0	0
T182	0	1	0	0
T187	0	1	0	0
T190	0	1	0	0
T192	0	1	0	0
T194	705	0	0	0
T210	0	1	0	0
T244	548	0	0	0
T245	507	0	0	0
T246	424	0	0	0
T247	566	0	0	0
T248	1341	0	0	0
T249	491	0	0	0
T250	751	0	0	0
T251	402	0	0	0
T260	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T13 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T1 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T1 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T1 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T1 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T11 T12 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T18 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T18 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T1 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T1 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T1 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T1 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T1 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T1 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T1 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T1 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T1 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T1 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T11 T12 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T11 T12 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T11 T12 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T11 T12 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T11 T12 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T11 T12 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T11 T12 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T11 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T192 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T11 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T11 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T11 T12 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T11 T12 
191        1/1                      state_d = StableSt;
           Tests:       T3 T11 T12 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T11 T12 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T11 T12 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T11 T12 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T11 T12 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T11 T12 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T11 T12 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T1 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T1 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T1 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T13
1	Covered	T4,T5,T1

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T13
1	0	Covered	T4,T5,T1
1	1	Covered	T4,T5,T1

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T1	VC_COV_UNR
1	Covered	T3,T11,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T3,T11,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T8,T11
1	0	Covered	T4,T5,T13
1	1	Covered	T3,T11,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T11,T12
0	1	Covered	T3,T12,T47
1	0	Covered	T11,T30

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T11,T12
1	-	Covered	T3,T12,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T11,T12
DetectSt	168	Covered	T3,T11,T12
IdleSt	163	Covered	T4,T5,T1
StableSt	191	Covered	T3,T11,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T11,T12
DebounceSt->IdleSt	163	Covered	T172,T192
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T11,T12
IdleSt->DebounceSt	148	Covered	T3,T11,T12
StableSt->IdleSt	206	Covered	T3,T11,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T3,T11,T12
0	1	Covered	T3,T11,T12
0	0	Excluded	T4,T5,T1	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T11,T12
0	Covered	T4,T5,T1

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T11,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T1
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T11,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T192
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T11,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T11,T12
StableSt	-	-	-	-	-	-	0	Covered	T3,T11,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T1
0	Covered	T4,T5,T1

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6968781	53	0	0
CntIncr_A	6968781	113602	0	0
CntNoWrap_A	6968781	6510244	0	0
DetectStDropOut_A	6968781	0	0	0
DetectedOut_A	6968781	1811	0	0
DetectedPulseOut_A	6968781	26	0	0
DisabledIdleSt_A	6968781	5957602	0	0
DisabledNoDetection_A	6968781	5959395	0	0
EnterDebounceSt_A	6968781	28	0	0
EnterDetectSt_A	6968781	26	0	0
EnterStableSt_A	6968781	26	0	0
PulseIsPulse_A	6968781	26	0	0
StayInStableSt	6968781	1768	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6968781	5336	0	0
gen_low_level_sva.LowLevelEvent_A	6968781	6512128	0	0
gen_not_sticky_sva.StableStDropOut_A	6968781	7	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	53	0	0
T3	813	4	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	2	0	0
T12	0	2	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	2	0	0
T45	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T190	0	2	0	0
T203	0	2	0	0
T210	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	113602	0	0
T3	813	84	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	19	0	0
T12	0	20	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	26	0	0
T45	0	37	0	0
T47	0	30	0	0
T48	0	30	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T190	0	88	0	0
T203	0	52	0	0
T210	0	95	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6510244	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1811	0	0
T3	813	83	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	16	0	0
T12	0	43	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	10	0	0
T45	0	44	0	0
T47	0	54	0	0
T48	0	266	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T190	0	55	0	0
T203	0	47	0	0
T210	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	26	0	0
T3	813	2	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T190	0	1	0	0
T203	0	1	0	0
T210	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5957602	0	0
T1	522	121	0	0
T2	2225	1824	0	0
T4	496	95	0	0
T5	423	22	0	0
T13	499	98	0	0
T14	405	4	0	0
T15	652	251	0	0
T16	408	7	0	0
T17	524	123	0	0
T18	446	45	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5959395	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	28	0	0
T3	813	2	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T190	0	1	0	0
T203	0	1	0	0
T210	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	26	0	0
T3	813	2	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T190	0	1	0	0
T203	0	1	0	0
T210	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	26	0	0
T3	813	2	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T190	0	1	0	0
T203	0	1	0	0
T210	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	26	0	0
T3	813	2	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	1	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	1	0	0
T45	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T190	0	1	0	0
T203	0	1	0	0
T210	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	1768	0	0
T3	813	80	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T11	0	15	0	0
T12	0	42	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T30	0	9	0	0
T45	0	42	0	0
T47	0	53	0	0
T48	0	264	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T190	0	54	0	0
T203	0	45	0	0
T210	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	5336	0	0
T1	522	0	0	0
T2	2225	10	0	0
T3	0	2	0	0
T4	496	8	0	0
T5	423	2	0	0
T13	499	6	0	0
T14	405	0	0	0
T15	652	3	0	0
T16	408	0	0	0
T17	524	5	0	0
T18	446	0	0	0
T19	0	2	0	0
T20	0	2	0	0
T27	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	6512128	0	0
T1	522	122	0	0
T2	2225	1825	0	0
T4	496	96	0	0
T5	423	23	0	0
T13	499	99	0	0
T14	405	5	0	0
T15	652	252	0	0
T16	408	8	0	0
T17	524	124	0	0
T18	446	46	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6968781	7	0	0
T3	813	1	0	0
T6	848	0	0	0
T7	480	0	0	0
T8	548	0	0	0
T12	0	1	0	0
T24	854	0	0	0
T26	496	0	0	0
T29	468	0	0	0
T47	0	1	0	0
T62	426	0	0	0
T80	434	0	0	0
T81	403	0	0	0
T175	0	1	0	0
T190	0	1	0	0
T243	0	1	0	0
T261	0	1	0	0