Unified Coverage Report :: Module :: sysrst_ctrl_autoblock

Module : sysrst_ctrl_autoblock

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Source File(s) :
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/sim-vcs/../src/lowrisc_ip_sysrst_ctrl_1.0/rtl/sysrst_ctrl_autoblock.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.u_sysrst_ctrl_autoblock	100.00	100.00	100.00			100.00

---

Module Instance : tb.dut.u_sysrst_ctrl_autoblock

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00			100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.44	100.00	97.22		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
99.02	100.00	96.08	100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_sysrst_ctrl_detect	99.05	100.00	95.24		100.00	100.00	100.00

---

Since this is the module's only instance, the coverage report is the same as for the module.

Line Coverage for Module : sysrst_ctrl_autoblock

	Line No.	Total	Covered	Percent
TOTAL		4	4	100.00
CONT_ASSIGN	50	1	1	100.00
CONT_ASSIGN	51	1	1	100.00
CONT_ASSIGN	53	1	1	100.00
CONT_ASSIGN	55	1	1	100.00

49                      
50         1/1            assign pwrb_out_hw_o = pwrb_int_i;
           Tests:       T4 T5 T13 
51         1/1            assign key0_out_hw_o = (aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q) ?
           Tests:       T4 T5 T1 
52                                               aon_auto_block_out_ctl_i.key0_out_value.q : key0_int_i;
53         1/1            assign key1_out_hw_o = (aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q) ?
           Tests:       T4 T5 T1 
54                                               aon_auto_block_out_ctl_i.key1_out_value.q : key1_int_i;
55         1/1            assign key2_out_hw_o = (aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q) ?
           Tests:       T4 T5 T1 

---

Cond Coverage for Module : sysrst_ctrl_autoblock

	Total	Covered	Percent
Conditions	15	15	100.00
Logical	15	15	100.00
Non-Logical	0	0
Event	0	0

 LINE       51
 EXPRESSION ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q) ? aon_auto_block_out_ctl_i.key0_out_value.q : key0_int_i)
             -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T11,T52

 LINE       51
 SUB-EXPRESSION (aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q)
                 -------1-------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T11,T52
1	0	Covered	T15,T28,T52
1	1	Covered	T15,T11,T52

 LINE       53
 EXPRESSION ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q) ? aon_auto_block_out_ctl_i.key1_out_value.q : key1_int_i)
             -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T52,T55,T58

 LINE       53
 SUB-EXPRESSION (aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q)
                 -------1-------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T28,T52,T55
1	0	Covered	T15,T11,T28
1	1	Covered	T52,T55,T58

 LINE       55
 EXPRESSION ((aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q) ? aon_auto_block_out_ctl_i.key2_out_value.q : key2_int_i)
             -----------------------------1-----------------------------

-1-	Status	Tests
0	Covered	T4,T5,T1
1	Covered	T15,T28,T52

 LINE       55
 SUB-EXPRESSION (aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q)
                 -------1-------   -------------------2-------------------

-1-	-2-	Status	Tests
0	1	Covered	T15,T28,T52
1	0	Covered	T15,T11,T52
1	1	Covered	T15,T28,T52

---

Branch Coverage for Module : sysrst_ctrl_autoblock

	Line No.	Total	Covered	Percent
Branches		6	6	100.00
TERNARY	51	2	2	100.00
TERNARY	53	2	2	100.00
TERNARY	55	2	2	100.00

51           assign key0_out_hw_o = (aon_ab_cond_met & aon_auto_block_out_ctl_i.key0_out_sel.q) ?
                                                                                                -1-  
                                                                                                ==>  
                                                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T15,T11,T52
0	Covered	T4,T5,T1

53           assign key1_out_hw_o = (aon_ab_cond_met & aon_auto_block_out_ctl_i.key1_out_sel.q) ?
                                                                                                -1-  
                                                                                                ==>  
                                                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T52,T55,T58
0	Covered	T4,T5,T1

55           assign key2_out_hw_o = (aon_ab_cond_met & aon_auto_block_out_ctl_i.key2_out_sel.q) ?
                                                                                                -1-  
                                                                                                ==>  
                                                                                                ==>  

Branches:

-1-	Status	Tests
1	Covered	T15,T28,T52
0	Covered	T4,T5,T1