| T86 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1818458064 |
|
|
Aug 25 06:33:15 AM UTC 24 |
Aug 25 06:34:24 AM UTC 24 |
122432365850 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.4049623594 |
|
|
Aug 25 06:34:12 AM UTC 24 |
Aug 25 06:34:27 AM UTC 24 |
2447421507 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1652600675 |
|
|
Aug 25 06:34:14 AM UTC 24 |
Aug 25 06:34:28 AM UTC 24 |
4099693957 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.2659919809 |
|
|
Aug 25 06:34:25 AM UTC 24 |
Aug 25 06:34:29 AM UTC 24 |
2030282885 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1261387142 |
|
|
Aug 25 06:34:16 AM UTC 24 |
Aug 25 06:34:30 AM UTC 24 |
7749767676 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1705103295 |
|
|
Aug 25 06:34:27 AM UTC 24 |
Aug 25 06:34:31 AM UTC 24 |
2169190396 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.78650786 |
|
|
Aug 25 06:33:11 AM UTC 24 |
Aug 25 06:34:32 AM UTC 24 |
608239414640 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.2583970152 |
|
|
Aug 25 06:34:27 AM UTC 24 |
Aug 25 06:34:32 AM UTC 24 |
2492546103 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3611009092 |
|
|
Aug 25 06:34:16 AM UTC 24 |
Aug 25 06:34:32 AM UTC 24 |
3230779929 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.1295387448 |
|
|
Aug 25 06:34:30 AM UTC 24 |
Aug 25 06:34:35 AM UTC 24 |
2537728684 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.1279847396 |
|
|
Aug 25 06:34:18 AM UTC 24 |
Aug 25 06:34:35 AM UTC 24 |
5212341287 ps |
| T92 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.229021589 |
|
|
Aug 25 06:33:37 AM UTC 24 |
Aug 25 06:34:35 AM UTC 24 |
14307674389 ps |
| T87 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1611794366 |
|
|
Aug 25 06:30:29 AM UTC 24 |
Aug 25 06:34:37 AM UTC 24 |
89709623917 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.326793824 |
|
|
Aug 25 06:34:33 AM UTC 24 |
Aug 25 06:34:37 AM UTC 24 |
2796567189 ps |
| T93 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.342512842 |
|
|
Aug 25 06:34:33 AM UTC 24 |
Aug 25 06:34:38 AM UTC 24 |
2695882453 ps |
| T129 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.2171909024 |
|
|
Aug 25 06:34:38 AM UTC 24 |
Aug 25 06:34:40 AM UTC 24 |
2168847953 ps |
| T130 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.379694896 |
|
|
Aug 25 06:34:32 AM UTC 24 |
Aug 25 06:34:41 AM UTC 24 |
3097407997 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.939193075 |
|
|
Aug 25 06:34:28 AM UTC 24 |
Aug 25 06:34:42 AM UTC 24 |
2143830258 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.653110475 |
|
|
Aug 25 06:34:39 AM UTC 24 |
Aug 25 06:34:43 AM UTC 24 |
2473293856 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.25157334 |
|
|
Aug 25 06:34:31 AM UTC 24 |
Aug 25 06:34:44 AM UTC 24 |
2612654215 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.1128222015 |
|
|
Aug 25 06:34:42 AM UTC 24 |
Aug 25 06:34:47 AM UTC 24 |
2524496714 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1259581607 |
|
|
Aug 25 06:34:43 AM UTC 24 |
Aug 25 06:34:48 AM UTC 24 |
2630469352 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.669095853 |
|
|
Aug 25 06:33:47 AM UTC 24 |
Aug 25 06:34:49 AM UTC 24 |
27319148009 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.2369951560 |
|
|
Aug 25 06:34:38 AM UTC 24 |
Aug 25 06:34:49 AM UTC 24 |
2011471461 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1257806369 |
|
|
Aug 25 06:34:44 AM UTC 24 |
Aug 25 06:34:51 AM UTC 24 |
3411365836 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.307235351 |
|
|
Aug 25 06:34:44 AM UTC 24 |
Aug 25 06:34:52 AM UTC 24 |
2953891371 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1417511813 |
|
|
Aug 25 06:34:41 AM UTC 24 |
Aug 25 06:34:53 AM UTC 24 |
2078322802 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2467274214 |
|
|
Aug 25 06:34:31 AM UTC 24 |
Aug 25 06:34:53 AM UTC 24 |
4046902098 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1697309617 |
|
|
Aug 25 06:31:11 AM UTC 24 |
Aug 25 06:34:55 AM UTC 24 |
46701800763 ps |
| T106 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.3326473772 |
|
|
Aug 25 06:33:13 AM UTC 24 |
Aug 25 06:34:56 AM UTC 24 |
54893176415 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.2822967325 |
|
|
Aug 25 06:34:53 AM UTC 24 |
Aug 25 06:34:57 AM UTC 24 |
2037644097 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.2724217387 |
|
|
Aug 25 06:34:53 AM UTC 24 |
Aug 25 06:34:57 AM UTC 24 |
9005691469 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.1604770531 |
|
|
Aug 25 06:34:54 AM UTC 24 |
Aug 25 06:34:58 AM UTC 24 |
2134980297 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.3804827320 |
|
|
Aug 25 06:34:05 AM UTC 24 |
Aug 25 06:35:00 AM UTC 24 |
10064821683 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2278271452 |
|
|
Aug 25 06:34:52 AM UTC 24 |
Aug 25 06:35:01 AM UTC 24 |
11852807728 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.331179194 |
|
|
Aug 25 06:34:58 AM UTC 24 |
Aug 25 06:35:02 AM UTC 24 |
2547884064 ps |
| T101 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1356926958 |
|
|
Aug 25 06:34:35 AM UTC 24 |
Aug 25 06:35:03 AM UTC 24 |
25770297985 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.79366166 |
|
|
Aug 25 06:34:56 AM UTC 24 |
Aug 25 06:35:03 AM UTC 24 |
2466935349 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3309794843 |
|
|
Aug 25 06:35:00 AM UTC 24 |
Aug 25 06:35:06 AM UTC 24 |
4348985802 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3944354536 |
|
|
Aug 25 06:34:59 AM UTC 24 |
Aug 25 06:35:06 AM UTC 24 |
2618916552 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.2651796330 |
|
|
Aug 25 06:34:50 AM UTC 24 |
Aug 25 06:35:07 AM UTC 24 |
6360911665 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.1521817195 |
|
|
Aug 25 06:34:56 AM UTC 24 |
Aug 25 06:35:07 AM UTC 24 |
2027592149 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.4020260314 |
|
|
Aug 25 06:35:04 AM UTC 24 |
Aug 25 06:35:11 AM UTC 24 |
3853564415 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.2846357501 |
|
|
Aug 25 06:35:08 AM UTC 24 |
Aug 25 06:35:11 AM UTC 24 |
2038861222 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2665330127 |
|
|
Aug 25 06:35:08 AM UTC 24 |
Aug 25 06:35:12 AM UTC 24 |
2131346715 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.459194176 |
|
|
Aug 25 06:34:23 AM UTC 24 |
Aug 25 06:35:13 AM UTC 24 |
2364665954549 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.3534528436 |
|
|
Aug 25 06:31:29 AM UTC 24 |
Aug 25 06:35:13 AM UTC 24 |
197081342120 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2922598988 |
|
|
Aug 25 06:35:04 AM UTC 24 |
Aug 25 06:35:13 AM UTC 24 |
4590458388 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3686799382 |
|
|
Aug 25 06:34:24 AM UTC 24 |
Aug 25 06:35:14 AM UTC 24 |
183610814332 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.1437573437 |
|
|
Aug 25 06:35:03 AM UTC 24 |
Aug 25 06:35:16 AM UTC 24 |
3946569490 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.2113677255 |
|
|
Aug 25 06:35:12 AM UTC 24 |
Aug 25 06:35:16 AM UTC 24 |
2523274103 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3838061935 |
|
|
Aug 25 06:35:13 AM UTC 24 |
Aug 25 06:35:17 AM UTC 24 |
3618592503 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3736016479 |
|
|
Aug 25 06:31:47 AM UTC 24 |
Aug 25 06:35:18 AM UTC 24 |
41415303275 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.590759470 |
|
|
Aug 25 06:35:08 AM UTC 24 |
Aug 25 06:35:19 AM UTC 24 |
2466869880 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.1432248566 |
|
|
Aug 25 06:35:08 AM UTC 24 |
Aug 25 06:35:19 AM UTC 24 |
2047450304 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1595781185 |
|
|
Aug 25 06:35:14 AM UTC 24 |
Aug 25 06:35:21 AM UTC 24 |
12943723033 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.1928935976 |
|
|
Aug 25 06:35:19 AM UTC 24 |
Aug 25 06:35:22 AM UTC 24 |
2146892823 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.1643488492 |
|
|
Aug 25 06:35:20 AM UTC 24 |
Aug 25 06:35:24 AM UTC 24 |
2230463057 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.3324020787 |
|
|
Aug 25 06:35:18 AM UTC 24 |
Aug 25 06:35:24 AM UTC 24 |
2026517058 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2570635010 |
|
|
Aug 25 06:33:34 AM UTC 24 |
Aug 25 06:35:25 AM UTC 24 |
26270133646 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.211698487 |
|
|
Aug 25 06:35:13 AM UTC 24 |
Aug 25 06:35:26 AM UTC 24 |
2689615607 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1329124846 |
|
|
Aug 25 06:35:12 AM UTC 24 |
Aug 25 06:35:27 AM UTC 24 |
2612282604 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.363922466 |
|
|
Aug 25 06:35:20 AM UTC 24 |
Aug 25 06:35:28 AM UTC 24 |
2462967632 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2631938308 |
|
|
Aug 25 06:35:17 AM UTC 24 |
Aug 25 06:35:30 AM UTC 24 |
5618494900 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1978721937 |
|
|
Aug 25 06:35:24 AM UTC 24 |
Aug 25 06:35:31 AM UTC 24 |
4025382771 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.2889950861 |
|
|
Aug 25 06:35:14 AM UTC 24 |
Aug 25 06:35:31 AM UTC 24 |
5999075301 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.132564983 |
|
|
Aug 25 06:35:06 AM UTC 24 |
Aug 25 06:35:34 AM UTC 24 |
12532184827 ps |
| T205 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1284536098 |
|
|
Aug 25 06:35:18 AM UTC 24 |
Aug 25 06:35:34 AM UTC 24 |
12062282476 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3354299161 |
|
|
Aug 25 06:34:20 AM UTC 24 |
Aug 25 06:35:35 AM UTC 24 |
57644750655 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.3669128580 |
|
|
Aug 25 06:35:22 AM UTC 24 |
Aug 25 06:35:36 AM UTC 24 |
2512586243 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.118548136 |
|
|
Aug 25 06:35:23 AM UTC 24 |
Aug 25 06:35:37 AM UTC 24 |
2611363464 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.4232433642 |
|
|
Aug 25 06:35:35 AM UTC 24 |
Aug 25 06:35:38 AM UTC 24 |
2066005360 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1639094450 |
|
|
Aug 25 06:35:25 AM UTC 24 |
Aug 25 06:35:40 AM UTC 24 |
3131667192 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.3149684914 |
|
|
Aug 25 06:35:35 AM UTC 24 |
Aug 25 06:35:40 AM UTC 24 |
2528981635 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.2944430277 |
|
|
Aug 25 06:35:35 AM UTC 24 |
Aug 25 06:35:40 AM UTC 24 |
2472175145 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.696150571 |
|
|
Aug 25 06:35:26 AM UTC 24 |
Aug 25 06:35:41 AM UTC 24 |
4305579426 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3987962524 |
|
|
Aug 25 06:35:29 AM UTC 24 |
Aug 25 06:35:42 AM UTC 24 |
2835573536 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2821977429 |
|
|
Aug 25 06:35:37 AM UTC 24 |
Aug 25 06:35:43 AM UTC 24 |
3400034370 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3263462046 |
|
|
Aug 25 06:32:55 AM UTC 24 |
Aug 25 06:35:44 AM UTC 24 |
82781335416 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.4022828706 |
|
|
Aug 25 06:35:32 AM UTC 24 |
Aug 25 06:35:44 AM UTC 24 |
2009566185 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.3640039140 |
|
|
Aug 25 06:33:26 AM UTC 24 |
Aug 25 06:35:44 AM UTC 24 |
122165753601 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.2718010750 |
|
|
Aug 25 06:35:35 AM UTC 24 |
Aug 25 06:35:46 AM UTC 24 |
2113250818 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.2334564620 |
|
|
Aug 25 06:35:42 AM UTC 24 |
Aug 25 06:35:47 AM UTC 24 |
6336265595 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.1590228961 |
|
|
Aug 25 06:35:43 AM UTC 24 |
Aug 25 06:35:47 AM UTC 24 |
2135274665 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.967510636 |
|
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Aug 25 06:35:36 AM UTC 24 |
Aug 25 06:35:50 AM UTC 24 |
2716991197 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.2037087551 |
|
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Aug 25 06:35:36 AM UTC 24 |
Aug 25 06:35:50 AM UTC 24 |
2613189785 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1148980671 |
|
|
Aug 25 06:35:47 AM UTC 24 |
Aug 25 06:35:52 AM UTC 24 |
2634093626 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.2998073474 |
|
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Aug 25 06:31:10 AM UTC 24 |
Aug 25 06:35:52 AM UTC 24 |
73950284489 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.707788387 |
|
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Aug 25 06:35:43 AM UTC 24 |
Aug 25 06:35:53 AM UTC 24 |
2011000810 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.954175415 |
|
|
Aug 25 06:35:41 AM UTC 24 |
Aug 25 06:35:56 AM UTC 24 |
4346485288 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1220717667 |
|
|
Aug 25 06:35:45 AM UTC 24 |
Aug 25 06:35:56 AM UTC 24 |
2158643718 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2888814963 |
|
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Aug 25 06:35:48 AM UTC 24 |
Aug 25 06:35:58 AM UTC 24 |
2989450269 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.687847096 |
|
|
Aug 25 06:35:45 AM UTC 24 |
Aug 25 06:35:59 AM UTC 24 |
2508210138 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.121308016 |
|
|
Aug 25 06:35:44 AM UTC 24 |
Aug 25 06:35:59 AM UTC 24 |
2450487844 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2122658264 |
|
|
Aug 25 06:35:41 AM UTC 24 |
Aug 25 06:36:00 AM UTC 24 |
190868229764 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.1642746697 |
|
|
Aug 25 06:35:58 AM UTC 24 |
Aug 25 06:36:03 AM UTC 24 |
2034839044 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.340048720 |
|
|
Aug 25 06:35:51 AM UTC 24 |
Aug 25 06:36:04 AM UTC 24 |
6312117293 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.3859383166 |
|
|
Aug 25 06:36:00 AM UTC 24 |
Aug 25 06:36:04 AM UTC 24 |
2531642228 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.2827091570 |
|
|
Aug 25 06:36:00 AM UTC 24 |
Aug 25 06:36:05 AM UTC 24 |
2117627739 ps |
| T97 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.411307716 |
|
|
Aug 25 06:33:28 AM UTC 24 |
Aug 25 06:36:06 AM UTC 24 |
69087690015 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.840609675 |
|
|
Aug 25 06:35:52 AM UTC 24 |
Aug 25 06:36:06 AM UTC 24 |
5514229402 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2265160695 |
|
|
Aug 25 06:35:31 AM UTC 24 |
Aug 25 06:36:07 AM UTC 24 |
13595652772 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.1786186857 |
|
|
Aug 25 06:36:05 AM UTC 24 |
Aug 25 06:36:15 AM UTC 24 |
3614145703 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.3295476933 |
|
|
Aug 25 06:35:59 AM UTC 24 |
Aug 25 06:36:07 AM UTC 24 |
2468839461 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.785632544 |
|
|
Aug 25 06:36:01 AM UTC 24 |
Aug 25 06:36:07 AM UTC 24 |
2618754139 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.4138312827 |
|
|
Aug 25 06:35:48 AM UTC 24 |
Aug 25 06:36:08 AM UTC 24 |
3214293633 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2193606154 |
|
|
Aug 25 06:36:03 AM UTC 24 |
Aug 25 06:36:08 AM UTC 24 |
2617153585 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.2581289385 |
|
|
Aug 25 06:35:59 AM UTC 24 |
Aug 25 06:36:11 AM UTC 24 |
2114810830 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1254251502 |
|
|
Aug 25 06:35:54 AM UTC 24 |
Aug 25 06:36:13 AM UTC 24 |
4980134502 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2869584959 |
|
|
Aug 25 06:36:05 AM UTC 24 |
Aug 25 06:36:13 AM UTC 24 |
5525789491 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.2361830419 |
|
|
Aug 25 06:36:08 AM UTC 24 |
Aug 25 06:36:13 AM UTC 24 |
2043508703 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.1839065213 |
|
|
Aug 25 06:36:08 AM UTC 24 |
Aug 25 06:36:13 AM UTC 24 |
2130951169 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.3336811529 |
|
|
Aug 25 06:35:31 AM UTC 24 |
Aug 25 06:36:17 AM UTC 24 |
49538216514 ps |
| T108 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1884150077 |
|
|
Aug 25 06:35:04 AM UTC 24 |
Aug 25 06:36:17 AM UTC 24 |
29839089910 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.18241130 |
|
|
Aug 25 06:36:14 AM UTC 24 |
Aug 25 06:36:18 AM UTC 24 |
2650413769 ps |
| T95 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.162748133 |
|
|
Aug 25 06:35:37 AM UTC 24 |
Aug 25 06:36:18 AM UTC 24 |
544989642817 ps |
| T109 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3273060954 |
|
|
Aug 25 06:35:15 AM UTC 24 |
Aug 25 06:36:18 AM UTC 24 |
25089065813 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.2099157822 |
|
|
Aug 25 06:36:14 AM UTC 24 |
Aug 25 06:36:19 AM UTC 24 |
2529417263 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3849703797 |
|
|
Aug 25 06:36:14 AM UTC 24 |
Aug 25 06:36:19 AM UTC 24 |
2679659117 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2826080542 |
|
|
Aug 25 06:36:12 AM UTC 24 |
Aug 25 06:36:19 AM UTC 24 |
2224459198 ps |
| T326 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1750716580 |
|
|
Aug 25 06:36:08 AM UTC 24 |
Aug 25 06:36:21 AM UTC 24 |
4190810965 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.417091102 |
|
|
Aug 25 06:36:09 AM UTC 24 |
Aug 25 06:36:22 AM UTC 24 |
2471436706 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.526660056 |
|
|
Aug 25 06:36:18 AM UTC 24 |
Aug 25 06:36:23 AM UTC 24 |
2468448366 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.2536436436 |
|
|
Aug 25 06:36:20 AM UTC 24 |
Aug 25 06:36:23 AM UTC 24 |
2148912213 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1774705035 |
|
|
Aug 25 06:36:22 AM UTC 24 |
Aug 25 06:36:27 AM UTC 24 |
2254565003 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.3176926282 |
|
|
Aug 25 06:36:23 AM UTC 24 |
Aug 25 06:36:27 AM UTC 24 |
2562177603 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.3491092647 |
|
|
Aug 25 06:36:20 AM UTC 24 |
Aug 25 06:36:27 AM UTC 24 |
2016482964 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.54313029 |
|
|
Aug 25 06:36:16 AM UTC 24 |
Aug 25 06:36:27 AM UTC 24 |
6166007760 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2653455680 |
|
|
Aug 25 06:36:23 AM UTC 24 |
Aug 25 06:36:27 AM UTC 24 |
2629706271 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2523117632 |
|
|
Aug 25 06:33:35 AM UTC 24 |
Aug 25 06:36:27 AM UTC 24 |
131669995219 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.2029689437 |
|
|
Aug 25 06:36:20 AM UTC 24 |
Aug 25 06:36:28 AM UTC 24 |
2458571860 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1538802783 |
|
|
Aug 25 06:36:18 AM UTC 24 |
Aug 25 06:36:29 AM UTC 24 |
27352085532 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1957418504 |
|
|
Aug 25 06:36:28 AM UTC 24 |
Aug 25 06:36:33 AM UTC 24 |
2663451641 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.2674841603 |
|
|
Aug 25 06:36:29 AM UTC 24 |
Aug 25 06:36:34 AM UTC 24 |
2132391592 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.4013481027 |
|
|
Aug 25 06:36:29 AM UTC 24 |
Aug 25 06:36:37 AM UTC 24 |
2018420924 ps |
| T351 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3987783505 |
|
|
Aug 25 06:35:51 AM UTC 24 |
Aug 25 06:36:37 AM UTC 24 |
59536006624 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.243012323 |
|
|
Aug 25 06:36:25 AM UTC 24 |
Aug 25 06:36:39 AM UTC 24 |
3089560533 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.2513209114 |
|
|
Aug 25 06:36:35 AM UTC 24 |
Aug 25 06:36:39 AM UTC 24 |
2131813591 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.3038894591 |
|
|
Aug 25 06:36:34 AM UTC 24 |
Aug 25 06:36:42 AM UTC 24 |
2441520445 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.2334732987 |
|
|
Aug 25 06:36:37 AM UTC 24 |
Aug 25 06:36:43 AM UTC 24 |
2522260403 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2317387020 |
|
|
Aug 25 06:36:38 AM UTC 24 |
Aug 25 06:36:43 AM UTC 24 |
3870540747 ps |
| T328 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2543052314 |
|
|
Aug 25 06:36:28 AM UTC 24 |
Aug 25 06:36:44 AM UTC 24 |
13076984970 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.24288678 |
|
|
Aug 25 06:36:24 AM UTC 24 |
Aug 25 06:36:47 AM UTC 24 |
3355175609 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.3718506311 |
|
|
Aug 25 06:36:43 AM UTC 24 |
Aug 25 06:36:47 AM UTC 24 |
4244313158 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.4273848871 |
|
|
Aug 25 06:36:40 AM UTC 24 |
Aug 25 06:36:47 AM UTC 24 |
7254557434 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1621979471 |
|
|
Aug 25 06:34:35 AM UTC 24 |
Aug 25 06:36:49 AM UTC 24 |
28329656636 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1283844448 |
|
|
Aug 25 06:36:40 AM UTC 24 |
Aug 25 06:36:50 AM UTC 24 |
3354746568 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.3362783629 |
|
|
Aug 25 06:36:48 AM UTC 24 |
Aug 25 06:36:50 AM UTC 24 |
2092675641 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.545059561 |
|
|
Aug 25 06:36:38 AM UTC 24 |
Aug 25 06:36:51 AM UTC 24 |
2610827564 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.3108168290 |
|
|
Aug 25 06:36:49 AM UTC 24 |
Aug 25 06:36:53 AM UTC 24 |
2147633980 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.3508877491 |
|
|
Aug 25 06:36:29 AM UTC 24 |
Aug 25 06:36:54 AM UTC 24 |
7124390391 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.4174711739 |
|
|
Aug 25 06:36:20 AM UTC 24 |
Aug 25 06:36:55 AM UTC 24 |
70512029693 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.974874795 |
|
|
Aug 25 06:36:51 AM UTC 24 |
Aug 25 06:36:56 AM UTC 24 |
2142348280 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.4024703387 |
|
|
Aug 25 06:36:51 AM UTC 24 |
Aug 25 06:36:56 AM UTC 24 |
2527237050 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1363749452 |
|
|
Aug 25 06:36:51 AM UTC 24 |
Aug 25 06:36:56 AM UTC 24 |
2624319621 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.406154949 |
|
|
Aug 25 06:36:48 AM UTC 24 |
Aug 25 06:36:57 AM UTC 24 |
8324170845 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1906052903 |
|
|
Aug 25 06:36:55 AM UTC 24 |
Aug 25 06:36:58 AM UTC 24 |
7397696832 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.2655508823 |
|
|
Aug 25 06:36:50 AM UTC 24 |
Aug 25 06:36:58 AM UTC 24 |
2461349077 ps |
| T243 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.2319841904 |
|
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Aug 25 06:36:57 AM UTC 24 |
Aug 25 06:37:00 AM UTC 24 |
4135435034 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.3365294261 |
|
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Aug 25 06:36:45 AM UTC 24 |
Aug 25 06:37:00 AM UTC 24 |
3163874088 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1777081532 |
|
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Aug 25 06:36:53 AM UTC 24 |
Aug 25 06:37:03 AM UTC 24 |
3316201051 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.1147551481 |
|
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Aug 25 06:36:59 AM UTC 24 |
Aug 25 06:37:03 AM UTC 24 |
2047465687 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1514850487 |
|
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Aug 25 06:36:51 AM UTC 24 |
Aug 25 06:37:03 AM UTC 24 |
4371738379 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.786079071 |
|
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Aug 25 06:32:57 AM UTC 24 |
Aug 25 06:37:06 AM UTC 24 |
59106206518 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.3528658948 |
|
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Aug 25 06:37:05 AM UTC 24 |
Aug 25 06:37:07 AM UTC 24 |
3242340493 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1960056910 |
|
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Aug 25 06:37:05 AM UTC 24 |
Aug 25 06:37:07 AM UTC 24 |
2702682369 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.727952430 |
|
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Aug 25 06:37:03 AM UTC 24 |
Aug 25 06:37:08 AM UTC 24 |
2531417133 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.1825087777 |
|
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Aug 25 06:36:58 AM UTC 24 |
Aug 25 06:37:09 AM UTC 24 |
8445645217 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3776180542 |
|
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Aug 25 06:35:29 AM UTC 24 |
Aug 25 06:37:11 AM UTC 24 |
41437548566 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.3172154290 |
|
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Aug 25 06:37:01 AM UTC 24 |
Aug 25 06:37:12 AM UTC 24 |
2197695554 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.261250646 |
|
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Aug 25 06:37:01 AM UTC 24 |
Aug 25 06:37:13 AM UTC 24 |
2470287651 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.2235250172 |
|
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Aug 25 06:36:59 AM UTC 24 |
Aug 25 06:37:13 AM UTC 24 |
2113991055 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.1425562106 |
|
|
Aug 25 06:37:09 AM UTC 24 |
Aug 25 06:37:14 AM UTC 24 |
3241155554 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3534091025 |
|
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Aug 25 06:36:57 AM UTC 24 |
Aug 25 06:37:17 AM UTC 24 |
3743718751 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1625443910 |
|
|
Aug 25 06:37:13 AM UTC 24 |
Aug 25 06:37:18 AM UTC 24 |
2040266185 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2772216869 |
|
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Aug 25 06:37:15 AM UTC 24 |
Aug 25 06:37:18 AM UTC 24 |
2117159197 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1068848006 |
|
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Aug 25 06:37:08 AM UTC 24 |
Aug 25 06:37:19 AM UTC 24 |
2565948055 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.1437985836 |
|
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Aug 25 06:37:15 AM UTC 24 |
Aug 25 06:37:19 AM UTC 24 |
2480860458 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.3537744523 |
|
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Aug 25 06:37:13 AM UTC 24 |
Aug 25 06:37:20 AM UTC 24 |
2114256519 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.2806644062 |
|
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Aug 25 06:37:13 AM UTC 24 |
Aug 25 06:37:21 AM UTC 24 |
17150622660 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.1128927320 |
|
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Aug 25 06:36:17 AM UTC 24 |
Aug 25 06:37:22 AM UTC 24 |
52411838117 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1625218452 |
|
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Aug 25 06:37:20 AM UTC 24 |
Aug 25 06:37:24 AM UTC 24 |
5647616834 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.248410074 |
|
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Aug 25 06:37:07 AM UTC 24 |
Aug 25 06:37:24 AM UTC 24 |
3894836983 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2829070101 |
|
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Aug 25 06:37:20 AM UTC 24 |
Aug 25 06:37:27 AM UTC 24 |
3545161007 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.4280095151 |
|
|
Aug 25 06:37:19 AM UTC 24 |
Aug 25 06:37:27 AM UTC 24 |
2617384361 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.219563674 |
|
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Aug 25 06:34:50 AM UTC 24 |
Aug 25 06:37:30 AM UTC 24 |
150420561377 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.3536114952 |
|
|
Aug 25 06:37:28 AM UTC 24 |
Aug 25 06:37:32 AM UTC 24 |
2025882531 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.1078601945 |
|
|
Aug 25 06:37:19 AM UTC 24 |
Aug 25 06:37:33 AM UTC 24 |
2511436226 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1007996636 |
|
|
Aug 25 06:32:53 AM UTC 24 |
Aug 25 06:37:35 AM UTC 24 |
66278244547 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.910404725 |
|
|
Aug 25 06:37:22 AM UTC 24 |
Aug 25 06:37:36 AM UTC 24 |
2824683642 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.4237231844 |
|
|
Aug 25 06:37:31 AM UTC 24 |
Aug 25 06:37:36 AM UTC 24 |
2496909660 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.2563264851 |
|
|
Aug 25 06:37:20 AM UTC 24 |
Aug 25 06:37:40 AM UTC 24 |
3553687650 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1219502299 |
|
|
Aug 25 06:37:36 AM UTC 24 |
Aug 25 06:37:40 AM UTC 24 |
2672182444 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.2959541033 |
|
|
Aug 25 06:37:34 AM UTC 24 |
Aug 25 06:37:40 AM UTC 24 |
2529354269 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2904515735 |
|
|
Aug 25 06:37:10 AM UTC 24 |
Aug 25 06:37:41 AM UTC 24 |
34700655624 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.3798594725 |
|
|
Aug 25 06:37:29 AM UTC 24 |
Aug 25 06:37:41 AM UTC 24 |
2107172765 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.763809595 |
|
|
Aug 25 06:36:43 AM UTC 24 |
Aug 25 06:37:43 AM UTC 24 |
47599886088 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.2488052557 |
|
|
Aug 25 06:37:33 AM UTC 24 |
Aug 25 06:37:45 AM UTC 24 |
2020254975 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.2641718939 |
|
|
Aug 25 06:37:41 AM UTC 24 |
Aug 25 06:37:46 AM UTC 24 |
4395771248 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.837772947 |
|
|
Aug 25 06:37:44 AM UTC 24 |
Aug 25 06:37:48 AM UTC 24 |
2029769260 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1726056333 |
|
|
Aug 25 06:37:12 AM UTC 24 |
Aug 25 06:37:49 AM UTC 24 |
6941975956 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.2987245480 |
|
|
Aug 25 06:37:45 AM UTC 24 |
Aug 25 06:37:49 AM UTC 24 |
2134496472 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1832134403 |
|
|
Aug 25 06:37:40 AM UTC 24 |
Aug 25 06:37:49 AM UTC 24 |
5783584289 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.1035790936 |
|
|
Aug 25 06:37:47 AM UTC 24 |
Aug 25 06:37:51 AM UTC 24 |
2504921690 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.2538082637 |
|
|
Aug 25 06:37:49 AM UTC 24 |
Aug 25 06:37:54 AM UTC 24 |
2054084679 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.1200568762 |
|
|
Aug 25 06:37:24 AM UTC 24 |
Aug 25 06:37:55 AM UTC 24 |
10374521498 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3655558206 |
|
|
Aug 25 06:37:37 AM UTC 24 |
Aug 25 06:37:55 AM UTC 24 |
3026669581 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.1460448695 |
|
|
Aug 25 06:37:50 AM UTC 24 |
Aug 25 06:37:56 AM UTC 24 |
2537359419 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1788672785 |
|
|
Aug 25 06:37:51 AM UTC 24 |
Aug 25 06:37:56 AM UTC 24 |
3593390042 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3777286715 |
|
|
Aug 25 06:36:28 AM UTC 24 |
Aug 25 06:37:57 AM UTC 24 |
40844167962 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2087384862 |
|
|
Aug 25 06:37:36 AM UTC 24 |
Aug 25 06:37:57 AM UTC 24 |
3860986828 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.3540952432 |
|
|
Aug 25 06:34:33 AM UTC 24 |
Aug 25 06:37:59 AM UTC 24 |
96977133676 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3174685218 |
|
|
Aug 25 06:37:50 AM UTC 24 |
Aug 25 06:37:59 AM UTC 24 |
5312857039 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3843563439 |
|
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Aug 25 06:37:50 AM UTC 24 |
Aug 25 06:37:59 AM UTC 24 |
2617429122 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.1439535613 |
|
|
Aug 25 06:37:44 AM UTC 24 |
Aug 25 06:38:01 AM UTC 24 |
6734290121 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.513752662 |
|
|
Aug 25 06:37:58 AM UTC 24 |
Aug 25 06:38:01 AM UTC 24 |
2071777381 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2420167864 |
|
|
Aug 25 06:37:43 AM UTC 24 |
Aug 25 06:38:03 AM UTC 24 |
93420741605 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.1317468632 |
|
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Aug 25 06:37:59 AM UTC 24 |
Aug 25 06:38:05 AM UTC 24 |
2477466580 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.1756062704 |
|
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Aug 25 06:37:59 AM UTC 24 |
Aug 25 06:38:05 AM UTC 24 |
2116650967 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.1453436871 |
|
|
Aug 25 06:38:01 AM UTC 24 |
Aug 25 06:38:09 AM UTC 24 |
2516169122 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1019109594 |
|
|
Aug 25 06:37:57 AM UTC 24 |
Aug 25 06:38:11 AM UTC 24 |
3905365546 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.995689599 |
|
|
Aug 25 06:36:57 AM UTC 24 |
Aug 25 06:38:11 AM UTC 24 |
35783725470 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.3999398150 |
|
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Aug 25 06:38:00 AM UTC 24 |
Aug 25 06:38:11 AM UTC 24 |
2206062514 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.1589250452 |
|
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Aug 25 06:37:56 AM UTC 24 |
Aug 25 06:38:11 AM UTC 24 |
2833476382 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1430377651 |
|
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Aug 25 06:38:07 AM UTC 24 |
Aug 25 06:38:12 AM UTC 24 |
5246940722 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.283295421 |
|
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Aug 25 06:38:01 AM UTC 24 |
Aug 25 06:38:14 AM UTC 24 |
2613916240 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.2754168633 |
|
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Aug 25 06:38:12 AM UTC 24 |
Aug 25 06:38:17 AM UTC 24 |
2695548344 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.2627077258 |
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Aug 25 06:38:13 AM UTC 24 |
Aug 25 06:38:17 AM UTC 24 |
2040445357 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.641189327 |
|
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Aug 25 06:38:15 AM UTC 24 |
Aug 25 06:38:20 AM UTC 24 |
2136745029 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.2353609097 |
|
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Aug 25 06:38:18 AM UTC 24 |
Aug 25 06:38:22 AM UTC 24 |
2498797990 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3392859388 |
|
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Aug 25 06:38:06 AM UTC 24 |
Aug 25 06:38:23 AM UTC 24 |
3212721245 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.3993917553 |
|
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Aug 25 06:34:37 AM UTC 24 |
Aug 25 06:38:23 AM UTC 24 |
1173729978399 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3831645468 |
|
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Aug 25 06:38:18 AM UTC 24 |
Aug 25 06:38:25 AM UTC 24 |
2234334592 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.2597682444 |
|
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Aug 25 06:38:21 AM UTC 24 |
Aug 25 06:38:26 AM UTC 24 |
2529462552 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.2066077791 |
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Aug 25 06:37:40 AM UTC 24 |
Aug 25 06:38:27 AM UTC 24 |
47998920719 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.623085438 |
|
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Aug 25 06:37:25 AM UTC 24 |
Aug 25 06:38:30 AM UTC 24 |
12439981459 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1833633051 |
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Aug 25 06:38:23 AM UTC 24 |
Aug 25 06:38:33 AM UTC 24 |
3499518313 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.600723362 |
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Aug 25 06:38:12 AM UTC 24 |
Aug 25 06:38:33 AM UTC 24 |
18284522149 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1072179386 |
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Aug 25 06:38:23 AM UTC 24 |
Aug 25 06:38:34 AM UTC 24 |
4048477108 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1235361716 |
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Aug 25 06:38:22 AM UTC 24 |
Aug 25 06:38:36 AM UTC 24 |
2611369935 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.902652961 |
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Aug 25 06:38:24 AM UTC 24 |
Aug 25 06:38:38 AM UTC 24 |
7654207257 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.2875989669 |
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Aug 25 06:38:35 AM UTC 24 |
Aug 25 06:38:40 AM UTC 24 |
2030118891 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3672578119 |
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Aug 25 06:38:37 AM UTC 24 |
Aug 25 06:38:41 AM UTC 24 |
2140998986 ps |
| T104 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.2643405493 |
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Aug 25 06:38:12 AM UTC 24 |
Aug 25 06:38:44 AM UTC 24 |
8172267269 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.4040972330 |
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Aug 25 06:38:40 AM UTC 24 |
Aug 25 06:38:44 AM UTC 24 |
2622401839 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.1956874452 |
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Aug 25 06:38:39 AM UTC 24 |
Aug 25 06:38:44 AM UTC 24 |
2532286056 ps |
| T102 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.754813870 |
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Aug 25 06:38:27 AM UTC 24 |
Aug 25 06:38:45 AM UTC 24 |
3927829481 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2583063316 |
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Aug 25 06:38:35 AM UTC 24 |
Aug 25 06:38:47 AM UTC 24 |
2107921629 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3043766900 |
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Aug 25 06:38:31 AM UTC 24 |
Aug 25 06:38:47 AM UTC 24 |
2971574830 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.569113366 |
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Aug 25 06:38:42 AM UTC 24 |
Aug 25 06:38:48 AM UTC 24 |
2597657110 ps |