| T149 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.1932581373 |
|
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Aug 25 06:40:07 AM UTC 24 |
Aug 25 06:40:16 AM UTC 24 |
2014682926 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.835901604 |
|
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Aug 25 06:38:37 AM UTC 24 |
Aug 25 06:38:50 AM UTC 24 |
2472455574 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3740421459 |
|
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Aug 25 06:38:45 AM UTC 24 |
Aug 25 06:38:50 AM UTC 24 |
7677998918 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.3829555244 |
|
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Aug 25 06:38:51 AM UTC 24 |
Aug 25 06:38:56 AM UTC 24 |
2128093647 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.3699063156 |
|
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Aug 25 06:38:51 AM UTC 24 |
Aug 25 06:38:56 AM UTC 24 |
2479685004 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.4117966269 |
|
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Aug 25 06:38:48 AM UTC 24 |
Aug 25 06:38:56 AM UTC 24 |
2024048291 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.97148049 |
|
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Aug 25 06:38:44 AM UTC 24 |
Aug 25 06:39:00 AM UTC 24 |
3472676652 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.2773679340 |
|
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Aug 25 06:38:46 AM UTC 24 |
Aug 25 06:39:00 AM UTC 24 |
3511800302 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.1628190035 |
|
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Aug 25 06:38:56 AM UTC 24 |
Aug 25 06:39:01 AM UTC 24 |
2540381317 ps |
| T329 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1926795313 |
|
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Aug 25 06:38:48 AM UTC 24 |
Aug 25 06:39:02 AM UTC 24 |
3533785630 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3034239918 |
|
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Aug 25 06:38:58 AM UTC 24 |
Aug 25 06:39:03 AM UTC 24 |
2623080349 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1331105463 |
|
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Aug 25 06:39:02 AM UTC 24 |
Aug 25 06:39:05 AM UTC 24 |
3280730685 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2355715170 |
|
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Aug 25 06:39:02 AM UTC 24 |
Aug 25 06:39:06 AM UTC 24 |
3655614396 ps |
| T367 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2364670295 |
|
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Aug 25 06:37:23 AM UTC 24 |
Aug 25 06:39:07 AM UTC 24 |
78875310595 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2262766368 |
|
|
Aug 25 06:38:56 AM UTC 24 |
Aug 25 06:39:09 AM UTC 24 |
2077907374 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.330523826 |
|
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Aug 25 06:38:12 AM UTC 24 |
Aug 25 06:39:11 AM UTC 24 |
60299100089 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.710793480 |
|
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Aug 25 06:39:10 AM UTC 24 |
Aug 25 06:39:13 AM UTC 24 |
2157897136 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.2783634142 |
|
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Aug 25 06:39:03 AM UTC 24 |
Aug 25 06:39:14 AM UTC 24 |
4312082493 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.893282449 |
|
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Aug 25 06:39:02 AM UTC 24 |
Aug 25 06:39:18 AM UTC 24 |
7251084267 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3277515652 |
|
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Aug 25 06:30:40 AM UTC 24 |
Aug 25 06:39:18 AM UTC 24 |
109559615392 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2315341333 |
|
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Aug 25 06:39:15 AM UTC 24 |
Aug 25 06:39:19 AM UTC 24 |
2538941501 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.3432692361 |
|
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Aug 25 06:38:45 AM UTC 24 |
Aug 25 06:39:19 AM UTC 24 |
27136586903 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1444068016 |
|
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Aug 25 06:32:00 AM UTC 24 |
Aug 25 06:39:20 AM UTC 24 |
132421336682 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.1217173333 |
|
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Aug 25 06:39:15 AM UTC 24 |
Aug 25 06:39:21 AM UTC 24 |
2151077253 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.1059695026 |
|
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Aug 25 06:39:09 AM UTC 24 |
Aug 25 06:39:22 AM UTC 24 |
2010481154 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.1582851134 |
|
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Aug 25 06:37:58 AM UTC 24 |
Aug 25 06:39:25 AM UTC 24 |
18731719574 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.218382438 |
|
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Aug 25 06:39:20 AM UTC 24 |
Aug 25 06:39:26 AM UTC 24 |
3508955135 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.3184553923 |
|
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Aug 25 06:39:12 AM UTC 24 |
Aug 25 06:39:27 AM UTC 24 |
2453407114 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4180330218 |
|
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Aug 25 06:39:19 AM UTC 24 |
Aug 25 06:39:29 AM UTC 24 |
3185583766 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.65085713 |
|
|
Aug 25 06:36:08 AM UTC 24 |
Aug 25 06:39:29 AM UTC 24 |
2210474670379 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.2096385509 |
|
|
Aug 25 06:38:48 AM UTC 24 |
Aug 25 06:39:30 AM UTC 24 |
9046008917 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.2229323316 |
|
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Aug 25 06:39:27 AM UTC 24 |
Aug 25 06:39:31 AM UTC 24 |
6333000186 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.1395602689 |
|
|
Aug 25 06:39:28 AM UTC 24 |
Aug 25 06:39:32 AM UTC 24 |
2035482088 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.214300428 |
|
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Aug 25 06:39:22 AM UTC 24 |
Aug 25 06:39:33 AM UTC 24 |
3806877448 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.1240831158 |
|
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Aug 25 06:35:14 AM UTC 24 |
Aug 25 06:40:13 AM UTC 24 |
74755686899 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3794598813 |
|
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Aug 25 06:39:19 AM UTC 24 |
Aug 25 06:39:34 AM UTC 24 |
2613761955 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1122974121 |
|
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Aug 25 06:39:31 AM UTC 24 |
Aug 25 06:39:35 AM UTC 24 |
2122792718 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.3895262054 |
|
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Aug 25 06:40:09 AM UTC 24 |
Aug 25 06:40:14 AM UTC 24 |
2491669498 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.2432052844 |
|
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Aug 25 06:39:07 AM UTC 24 |
Aug 25 06:39:37 AM UTC 24 |
13788050601 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2125980563 |
|
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Aug 25 06:39:07 AM UTC 24 |
Aug 25 06:39:38 AM UTC 24 |
7551763216 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.911507383 |
|
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Aug 25 06:39:26 AM UTC 24 |
Aug 25 06:39:39 AM UTC 24 |
10854831331 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.4175468872 |
|
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Aug 25 06:39:33 AM UTC 24 |
Aug 25 06:39:41 AM UTC 24 |
5146692618 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.4001352460 |
|
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Aug 25 06:39:35 AM UTC 24 |
Aug 25 06:39:41 AM UTC 24 |
3226254220 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1386419535 |
|
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Aug 25 06:39:32 AM UTC 24 |
Aug 25 06:39:41 AM UTC 24 |
2619449504 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.2183351977 |
|
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Aug 25 06:39:38 AM UTC 24 |
Aug 25 06:39:42 AM UTC 24 |
2652344289 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.397156455 |
|
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Aug 25 06:39:30 AM UTC 24 |
Aug 25 06:39:43 AM UTC 24 |
2462376998 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.3383087389 |
|
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Aug 25 06:39:30 AM UTC 24 |
Aug 25 06:39:43 AM UTC 24 |
2111542228 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.3924392113 |
|
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Aug 25 06:39:42 AM UTC 24 |
Aug 25 06:39:45 AM UTC 24 |
2494186025 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.2840455551 |
|
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Aug 25 06:39:41 AM UTC 24 |
Aug 25 06:39:45 AM UTC 24 |
2124061813 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.717924663 |
|
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Aug 25 06:39:32 AM UTC 24 |
Aug 25 06:39:46 AM UTC 24 |
2510903398 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.2374270129 |
|
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Aug 25 06:39:42 AM UTC 24 |
Aug 25 06:39:47 AM UTC 24 |
2138481352 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1323946505 |
|
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Aug 25 06:39:47 AM UTC 24 |
Aug 25 06:39:50 AM UTC 24 |
7298682403 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.850979293 |
|
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Aug 25 06:39:35 AM UTC 24 |
Aug 25 06:39:51 AM UTC 24 |
6798680528 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.1949095993 |
|
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Aug 25 06:39:40 AM UTC 24 |
Aug 25 06:39:51 AM UTC 24 |
2010770829 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2964224846 |
|
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Aug 25 06:39:44 AM UTC 24 |
Aug 25 06:39:52 AM UTC 24 |
2616994225 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.1883868856 |
|
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Aug 25 06:31:41 AM UTC 24 |
Aug 25 06:39:52 AM UTC 24 |
111581610069 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.4283333446 |
|
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Aug 25 06:39:46 AM UTC 24 |
Aug 25 06:39:53 AM UTC 24 |
3526115919 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.2574400304 |
|
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Aug 25 06:39:43 AM UTC 24 |
Aug 25 06:39:55 AM UTC 24 |
2512398901 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2006827901 |
|
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Aug 25 06:39:52 AM UTC 24 |
Aug 25 06:39:56 AM UTC 24 |
2132008525 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.2857389697 |
|
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Aug 25 06:39:48 AM UTC 24 |
Aug 25 06:39:57 AM UTC 24 |
4354305705 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.3880087723 |
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Aug 25 06:39:56 AM UTC 24 |
Aug 25 06:39:59 AM UTC 24 |
2601063092 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3141742175 |
|
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Aug 25 06:39:44 AM UTC 24 |
Aug 25 06:40:00 AM UTC 24 |
4660631914 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.2107006603 |
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Aug 25 06:39:52 AM UTC 24 |
Aug 25 06:40:00 AM UTC 24 |
2019641997 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.1712035465 |
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Aug 25 06:39:40 AM UTC 24 |
Aug 25 06:40:01 AM UTC 24 |
19417216997 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3769102599 |
|
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Aug 25 06:36:14 AM UTC 24 |
Aug 25 06:40:02 AM UTC 24 |
108434258262 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2804844031 |
|
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Aug 25 06:39:57 AM UTC 24 |
Aug 25 06:40:05 AM UTC 24 |
2616690974 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.225653068 |
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Aug 25 06:39:54 AM UTC 24 |
Aug 25 06:40:05 AM UTC 24 |
2027809800 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.1739677911 |
|
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Aug 25 06:39:54 AM UTC 24 |
Aug 25 06:40:06 AM UTC 24 |
2454221650 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1907135088 |
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Aug 25 06:39:39 AM UTC 24 |
Aug 25 06:40:06 AM UTC 24 |
5514282127 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.481376932 |
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Aug 25 06:40:01 AM UTC 24 |
Aug 25 06:40:08 AM UTC 24 |
2357848563 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.8539213 |
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Aug 25 06:39:52 AM UTC 24 |
Aug 25 06:40:09 AM UTC 24 |
14667374636 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.362932102 |
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Aug 25 06:31:27 AM UTC 24 |
Aug 25 06:40:10 AM UTC 24 |
119338441273 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2277363664 |
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Aug 25 06:39:39 AM UTC 24 |
Aug 25 06:40:11 AM UTC 24 |
27351897243 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1267072132 |
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Aug 25 06:30:04 AM UTC 24 |
Aug 25 06:40:11 AM UTC 24 |
128971376083 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.3220774299 |
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Aug 25 06:40:07 AM UTC 24 |
Aug 25 06:40:11 AM UTC 24 |
7437765671 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2278559244 |
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Aug 25 06:40:00 AM UTC 24 |
Aug 25 06:40:12 AM UTC 24 |
3450675370 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1312763432 |
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Aug 25 06:35:41 AM UTC 24 |
Aug 25 06:40:12 AM UTC 24 |
66077879486 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.3289732319 |
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Aug 25 06:40:10 AM UTC 24 |
Aug 25 06:40:14 AM UTC 24 |
2168022029 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4239239778 |
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Aug 25 06:40:13 AM UTC 24 |
Aug 25 06:40:16 AM UTC 24 |
7266677694 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.1061139182 |
|
|
Aug 25 06:40:11 AM UTC 24 |
Aug 25 06:40:17 AM UTC 24 |
2535720419 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.217318577 |
|
|
Aug 25 06:40:12 AM UTC 24 |
Aug 25 06:40:18 AM UTC 24 |
2625494303 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.698312424 |
|
|
Aug 25 06:41:04 AM UTC 24 |
Aug 25 06:41:18 AM UTC 24 |
4676814226 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.569581326 |
|
|
Aug 25 06:40:07 AM UTC 24 |
Aug 25 06:40:19 AM UTC 24 |
2111750446 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.764189983 |
|
|
Aug 25 06:40:14 AM UTC 24 |
Aug 25 06:40:19 AM UTC 24 |
3092516059 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1771265548 |
|
|
Aug 25 06:40:12 AM UTC 24 |
Aug 25 06:40:19 AM UTC 24 |
3481006888 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.3649899789 |
|
|
Aug 25 06:40:17 AM UTC 24 |
Aug 25 06:40:21 AM UTC 24 |
2039422695 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.2527968531 |
|
|
Aug 25 06:39:52 AM UTC 24 |
Aug 25 06:40:21 AM UTC 24 |
11955791759 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.348959944 |
|
|
Aug 25 06:40:18 AM UTC 24 |
Aug 25 06:40:21 AM UTC 24 |
2208697073 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.4268965754 |
|
|
Aug 25 06:36:06 AM UTC 24 |
Aug 25 06:40:22 AM UTC 24 |
104147608585 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3298389342 |
|
|
Aug 25 06:39:58 AM UTC 24 |
Aug 25 06:40:22 AM UTC 24 |
4228998885 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2306355613 |
|
|
Aug 25 06:39:51 AM UTC 24 |
Aug 25 06:40:22 AM UTC 24 |
27862743874 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.97427568 |
|
|
Aug 25 06:40:12 AM UTC 24 |
Aug 25 06:40:23 AM UTC 24 |
3782480304 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.4000474103 |
|
|
Aug 25 06:40:20 AM UTC 24 |
Aug 25 06:40:25 AM UTC 24 |
2637359789 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3923901825 |
|
|
Aug 25 06:40:20 AM UTC 24 |
Aug 25 06:40:25 AM UTC 24 |
2610813934 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2390700470 |
|
|
Aug 25 06:40:23 AM UTC 24 |
Aug 25 06:40:26 AM UTC 24 |
6822154716 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.2902137407 |
|
|
Aug 25 06:40:19 AM UTC 24 |
Aug 25 06:40:26 AM UTC 24 |
2036362339 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.55123632 |
|
|
Aug 25 06:40:15 AM UTC 24 |
Aug 25 06:40:26 AM UTC 24 |
3288837283 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2342081190 |
|
|
Aug 25 06:40:06 AM UTC 24 |
Aug 25 06:40:30 AM UTC 24 |
6541700639 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.93174648 |
|
|
Aug 25 06:40:25 AM UTC 24 |
Aug 25 06:40:30 AM UTC 24 |
2031391774 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.168680442 |
|
|
Aug 25 06:37:09 AM UTC 24 |
Aug 25 06:40:30 AM UTC 24 |
44289778421 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.885079980 |
|
|
Aug 25 06:40:23 AM UTC 24 |
Aug 25 06:40:32 AM UTC 24 |
4106149607 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1740552623 |
|
|
Aug 25 06:40:27 AM UTC 24 |
Aug 25 06:40:32 AM UTC 24 |
2469310322 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1229414799 |
|
|
Aug 25 06:36:07 AM UTC 24 |
Aug 25 06:40:33 AM UTC 24 |
261299171528 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.3255424505 |
|
|
Aug 25 06:40:18 AM UTC 24 |
Aug 25 06:40:33 AM UTC 24 |
2476117131 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.1122888486 |
|
|
Aug 25 06:40:28 AM UTC 24 |
Aug 25 06:40:33 AM UTC 24 |
2531989795 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2009233501 |
|
|
Aug 25 06:30:56 AM UTC 24 |
Aug 25 06:40:34 AM UTC 24 |
1225271527592 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.1194599211 |
|
|
Aug 25 06:40:20 AM UTC 24 |
Aug 25 06:40:35 AM UTC 24 |
2510851281 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2159624059 |
|
|
Aug 25 06:40:31 AM UTC 24 |
Aug 25 06:40:36 AM UTC 24 |
3201998557 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.4041359725 |
|
|
Aug 25 06:40:25 AM UTC 24 |
Aug 25 06:40:37 AM UTC 24 |
2110896684 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.3441234970 |
|
|
Aug 25 06:40:32 AM UTC 24 |
Aug 25 06:40:37 AM UTC 24 |
2935487890 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3974312853 |
|
|
Aug 25 06:40:22 AM UTC 24 |
Aug 25 06:40:38 AM UTC 24 |
3524452712 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1254961428 |
|
|
Aug 25 06:40:28 AM UTC 24 |
Aug 25 06:40:39 AM UTC 24 |
2610776810 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3690297353 |
|
|
Aug 25 06:40:27 AM UTC 24 |
Aug 25 06:40:39 AM UTC 24 |
2055783734 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.577467479 |
|
|
Aug 25 06:40:31 AM UTC 24 |
Aug 25 06:40:39 AM UTC 24 |
4349290050 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3777401287 |
|
|
Aug 25 06:40:23 AM UTC 24 |
Aug 25 06:40:40 AM UTC 24 |
10844251153 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.4194498736 |
|
|
Aug 25 06:40:35 AM UTC 24 |
Aug 25 06:40:41 AM UTC 24 |
2470469622 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.4120356147 |
|
|
Aug 25 06:40:34 AM UTC 24 |
Aug 25 06:40:41 AM UTC 24 |
2020951226 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1833358589 |
|
|
Aug 25 06:40:38 AM UTC 24 |
Aug 25 06:40:42 AM UTC 24 |
2639667201 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.138190054 |
|
|
Aug 25 06:40:41 AM UTC 24 |
Aug 25 06:40:46 AM UTC 24 |
3123232157 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2672819326 |
|
|
Aug 25 06:40:34 AM UTC 24 |
Aug 25 06:40:46 AM UTC 24 |
6128589809 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.2548962036 |
|
|
Aug 25 06:40:35 AM UTC 24 |
Aug 25 06:40:46 AM UTC 24 |
2112527211 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.920012478 |
|
|
Aug 25 06:40:34 AM UTC 24 |
Aug 25 06:40:46 AM UTC 24 |
9290610749 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.1717332340 |
|
|
Aug 25 06:40:38 AM UTC 24 |
Aug 25 06:40:47 AM UTC 24 |
2523725584 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.3237703003 |
|
|
Aug 25 06:40:37 AM UTC 24 |
Aug 25 06:40:49 AM UTC 24 |
2046168809 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2021990162 |
|
|
Aug 25 06:40:39 AM UTC 24 |
Aug 25 06:40:50 AM UTC 24 |
3798928715 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.1269093030 |
|
|
Aug 25 06:40:46 AM UTC 24 |
Aug 25 06:40:51 AM UTC 24 |
2037743803 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.3531192184 |
|
|
Aug 25 06:40:48 AM UTC 24 |
Aug 25 06:40:52 AM UTC 24 |
2109935075 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3067212097 |
|
|
Aug 25 06:40:48 AM UTC 24 |
Aug 25 06:40:52 AM UTC 24 |
2536328431 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3025260059 |
|
|
Aug 25 06:40:31 AM UTC 24 |
Aug 25 06:40:54 AM UTC 24 |
3934982214 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.1607494621 |
|
|
Aug 25 06:40:46 AM UTC 24 |
Aug 25 06:40:54 AM UTC 24 |
2475216825 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.17062706 |
|
|
Aug 25 06:40:42 AM UTC 24 |
Aug 25 06:40:54 AM UTC 24 |
7411273679 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.662905095 |
|
|
Aug 25 06:40:46 AM UTC 24 |
Aug 25 06:40:56 AM UTC 24 |
2113434199 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3529612667 |
|
|
Aug 25 06:40:48 AM UTC 24 |
Aug 25 06:40:57 AM UTC 24 |
2621964638 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2421244296 |
|
|
Aug 25 06:39:03 AM UTC 24 |
Aug 25 06:40:57 AM UTC 24 |
102124126007 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.472410532 |
|
|
Aug 25 06:41:05 AM UTC 24 |
Aug 25 06:41:24 AM UTC 24 |
3581301231 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3033646924 |
|
|
Aug 25 06:40:42 AM UTC 24 |
Aug 25 06:41:00 AM UTC 24 |
46488101921 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.1248298216 |
|
|
Aug 25 06:40:57 AM UTC 24 |
Aug 25 06:41:02 AM UTC 24 |
2035132109 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.2508076686 |
|
|
Aug 25 06:40:59 AM UTC 24 |
Aug 25 06:41:03 AM UTC 24 |
2461162100 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3077094082 |
|
|
Aug 25 06:40:52 AM UTC 24 |
Aug 25 06:41:04 AM UTC 24 |
5122679144 ps |
| T96 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2815978604 |
|
|
Aug 25 06:40:01 AM UTC 24 |
Aug 25 06:41:06 AM UTC 24 |
140729847960 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.989226194 |
|
|
Aug 25 06:41:01 AM UTC 24 |
Aug 25 06:41:07 AM UTC 24 |
2119517205 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.168145836 |
|
|
Aug 25 06:40:51 AM UTC 24 |
Aug 25 06:41:07 AM UTC 24 |
3431350031 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1433820935 |
|
|
Aug 25 06:41:03 AM UTC 24 |
Aug 25 06:41:08 AM UTC 24 |
2640262770 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.2817803657 |
|
|
Aug 25 06:40:53 AM UTC 24 |
Aug 25 06:41:08 AM UTC 24 |
2696735885 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.1437499967 |
|
|
Aug 25 06:40:57 AM UTC 24 |
Aug 25 06:41:08 AM UTC 24 |
2112649846 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.4159384335 |
|
|
Aug 25 06:40:50 AM UTC 24 |
Aug 25 06:41:08 AM UTC 24 |
2973858440 ps |
| T99 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.211625266 |
|
|
Aug 25 06:38:28 AM UTC 24 |
Aug 25 06:41:09 AM UTC 24 |
50788936896 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.4204502213 |
|
|
Aug 25 06:41:01 AM UTC 24 |
Aug 25 06:41:15 AM UTC 24 |
2508347229 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.1425790782 |
|
|
Aug 25 06:41:10 AM UTC 24 |
Aug 25 06:41:16 AM UTC 24 |
2014405641 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1797219772 |
|
|
Aug 25 06:40:54 AM UTC 24 |
Aug 25 06:41:22 AM UTC 24 |
5013286929 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.885654991 |
|
|
Aug 25 06:40:23 AM UTC 24 |
Aug 25 06:41:25 AM UTC 24 |
73721766527 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2494233127 |
|
|
Aug 25 06:41:08 AM UTC 24 |
Aug 25 06:41:25 AM UTC 24 |
3326708509 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.3275390384 |
|
|
Aug 25 06:41:08 AM UTC 24 |
Aug 25 06:41:28 AM UTC 24 |
3109113585 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2563135990 |
|
|
Aug 25 06:41:22 AM UTC 24 |
Aug 25 06:41:33 AM UTC 24 |
24416409135 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.3572058578 |
|
|
Aug 25 06:38:10 AM UTC 24 |
Aug 25 06:41:43 AM UTC 24 |
48467617159 ps |
| T100 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2447427952 |
|
|
Aug 25 06:36:18 AM UTC 24 |
Aug 25 06:41:44 AM UTC 24 |
128344451616 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.973898858 |
|
|
Aug 25 06:40:55 AM UTC 24 |
Aug 25 06:41:54 AM UTC 24 |
11760875448 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2611380370 |
|
|
Aug 25 06:41:08 AM UTC 24 |
Aug 25 06:41:56 AM UTC 24 |
42150072864 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.1971109979 |
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Aug 25 06:39:37 AM UTC 24 |
Aug 25 06:41:56 AM UTC 24 |
56522312072 ps |
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Aug 25 06:37:57 AM UTC 24 |
Aug 25 06:41:57 AM UTC 24 |
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Aug 25 06:41:26 AM UTC 24 |
Aug 25 06:42:01 AM UTC 24 |
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Aug 25 06:41:10 AM UTC 24 |
Aug 25 06:42:03 AM UTC 24 |
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Aug 25 06:30:03 AM UTC 24 |
Aug 25 06:42:06 AM UTC 24 |
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Aug 25 06:40:40 AM UTC 24 |
Aug 25 06:42:07 AM UTC 24 |
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Aug 25 06:37:55 AM UTC 24 |
Aug 25 06:42:08 AM UTC 24 |
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Aug 25 06:41:58 AM UTC 24 |
Aug 25 06:42:09 AM UTC 24 |
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Aug 25 06:41:28 AM UTC 24 |
Aug 25 06:42:10 AM UTC 24 |
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Aug 25 06:42:07 AM UTC 24 |
Aug 25 06:45:05 AM UTC 24 |
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Aug 25 06:40:31 AM UTC 24 |
Aug 25 06:42:19 AM UTC 24 |
92747925338 ps |
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Aug 25 06:41:55 AM UTC 24 |
Aug 25 06:42:24 AM UTC 24 |
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Aug 25 06:40:23 AM UTC 24 |
Aug 25 06:42:30 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.777102419 |
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Aug 25 06:35:53 AM UTC 24 |
Aug 25 06:42:31 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2242495767 |
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Aug 25 06:42:11 AM UTC 24 |
Aug 25 06:42:36 AM UTC 24 |
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Aug 25 06:38:34 AM UTC 24 |
Aug 25 06:42:40 AM UTC 24 |
53977153044 ps |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3778408221 |
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Aug 25 06:41:44 AM UTC 24 |
Aug 25 06:42:44 AM UTC 24 |
49729824735 ps |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2387803670 |
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Aug 25 06:41:22 AM UTC 24 |
Aug 25 06:42:48 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.4036491122 |
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Aug 25 06:42:20 AM UTC 24 |
Aug 25 06:42:54 AM UTC 24 |
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| T117 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2380564950 |
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Aug 25 06:36:28 AM UTC 24 |
Aug 25 06:42:56 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.1940055464 |
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Aug 25 06:41:08 AM UTC 24 |
Aug 25 06:42:59 AM UTC 24 |
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| T405 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3447201135 |
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Aug 25 06:40:54 AM UTC 24 |
Aug 25 06:43:09 AM UTC 24 |
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Aug 25 06:43:01 AM UTC 24 |
Aug 25 06:43:10 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2673511708 |
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Aug 25 06:40:02 AM UTC 24 |
Aug 25 06:43:13 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1211053834 |
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Aug 25 06:41:29 AM UTC 24 |
Aug 25 06:43:14 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.253032350 |
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Aug 25 06:38:46 AM UTC 24 |
Aug 25 06:43:14 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2013419308 |
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Aug 25 06:42:57 AM UTC 24 |
Aug 25 06:43:18 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1241723824 |
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Aug 25 06:42:46 AM UTC 24 |
Aug 25 06:43:19 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2641434672 |
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Aug 25 06:42:44 AM UTC 24 |
Aug 25 06:43:21 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1053734319 |
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Aug 25 06:41:19 AM UTC 24 |
Aug 25 06:43:22 AM UTC 24 |
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| T283 |
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Aug 25 06:39:47 AM UTC 24 |
Aug 25 06:43:23 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3776485724 |
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Aug 25 06:42:55 AM UTC 24 |
Aug 25 06:43:28 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1855047577 |
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Aug 25 06:41:19 AM UTC 24 |
Aug 25 06:43:32 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.230943592 |
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Aug 25 06:41:26 AM UTC 24 |
Aug 25 06:43:33 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.429653372 |
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Aug 25 06:39:06 AM UTC 24 |
Aug 25 06:43:38 AM UTC 24 |
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| T773 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.586434185 |
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Aug 25 06:40:24 AM UTC 24 |
Aug 25 06:43:45 AM UTC 24 |
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Aug 25 06:36:56 AM UTC 24 |
Aug 25 06:43:46 AM UTC 24 |
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Aug 25 06:42:49 AM UTC 24 |
Aug 25 06:43:48 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3826811091 |
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Aug 25 06:43:14 AM UTC 24 |
Aug 25 06:43:50 AM UTC 24 |
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| T262 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1102939718 |
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Aug 25 06:40:15 AM UTC 24 |
Aug 25 06:44:00 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3003071109 |
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Aug 25 06:41:13 AM UTC 24 |
Aug 25 06:44:00 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.4055172319 |
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Aug 25 06:31:39 AM UTC 24 |
Aug 25 06:44:04 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3133898767 |
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Aug 25 06:42:32 AM UTC 24 |
Aug 25 06:44:05 AM UTC 24 |
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Aug 25 06:35:28 AM UTC 24 |
Aug 25 06:44:09 AM UTC 24 |
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Aug 25 06:41:59 AM UTC 24 |
Aug 25 06:44:13 AM UTC 24 |
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Aug 25 06:40:53 AM UTC 24 |
Aug 25 06:44:14 AM UTC 24 |
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Aug 25 06:40:01 AM UTC 24 |
Aug 25 06:44:16 AM UTC 24 |
115178398144 ps |
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Aug 25 06:30:16 AM UTC 24 |
Aug 25 06:44:24 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1856866995 |
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Aug 25 06:43:09 AM UTC 24 |
Aug 25 06:44:35 AM UTC 24 |
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Aug 25 06:34:17 AM UTC 24 |
Aug 25 06:44:36 AM UTC 24 |
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Aug 25 06:33:47 AM UTC 24 |
Aug 25 06:44:37 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.460108676 |
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Aug 25 06:43:15 AM UTC 24 |
Aug 25 06:44:42 AM UTC 24 |
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Aug 25 06:42:40 AM UTC 24 |
Aug 25 06:44:46 AM UTC 24 |
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Aug 25 06:34:03 AM UTC 24 |
Aug 25 06:44:50 AM UTC 24 |
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Aug 25 06:43:18 AM UTC 24 |
Aug 25 06:44:54 AM UTC 24 |
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Aug 25 06:41:58 AM UTC 24 |
Aug 25 06:44:57 AM UTC 24 |
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Aug 25 06:42:02 AM UTC 24 |
Aug 25 06:44:59 AM UTC 24 |
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Aug 25 06:42:25 AM UTC 24 |
Aug 25 06:45:04 AM UTC 24 |
218172204228 ps |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.64740391 |
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Aug 25 06:42:31 AM UTC 24 |
Aug 25 06:45:09 AM UTC 24 |
65312539963 ps |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3897308920 |
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Aug 25 06:40:40 AM UTC 24 |
Aug 25 06:45:12 AM UTC 24 |
1891266561695 ps |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3467886515 |
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Aug 25 06:40:40 AM UTC 24 |
Aug 25 06:45:14 AM UTC 24 |
58926414457 ps |
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Aug 25 06:43:14 AM UTC 24 |
Aug 25 06:45:14 AM UTC 24 |
143195653448 ps |
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/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3230145231 |
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Aug 25 06:33:10 AM UTC 24 |
Aug 25 06:45:17 AM UTC 24 |
329887693486 ps |
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Aug 25 06:42:04 AM UTC 24 |
Aug 25 06:45:19 AM UTC 24 |
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Aug 25 06:41:33 AM UTC 24 |
Aug 25 06:45:34 AM UTC 24 |
106015377491 ps |
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Aug 25 06:42:08 AM UTC 24 |
Aug 25 06:45:52 AM UTC 24 |
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Aug 25 06:34:47 AM UTC 24 |
Aug 25 06:45:53 AM UTC 24 |
1416926285287 ps |
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Aug 25 06:35:39 AM UTC 24 |
Aug 25 06:45:54 AM UTC 24 |
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Aug 25 06:35:03 AM UTC 24 |
Aug 25 06:45:54 AM UTC 24 |
147353178752 ps |
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Aug 25 06:41:16 AM UTC 24 |
Aug 25 06:45:59 AM UTC 24 |
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Aug 25 06:43:00 AM UTC 24 |
Aug 25 06:45:59 AM UTC 24 |
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Aug 25 06:43:15 AM UTC 24 |
Aug 25 06:46:20 AM UTC 24 |
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Aug 25 06:40:13 AM UTC 24 |
Aug 25 06:46:25 AM UTC 24 |
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Aug 25 06:39:22 AM UTC 24 |
Aug 25 06:46:35 AM UTC 24 |
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Aug 25 06:34:04 AM UTC 24 |
Aug 25 06:46:43 AM UTC 24 |
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Aug 25 06:34:50 AM UTC 24 |
Aug 25 06:46:44 AM UTC 24 |
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Aug 25 06:36:42 AM UTC 24 |
Aug 25 06:47:02 AM UTC 24 |
151365795427 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2704362846 |
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Aug 25 06:38:04 AM UTC 24 |
Aug 25 06:47:02 AM UTC 24 |
1065996082259 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.765897693 |
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Aug 25 06:42:45 AM UTC 24 |
Aug 25 06:47:03 AM UTC 24 |
69667507804 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.4112094867 |
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Aug 25 06:36:07 AM UTC 24 |
Aug 25 06:47:16 AM UTC 24 |
177026667165 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.95881166 |
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Aug 25 06:38:25 AM UTC 24 |
Aug 25 06:47:29 AM UTC 24 |
134874019883 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.3115803450 |
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Aug 25 06:37:21 AM UTC 24 |
Aug 25 06:47:47 AM UTC 24 |
153058880683 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.764687243 |
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Aug 25 06:41:08 AM UTC 24 |
Aug 25 06:48:10 AM UTC 24 |
956642069994 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2507911714 |
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Aug 25 06:37:56 AM UTC 24 |
Aug 25 06:48:32 AM UTC 24 |
167781455605 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.4224149536 |
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Aug 25 06:33:14 AM UTC 24 |
Aug 25 06:48:53 AM UTC 24 |
1420003042098 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.1292362933 |
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Aug 25 06:40:17 AM UTC 24 |
Aug 25 06:49:22 AM UTC 24 |
307075318648 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2690576228 |
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Aug 25 06:42:09 AM UTC 24 |
Aug 25 06:49:30 AM UTC 24 |
139928559861 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3063962776 |
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Aug 25 06:43:11 AM UTC 24 |
Aug 25 06:49:35 AM UTC 24 |
129643748694 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.301376614 |
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Aug 25 06:35:56 AM UTC 24 |
Aug 25 06:50:43 AM UTC 24 |
1104398824507 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.3387834087 |
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Aug 25 06:40:43 AM UTC 24 |
Aug 25 06:51:03 AM UTC 24 |
203505772233 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3319703175 |
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Aug 25 06:43:23 AM UTC 24 |
Aug 25 06:43:28 AM UTC 24 |
2038817658 ps |
| T32 |
/workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3019960994 |
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Aug 25 06:43:27 AM UTC 24 |
Aug 25 06:43:32 AM UTC 24 |
2071526333 ps |