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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
97.38 98.75 96.73 100.00 95.51 98.23 99.33 93.13


Total test records in report: 913
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T301 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1362371711 Aug 25 06:43:20 AM UTC 24 Aug 25 06:43:35 AM UTC 24 2043942750 ps
T33 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1405962423 Aug 25 06:43:24 AM UTC 24 Aug 25 06:43:37 AM UTC 24 4027243146 ps
T34 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2782805926 Aug 25 06:43:29 AM UTC 24 Aug 25 06:43:40 AM UTC 24 2419925368 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4247206967 Aug 25 06:43:33 AM UTC 24 Aug 25 06:43:41 AM UTC 24 2054598308 ps
T302 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3033478320 Aug 25 06:43:33 AM UTC 24 Aug 25 06:43:47 AM UTC 24 2081817983 ps
T796 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4153809340 Aug 25 06:43:35 AM UTC 24 Aug 25 06:43:47 AM UTC 24 2017890084 ps
T334 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2289785631 Aug 25 06:43:41 AM UTC 24 Aug 25 06:43:48 AM UTC 24 2743127399 ps
T335 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3377545273 Aug 25 06:43:37 AM UTC 24 Aug 25 06:43:51 AM UTC 24 2037385965 ps
T336 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2655963968 Aug 25 06:43:48 AM UTC 24 Aug 25 06:43:53 AM UTC 24 2048852241 ps
T21 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4242388108 Aug 25 06:43:42 AM UTC 24 Aug 25 06:43:54 AM UTC 24 7547719453 ps
T35 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.126409964 Aug 25 06:43:48 AM UTC 24 Aug 25 06:43:55 AM UTC 24 4051192869 ps
T308 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3518028836 Aug 25 06:43:42 AM UTC 24 Aug 25 06:43:56 AM UTC 24 2044801175 ps
T304 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.616688944 Aug 25 06:43:33 AM UTC 24 Aug 25 06:43:59 AM UTC 24 22274744549 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1626221568 Aug 25 06:43:47 AM UTC 24 Aug 25 06:44:00 AM UTC 24 2012359409 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2728043762 Aug 25 06:43:36 AM UTC 24 Aug 25 06:44:00 AM UTC 24 4013843343 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3590632565 Aug 25 06:43:56 AM UTC 24 Aug 25 06:44:01 AM UTC 24 2039162656 ps
T303 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.42987008 Aug 25 06:43:46 AM UTC 24 Aug 25 06:44:01 AM UTC 24 2122527290 ps
T337 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3534838164 Aug 25 06:43:49 AM UTC 24 Aug 25 06:44:03 AM UTC 24 2945964982 ps
T394 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3523607281 Aug 25 06:43:52 AM UTC 24 Aug 25 06:44:05 AM UTC 24 2037228507 ps
T396 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2307228308 Aug 25 06:44:01 AM UTC 24 Aug 25 06:44:06 AM UTC 24 2228049622 ps
T312 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3802919372 Aug 25 06:44:01 AM UTC 24 Aug 25 06:44:06 AM UTC 24 2567655592 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1852838778 Aug 25 06:44:04 AM UTC 24 Aug 25 06:44:06 AM UTC 24 2103194825 ps
T313 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.607606781 Aug 25 06:43:54 AM UTC 24 Aug 25 06:44:07 AM UTC 24 2056651859 ps
T309 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.404659926 Aug 25 06:44:00 AM UTC 24 Aug 25 06:44:08 AM UTC 24 2560526979 ps
T343 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3149970383 Aug 25 06:44:06 AM UTC 24 Aug 25 06:44:09 AM UTC 24 2291256791 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2957603492 Aug 25 06:44:07 AM UTC 24 Aug 25 06:44:12 AM UTC 24 2195288567 ps
T344 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.734085052 Aug 25 06:44:00 AM UTC 24 Aug 25 06:44:14 AM UTC 24 2030920120 ps
T338 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1545300721 Aug 25 06:44:10 AM UTC 24 Aug 25 06:44:14 AM UTC 24 2071056981 ps
T339 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3110372359 Aug 25 06:44:07 AM UTC 24 Aug 25 06:44:16 AM UTC 24 2408660138 ps
T22 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3030960806 Aug 25 06:43:29 AM UTC 24 Aug 25 06:44:17 AM UTC 24 6893410078 ps
T340 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3319992518 Aug 25 06:43:57 AM UTC 24 Aug 25 06:44:21 AM UTC 24 4017748517 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1187445714 Aug 25 06:44:09 AM UTC 24 Aug 25 06:44:21 AM UTC 24 2011570947 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.924302710 Aug 25 06:44:14 AM UTC 24 Aug 25 06:44:21 AM UTC 24 2079599983 ps
T393 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.360590042 Aug 25 06:44:18 AM UTC 24 Aug 25 06:44:23 AM UTC 24 2129850407 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3505184201 Aug 25 06:44:08 AM UTC 24 Aug 25 06:44:23 AM UTC 24 2106240730 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1850110418 Aug 25 06:43:50 AM UTC 24 Aug 25 06:44:24 AM UTC 24 10300931731 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1403294893 Aug 25 06:44:05 AM UTC 24 Aug 25 06:44:24 AM UTC 24 6051507729 ps
T305 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1229231084 Aug 25 06:43:22 AM UTC 24 Aug 25 06:44:25 AM UTC 24 42807497713 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3400606804 Aug 25 06:44:22 AM UTC 24 Aug 25 06:44:27 AM UTC 24 2045043043 ps
T311 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1852112611 Aug 25 06:44:15 AM UTC 24 Aug 25 06:44:29 AM UTC 24 2060601737 ps
T314 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3757424150 Aug 25 06:44:21 AM UTC 24 Aug 25 06:44:29 AM UTC 24 2551280472 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3149889066 Aug 25 06:44:16 AM UTC 24 Aug 25 06:44:29 AM UTC 24 2014196001 ps
T341 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.271001649 Aug 25 06:44:17 AM UTC 24 Aug 25 06:44:30 AM UTC 24 2024847964 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1718812794 Aug 25 06:44:25 AM UTC 24 Aug 25 06:44:32 AM UTC 24 2050039349 ps
T315 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3790651362 Aug 25 06:44:25 AM UTC 24 Aug 25 06:44:33 AM UTC 24 2036444488 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3844012003 Aug 25 06:44:28 AM UTC 24 Aug 25 06:44:35 AM UTC 24 2045475026 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1980755602 Aug 25 06:44:23 AM UTC 24 Aug 25 06:44:36 AM UTC 24 9847810834 ps
T342 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3678204001 Aug 25 06:44:23 AM UTC 24 Aug 25 06:44:36 AM UTC 24 2061991591 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3488121646 Aug 25 06:44:29 AM UTC 24 Aug 25 06:44:36 AM UTC 24 2044429757 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2446038478 Aug 25 06:44:26 AM UTC 24 Aug 25 06:44:37 AM UTC 24 2013011383 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3987445562 Aug 25 06:44:07 AM UTC 24 Aug 25 06:44:41 AM UTC 24 6838154169 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3938968762 Aug 25 06:44:14 AM UTC 24 Aug 25 06:44:41 AM UTC 24 5028880022 ps
T395 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3878964385 Aug 25 06:43:29 AM UTC 24 Aug 25 06:44:42 AM UTC 24 62454050487 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2804734130 Aug 25 06:44:37 AM UTC 24 Aug 25 06:44:42 AM UTC 24 5433361935 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.355037145 Aug 25 06:44:31 AM UTC 24 Aug 25 06:44:43 AM UTC 24 2013994698 ps
T397 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2956779293 Aug 25 06:44:06 AM UTC 24 Aug 25 06:44:43 AM UTC 24 38498189019 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3326323880 Aug 25 06:44:17 AM UTC 24 Aug 25 06:44:43 AM UTC 24 9452653961 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3391372243 Aug 25 06:44:33 AM UTC 24 Aug 25 06:44:43 AM UTC 24 2030831083 ps
T316 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4114730222 Aug 25 06:44:30 AM UTC 24 Aug 25 06:44:43 AM UTC 24 2028599521 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.905712484 Aug 25 06:44:36 AM UTC 24 Aug 25 06:44:44 AM UTC 24 2100493022 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1094465399 Aug 25 06:44:42 AM UTC 24 Aug 25 06:44:45 AM UTC 24 2059228035 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.957916734 Aug 25 06:44:39 AM UTC 24 Aug 25 06:44:46 AM UTC 24 2638798101 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1835196877 Aug 25 06:44:45 AM UTC 24 Aug 25 06:44:47 AM UTC 24 2430714490 ps
T398 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1028335382 Aug 25 06:44:43 AM UTC 24 Aug 25 06:44:48 AM UTC 24 2211638768 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3794786099 Aug 25 06:44:37 AM UTC 24 Aug 25 06:44:50 AM UTC 24 2032480859 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.102632805 Aug 25 06:44:36 AM UTC 24 Aug 25 06:44:50 AM UTC 24 2025078620 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.137152294 Aug 25 06:44:37 AM UTC 24 Aug 25 06:44:50 AM UTC 24 2082290397 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.95851282 Aug 25 06:44:43 AM UTC 24 Aug 25 06:44:51 AM UTC 24 2246066855 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1157296557 Aug 25 06:44:37 AM UTC 24 Aug 25 06:44:51 AM UTC 24 2015857222 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.282680434 Aug 25 06:44:01 AM UTC 24 Aug 25 06:44:52 AM UTC 24 7862474566 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3801580594 Aug 25 06:44:48 AM UTC 24 Aug 25 06:44:53 AM UTC 24 2069588494 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.967328347 Aug 25 06:44:49 AM UTC 24 Aug 25 06:44:53 AM UTC 24 4626597519 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1143145797 Aug 25 06:44:43 AM UTC 24 Aug 25 06:44:54 AM UTC 24 2014239515 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2780215865 Aug 25 06:44:43 AM UTC 24 Aug 25 06:44:54 AM UTC 24 2045826551 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2575780157 Aug 25 06:44:47 AM UTC 24 Aug 25 06:44:57 AM UTC 24 2058068422 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2289389239 Aug 25 06:44:50 AM UTC 24 Aug 25 06:44:57 AM UTC 24 2416006891 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2014042421 Aug 25 06:44:44 AM UTC 24 Aug 25 06:44:57 AM UTC 24 2028903668 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3548317399 Aug 25 06:44:48 AM UTC 24 Aug 25 06:44:58 AM UTC 24 2014654922 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2867394461 Aug 25 06:44:34 AM UTC 24 Aug 25 06:44:59 AM UTC 24 4793053051 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.603598590 Aug 25 06:44:54 AM UTC 24 Aug 25 06:44:59 AM UTC 24 2225749800 ps
T306 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3514226415 Aug 25 06:44:26 AM UTC 24 Aug 25 06:45:00 AM UTC 24 22252463184 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2959782007 Aug 25 06:44:58 AM UTC 24 Aug 25 06:45:01 AM UTC 24 2089937378 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3467449477 Aug 25 06:44:31 AM UTC 24 Aug 25 06:45:02 AM UTC 24 22251399887 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1730022687 Aug 25 06:44:15 AM UTC 24 Aug 25 06:45:02 AM UTC 24 22285207979 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4041286325 Aug 25 06:44:58 AM UTC 24 Aug 25 06:45:02 AM UTC 24 2540274716 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1337940401 Aug 25 06:44:55 AM UTC 24 Aug 25 06:45:02 AM UTC 24 2074086871 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.943694697 Aug 25 06:44:55 AM UTC 24 Aug 25 06:45:02 AM UTC 24 2021913264 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2001697326 Aug 25 06:44:50 AM UTC 24 Aug 25 06:45:03 AM UTC 24 2048909098 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.498943463 Aug 25 06:44:52 AM UTC 24 Aug 25 06:45:03 AM UTC 24 2014920401 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.41986641 Aug 25 06:44:52 AM UTC 24 Aug 25 06:45:04 AM UTC 24 2030894009 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.919046887 Aug 25 06:44:53 AM UTC 24 Aug 25 06:45:05 AM UTC 24 2065793882 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.513403812 Aug 25 06:44:56 AM UTC 24 Aug 25 06:45:05 AM UTC 24 2066944602 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2071824180 Aug 25 06:45:00 AM UTC 24 Aug 25 06:45:05 AM UTC 24 2090339096 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3181759235 Aug 25 06:44:29 AM UTC 24 Aug 25 06:45:06 AM UTC 24 6706117684 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1695222610 Aug 25 06:45:04 AM UTC 24 Aug 25 06:45:07 AM UTC 24 2275010183 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1188886643 Aug 25 06:45:03 AM UTC 24 Aug 25 06:45:08 AM UTC 24 2065005121 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.841800481 Aug 25 06:44:45 AM UTC 24 Aug 25 06:45:10 AM UTC 24 4505119431 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2752748736 Aug 25 06:44:58 AM UTC 24 Aug 25 06:45:10 AM UTC 24 2029769384 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3290979021 Aug 25 06:44:59 AM UTC 24 Aug 25 06:45:11 AM UTC 24 9207917622 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1945222620 Aug 25 06:45:05 AM UTC 24 Aug 25 06:45:11 AM UTC 24 2152154192 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2505435352 Aug 25 06:45:04 AM UTC 24 Aug 25 06:45:11 AM UTC 24 2022189725 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3379810147 Aug 25 06:44:52 AM UTC 24 Aug 25 06:45:12 AM UTC 24 5019006562 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2658163 Aug 25 06:45:00 AM UTC 24 Aug 25 06:45:12 AM UTC 24 2011341075 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1461180297 Aug 25 06:45:07 AM UTC 24 Aug 25 06:45:12 AM UTC 24 2106531786 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.938145636 Aug 25 06:45:00 AM UTC 24 Aug 25 06:45:13 AM UTC 24 2081606867 ps
T374 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.123340066 Aug 25 06:44:54 AM UTC 24 Aug 25 06:45:50 AM UTC 24 22329541924 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4071388413 Aug 25 06:45:09 AM UTC 24 Aug 25 06:45:13 AM UTC 24 2058021356 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.386640111 Aug 25 06:45:04 AM UTC 24 Aug 25 06:45:13 AM UTC 24 9966466131 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.922874645 Aug 25 06:45:03 AM UTC 24 Aug 25 06:45:13 AM UTC 24 2038063899 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.643536931 Aug 25 06:45:10 AM UTC 24 Aug 25 06:45:14 AM UTC 24 2042591306 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.418289748 Aug 25 06:45:12 AM UTC 24 Aug 25 06:45:15 AM UTC 24 2046973486 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.510905825 Aug 25 06:45:12 AM UTC 24 Aug 25 06:45:16 AM UTC 24 2035439232 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3799817413 Aug 25 06:45:09 AM UTC 24 Aug 25 06:45:16 AM UTC 24 2019023533 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1179595050 Aug 25 06:45:07 AM UTC 24 Aug 25 06:45:17 AM UTC 24 2011176363 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1165569812 Aug 25 06:45:05 AM UTC 24 Aug 25 06:45:18 AM UTC 24 2042204471 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2309378501 Aug 25 06:45:12 AM UTC 24 Aug 25 06:45:18 AM UTC 24 2023016659 ps
T375 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1813655698 Aug 25 06:44:51 AM UTC 24 Aug 25 06:45:19 AM UTC 24 22385380191 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2159499320 Aug 25 06:45:03 AM UTC 24 Aug 25 06:45:19 AM UTC 24 2049735090 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3760847213 Aug 25 06:45:14 AM UTC 24 Aug 25 06:45:19 AM UTC 24 2041829013 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1696836776 Aug 25 06:45:08 AM UTC 24 Aug 25 06:45:19 AM UTC 24 2016822407 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2248456625 Aug 25 06:45:16 AM UTC 24 Aug 25 06:45:20 AM UTC 24 2047292446 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1482446494 Aug 25 06:45:16 AM UTC 24 Aug 25 06:45:20 AM UTC 24 2045297627 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.189024757 Aug 25 06:45:13 AM UTC 24 Aug 25 06:45:21 AM UTC 24 2015854966 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3087084780 Aug 25 06:45:16 AM UTC 24 Aug 25 06:45:21 AM UTC 24 2029588252 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3230708275 Aug 25 06:45:08 AM UTC 24 Aug 25 06:45:21 AM UTC 24 2048429276 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1841879874 Aug 25 06:45:17 AM UTC 24 Aug 25 06:45:21 AM UTC 24 2028039785 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1680767286 Aug 25 06:45:14 AM UTC 24 Aug 25 06:45:22 AM UTC 24 2018301499 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1243839600 Aug 25 06:45:14 AM UTC 24 Aug 25 06:45:22 AM UTC 24 2024223112 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3770713014 Aug 25 06:43:39 AM UTC 24 Aug 25 06:45:22 AM UTC 24 20716741393 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.743941127 Aug 25 06:45:12 AM UTC 24 Aug 25 06:45:22 AM UTC 24 2014025236 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1176818172 Aug 25 06:45:18 AM UTC 24 Aug 25 06:45:23 AM UTC 24 2030650602 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1776290768 Aug 25 06:45:17 AM UTC 24 Aug 25 06:45:23 AM UTC 24 2023116180 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2595841065 Aug 25 06:45:13 AM UTC 24 Aug 25 06:45:24 AM UTC 24 2012567834 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3233403126 Aug 25 06:45:20 AM UTC 24 Aug 25 06:45:25 AM UTC 24 2032423277 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.494528821 Aug 25 06:45:13 AM UTC 24 Aug 25 06:45:25 AM UTC 24 2014855217 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3103264369 Aug 25 06:45:20 AM UTC 24 Aug 25 06:45:25 AM UTC 24 2032145109 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1456289758 Aug 25 06:45:20 AM UTC 24 Aug 25 06:45:26 AM UTC 24 2020408216 ps
T376 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1718131932 Aug 25 06:44:58 AM UTC 24 Aug 25 06:45:26 AM UTC 24 22446673144 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.48897587 Aug 25 06:45:13 AM UTC 24 Aug 25 06:45:26 AM UTC 24 2015449838 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2974724024 Aug 25 06:45:14 AM UTC 24 Aug 25 06:45:26 AM UTC 24 2012475594 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1566149283 Aug 25 06:45:20 AM UTC 24 Aug 25 06:45:27 AM UTC 24 2023745962 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1068274389 Aug 25 06:45:17 AM UTC 24 Aug 25 06:45:27 AM UTC 24 2013934602 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.4047210398 Aug 25 06:45:20 AM UTC 24 Aug 25 06:45:27 AM UTC 24 2015408354 ps
T377 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.35518179 Aug 25 06:44:42 AM UTC 24 Aug 25 06:45:29 AM UTC 24 42793636608 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.399841185 Aug 25 06:44:43 AM UTC 24 Aug 25 06:45:29 AM UTC 24 9769570822 ps
T897 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3758820125 Aug 25 06:45:18 AM UTC 24 Aug 25 06:45:30 AM UTC 24 2012687760 ps
T898 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.255294017 Aug 25 06:45:03 AM UTC 24 Aug 25 06:45:33 AM UTC 24 9233847049 ps
T899 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2763820746 Aug 25 06:45:20 AM UTC 24 Aug 25 06:45:33 AM UTC 24 2010862105 ps
T900 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3589366645 Aug 25 06:43:47 AM UTC 24 Aug 25 06:45:38 AM UTC 24 42620132124 ps
T901 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1354653738 Aug 25 06:44:56 AM UTC 24 Aug 25 06:45:39 AM UTC 24 8478622392 ps
T902 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2261281800 Aug 25 06:44:47 AM UTC 24 Aug 25 06:45:41 AM UTC 24 42540974007 ps
T903 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1485677326 Aug 25 06:45:07 AM UTC 24 Aug 25 06:45:46 AM UTC 24 8012428987 ps
T904 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.606263590 Aug 25 06:45:07 AM UTC 24 Aug 25 06:45:50 AM UTC 24 43143751247 ps
T378 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2751839220 Aug 25 06:45:04 AM UTC 24 Aug 25 06:45:52 AM UTC 24 22289840155 ps
T905 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1586820061 Aug 25 06:44:22 AM UTC 24 Aug 25 06:45:56 AM UTC 24 22228054414 ps
T906 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3490671348 Aug 25 06:45:00 AM UTC 24 Aug 25 06:45:57 AM UTC 24 22282368575 ps
T907 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2347728113 Aug 25 06:44:36 AM UTC 24 Aug 25 06:46:05 AM UTC 24 22190563953 ps
T908 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.587474052 Aug 25 06:44:43 AM UTC 24 Aug 25 06:46:19 AM UTC 24 22252500060 ps
T909 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2935976031 Aug 25 06:43:55 AM UTC 24 Aug 25 06:46:45 AM UTC 24 42355574356 ps
T910 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3512280691 Aug 25 06:44:02 AM UTC 24 Aug 25 06:46:47 AM UTC 24 42360153205 ps
T911 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.517123468 Aug 25 06:44:08 AM UTC 24 Aug 25 06:46:51 AM UTC 24 42464879943 ps
T912 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.4291118006 Aug 25 06:44:00 AM UTC 24 Aug 25 06:47:19 AM UTC 24 37994374023 ps
T913 /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1588748095 Aug 25 06:43:49 AM UTC 24 Aug 25 06:47:32 AM UTC 24 75433291214 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.2664273771
Short name T18
Test name
Test status
Simulation time 2230584728 ps
CPU time 5.96 seconds
Started Aug 25 06:29:46 AM UTC 24
Finished Aug 25 06:29:53 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2664273771 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.2664273771
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.921216753
Short name T11
Test name
Test status
Simulation time 37025362924 ps
CPU time 13.15 seconds
Started Aug 25 06:29:53 AM UTC 24
Finished Aug 25 06:30:07 AM UTC 24
Peak memory 210000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921216753 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.921216753
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_feature_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.187949334
Short name T72
Test name
Test status
Simulation time 15102611095 ps
CPU time 16.59 seconds
Started Aug 25 06:30:18 AM UTC 24
Finished Aug 25 06:30:36 AM UTC 24
Peak memory 220532 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=187949334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.187949334
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3334963021
Short name T27
Test name
Test status
Simulation time 2515282952 ps
CPU time 8.01 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:29:54 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334963021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3334963021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.411520566
Short name T37
Test name
Test status
Simulation time 59735757926 ps
CPU time 122.53 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:31:50 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411520566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_with_pre_cond.411520566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.727063956
Short name T48
Test name
Test status
Simulation time 17548463004 ps
CPU time 18.76 seconds
Started Aug 25 06:30:43 AM UTC 24
Finished Aug 25 06:31:03 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727063956 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.727063956
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.616688944
Short name T304
Test name
Test status
Simulation time 22274744549 ps
CPU time 24.66 seconds
Started Aug 25 06:43:33 AM UTC 24
Finished Aug 25 06:43:59 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=616688944 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.616688944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.3534528436
Short name T107
Test name
Test status
Simulation time 197081342120 ps
CPU time 220.51 seconds
Started Aug 25 06:31:29 AM UTC 24
Finished Aug 25 06:35:13 AM UTC 24
Peak memory 210224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534528436 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.3534528436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.923159914
Short name T75
Test name
Test status
Simulation time 13879932718 ps
CPU time 27.8 seconds
Started Aug 25 06:30:32 AM UTC 24
Finished Aug 25 06:31:01 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=923159914 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.923159914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.90237301
Short name T119
Test name
Test status
Simulation time 67071514683 ps
CPU time 49.89 seconds
Started Aug 25 06:32:39 AM UTC 24
Finished Aug 25 06:33:31 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90237301 -assert nopostproc +UVM_TESTNA
ME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.90237301
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.579392046
Short name T45
Test name
Test status
Simulation time 7919863177 ps
CPU time 11.89 seconds
Started Aug 25 06:30:43 AM UTC 24
Finished Aug 25 06:30:56 AM UTC 24
Peak memory 210396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=579392046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.579392046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2709541395
Short name T39
Test name
Test status
Simulation time 71285001034 ps
CPU time 77.86 seconds
Started Aug 25 06:30:28 AM UTC 24
Finished Aug 25 06:31:48 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709541395 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.2709541395
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3263462046
Short name T355
Test name
Test status
Simulation time 82781335416 ps
CPU time 165.54 seconds
Started Aug 25 06:32:55 AM UTC 24
Finished Aug 25 06:35:44 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3263462046 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.3263462046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.414056566
Short name T28
Test name
Test status
Simulation time 3170604539 ps
CPU time 7.37 seconds
Started Aug 25 06:30:02 AM UTC 24
Finished Aug 25 06:30:10 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414056566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.414056566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1356926958
Short name T101
Test name
Test status
Simulation time 25770297985 ps
CPU time 26.43 seconds
Started Aug 25 06:34:35 AM UTC 24
Finished Aug 25 06:35:03 AM UTC 24
Peak memory 220480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1356926958 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.1356926958
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.1048444776
Short name T31
Test name
Test status
Simulation time 44801947307 ps
CPU time 38.18 seconds
Started Aug 25 06:30:58 AM UTC 24
Finished Aug 25 06:31:38 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048444776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_with_pre_cond.1048444776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.2562097485
Short name T3
Test name
Test status
Simulation time 4067943234 ps
CPU time 8.42 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:29:55 AM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2562097485 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.2562097485
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.764189983
Short name T181
Test name
Test status
Simulation time 3092516059 ps
CPU time 4.37 seconds
Started Aug 25 06:40:14 AM UTC 24
Finished Aug 25 06:40:19 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764189983 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.764189983
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.18331359
Short name T178
Test name
Test status
Simulation time 42126127899 ps
CPU time 47.16 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:30:34 AM UTC 24
Peak memory 240344 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18331359 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.18331359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.168680442
Short name T282
Test name
Test status
Simulation time 44289778421 ps
CPU time 198.02 seconds
Started Aug 25 06:37:09 AM UTC 24
Finished Aug 25 06:40:30 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168680442 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.168680442
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.1362371711
Short name T301
Test name
Test status
Simulation time 2043942750 ps
CPU time 13.48 seconds
Started Aug 25 06:43:20 AM UTC 24
Finished Aug 25 06:43:35 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1362371711 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.1362371711
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.229021589
Short name T92
Test name
Test status
Simulation time 14307674389 ps
CPU time 55.9 seconds
Started Aug 25 06:33:37 AM UTC 24
Finished Aug 25 06:34:35 AM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=229021589 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.229021589
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.481376932
Short name T180
Test name
Test status
Simulation time 2357848563 ps
CPU time 6.01 seconds
Started Aug 25 06:40:01 AM UTC 24
Finished Aug 25 06:40:08 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=481376932 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.481376932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.563972239
Short name T9
Test name
Test status
Simulation time 10155567232 ps
CPU time 10.39 seconds
Started Aug 25 06:29:51 AM UTC 24
Finished Aug 25 06:30:03 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=563972239 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.563972239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.1748179824
Short name T166
Test name
Test status
Simulation time 5033599973 ps
CPU time 10.13 seconds
Started Aug 25 06:32:56 AM UTC 24
Finished Aug 25 06:33:07 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1748179824 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.1748179824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3019960994
Short name T32
Test name
Test status
Simulation time 2071526333 ps
CPU time 4.03 seconds
Started Aug 25 06:43:27 AM UTC 24
Finished Aug 25 06:43:32 AM UTC 24
Peak memory 211004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3019960994 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.3019960994
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.2425045046
Short name T164
Test name
Test status
Simulation time 18310926750 ps
CPU time 9.31 seconds
Started Aug 25 06:31:48 AM UTC 24
Finished Aug 25 06:31:59 AM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2425045046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.2425045046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.492972985
Short name T65
Test name
Test status
Simulation time 6348657954 ps
CPU time 5.65 seconds
Started Aug 25 06:31:41 AM UTC 24
Finished Aug 25 06:31:48 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=492972985 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.492972985
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.3374803290
Short name T299
Test name
Test status
Simulation time 164895059524 ps
CPU time 145.38 seconds
Started Aug 25 06:31:12 AM UTC 24
Finished Aug 25 06:33:40 AM UTC 24
Peak memory 210216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3374803290 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.3374803290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.3514226415
Short name T306
Test name
Test status
Simulation time 22252463184 ps
CPU time 32.34 seconds
Started Aug 25 06:44:26 AM UTC 24
Finished Aug 25 06:45:00 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3514226415 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.3514226415
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.3993917553
Short name T346
Test name
Test status
Simulation time 1173729978399 ps
CPU time 222.96 seconds
Started Aug 25 06:34:37 AM UTC 24
Finished Aug 25 06:38:23 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3993917553 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.3993917553
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.2643405493
Short name T104
Test name
Test status
Simulation time 8172267269 ps
CPU time 30.21 seconds
Started Aug 25 06:38:12 AM UTC 24
Finished Aug 25 06:38:44 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2643405493 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.2643405493
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.910404725
Short name T222
Test name
Test status
Simulation time 2824683642 ps
CPU time 12.16 seconds
Started Aug 25 06:37:22 AM UTC 24
Finished Aug 25 06:37:36 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=910404725 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.910404725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.214300428
Short name T175
Test name
Test status
Simulation time 3806877448 ps
CPU time 9.3 seconds
Started Aug 25 06:39:22 AM UTC 24
Finished Aug 25 06:39:33 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214300428 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.214300428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.2447427952
Short name T100
Test name
Test status
Simulation time 128344451616 ps
CPU time 320.61 seconds
Started Aug 25 06:36:18 AM UTC 24
Finished Aug 25 06:41:44 AM UTC 24
Peak memory 210632 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2447427952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_with_pre_cond.2447427952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.4020260314
Short name T171
Test name
Test status
Simulation time 3853564415 ps
CPU time 5.37 seconds
Started Aug 25 06:35:04 AM UTC 24
Finished Aug 25 06:35:11 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020260314 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.4020260314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.1425562106
Short name T201
Test name
Test status
Simulation time 3241155554 ps
CPU time 3.48 seconds
Started Aug 25 06:37:09 AM UTC 24
Finished Aug 25 06:37:14 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425562106 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.1425562106
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.8539213
Short name T192
Test name
Test status
Simulation time 14667374636 ps
CPU time 15.67 seconds
Started Aug 25 06:39:52 AM UTC 24
Finished Aug 25 06:40:09 AM UTC 24
Peak memory 220408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=8539213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/
null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.8539213
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.1818233315
Short name T215
Test name
Test status
Simulation time 69079533374 ps
CPU time 7.37 seconds
Started Aug 25 06:33:29 AM UTC 24
Finished Aug 25 06:33:37 AM UTC 24
Peak memory 220724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1818233315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.1818233315
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1053734319
Short name T368
Test name
Test status
Simulation time 112424227975 ps
CPU time 120.56 seconds
Started Aug 25 06:41:19 AM UTC 24
Finished Aug 25 06:43:22 AM UTC 24
Peak memory 210312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053734319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_with_pre_cond.1053734319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.3121430254
Short name T17
Test name
Test status
Simulation time 2621349983 ps
CPU time 5.69 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:29:52 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3121430254 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.3121430254
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.460108676
Short name T363
Test name
Test status
Simulation time 79453682294 ps
CPU time 85.41 seconds
Started Aug 25 06:43:15 AM UTC 24
Finished Aug 25 06:44:42 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=460108676 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_with_pre_cond.460108676
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.752217690
Short name T206
Test name
Test status
Simulation time 2013524586 ps
CPU time 9.31 seconds
Started Aug 25 06:30:05 AM UTC 24
Finished Aug 25 06:30:15 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=752217690 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.752217690
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.123149025
Short name T41
Test name
Test status
Simulation time 93813204117 ps
CPU time 112.87 seconds
Started Aug 25 06:30:37 AM UTC 24
Finished Aug 25 06:32:33 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123149025 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.123149025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.615838127
Short name T30
Test name
Test status
Simulation time 39009427158 ps
CPU time 49.01 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:30:36 AM UTC 24
Peak memory 210000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615838127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.615838127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3030960806
Short name T22
Test name
Test status
Simulation time 6893410078 ps
CPU time 46.36 seconds
Started Aug 25 06:43:29 AM UTC 24
Finished Aug 25 06:44:17 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3030960806 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.3030960806
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3686799382
Short name T354
Test name
Test status
Simulation time 183610814332 ps
CPU time 48.63 seconds
Started Aug 25 06:34:24 AM UTC 24
Finished Aug 25 06:35:14 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686799382 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.3686799382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.3491780034
Short name T79
Test name
Test status
Simulation time 2510523908 ps
CPU time 12.64 seconds
Started Aug 25 06:30:12 AM UTC 24
Finished Aug 25 06:30:26 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491780034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.3491780034
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.957916734
Short name T819
Test name
Test status
Simulation time 2638798101 ps
CPU time 6.13 seconds
Started Aug 25 06:44:39 AM UTC 24
Finished Aug 25 06:44:46 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957916734 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.957916734
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3782290935
Short name T380
Test name
Test status
Simulation time 135727779053 ps
CPU time 642.13 seconds
Started Aug 25 06:33:47 AM UTC 24
Finished Aug 25 06:44:37 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782290935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_with_pre_cond.3782290935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.777102419
Short name T370
Test name
Test status
Simulation time 81239643970 ps
CPU time 392.09 seconds
Started Aug 25 06:35:53 AM UTC 24
Finished Aug 25 06:42:31 AM UTC 24
Peak memory 210332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=777102419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_with_pre_cond.777102419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.1372872875
Short name T360
Test name
Test status
Simulation time 81167456894 ps
CPU time 405.21 seconds
Started Aug 25 06:36:56 AM UTC 24
Finished Aug 25 06:43:46 AM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1372872875 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.1372872875
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.95881166
Short name T371
Test name
Test status
Simulation time 134874019883 ps
CPU time 537.3 seconds
Started Aug 25 06:38:25 AM UTC 24
Finished Aug 25 06:47:29 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95881166 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.95881166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.562099404
Short name T51
Test name
Test status
Simulation time 19671647554 ps
CPU time 18.24 seconds
Started Aug 25 06:29:54 AM UTC 24
Finished Aug 25 06:30:14 AM UTC 24
Peak memory 220524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=562099404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.562099404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.1502731699
Short name T137
Test name
Test status
Simulation time 3527524084 ps
CPU time 18.73 seconds
Started Aug 25 06:32:32 AM UTC 24
Finished Aug 25 06:32:52 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502731699 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.1502731699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1818458064
Short name T86
Test name
Test status
Simulation time 122432365850 ps
CPU time 67.07 seconds
Started Aug 25 06:33:15 AM UTC 24
Finished Aug 25 06:34:24 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1818458064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_with_pre_cond.1818458064
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3117424484
Short name T38
Test name
Test status
Simulation time 70186860220 ps
CPU time 176.09 seconds
Started Aug 25 06:30:16 AM UTC 24
Finished Aug 25 06:33:15 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3117424484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_with_pre_cond.3117424484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.2364670295
Short name T367
Test name
Test status
Simulation time 78875310595 ps
CPU time 100.89 seconds
Started Aug 25 06:37:23 AM UTC 24
Finished Aug 25 06:39:07 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2364670295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_with_pre_cond.2364670295
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3003071109
Short name T372
Test name
Test status
Simulation time 114878402317 ps
CPU time 164.72 seconds
Started Aug 25 06:41:13 AM UTC 24
Finished Aug 25 06:44:00 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3003071109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_with_pre_cond.3003071109
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1683410776
Short name T353
Test name
Test status
Simulation time 154869581744 ps
CPU time 174.69 seconds
Started Aug 25 06:42:07 AM UTC 24
Finished Aug 25 06:45:05 AM UTC 24
Peak memory 210312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683410776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_with_pre_cond.1683410776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.35518179
Short name T377
Test name
Test status
Simulation time 42793636608 ps
CPU time 45.37 seconds
Started Aug 25 06:44:42 AM UTC 24
Finished Aug 25 06:45:29 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35518179 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.35518179
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.1137866360
Short name T76
Test name
Test status
Simulation time 2510173598 ps
CPU time 14.33 seconds
Started Aug 25 06:29:48 AM UTC 24
Finished Aug 25 06:30:04 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137866360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.1137866360
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.78650786
Short name T408
Test name
Test status
Simulation time 608239414640 ps
CPU time 78.54 seconds
Started Aug 25 06:33:11 AM UTC 24
Finished Aug 25 06:34:32 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78650786 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.78650786
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.459194176
Short name T142
Test name
Test status
Simulation time 2364665954549 ps
CPU time 48.69 seconds
Started Aug 25 06:34:23 AM UTC 24
Finished Aug 25 06:35:13 AM UTC 24
Peak memory 220460 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=459194176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.459194176
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.727008798
Short name T777
Test name
Test status
Simulation time 107216550783 ps
CPU time 515.38 seconds
Started Aug 25 06:35:28 AM UTC 24
Finished Aug 25 06:44:09 AM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727008798 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.727008798
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.1312763432
Short name T257
Test name
Test status
Simulation time 66077879486 ps
CPU time 266.44 seconds
Started Aug 25 06:35:41 AM UTC 24
Finished Aug 25 06:40:12 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1312763432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_with_pre_cond.1312763432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3447201135
Short name T405
Test name
Test status
Simulation time 54814128613 ps
CPU time 132.13 seconds
Started Aug 25 06:40:54 AM UTC 24
Finished Aug 25 06:43:09 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3447201135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_with_pre_cond.3447201135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.2611380370
Short name T404
Test name
Test status
Simulation time 42150072864 ps
CPU time 46.2 seconds
Started Aug 25 06:41:08 AM UTC 24
Finished Aug 25 06:41:56 AM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2611380370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_with_pre_cond.2611380370
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.3277515652
Short name T384
Test name
Test status
Simulation time 109559615392 ps
CPU time 511.15 seconds
Started Aug 25 06:30:40 AM UTC 24
Finished Aug 25 06:39:18 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3277515652 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_with_pre_cond.3277515652
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2243041016
Short name T352
Test name
Test status
Simulation time 111124398590 ps
CPU time 34.36 seconds
Started Aug 25 06:41:26 AM UTC 24
Finished Aug 25 06:42:01 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243041016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_with_pre_cond.2243041016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1211053834
Short name T403
Test name
Test status
Simulation time 48419528760 ps
CPU time 102.75 seconds
Started Aug 25 06:41:29 AM UTC 24
Finished Aug 25 06:43:14 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211053834 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_with_pre_cond.1211053834
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.1258041627
Short name T383
Test name
Test status
Simulation time 216862036882 ps
CPU time 176.31 seconds
Started Aug 25 06:41:58 AM UTC 24
Finished Aug 25 06:44:57 AM UTC 24
Peak memory 210316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1258041627 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_with_pre_cond.1258041627
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.2673579026
Short name T382
Test name
Test status
Simulation time 83581099450 ps
CPU time 191.35 seconds
Started Aug 25 06:42:04 AM UTC 24
Finished Aug 25 06:45:19 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673579026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_with_pre_cond.2673579026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.2773297723
Short name T373
Test name
Test status
Simulation time 106794217909 ps
CPU time 123.67 seconds
Started Aug 25 06:42:40 AM UTC 24
Finished Aug 25 06:44:46 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773297723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_with_pre_cond.2773297723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.964637385
Short name T386
Test name
Test status
Simulation time 74957817484 ps
CPU time 93.62 seconds
Started Aug 25 06:43:18 AM UTC 24
Finished Aug 25 06:44:54 AM UTC 24
Peak memory 210520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=964637385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_with_pre_cond.964637385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.102632805
Short name T822
Test name
Test status
Simulation time 2025078620 ps
CPU time 12.37 seconds
Started Aug 25 06:44:36 AM UTC 24
Finished Aug 25 06:44:50 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=102632805 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.102632805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.4091472791
Short name T278
Test name
Test status
Simulation time 55414346452 ps
CPU time 57.95 seconds
Started Aug 25 06:42:49 AM UTC 24
Finished Aug 25 06:43:48 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4091472791 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_with_pre_cond.4091472791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2782805926
Short name T34
Test name
Test status
Simulation time 2419925368 ps
CPU time 9.53 seconds
Started Aug 25 06:43:29 AM UTC 24
Finished Aug 25 06:43:40 AM UTC 24
Peak memory 211324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2782805926 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.2782805926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.3878964385
Short name T395
Test name
Test status
Simulation time 62454050487 ps
CPU time 70.52 seconds
Started Aug 25 06:43:29 AM UTC 24
Finished Aug 25 06:44:42 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878964385 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.3878964385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1405962423
Short name T33
Test name
Test status
Simulation time 4027243146 ps
CPU time 11.13 seconds
Started Aug 25 06:43:24 AM UTC 24
Finished Aug 25 06:43:37 AM UTC 24
Peak memory 211004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1405962423 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.1405962423
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.4247206967
Short name T319
Test name
Test status
Simulation time 2054598308 ps
CPU time 6.91 seconds
Started Aug 25 06:43:33 AM UTC 24
Finished Aug 25 06:43:41 AM UTC 24
Peak memory 210880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4247206967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_csr_mem_rw_with_rand_reset.4247206967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.3319703175
Short name T795
Test name
Test status
Simulation time 2038817658 ps
CPU time 3.28 seconds
Started Aug 25 06:43:23 AM UTC 24
Finished Aug 25 06:43:28 AM UTC 24
Peak memory 210828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319703175 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.3319703175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1229231084
Short name T305
Test name
Test status
Simulation time 42807497713 ps
CPU time 60.92 seconds
Started Aug 25 06:43:22 AM UTC 24
Finished Aug 25 06:44:25 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229231084 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.1229231084
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.2289785631
Short name T334
Test name
Test status
Simulation time 2743127399 ps
CPU time 5.63 seconds
Started Aug 25 06:43:41 AM UTC 24
Finished Aug 25 06:43:48 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289785631 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.2289785631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3770713014
Short name T882
Test name
Test status
Simulation time 20716741393 ps
CPU time 101.04 seconds
Started Aug 25 06:43:39 AM UTC 24
Finished Aug 25 06:45:22 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3770713014 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.3770713014
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2728043762
Short name T345
Test name
Test status
Simulation time 4013843343 ps
CPU time 22.47 seconds
Started Aug 25 06:43:36 AM UTC 24
Finished Aug 25 06:44:00 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2728043762 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.2728043762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.3518028836
Short name T308
Test name
Test status
Simulation time 2044801175 ps
CPU time 12.34 seconds
Started Aug 25 06:43:42 AM UTC 24
Finished Aug 25 06:43:56 AM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3518028836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_csr_mem_rw_with_rand_reset.3518028836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.3377545273
Short name T335
Test name
Test status
Simulation time 2037385965 ps
CPU time 11.96 seconds
Started Aug 25 06:43:37 AM UTC 24
Finished Aug 25 06:43:51 AM UTC 24
Peak memory 210932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377545273 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.3377545273
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.4153809340
Short name T796
Test name
Test status
Simulation time 2017890084 ps
CPU time 10.73 seconds
Started Aug 25 06:43:35 AM UTC 24
Finished Aug 25 06:43:47 AM UTC 24
Peak memory 210676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4153809340 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.4153809340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.4242388108
Short name T21
Test name
Test status
Simulation time 7547719453 ps
CPU time 10.77 seconds
Started Aug 25 06:43:42 AM UTC 24
Finished Aug 25 06:43:54 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242388108 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.4242388108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.3033478320
Short name T302
Test name
Test status
Simulation time 2081817983 ps
CPU time 12.2 seconds
Started Aug 25 06:43:33 AM UTC 24
Finished Aug 25 06:43:47 AM UTC 24
Peak memory 211192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033478320 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.3033478320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.137152294
Short name T823
Test name
Test status
Simulation time 2082290397 ps
CPU time 11.49 seconds
Started Aug 25 06:44:37 AM UTC 24
Finished Aug 25 06:44:50 AM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=137152294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10
.sysrst_ctrl_csr_mem_rw_with_rand_reset.137152294
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.3794786099
Short name T821
Test name
Test status
Simulation time 2032480859 ps
CPU time 11.06 seconds
Started Aug 25 06:44:37 AM UTC 24
Finished Aug 25 06:44:50 AM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794786099 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.3794786099
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.1157296557
Short name T825
Test name
Test status
Simulation time 2015857222 ps
CPU time 12.47 seconds
Started Aug 25 06:44:37 AM UTC 24
Finished Aug 25 06:44:51 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1157296557 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.1157296557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.2804734130
Short name T813
Test name
Test status
Simulation time 5433361935 ps
CPU time 3.29 seconds
Started Aug 25 06:44:37 AM UTC 24
Finished Aug 25 06:44:42 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804734130 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.2804734130
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.2347728113
Short name T907
Test name
Test status
Simulation time 22190563953 ps
CPU time 87.16 seconds
Started Aug 25 06:44:36 AM UTC 24
Finished Aug 25 06:46:05 AM UTC 24
Peak memory 211416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2347728113 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.2347728113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.1028335382
Short name T398
Test name
Test status
Simulation time 2211638768 ps
CPU time 3.45 seconds
Started Aug 25 06:44:43 AM UTC 24
Finished Aug 25 06:44:48 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1028335382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
1.sysrst_ctrl_csr_mem_rw_with_rand_reset.1028335382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.2780215865
Short name T830
Test name
Test status
Simulation time 2045826551 ps
CPU time 10.07 seconds
Started Aug 25 06:44:43 AM UTC 24
Finished Aug 25 06:44:54 AM UTC 24
Peak memory 210900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780215865 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.2780215865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.1094465399
Short name T818
Test name
Test status
Simulation time 2059228035 ps
CPU time 2.71 seconds
Started Aug 25 06:44:42 AM UTC 24
Finished Aug 25 06:44:45 AM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1094465399 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.1094465399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.399841185
Short name T896
Test name
Test status
Simulation time 9769570822 ps
CPU time 44.08 seconds
Started Aug 25 06:44:43 AM UTC 24
Finished Aug 25 06:45:29 AM UTC 24
Peak memory 211304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=399841185 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.399841185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.1835196877
Short name T820
Test name
Test status
Simulation time 2430714490 ps
CPU time 1.71 seconds
Started Aug 25 06:44:45 AM UTC 24
Finished Aug 25 06:44:47 AM UTC 24
Peak memory 209740 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1835196877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_csr_mem_rw_with_rand_reset.1835196877
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2014042421
Short name T833
Test name
Test status
Simulation time 2028903668 ps
CPU time 11.46 seconds
Started Aug 25 06:44:44 AM UTC 24
Finished Aug 25 06:44:57 AM UTC 24
Peak memory 211020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2014042421 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.2014042421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1143145797
Short name T829
Test name
Test status
Simulation time 2014239515 ps
CPU time 9.19 seconds
Started Aug 25 06:44:43 AM UTC 24
Finished Aug 25 06:44:54 AM UTC 24
Peak memory 210544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1143145797 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.1143145797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.841800481
Short name T852
Test name
Test status
Simulation time 4505119431 ps
CPU time 23.78 seconds
Started Aug 25 06:44:45 AM UTC 24
Finished Aug 25 06:45:10 AM UTC 24
Peak memory 211312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=841800481 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.841800481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.95851282
Short name T824
Test name
Test status
Simulation time 2246066855 ps
CPU time 6.33 seconds
Started Aug 25 06:44:43 AM UTC 24
Finished Aug 25 06:44:51 AM UTC 24
Peak memory 211276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95851282 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.95851282
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.587474052
Short name T908
Test name
Test status
Simulation time 22252500060 ps
CPU time 93.39 seconds
Started Aug 25 06:44:43 AM UTC 24
Finished Aug 25 06:46:19 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587474052 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.587474052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2001697326
Short name T843
Test name
Test status
Simulation time 2048909098 ps
CPU time 11.41 seconds
Started Aug 25 06:44:50 AM UTC 24
Finished Aug 25 06:45:03 AM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2001697326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2001697326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.3801580594
Short name T827
Test name
Test status
Simulation time 2069588494 ps
CPU time 3.71 seconds
Started Aug 25 06:44:48 AM UTC 24
Finished Aug 25 06:44:53 AM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3801580594 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.3801580594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.3548317399
Short name T834
Test name
Test status
Simulation time 2014654922 ps
CPU time 9.45 seconds
Started Aug 25 06:44:48 AM UTC 24
Finished Aug 25 06:44:58 AM UTC 24
Peak memory 210536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3548317399 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.3548317399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.967328347
Short name T828
Test name
Test status
Simulation time 4626597519 ps
CPU time 3.28 seconds
Started Aug 25 06:44:49 AM UTC 24
Finished Aug 25 06:44:53 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967328347 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.967328347
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.2575780157
Short name T831
Test name
Test status
Simulation time 2058068422 ps
CPU time 8.47 seconds
Started Aug 25 06:44:47 AM UTC 24
Finished Aug 25 06:44:57 AM UTC 24
Peak memory 211124 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2575780157 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.2575780157
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.2261281800
Short name T902
Test name
Test status
Simulation time 42540974007 ps
CPU time 52.96 seconds
Started Aug 25 06:44:47 AM UTC 24
Finished Aug 25 06:45:41 AM UTC 24
Peak memory 211188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2261281800 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.2261281800
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.919046887
Short name T846
Test name
Test status
Simulation time 2065793882 ps
CPU time 11.26 seconds
Started Aug 25 06:44:53 AM UTC 24
Finished Aug 25 06:45:05 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=919046887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14
.sysrst_ctrl_csr_mem_rw_with_rand_reset.919046887
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.41986641
Short name T845
Test name
Test status
Simulation time 2030894009 ps
CPU time 11.34 seconds
Started Aug 25 06:44:52 AM UTC 24
Finished Aug 25 06:45:04 AM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=41986641 -assert nopostproc +UVM_TESTNAME=sy
srst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regres
sion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.41986641
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.498943463
Short name T844
Test name
Test status
Simulation time 2014920401 ps
CPU time 10.43 seconds
Started Aug 25 06:44:52 AM UTC 24
Finished Aug 25 06:45:03 AM UTC 24
Peak memory 210688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498943463 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.498943463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.3379810147
Short name T857
Test name
Test status
Simulation time 5019006562 ps
CPU time 19.36 seconds
Started Aug 25 06:44:52 AM UTC 24
Finished Aug 25 06:45:12 AM UTC 24
Peak memory 211160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3379810147 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.3379810147
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.2289389239
Short name T832
Test name
Test status
Simulation time 2416006891 ps
CPU time 5.78 seconds
Started Aug 25 06:44:50 AM UTC 24
Finished Aug 25 06:44:57 AM UTC 24
Peak memory 221540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289389239 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.2289389239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.1813655698
Short name T375
Test name
Test status
Simulation time 22385380191 ps
CPU time 25.59 seconds
Started Aug 25 06:44:51 AM UTC 24
Finished Aug 25 06:45:19 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813655698 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.1813655698
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.513403812
Short name T847
Test name
Test status
Simulation time 2066944602 ps
CPU time 8.65 seconds
Started Aug 25 06:44:56 AM UTC 24
Finished Aug 25 06:45:05 AM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=513403812 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15
.sysrst_ctrl_csr_mem_rw_with_rand_reset.513403812
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1337940401
Short name T841
Test name
Test status
Simulation time 2074086871 ps
CPU time 5.78 seconds
Started Aug 25 06:44:55 AM UTC 24
Finished Aug 25 06:45:02 AM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337940401 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.1337940401
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.943694697
Short name T842
Test name
Test status
Simulation time 2021913264 ps
CPU time 5.98 seconds
Started Aug 25 06:44:55 AM UTC 24
Finished Aug 25 06:45:02 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=943694697 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.943694697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.1354653738
Short name T901
Test name
Test status
Simulation time 8478622392 ps
CPU time 42.21 seconds
Started Aug 25 06:44:56 AM UTC 24
Finished Aug 25 06:45:39 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1354653738 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.1354653738
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.603598590
Short name T836
Test name
Test status
Simulation time 2225749800 ps
CPU time 4.46 seconds
Started Aug 25 06:44:54 AM UTC 24
Finished Aug 25 06:44:59 AM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=603598590 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.603598590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.123340066
Short name T374
Test name
Test status
Simulation time 22329541924 ps
CPU time 54.25 seconds
Started Aug 25 06:44:54 AM UTC 24
Finished Aug 25 06:45:50 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=123340066 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.123340066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.938145636
Short name T860
Test name
Test status
Simulation time 2081606867 ps
CPU time 11.42 seconds
Started Aug 25 06:45:00 AM UTC 24
Finished Aug 25 06:45:13 AM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=938145636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16
.sysrst_ctrl_csr_mem_rw_with_rand_reset.938145636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2752748736
Short name T853
Test name
Test status
Simulation time 2029769384 ps
CPU time 11.34 seconds
Started Aug 25 06:44:58 AM UTC 24
Finished Aug 25 06:45:10 AM UTC 24
Peak memory 210940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752748736 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.2752748736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.2959782007
Short name T837
Test name
Test status
Simulation time 2089937378 ps
CPU time 2.27 seconds
Started Aug 25 06:44:58 AM UTC 24
Finished Aug 25 06:45:01 AM UTC 24
Peak memory 210600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959782007 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.2959782007
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3290979021
Short name T854
Test name
Test status
Simulation time 9207917622 ps
CPU time 10.54 seconds
Started Aug 25 06:44:59 AM UTC 24
Finished Aug 25 06:45:11 AM UTC 24
Peak memory 211396 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290979021 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.3290979021
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.4041286325
Short name T840
Test name
Test status
Simulation time 2540274716 ps
CPU time 3.15 seconds
Started Aug 25 06:44:58 AM UTC 24
Finished Aug 25 06:45:02 AM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041286325 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.4041286325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.1718131932
Short name T376
Test name
Test status
Simulation time 22446673144 ps
CPU time 26.43 seconds
Started Aug 25 06:44:58 AM UTC 24
Finished Aug 25 06:45:26 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1718131932 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.1718131932
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.922874645
Short name T863
Test name
Test status
Simulation time 2038063899 ps
CPU time 9.46 seconds
Started Aug 25 06:45:03 AM UTC 24
Finished Aug 25 06:45:13 AM UTC 24
Peak memory 210696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=922874645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_csr_mem_rw_with_rand_reset.922874645
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.1188886643
Short name T851
Test name
Test status
Simulation time 2065005121 ps
CPU time 3.89 seconds
Started Aug 25 06:45:03 AM UTC 24
Finished Aug 25 06:45:08 AM UTC 24
Peak memory 210836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1188886643 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.1188886643
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.2658163
Short name T858
Test name
Test status
Simulation time 2011341075 ps
CPU time 10.66 seconds
Started Aug 25 06:45:00 AM UTC 24
Finished Aug 25 06:45:12 AM UTC 24
Peak memory 210672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2658163 -assert nopostproc +UVM_TESTNAME=sysrst
_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.2658163
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.255294017
Short name T898
Test name
Test status
Simulation time 9233847049 ps
CPU time 28.46 seconds
Started Aug 25 06:45:03 AM UTC 24
Finished Aug 25 06:45:33 AM UTC 24
Peak memory 211328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=255294017 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.255294017
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.2071824180
Short name T848
Test name
Test status
Simulation time 2090339096 ps
CPU time 4.19 seconds
Started Aug 25 06:45:00 AM UTC 24
Finished Aug 25 06:45:05 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2071824180 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.2071824180
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.3490671348
Short name T906
Test name
Test status
Simulation time 22282368575 ps
CPU time 55.33 seconds
Started Aug 25 06:45:00 AM UTC 24
Finished Aug 25 06:45:57 AM UTC 24
Peak memory 211268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3490671348 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.3490671348
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.1945222620
Short name T855
Test name
Test status
Simulation time 2152154192 ps
CPU time 4.68 seconds
Started Aug 25 06:45:05 AM UTC 24
Finished Aug 25 06:45:11 AM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1945222620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
8.sysrst_ctrl_csr_mem_rw_with_rand_reset.1945222620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.1695222610
Short name T850
Test name
Test status
Simulation time 2275010183 ps
CPU time 1.9 seconds
Started Aug 25 06:45:04 AM UTC 24
Finished Aug 25 06:45:07 AM UTC 24
Peak memory 209676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695222610 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.1695222610
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.2505435352
Short name T856
Test name
Test status
Simulation time 2022189725 ps
CPU time 6.01 seconds
Started Aug 25 06:45:04 AM UTC 24
Finished Aug 25 06:45:11 AM UTC 24
Peak memory 210536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2505435352 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.2505435352
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.386640111
Short name T862
Test name
Test status
Simulation time 9966466131 ps
CPU time 8.11 seconds
Started Aug 25 06:45:04 AM UTC 24
Finished Aug 25 06:45:13 AM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=386640111 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.386640111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2159499320
Short name T871
Test name
Test status
Simulation time 2049735090 ps
CPU time 14.68 seconds
Started Aug 25 06:45:03 AM UTC 24
Finished Aug 25 06:45:19 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159499320 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.2159499320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.2751839220
Short name T378
Test name
Test status
Simulation time 22289840155 ps
CPU time 46.2 seconds
Started Aug 25 06:45:04 AM UTC 24
Finished Aug 25 06:45:52 AM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2751839220 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.2751839220
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.3230708275
Short name T878
Test name
Test status
Simulation time 2048429276 ps
CPU time 11.91 seconds
Started Aug 25 06:45:08 AM UTC 24
Finished Aug 25 06:45:21 AM UTC 24
Peak memory 211020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3230708275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_csr_mem_rw_with_rand_reset.3230708275
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.1461180297
Short name T859
Test name
Test status
Simulation time 2106531786 ps
CPU time 4.72 seconds
Started Aug 25 06:45:07 AM UTC 24
Finished Aug 25 06:45:12 AM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1461180297 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.1461180297
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.1179595050
Short name T868
Test name
Test status
Simulation time 2011176363 ps
CPU time 9.54 seconds
Started Aug 25 06:45:07 AM UTC 24
Finished Aug 25 06:45:17 AM UTC 24
Peak memory 210544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1179595050 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.1179595050
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.1485677326
Short name T903
Test name
Test status
Simulation time 8012428987 ps
CPU time 38.24 seconds
Started Aug 25 06:45:07 AM UTC 24
Finished Aug 25 06:45:46 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1485677326 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.1485677326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1165569812
Short name T869
Test name
Test status
Simulation time 2042204471 ps
CPU time 11.93 seconds
Started Aug 25 06:45:05 AM UTC 24
Finished Aug 25 06:45:18 AM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1165569812 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.1165569812
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.606263590
Short name T904
Test name
Test status
Simulation time 43143751247 ps
CPU time 42.3 seconds
Started Aug 25 06:45:07 AM UTC 24
Finished Aug 25 06:45:50 AM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=606263590 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.606263590
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.3534838164
Short name T337
Test name
Test status
Simulation time 2945964982 ps
CPU time 12.13 seconds
Started Aug 25 06:43:49 AM UTC 24
Finished Aug 25 06:44:03 AM UTC 24
Peak memory 211232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3534838164 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.3534838164
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.1588748095
Short name T913
Test name
Test status
Simulation time 75433291214 ps
CPU time 218.7 seconds
Started Aug 25 06:43:49 AM UTC 24
Finished Aug 25 06:47:32 AM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588748095 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.1588748095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.126409964
Short name T35
Test name
Test status
Simulation time 4051192869 ps
CPU time 5.42 seconds
Started Aug 25 06:43:48 AM UTC 24
Finished Aug 25 06:43:55 AM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=126409964 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.126409964
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.3523607281
Short name T394
Test name
Test status
Simulation time 2037228507 ps
CPU time 11.79 seconds
Started Aug 25 06:43:52 AM UTC 24
Finished Aug 25 06:44:05 AM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3523607281 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2
.sysrst_ctrl_csr_mem_rw_with_rand_reset.3523607281
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.2655963968
Short name T336
Test name
Test status
Simulation time 2048852241 ps
CPU time 3.58 seconds
Started Aug 25 06:43:48 AM UTC 24
Finished Aug 25 06:43:53 AM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655963968 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.2655963968
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1626221568
Short name T797
Test name
Test status
Simulation time 2012359409 ps
CPU time 11.47 seconds
Started Aug 25 06:43:47 AM UTC 24
Finished Aug 25 06:44:00 AM UTC 24
Peak memory 210664 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1626221568 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.1626221568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1850110418
Short name T23
Test name
Test status
Simulation time 10300931731 ps
CPU time 32.04 seconds
Started Aug 25 06:43:50 AM UTC 24
Finished Aug 25 06:44:24 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1850110418 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.1850110418
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.42987008
Short name T303
Test name
Test status
Simulation time 2122527290 ps
CPU time 13.37 seconds
Started Aug 25 06:43:46 AM UTC 24
Finished Aug 25 06:44:01 AM UTC 24
Peak memory 211340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42987008 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.42987008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.3589366645
Short name T900
Test name
Test status
Simulation time 42620132124 ps
CPU time 108.85 seconds
Started Aug 25 06:43:47 AM UTC 24
Finished Aug 25 06:45:38 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3589366645 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.3589366645
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.1696836776
Short name T873
Test name
Test status
Simulation time 2016822407 ps
CPU time 9.77 seconds
Started Aug 25 06:45:08 AM UTC 24
Finished Aug 25 06:45:19 AM UTC 24
Peak memory 210912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1696836776 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.1696836776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.3799817413
Short name T867
Test name
Test status
Simulation time 2019023533 ps
CPU time 5.46 seconds
Started Aug 25 06:45:09 AM UTC 24
Finished Aug 25 06:45:16 AM UTC 24
Peak memory 210536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3799817413 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.3799817413
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.4071388413
Short name T861
Test name
Test status
Simulation time 2058021356 ps
CPU time 2.88 seconds
Started Aug 25 06:45:09 AM UTC 24
Finished Aug 25 06:45:13 AM UTC 24
Peak memory 210600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4071388413 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.4071388413
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.643536931
Short name T864
Test name
Test status
Simulation time 2042591306 ps
CPU time 2.99 seconds
Started Aug 25 06:45:10 AM UTC 24
Finished Aug 25 06:45:14 AM UTC 24
Peak memory 210600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=643536931 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.643536931
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.743941127
Short name T883
Test name
Test status
Simulation time 2014025236 ps
CPU time 9.79 seconds
Started Aug 25 06:45:12 AM UTC 24
Finished Aug 25 06:45:22 AM UTC 24
Peak memory 210860 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743941127 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.743941127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.418289748
Short name T865
Test name
Test status
Simulation time 2046973486 ps
CPU time 2.71 seconds
Started Aug 25 06:45:12 AM UTC 24
Finished Aug 25 06:45:15 AM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418289748 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.418289748
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.510905825
Short name T866
Test name
Test status
Simulation time 2035439232 ps
CPU time 3.18 seconds
Started Aug 25 06:45:12 AM UTC 24
Finished Aug 25 06:45:16 AM UTC 24
Peak memory 210828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=510905825 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.510905825
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.2309378501
Short name T870
Test name
Test status
Simulation time 2023016659 ps
CPU time 5.64 seconds
Started Aug 25 06:45:12 AM UTC 24
Finished Aug 25 06:45:18 AM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309378501 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.2309378501
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.48897587
Short name T891
Test name
Test status
Simulation time 2015449838 ps
CPU time 11.53 seconds
Started Aug 25 06:45:13 AM UTC 24
Finished Aug 25 06:45:26 AM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=48897587 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.48897587
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.189024757
Short name T876
Test name
Test status
Simulation time 2015854966 ps
CPU time 6.4 seconds
Started Aug 25 06:45:13 AM UTC 24
Finished Aug 25 06:45:21 AM UTC 24
Peak memory 210868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189024757 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.189024757
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.404659926
Short name T309
Test name
Test status
Simulation time 2560526979 ps
CPU time 6.05 seconds
Started Aug 25 06:44:00 AM UTC 24
Finished Aug 25 06:44:08 AM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404659926 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os
_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.404659926
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.4291118006
Short name T912
Test name
Test status
Simulation time 37994374023 ps
CPU time 195.29 seconds
Started Aug 25 06:44:00 AM UTC 24
Finished Aug 25 06:47:19 AM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4291118006 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.4291118006
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3319992518
Short name T340
Test name
Test status
Simulation time 4017748517 ps
CPU time 21.91 seconds
Started Aug 25 06:43:57 AM UTC 24
Finished Aug 25 06:44:21 AM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319992518 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.3319992518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2307228308
Short name T396
Test name
Test status
Simulation time 2228049622 ps
CPU time 3.25 seconds
Started Aug 25 06:44:01 AM UTC 24
Finished Aug 25 06:44:06 AM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2307228308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2307228308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.734085052
Short name T344
Test name
Test status
Simulation time 2030920120 ps
CPU time 12.65 seconds
Started Aug 25 06:44:00 AM UTC 24
Finished Aug 25 06:44:14 AM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=734085052 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.734085052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3590632565
Short name T798
Test name
Test status
Simulation time 2039162656 ps
CPU time 3.31 seconds
Started Aug 25 06:43:56 AM UTC 24
Finished Aug 25 06:44:01 AM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3590632565 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.3590632565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.282680434
Short name T826
Test name
Test status
Simulation time 7862474566 ps
CPU time 48.4 seconds
Started Aug 25 06:44:01 AM UTC 24
Finished Aug 25 06:44:52 AM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282680434 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.282680434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.607606781
Short name T313
Test name
Test status
Simulation time 2056651859 ps
CPU time 12.2 seconds
Started Aug 25 06:43:54 AM UTC 24
Finished Aug 25 06:44:07 AM UTC 24
Peak memory 211308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=607606781 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.607606781
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.2935976031
Short name T909
Test name
Test status
Simulation time 42355574356 ps
CPU time 167.05 seconds
Started Aug 25 06:43:55 AM UTC 24
Finished Aug 25 06:46:45 AM UTC 24
Peak memory 211160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2935976031 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.2935976031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.494528821
Short name T888
Test name
Test status
Simulation time 2014855217 ps
CPU time 10.37 seconds
Started Aug 25 06:45:13 AM UTC 24
Finished Aug 25 06:45:25 AM UTC 24
Peak memory 210548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=494528821 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.494528821
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.2595841065
Short name T886
Test name
Test status
Simulation time 2012567834 ps
CPU time 10 seconds
Started Aug 25 06:45:13 AM UTC 24
Finished Aug 25 06:45:24 AM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2595841065 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.2595841065
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1243839600
Short name T881
Test name
Test status
Simulation time 2024223112 ps
CPU time 6.16 seconds
Started Aug 25 06:45:14 AM UTC 24
Finished Aug 25 06:45:22 AM UTC 24
Peak memory 210544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243839600 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.1243839600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2974724024
Short name T892
Test name
Test status
Simulation time 2012475594 ps
CPU time 10.27 seconds
Started Aug 25 06:45:14 AM UTC 24
Finished Aug 25 06:45:26 AM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2974724024 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.2974724024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.3760847213
Short name T872
Test name
Test status
Simulation time 2041829013 ps
CPU time 3.14 seconds
Started Aug 25 06:45:14 AM UTC 24
Finished Aug 25 06:45:19 AM UTC 24
Peak memory 210840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760847213 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.3760847213
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.1680767286
Short name T880
Test name
Test status
Simulation time 2018301499 ps
CPU time 6.01 seconds
Started Aug 25 06:45:14 AM UTC 24
Finished Aug 25 06:45:22 AM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1680767286 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.1680767286
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.1482446494
Short name T875
Test name
Test status
Simulation time 2045297627 ps
CPU time 3.05 seconds
Started Aug 25 06:45:16 AM UTC 24
Finished Aug 25 06:45:20 AM UTC 24
Peak memory 210368 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1482446494 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.1482446494
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.3087084780
Short name T877
Test name
Test status
Simulation time 2029588252 ps
CPU time 3.62 seconds
Started Aug 25 06:45:16 AM UTC 24
Finished Aug 25 06:45:21 AM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087084780 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.3087084780
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.2248456625
Short name T874
Test name
Test status
Simulation time 2047292446 ps
CPU time 2.63 seconds
Started Aug 25 06:45:16 AM UTC 24
Finished Aug 25 06:45:20 AM UTC 24
Peak memory 210840 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2248456625 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.2248456625
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.1776290768
Short name T885
Test name
Test status
Simulation time 2023116180 ps
CPU time 5.34 seconds
Started Aug 25 06:45:17 AM UTC 24
Finished Aug 25 06:45:23 AM UTC 24
Peak memory 210596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1776290768 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.1776290768
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.3110372359
Short name T339
Test name
Test status
Simulation time 2408660138 ps
CPU time 8.23 seconds
Started Aug 25 06:44:07 AM UTC 24
Finished Aug 25 06:44:16 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110372359 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.3110372359
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2956779293
Short name T397
Test name
Test status
Simulation time 38498189019 ps
CPU time 35.33 seconds
Started Aug 25 06:44:06 AM UTC 24
Finished Aug 25 06:44:43 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956779293 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.2956779293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1403294893
Short name T803
Test name
Test status
Simulation time 6051507729 ps
CPU time 18.24 seconds
Started Aug 25 06:44:05 AM UTC 24
Finished Aug 25 06:44:24 AM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1403294893 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.1403294893
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.2957603492
Short name T800
Test name
Test status
Simulation time 2195288567 ps
CPU time 4.22 seconds
Started Aug 25 06:44:07 AM UTC 24
Finished Aug 25 06:44:12 AM UTC 24
Peak memory 211080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2957603492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2957603492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.3149970383
Short name T343
Test name
Test status
Simulation time 2291256791 ps
CPU time 2.01 seconds
Started Aug 25 06:44:06 AM UTC 24
Finished Aug 25 06:44:09 AM UTC 24
Peak memory 209672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149970383 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.3149970383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1852838778
Short name T799
Test name
Test status
Simulation time 2103194825 ps
CPU time 1.61 seconds
Started Aug 25 06:44:04 AM UTC 24
Finished Aug 25 06:44:06 AM UTC 24
Peak memory 210000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852838778 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.1852838778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.3987445562
Short name T811
Test name
Test status
Simulation time 6838154169 ps
CPU time 32.19 seconds
Started Aug 25 06:44:07 AM UTC 24
Finished Aug 25 06:44:41 AM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987445562 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.3987445562
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.3802919372
Short name T312
Test name
Test status
Simulation time 2567655592 ps
CPU time 3.56 seconds
Started Aug 25 06:44:01 AM UTC 24
Finished Aug 25 06:44:06 AM UTC 24
Peak memory 211436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802919372 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.3802919372
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.3512280691
Short name T910
Test name
Test status
Simulation time 42360153205 ps
CPU time 162.37 seconds
Started Aug 25 06:44:02 AM UTC 24
Finished Aug 25 06:46:47 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3512280691 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.3512280691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1068274389
Short name T894
Test name
Test status
Simulation time 2013934602 ps
CPU time 8.91 seconds
Started Aug 25 06:45:17 AM UTC 24
Finished Aug 25 06:45:27 AM UTC 24
Peak memory 210564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068274389 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.1068274389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1841879874
Short name T879
Test name
Test status
Simulation time 2028039785 ps
CPU time 3.16 seconds
Started Aug 25 06:45:17 AM UTC 24
Finished Aug 25 06:45:21 AM UTC 24
Peak memory 210600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1841879874 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.1841879874
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.1176818172
Short name T884
Test name
Test status
Simulation time 2030650602 ps
CPU time 3.32 seconds
Started Aug 25 06:45:18 AM UTC 24
Finished Aug 25 06:45:23 AM UTC 24
Peak memory 210600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1176818172 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.1176818172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.3758820125
Short name T897
Test name
Test status
Simulation time 2012687760 ps
CPU time 11.05 seconds
Started Aug 25 06:45:18 AM UTC 24
Finished Aug 25 06:45:30 AM UTC 24
Peak memory 210680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758820125 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.3758820125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.3233403126
Short name T887
Test name
Test status
Simulation time 2032423277 ps
CPU time 3.39 seconds
Started Aug 25 06:45:20 AM UTC 24
Finished Aug 25 06:45:25 AM UTC 24
Peak memory 210848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3233403126 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.3233403126
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.2763820746
Short name T899
Test name
Test status
Simulation time 2010862105 ps
CPU time 11.4 seconds
Started Aug 25 06:45:20 AM UTC 24
Finished Aug 25 06:45:33 AM UTC 24
Peak memory 210832 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2763820746 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.2763820746
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.4047210398
Short name T895
Test name
Test status
Simulation time 2015408354 ps
CPU time 6.01 seconds
Started Aug 25 06:45:20 AM UTC 24
Finished Aug 25 06:45:27 AM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4047210398 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.4047210398
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1456289758
Short name T890
Test name
Test status
Simulation time 2020408216 ps
CPU time 4.22 seconds
Started Aug 25 06:45:20 AM UTC 24
Finished Aug 25 06:45:26 AM UTC 24
Peak memory 210416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1456289758 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.1456289758
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.3103264369
Short name T889
Test name
Test status
Simulation time 2032145109 ps
CPU time 3.41 seconds
Started Aug 25 06:45:20 AM UTC 24
Finished Aug 25 06:45:25 AM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103264369 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.3103264369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.1566149283
Short name T893
Test name
Test status
Simulation time 2023745962 ps
CPU time 5.27 seconds
Started Aug 25 06:45:20 AM UTC 24
Finished Aug 25 06:45:27 AM UTC 24
Peak memory 210544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1566149283 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.1566149283
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.924302710
Short name T317
Test name
Test status
Simulation time 2079599983 ps
CPU time 6.72 seconds
Started Aug 25 06:44:14 AM UTC 24
Finished Aug 25 06:44:21 AM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=924302710 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.
sysrst_ctrl_csr_mem_rw_with_rand_reset.924302710
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.1545300721
Short name T338
Test name
Test status
Simulation time 2071056981 ps
CPU time 2.94 seconds
Started Aug 25 06:44:10 AM UTC 24
Finished Aug 25 06:44:14 AM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1545300721 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.1545300721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.1187445714
Short name T801
Test name
Test status
Simulation time 2011570947 ps
CPU time 10.77 seconds
Started Aug 25 06:44:09 AM UTC 24
Finished Aug 25 06:44:21 AM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1187445714 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.1187445714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.3938968762
Short name T812
Test name
Test status
Simulation time 5028880022 ps
CPU time 25.79 seconds
Started Aug 25 06:44:14 AM UTC 24
Finished Aug 25 06:44:41 AM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3938968762 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.3938968762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.3505184201
Short name T802
Test name
Test status
Simulation time 2106240730 ps
CPU time 13.27 seconds
Started Aug 25 06:44:08 AM UTC 24
Finished Aug 25 06:44:23 AM UTC 24
Peak memory 227536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3505184201 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.3505184201
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.517123468
Short name T911
Test name
Test status
Simulation time 42464879943 ps
CPU time 159.93 seconds
Started Aug 25 06:44:08 AM UTC 24
Finished Aug 25 06:46:51 AM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=517123468 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.517123468
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.360590042
Short name T393
Test name
Test status
Simulation time 2129850407 ps
CPU time 3.4 seconds
Started Aug 25 06:44:18 AM UTC 24
Finished Aug 25 06:44:23 AM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=360590042 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
sysrst_ctrl_csr_mem_rw_with_rand_reset.360590042
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.271001649
Short name T341
Test name
Test status
Simulation time 2024847964 ps
CPU time 11.73 seconds
Started Aug 25 06:44:17 AM UTC 24
Finished Aug 25 06:44:30 AM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271001649 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.271001649
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3149889066
Short name T805
Test name
Test status
Simulation time 2014196001 ps
CPU time 12.11 seconds
Started Aug 25 06:44:16 AM UTC 24
Finished Aug 25 06:44:29 AM UTC 24
Peak memory 210676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149889066 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.3149889066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.3326323880
Short name T815
Test name
Test status
Simulation time 9452653961 ps
CPU time 24.44 seconds
Started Aug 25 06:44:17 AM UTC 24
Finished Aug 25 06:44:43 AM UTC 24
Peak memory 211332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326323880 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.3326323880
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1852112611
Short name T311
Test name
Test status
Simulation time 2060601737 ps
CPU time 12.76 seconds
Started Aug 25 06:44:15 AM UTC 24
Finished Aug 25 06:44:29 AM UTC 24
Peak memory 211196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1852112611 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.1852112611
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.1730022687
Short name T839
Test name
Test status
Simulation time 22285207979 ps
CPU time 45.61 seconds
Started Aug 25 06:44:15 AM UTC 24
Finished Aug 25 06:45:02 AM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1730022687 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.1730022687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.1718812794
Short name T806
Test name
Test status
Simulation time 2050039349 ps
CPU time 6.4 seconds
Started Aug 25 06:44:25 AM UTC 24
Finished Aug 25 06:44:32 AM UTC 24
Peak memory 211092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1718812794 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_csr_mem_rw_with_rand_reset.1718812794
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.3678204001
Short name T342
Test name
Test status
Simulation time 2061991591 ps
CPU time 11.31 seconds
Started Aug 25 06:44:23 AM UTC 24
Finished Aug 25 06:44:36 AM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678204001 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.3678204001
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.3400606804
Short name T804
Test name
Test status
Simulation time 2045043043 ps
CPU time 3.4 seconds
Started Aug 25 06:44:22 AM UTC 24
Finished Aug 25 06:44:27 AM UTC 24
Peak memory 211004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3400606804 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.3400606804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1980755602
Short name T808
Test name
Test status
Simulation time 9847810834 ps
CPU time 10.99 seconds
Started Aug 25 06:44:23 AM UTC 24
Finished Aug 25 06:44:36 AM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1980755602 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.1980755602
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.3757424150
Short name T314
Test name
Test status
Simulation time 2551280472 ps
CPU time 6.48 seconds
Started Aug 25 06:44:21 AM UTC 24
Finished Aug 25 06:44:29 AM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3757424150 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.3757424150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.1586820061
Short name T905
Test name
Test status
Simulation time 22228054414 ps
CPU time 91.78 seconds
Started Aug 25 06:44:22 AM UTC 24
Finished Aug 25 06:45:56 AM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1586820061 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.1586820061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.3488121646
Short name T809
Test name
Test status
Simulation time 2044429757 ps
CPU time 5.96 seconds
Started Aug 25 06:44:29 AM UTC 24
Finished Aug 25 06:44:36 AM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3488121646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_csr_mem_rw_with_rand_reset.3488121646
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.3844012003
Short name T807
Test name
Test status
Simulation time 2045475026 ps
CPU time 6.48 seconds
Started Aug 25 06:44:28 AM UTC 24
Finished Aug 25 06:44:35 AM UTC 24
Peak memory 211068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3844012003 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.3844012003
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.2446038478
Short name T810
Test name
Test status
Simulation time 2013011383 ps
CPU time 9.64 seconds
Started Aug 25 06:44:26 AM UTC 24
Finished Aug 25 06:44:37 AM UTC 24
Peak memory 210536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2446038478 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.2446038478
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.3181759235
Short name T849
Test name
Test status
Simulation time 6706117684 ps
CPU time 35.71 seconds
Started Aug 25 06:44:29 AM UTC 24
Finished Aug 25 06:45:06 AM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3181759235 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.3181759235
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.3790651362
Short name T315
Test name
Test status
Simulation time 2036444488 ps
CPU time 6.87 seconds
Started Aug 25 06:44:25 AM UTC 24
Finished Aug 25 06:44:33 AM UTC 24
Peak memory 211176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3790651362 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.3790651362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.905712484
Short name T817
Test name
Test status
Simulation time 2100493022 ps
CPU time 6.73 seconds
Started Aug 25 06:44:36 AM UTC 24
Finished Aug 25 06:44:44 AM UTC 24
Peak memory 210928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=905712484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
sysrst_ctrl_csr_mem_rw_with_rand_reset.905712484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.3391372243
Short name T816
Test name
Test status
Simulation time 2030831083 ps
CPU time 9.2 seconds
Started Aug 25 06:44:33 AM UTC 24
Finished Aug 25 06:44:43 AM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3391372243 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.3391372243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.355037145
Short name T814
Test name
Test status
Simulation time 2013994698 ps
CPU time 10.79 seconds
Started Aug 25 06:44:31 AM UTC 24
Finished Aug 25 06:44:43 AM UTC 24
Peak memory 210676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=355037145 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.355037145
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.2867394461
Short name T835
Test name
Test status
Simulation time 4793053051 ps
CPU time 23.58 seconds
Started Aug 25 06:44:34 AM UTC 24
Finished Aug 25 06:44:59 AM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2867394461 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.2867394461
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.4114730222
Short name T316
Test name
Test status
Simulation time 2028599521 ps
CPU time 11.55 seconds
Started Aug 25 06:44:30 AM UTC 24
Finished Aug 25 06:44:43 AM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4114730222 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.4114730222
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.3467449477
Short name T838
Test name
Test status
Simulation time 22251399887 ps
CPU time 29.96 seconds
Started Aug 25 06:44:31 AM UTC 24
Finished Aug 25 06:45:02 AM UTC 24
Peak memory 211264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467449477 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.3467449477
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.2060150205
Short name T14
Test name
Test status
Simulation time 2030852594 ps
CPU time 3.13 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:29:50 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2060150205 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.2060150205
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.774925844
Short name T15
Test name
Test status
Simulation time 3261448594 ps
CPU time 3.94 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:29:50 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=774925844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.774925844
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.2844254749
Short name T98
Test name
Test status
Simulation time 94819447121 ps
CPU time 211.5 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:33:20 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2844254749 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.2844254749
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.2921533361
Short name T7
Test name
Test status
Simulation time 2399095315 ps
CPU time 11.81 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:29:57 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2921533361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.2921533361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3420924253
Short name T1
Test name
Test status
Simulation time 2613875752 ps
CPU time 1.9 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:29:48 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420924253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3420924253
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.921719333
Short name T66
Test name
Test status
Simulation time 3105408130 ps
CPU time 16.16 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:30:02 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=921719333 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.921719333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.3306491372
Short name T4
Test name
Test status
Simulation time 2482276037 ps
CPU time 4.07 seconds
Started Aug 25 06:29:41 AM UTC 24
Finished Aug 25 06:29:46 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3306491372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.3306491372
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.3651792412
Short name T62
Test name
Test status
Simulation time 2135223147 ps
CPU time 10.5 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:29:56 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3651792412 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.3651792412
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.2456471524
Short name T5
Test name
Test status
Simulation time 2114813075 ps
CPU time 5.69 seconds
Started Aug 25 06:29:40 AM UTC 24
Finished Aug 25 06:29:47 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2456471524 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2456471524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1931730842
Short name T88
Test name
Test status
Simulation time 9336678077 ps
CPU time 27.74 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:30:15 AM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1931730842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.1931730842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.2461769886
Short name T2
Test name
Test status
Simulation time 11123376859 ps
CPU time 3.83 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:29:50 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2461769886 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.2461769886
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.1033741096
Short name T81
Test name
Test status
Simulation time 2020844846 ps
CPU time 5.97 seconds
Started Aug 25 06:29:55 AM UTC 24
Finished Aug 25 06:30:02 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1033741096 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.1033741096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.629648082
Short name T52
Test name
Test status
Simulation time 3905840577 ps
CPU time 18.42 seconds
Started Aug 25 06:29:51 AM UTC 24
Finished Aug 25 06:30:11 AM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=629648082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.629648082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.600565195
Short name T42
Test name
Test status
Simulation time 175958869959 ps
CPU time 201.55 seconds
Started Aug 25 06:29:52 AM UTC 24
Finished Aug 25 06:33:17 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=600565195 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.600565195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1079761907
Short name T10
Test name
Test status
Simulation time 2506179266 ps
CPU time 15.68 seconds
Started Aug 25 06:29:47 AM UTC 24
Finished Aug 25 06:30:04 AM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079761907 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1079761907
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1536206456
Short name T83
Test name
Test status
Simulation time 65972452376 ps
CPU time 124.35 seconds
Started Aug 25 06:29:52 AM UTC 24
Finished Aug 25 06:31:59 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1536206456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_with_pre_cond.1536206456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1232980399
Short name T24
Test name
Test status
Simulation time 4269923069 ps
CPU time 5.55 seconds
Started Aug 25 06:29:50 AM UTC 24
Finished Aug 25 06:29:57 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1232980399 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.1232980399
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.1325124731
Short name T8
Test name
Test status
Simulation time 2741073317 ps
CPU time 7.47 seconds
Started Aug 25 06:29:52 AM UTC 24
Finished Aug 25 06:30:00 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325124731 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.1325124731
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.2676496097
Short name T19
Test name
Test status
Simulation time 2630953469 ps
CPU time 3.81 seconds
Started Aug 25 06:29:48 AM UTC 24
Finished Aug 25 06:29:53 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2676496097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.2676496097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.521909104
Short name T13
Test name
Test status
Simulation time 2500528010 ps
CPU time 2.57 seconds
Started Aug 25 06:29:46 AM UTC 24
Finished Aug 25 06:29:49 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521909104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.521909104
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.4102077810
Short name T16
Test name
Test status
Simulation time 2047111910 ps
CPU time 2.25 seconds
Started Aug 25 06:29:47 AM UTC 24
Finished Aug 25 06:29:50 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4102077810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.4102077810
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.4169439801
Short name T300
Test name
Test status
Simulation time 42007872910 ps
CPU time 192.87 seconds
Started Aug 25 06:29:55 AM UTC 24
Finished Aug 25 06:33:11 AM UTC 24
Peak memory 240284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4169439801 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.4169439801
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.480526581
Short name T20
Test name
Test status
Simulation time 2120900873 ps
CPU time 6.72 seconds
Started Aug 25 06:29:45 AM UTC 24
Finished Aug 25 06:29:53 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=480526581 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.480526581
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.244058236
Short name T406
Test name
Test status
Simulation time 419282032434 ps
CPU time 177.4 seconds
Started Aug 25 06:29:54 AM UTC 24
Finished Aug 25 06:32:55 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=244058236 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.244058236
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.1283249008
Short name T426
Test name
Test status
Simulation time 2041793681 ps
CPU time 2.65 seconds
Started Aug 25 06:32:09 AM UTC 24
Finished Aug 25 06:32:13 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283249008 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.1283249008
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3100325631
Short name T136
Test name
Test status
Simulation time 3916858299 ps
CPU time 5.85 seconds
Started Aug 25 06:31:56 AM UTC 24
Finished Aug 25 06:32:03 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3100325631 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.3100325631
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1444068016
Short name T273
Test name
Test status
Simulation time 132421336682 ps
CPU time 435.28 seconds
Started Aug 25 06:32:00 AM UTC 24
Finished Aug 25 06:39:20 AM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1444068016 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.1444068016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.540748797
Short name T84
Test name
Test status
Simulation time 41915508089 ps
CPU time 53.28 seconds
Started Aug 25 06:32:01 AM UTC 24
Finished Aug 25 06:32:56 AM UTC 24
Peak memory 210332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540748797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_with_pre_cond.540748797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.3266662667
Short name T423
Test name
Test status
Simulation time 3572053547 ps
CPU time 12.62 seconds
Started Aug 25 06:31:55 AM UTC 24
Finished Aug 25 06:32:09 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3266662667 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.3266662667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.1867941199
Short name T182
Test name
Test status
Simulation time 3946598846 ps
CPU time 7.08 seconds
Started Aug 25 06:32:01 AM UTC 24
Finished Aug 25 06:32:09 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1867941199 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.1867941199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.2639473539
Short name T424
Test name
Test status
Simulation time 2609236560 ps
CPU time 14.66 seconds
Started Aug 25 06:31:54 AM UTC 24
Finished Aug 25 06:32:10 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639473539 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.2639473539
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.226329032
Short name T162
Test name
Test status
Simulation time 2504028815 ps
CPU time 2.87 seconds
Started Aug 25 06:31:51 AM UTC 24
Finished Aug 25 06:31:55 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=226329032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.226329032
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.3333744216
Short name T163
Test name
Test status
Simulation time 2055625998 ps
CPU time 3.35 seconds
Started Aug 25 06:31:51 AM UTC 24
Finished Aug 25 06:31:55 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3333744216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.3333744216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3669570918
Short name T413
Test name
Test status
Simulation time 2517663192 ps
CPU time 8.14 seconds
Started Aug 25 06:31:53 AM UTC 24
Finished Aug 25 06:32:02 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669570918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3669570918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.707245592
Short name T161
Test name
Test status
Simulation time 2124739879 ps
CPU time 2.89 seconds
Started Aug 25 06:31:49 AM UTC 24
Finished Aug 25 06:31:53 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707245592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.707245592
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.2387196789
Short name T167
Test name
Test status
Simulation time 9673816723 ps
CPU time 9.01 seconds
Started Aug 25 06:32:04 AM UTC 24
Finished Aug 25 06:32:14 AM UTC 24
Peak memory 210072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387196789 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.2387196789
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.135973436
Short name T425
Test name
Test status
Simulation time 5637506163 ps
CPU time 7.54 seconds
Started Aug 25 06:32:03 AM UTC 24
Finished Aug 25 06:32:12 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=135973436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.135973436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.55485327
Short name T89
Test name
Test status
Simulation time 4124758133 ps
CPU time 10.61 seconds
Started Aug 25 06:31:59 AM UTC 24
Finished Aug 25 06:32:11 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55485327 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.55485327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.2964570957
Short name T433
Test name
Test status
Simulation time 2033266656 ps
CPU time 3.06 seconds
Started Aug 25 06:32:24 AM UTC 24
Finished Aug 25 06:32:28 AM UTC 24
Peak memory 209820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964570957 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.2964570957
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.3664302186
Short name T91
Test name
Test status
Simulation time 3888257738 ps
CPU time 6.54 seconds
Started Aug 25 06:32:15 AM UTC 24
Finished Aug 25 06:32:23 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3664302186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.3664302186
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.189666764
Short name T105
Test name
Test status
Simulation time 26366077739 ps
CPU time 111.48 seconds
Started Aug 25 06:32:19 AM UTC 24
Finished Aug 25 06:34:13 AM UTC 24
Peak memory 210488 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=189666764 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.189666764
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.760797618
Short name T427
Test name
Test status
Simulation time 3035176478 ps
CPU time 3.4 seconds
Started Aug 25 06:32:14 AM UTC 24
Finished Aug 25 06:32:18 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760797618 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.760797618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.3083217456
Short name T169
Test name
Test status
Simulation time 3505852381 ps
CPU time 6.88 seconds
Started Aug 25 06:32:21 AM UTC 24
Finished Aug 25 06:32:29 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3083217456 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.3083217456
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.4293148703
Short name T428
Test name
Test status
Simulation time 2614385088 ps
CPU time 6.88 seconds
Started Aug 25 06:32:13 AM UTC 24
Finished Aug 25 06:32:21 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293148703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.4293148703
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.1224656769
Short name T430
Test name
Test status
Simulation time 2455131787 ps
CPU time 10.01 seconds
Started Aug 25 06:32:10 AM UTC 24
Finished Aug 25 06:32:21 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224656769 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.1224656769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.630625118
Short name T431
Test name
Test status
Simulation time 2102900082 ps
CPU time 10.41 seconds
Started Aug 25 06:32:12 AM UTC 24
Finished Aug 25 06:32:23 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=630625118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.630625118
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2808949488
Short name T411
Test name
Test status
Simulation time 2529227962 ps
CPU time 3.87 seconds
Started Aug 25 06:32:12 AM UTC 24
Finished Aug 25 06:32:17 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2808949488 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2808949488
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.2565884197
Short name T429
Test name
Test status
Simulation time 2109150014 ps
CPU time 9.24 seconds
Started Aug 25 06:32:10 AM UTC 24
Finished Aug 25 06:32:21 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2565884197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.2565884197
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.1167046762
Short name T435
Test name
Test status
Simulation time 6452047895 ps
CPU time 8.68 seconds
Started Aug 25 06:32:23 AM UTC 24
Finished Aug 25 06:32:33 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167046762 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.1167046762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.3277662048
Short name T331
Test name
Test status
Simulation time 3512108695 ps
CPU time 17.21 seconds
Started Aug 25 06:32:23 AM UTC 24
Finished Aug 25 06:32:41 AM UTC 24
Peak memory 209936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3277662048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.3277662048
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3129225769
Short name T90
Test name
Test status
Simulation time 13998479694 ps
CPU time 13.17 seconds
Started Aug 25 06:32:17 AM UTC 24
Finished Aug 25 06:32:31 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129225769 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.3129225769
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.1533683927
Short name T442
Test name
Test status
Simulation time 2014560178 ps
CPU time 9.75 seconds
Started Aug 25 06:32:39 AM UTC 24
Finished Aug 25 06:32:50 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1533683927 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.1533683927
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.2354296378
Short name T43
Test name
Test status
Simulation time 118736877213 ps
CPU time 51.95 seconds
Started Aug 25 06:32:34 AM UTC 24
Finished Aug 25 06:33:28 AM UTC 24
Peak memory 210232 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354296378 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.2354296378
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.756719082
Short name T85
Test name
Test status
Simulation time 41676707040 ps
CPU time 41.81 seconds
Started Aug 25 06:32:34 AM UTC 24
Finished Aug 25 06:33:17 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=756719082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_with_pre_cond.756719082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.1198236035
Short name T441
Test name
Test status
Simulation time 2982658552 ps
CPU time 14.91 seconds
Started Aug 25 06:32:32 AM UTC 24
Finished Aug 25 06:32:48 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1198236035 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.1198236035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.1588176813
Short name T189
Test name
Test status
Simulation time 4542657250 ps
CPU time 3.75 seconds
Started Aug 25 06:32:34 AM UTC 24
Finished Aug 25 06:32:39 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1588176813 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.1588176813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.2342312751
Short name T437
Test name
Test status
Simulation time 2664000540 ps
CPU time 1.82 seconds
Started Aug 25 06:32:30 AM UTC 24
Finished Aug 25 06:32:33 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2342312751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.2342312751
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.2354820007
Short name T432
Test name
Test status
Simulation time 2530588783 ps
CPU time 1.72 seconds
Started Aug 25 06:32:24 AM UTC 24
Finished Aug 25 06:32:27 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354820007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2354820007
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.10799059
Short name T438
Test name
Test status
Simulation time 2209451321 ps
CPU time 11.19 seconds
Started Aug 25 06:32:28 AM UTC 24
Finished Aug 25 06:32:41 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=10799059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysr
st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.10799059
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.1205991388
Short name T436
Test name
Test status
Simulation time 2585483583 ps
CPU time 1.87 seconds
Started Aug 25 06:32:29 AM UTC 24
Finished Aug 25 06:32:33 AM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1205991388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.1205991388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.3601093162
Short name T434
Test name
Test status
Simulation time 2114219237 ps
CPU time 5.12 seconds
Started Aug 25 06:32:24 AM UTC 24
Finished Aug 25 06:32:30 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3601093162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.3601093162
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.1009659484
Short name T307
Test name
Test status
Simulation time 2937575966 ps
CPU time 15.5 seconds
Started Aug 25 06:32:35 AM UTC 24
Finished Aug 25 06:32:52 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1009659484 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.1009659484
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.621223357
Short name T103
Test name
Test status
Simulation time 11544728419 ps
CPU time 4.03 seconds
Started Aug 25 06:32:33 AM UTC 24
Finished Aug 25 06:32:38 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=621223357 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.621223357
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.112239533
Short name T449
Test name
Test status
Simulation time 2010289753 ps
CPU time 9.49 seconds
Started Aug 25 06:33:01 AM UTC 24
Finished Aug 25 06:33:11 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=112239533 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.112239533
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1007996636
Short name T611
Test name
Test status
Simulation time 66278244547 ps
CPU time 278.35 seconds
Started Aug 25 06:32:53 AM UTC 24
Finished Aug 25 06:37:35 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1007996636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.1007996636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.786079071
Short name T288
Test name
Test status
Simulation time 59106206518 ps
CPU time 244.94 seconds
Started Aug 25 06:32:57 AM UTC 24
Finished Aug 25 06:37:06 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=786079071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_with_pre_cond.786079071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1003375746
Short name T444
Test name
Test status
Simulation time 4572170050 ps
CPU time 7.57 seconds
Started Aug 25 06:32:51 AM UTC 24
Finished Aug 25 06:32:59 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1003375746 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.1003375746
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.2752601242
Short name T446
Test name
Test status
Simulation time 2607459188 ps
CPU time 12.17 seconds
Started Aug 25 06:32:49 AM UTC 24
Finished Aug 25 06:33:02 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2752601242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.2752601242
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.3324495238
Short name T440
Test name
Test status
Simulation time 2490593055 ps
CPU time 4.07 seconds
Started Aug 25 06:32:42 AM UTC 24
Finished Aug 25 06:32:48 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324495238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.3324495238
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.115060338
Short name T443
Test name
Test status
Simulation time 2130885946 ps
CPU time 9.69 seconds
Started Aug 25 06:32:47 AM UTC 24
Finished Aug 25 06:32:58 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=115060338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.115060338
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.3482260859
Short name T445
Test name
Test status
Simulation time 2511438596 ps
CPU time 10.93 seconds
Started Aug 25 06:32:49 AM UTC 24
Finished Aug 25 06:33:01 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3482260859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.3482260859
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.953588618
Short name T439
Test name
Test status
Simulation time 2125674126 ps
CPU time 3.28 seconds
Started Aug 25 06:32:41 AM UTC 24
Finished Aug 25 06:32:46 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=953588618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.953588618
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2758174245
Short name T469
Test name
Test status
Simulation time 9323210796 ps
CPU time 47.72 seconds
Started Aug 25 06:33:00 AM UTC 24
Finished Aug 25 06:33:49 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2758174245 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.2758174245
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.2644059826
Short name T138
Test name
Test status
Simulation time 11207970991 ps
CPU time 14.31 seconds
Started Aug 25 06:32:58 AM UTC 24
Finished Aug 25 06:33:14 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2644059826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.2644059826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2614180421
Short name T94
Test name
Test status
Simulation time 5470667513 ps
CPU time 2.12 seconds
Started Aug 25 06:32:53 AM UTC 24
Finished Aug 25 06:32:56 AM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2614180421 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.2614180421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.3827667443
Short name T458
Test name
Test status
Simulation time 2010604683 ps
CPU time 9.85 seconds
Started Aug 25 06:33:18 AM UTC 24
Finished Aug 25 06:33:29 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827667443 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.3827667443
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.3230145231
Short name T780
Test name
Test status
Simulation time 329887693486 ps
CPU time 718.27 seconds
Started Aug 25 06:33:10 AM UTC 24
Finished Aug 25 06:45:17 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3230145231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.3230145231
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.3326473772
Short name T106
Test name
Test status
Simulation time 54893176415 ps
CPU time 100.86 seconds
Started Aug 25 06:33:13 AM UTC 24
Finished Aug 25 06:34:56 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3326473772 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.3326473772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3542739635
Short name T454
Test name
Test status
Simulation time 3314729163 ps
CPU time 13.44 seconds
Started Aug 25 06:33:10 AM UTC 24
Finished Aug 25 06:33:25 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542739635 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.3542739635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.4224149536
Short name T232
Test name
Test status
Simulation time 1420003042098 ps
CPU time 929.22 seconds
Started Aug 25 06:33:14 AM UTC 24
Finished Aug 25 06:48:53 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4224149536 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.4224149536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1685070020
Short name T450
Test name
Test status
Simulation time 2640652695 ps
CPU time 3.67 seconds
Started Aug 25 06:33:08 AM UTC 24
Finished Aug 25 06:33:13 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1685070020 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1685070020
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.4081989660
Short name T451
Test name
Test status
Simulation time 2465007778 ps
CPU time 12.56 seconds
Started Aug 25 06:33:03 AM UTC 24
Finished Aug 25 06:33:16 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4081989660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.4081989660
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.2639700439
Short name T448
Test name
Test status
Simulation time 2097944643 ps
CPU time 3.06 seconds
Started Aug 25 06:33:05 AM UTC 24
Finished Aug 25 06:33:09 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2639700439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.2639700439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.791914622
Short name T414
Test name
Test status
Simulation time 2513867765 ps
CPU time 12.85 seconds
Started Aug 25 06:33:08 AM UTC 24
Finished Aug 25 06:33:22 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791914622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.791914622
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.315387742
Short name T447
Test name
Test status
Simulation time 2118760586 ps
CPU time 6.26 seconds
Started Aug 25 06:33:02 AM UTC 24
Finished Aug 25 06:33:09 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=315387742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.315387742
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.1283687321
Short name T452
Test name
Test status
Simulation time 8029373146 ps
CPU time 3.85 seconds
Started Aug 25 06:33:17 AM UTC 24
Finished Aug 25 06:33:22 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283687321 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.1283687321
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.137987080
Short name T461
Test name
Test status
Simulation time 4630963194 ps
CPU time 22.35 seconds
Started Aug 25 06:33:16 AM UTC 24
Finished Aug 25 06:33:39 AM UTC 24
Peak memory 220476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=137987080 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.137987080
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.690690108
Short name T123
Test name
Test status
Simulation time 2141792494 ps
CPU time 1.35 seconds
Started Aug 25 06:33:30 AM UTC 24
Finished Aug 25 06:33:32 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690690108 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.690690108
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2923213826
Short name T121
Test name
Test status
Simulation time 3631820560 ps
CPU time 5.79 seconds
Started Aug 25 06:33:24 AM UTC 24
Finished Aug 25 06:33:31 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923213826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2923213826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.3640039140
Short name T270
Test name
Test status
Simulation time 122165753601 ps
CPU time 135.4 seconds
Started Aug 25 06:33:26 AM UTC 24
Finished Aug 25 06:35:44 AM UTC 24
Peak memory 210284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640039140 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.3640039140
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.411307716
Short name T97
Test name
Test status
Simulation time 69087690015 ps
CPU time 155.46 seconds
Started Aug 25 06:33:28 AM UTC 24
Finished Aug 25 06:36:06 AM UTC 24
Peak memory 210520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=411307716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_with_pre_cond.411307716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.2274865328
Short name T457
Test name
Test status
Simulation time 2729378191 ps
CPU time 3.94 seconds
Started Aug 25 06:33:24 AM UTC 24
Finished Aug 25 06:33:29 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274865328 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.2274865328
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1123009025
Short name T120
Test name
Test status
Simulation time 2596819685 ps
CPU time 3.34 seconds
Started Aug 25 06:33:27 AM UTC 24
Finished Aug 25 06:33:31 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1123009025 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.1123009025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.631699082
Short name T456
Test name
Test status
Simulation time 2639633258 ps
CPU time 3.08 seconds
Started Aug 25 06:33:23 AM UTC 24
Finished Aug 25 06:33:27 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=631699082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.631699082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.1054686384
Short name T459
Test name
Test status
Simulation time 2456646051 ps
CPU time 8.18 seconds
Started Aug 25 06:33:20 AM UTC 24
Finished Aug 25 06:33:30 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054686384 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.1054686384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3583581661
Short name T455
Test name
Test status
Simulation time 2063233568 ps
CPU time 3.19 seconds
Started Aug 25 06:33:21 AM UTC 24
Finished Aug 25 06:33:26 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3583581661 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3583581661
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2527396555
Short name T127
Test name
Test status
Simulation time 2509323794 ps
CPU time 12.05 seconds
Started Aug 25 06:33:23 AM UTC 24
Finished Aug 25 06:33:36 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527396555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2527396555
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.988201876
Short name T453
Test name
Test status
Simulation time 2134548904 ps
CPU time 2.91 seconds
Started Aug 25 06:33:18 AM UTC 24
Finished Aug 25 06:33:22 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=988201876 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.988201876
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.1190462514
Short name T139
Test name
Test status
Simulation time 11683314003 ps
CPU time 22.32 seconds
Started Aug 25 06:33:30 AM UTC 24
Finished Aug 25 06:33:54 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1190462514 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.1190462514
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.1643120071
Short name T124
Test name
Test status
Simulation time 5262069259 ps
CPU time 6.86 seconds
Started Aug 25 06:33:25 AM UTC 24
Finished Aug 25 06:33:33 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643120071 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.1643120071
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.762393593
Short name T462
Test name
Test status
Simulation time 2036947662 ps
CPU time 3.2 seconds
Started Aug 25 06:33:39 AM UTC 24
Finished Aug 25 06:33:43 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=762393593 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.762393593
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.3049848550
Short name T470
Test name
Test status
Simulation time 3250292176 ps
CPU time 15.53 seconds
Started Aug 25 06:33:34 AM UTC 24
Finished Aug 25 06:33:51 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3049848550 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.3049848550
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2570635010
Short name T347
Test name
Test status
Simulation time 26270133646 ps
CPU time 108.62 seconds
Started Aug 25 06:33:34 AM UTC 24
Finished Aug 25 06:35:25 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2570635010 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.2570635010
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.2523117632
Short name T287
Test name
Test status
Simulation time 131669995219 ps
CPU time 169.04 seconds
Started Aug 25 06:33:35 AM UTC 24
Finished Aug 25 06:36:27 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2523117632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_with_pre_cond.2523117632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1629711045
Short name T285
Test name
Test status
Simulation time 3766905309 ps
CPU time 3.18 seconds
Started Aug 25 06:33:33 AM UTC 24
Finished Aug 25 06:33:37 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1629711045 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.1629711045
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.1133060434
Short name T190
Test name
Test status
Simulation time 4245478307 ps
CPU time 14.4 seconds
Started Aug 25 06:33:35 AM UTC 24
Finished Aug 25 06:33:51 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1133060434 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.1133060434
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.2192599614
Short name T466
Test name
Test status
Simulation time 2610149457 ps
CPU time 11.18 seconds
Started Aug 25 06:33:33 AM UTC 24
Finished Aug 25 06:33:45 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192599614 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.2192599614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.1350139503
Short name T463
Test name
Test status
Simulation time 2459313330 ps
CPU time 11.63 seconds
Started Aug 25 06:33:31 AM UTC 24
Finished Aug 25 06:33:44 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1350139503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.1350139503
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.3116232466
Short name T125
Test name
Test status
Simulation time 2188043543 ps
CPU time 2.01 seconds
Started Aug 25 06:33:31 AM UTC 24
Finished Aug 25 06:33:34 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3116232466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.3116232466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.991861673
Short name T465
Test name
Test status
Simulation time 2510851779 ps
CPU time 11.11 seconds
Started Aug 25 06:33:32 AM UTC 24
Finished Aug 25 06:33:45 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=991861673 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.991861673
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.4188575752
Short name T126
Test name
Test status
Simulation time 2134927419 ps
CPU time 3.19 seconds
Started Aug 25 06:33:30 AM UTC 24
Finished Aug 25 06:33:35 AM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4188575752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.4188575752
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.3944882623
Short name T478
Test name
Test status
Simulation time 6658124940 ps
CPU time 25.85 seconds
Started Aug 25 06:33:36 AM UTC 24
Finished Aug 25 06:34:03 AM UTC 24
Peak memory 220544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3944882623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.3944882623
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.707115774
Short name T460
Test name
Test status
Simulation time 5112341907 ps
CPU time 3.96 seconds
Started Aug 25 06:33:34 AM UTC 24
Finished Aug 25 06:33:39 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707115774 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.707115774
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.1682183765
Short name T475
Test name
Test status
Simulation time 2010337047 ps
CPU time 8.89 seconds
Started Aug 25 06:33:52 AM UTC 24
Finished Aug 25 06:34:02 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1682183765 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.1682183765
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1433752462
Short name T481
Test name
Test status
Simulation time 3400222986 ps
CPU time 20.01 seconds
Started Aug 25 06:33:47 AM UTC 24
Finished Aug 25 06:34:08 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433752462 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1433752462
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.669095853
Short name T184
Test name
Test status
Simulation time 27319148009 ps
CPU time 60.58 seconds
Started Aug 25 06:33:47 AM UTC 24
Finished Aug 25 06:34:49 AM UTC 24
Peak memory 210168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=669095853 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.669095853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2015086223
Short name T483
Test name
Test status
Simulation time 5211168264 ps
CPU time 25.69 seconds
Started Aug 25 06:33:45 AM UTC 24
Finished Aug 25 06:34:12 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2015086223 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.2015086223
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.3549669732
Short name T203
Test name
Test status
Simulation time 4680324423 ps
CPU time 3.14 seconds
Started Aug 25 06:33:47 AM UTC 24
Finished Aug 25 06:33:51 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3549669732 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.3549669732
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3088426239
Short name T471
Test name
Test status
Simulation time 2620207415 ps
CPU time 8.16 seconds
Started Aug 25 06:33:45 AM UTC 24
Finished Aug 25 06:33:54 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3088426239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.3088426239
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.658297375
Short name T468
Test name
Test status
Simulation time 2471032335 ps
CPU time 3.55 seconds
Started Aug 25 06:33:41 AM UTC 24
Finished Aug 25 06:33:45 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=658297375 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.658297375
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.3910247900
Short name T467
Test name
Test status
Simulation time 2082615866 ps
CPU time 3.14 seconds
Started Aug 25 06:33:41 AM UTC 24
Finished Aug 25 06:33:45 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3910247900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.3910247900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.3912370948
Short name T472
Test name
Test status
Simulation time 2508856594 ps
CPU time 11.97 seconds
Started Aug 25 06:33:44 AM UTC 24
Finished Aug 25 06:33:57 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3912370948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.3912370948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.2853951309
Short name T464
Test name
Test status
Simulation time 2122142038 ps
CPU time 3.95 seconds
Started Aug 25 06:33:40 AM UTC 24
Finished Aug 25 06:33:45 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853951309 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.2853951309
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.186346565
Short name T140
Test name
Test status
Simulation time 10085146723 ps
CPU time 4.81 seconds
Started Aug 25 06:33:52 AM UTC 24
Finished Aug 25 06:33:58 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186346565 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.186346565
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3010483149
Short name T141
Test name
Test status
Simulation time 5967949288 ps
CPU time 13.93 seconds
Started Aug 25 06:33:47 AM UTC 24
Finished Aug 25 06:34:02 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010483149 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.3010483149
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.457742622
Short name T486
Test name
Test status
Simulation time 2014539485 ps
CPU time 8.88 seconds
Started Aug 25 06:34:06 AM UTC 24
Finished Aug 25 06:34:16 AM UTC 24
Peak memory 209816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=457742622 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.457742622
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.822616822
Short name T482
Test name
Test status
Simulation time 4014071169 ps
CPU time 9.22 seconds
Started Aug 25 06:34:00 AM UTC 24
Finished Aug 25 06:34:11 AM UTC 24
Peak memory 210020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=822616822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.822616822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.391431806
Short name T118
Test name
Test status
Simulation time 175885171821 ps
CPU time 639.2 seconds
Started Aug 25 06:34:03 AM UTC 24
Finished Aug 25 06:44:50 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=391431806 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.391431806
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1319057067
Short name T785
Test name
Test status
Simulation time 169925484998 ps
CPU time 749.23 seconds
Started Aug 25 06:34:04 AM UTC 24
Finished Aug 25 06:46:43 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1319057067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_with_pre_cond.1319057067
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.2158115404
Short name T480
Test name
Test status
Simulation time 3368726280 ps
CPU time 3.38 seconds
Started Aug 25 06:34:00 AM UTC 24
Finished Aug 25 06:34:05 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2158115404 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.2158115404
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1735331868
Short name T170
Test name
Test status
Simulation time 2831063602 ps
CPU time 13.7 seconds
Started Aug 25 06:34:04 AM UTC 24
Finished Aug 25 06:34:19 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1735331868 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.1735331868
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.3568469882
Short name T485
Test name
Test status
Simulation time 2614526548 ps
CPU time 13.08 seconds
Started Aug 25 06:33:59 AM UTC 24
Finished Aug 25 06:34:13 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3568469882 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.3568469882
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.360718251
Short name T473
Test name
Test status
Simulation time 2506640533 ps
CPU time 3.66 seconds
Started Aug 25 06:33:54 AM UTC 24
Finished Aug 25 06:33:59 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360718251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.360718251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.873452052
Short name T474
Test name
Test status
Simulation time 2112126258 ps
CPU time 2.32 seconds
Started Aug 25 06:33:55 AM UTC 24
Finished Aug 25 06:33:59 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=873452052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.873452052
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.1039278365
Short name T479
Test name
Test status
Simulation time 2513520982 ps
CPU time 6.15 seconds
Started Aug 25 06:33:58 AM UTC 24
Finished Aug 25 06:34:05 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039278365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.1039278365
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.2052393260
Short name T477
Test name
Test status
Simulation time 2111950499 ps
CPU time 9.79 seconds
Started Aug 25 06:33:52 AM UTC 24
Finished Aug 25 06:34:03 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2052393260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.2052393260
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.3804827320
Short name T505
Test name
Test status
Simulation time 10064821683 ps
CPU time 52.7 seconds
Started Aug 25 06:34:05 AM UTC 24
Finished Aug 25 06:35:00 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3804827320 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.3804827320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1079143125
Short name T318
Test name
Test status
Simulation time 7346766735 ps
CPU time 16.36 seconds
Started Aug 25 06:34:04 AM UTC 24
Finished Aug 25 06:34:22 AM UTC 24
Peak memory 220736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1079143125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.1079143125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.2659919809
Short name T492
Test name
Test status
Simulation time 2030282885 ps
CPU time 3.22 seconds
Started Aug 25 06:34:25 AM UTC 24
Finished Aug 25 06:34:29 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2659919809 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.2659919809
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.3611009092
Short name T496
Test name
Test status
Simulation time 3230779929 ps
CPU time 14.64 seconds
Started Aug 25 06:34:16 AM UTC 24
Finished Aug 25 06:34:32 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3611009092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.3611009092
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.2907690368
Short name T284
Test name
Test status
Simulation time 142972873892 ps
CPU time 611.14 seconds
Started Aug 25 06:34:17 AM UTC 24
Finished Aug 25 06:44:36 AM UTC 24
Peak memory 210440 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907690368 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.2907690368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3354299161
Short name T265
Test name
Test status
Simulation time 57644750655 ps
CPU time 72.72 seconds
Started Aug 25 06:34:20 AM UTC 24
Finished Aug 25 06:35:35 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354299161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_with_pre_cond.3354299161
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1652600675
Short name T491
Test name
Test status
Simulation time 4099693957 ps
CPU time 12.33 seconds
Started Aug 25 06:34:14 AM UTC 24
Finished Aug 25 06:34:28 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1652600675 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.1652600675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.1279847396
Short name T186
Test name
Test status
Simulation time 5212341287 ps
CPU time 15.87 seconds
Started Aug 25 06:34:18 AM UTC 24
Finished Aug 25 06:34:35 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1279847396 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.1279847396
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2837589805
Short name T487
Test name
Test status
Simulation time 2727699858 ps
CPU time 1.68 seconds
Started Aug 25 06:34:14 AM UTC 24
Finished Aug 25 06:34:17 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2837589805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.2837589805
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.4049623594
Short name T490
Test name
Test status
Simulation time 2447421507 ps
CPU time 13.52 seconds
Started Aug 25 06:34:12 AM UTC 24
Finished Aug 25 06:34:27 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049623594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.4049623594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.3449930889
Short name T488
Test name
Test status
Simulation time 2159748747 ps
CPU time 2.99 seconds
Started Aug 25 06:34:13 AM UTC 24
Finished Aug 25 06:34:17 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3449930889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.3449930889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.537692177
Short name T489
Test name
Test status
Simulation time 2512740840 ps
CPU time 7.16 seconds
Started Aug 25 06:34:14 AM UTC 24
Finished Aug 25 06:34:23 AM UTC 24
Peak memory 210132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537692177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.537692177
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.58451864
Short name T484
Test name
Test status
Simulation time 2136922758 ps
CPU time 2.68 seconds
Started Aug 25 06:34:09 AM UTC 24
Finished Aug 25 06:34:13 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58451864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.58451864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.1261387142
Short name T493
Test name
Test status
Simulation time 7749767676 ps
CPU time 12.51 seconds
Started Aug 25 06:34:16 AM UTC 24
Finished Aug 25 06:34:30 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1261387142 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.1261387142
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.3641551199
Short name T389
Test name
Test status
Simulation time 143271314158 ps
CPU time 713.58 seconds
Started Aug 25 06:30:03 AM UTC 24
Finished Aug 25 06:42:06 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3641551199 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.3641551199
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.3586559582
Short name T53
Test name
Test status
Simulation time 2438482082 ps
CPU time 12.94 seconds
Started Aug 25 06:29:57 AM UTC 24
Finished Aug 25 06:30:11 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3586559582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.3586559582
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1689320410
Short name T29
Test name
Test status
Simulation time 2346325083 ps
CPU time 3.59 seconds
Started Aug 25 06:29:57 AM UTC 24
Finished Aug 25 06:30:02 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1689320410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1689320410
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1267072132
Short name T254
Test name
Test status
Simulation time 128971376083 ps
CPU time 598.85 seconds
Started Aug 25 06:30:04 AM UTC 24
Finished Aug 25 06:40:11 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267072132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_with_pre_cond.1267072132
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.168981085
Short name T327
Test name
Test status
Simulation time 3861633408 ps
CPU time 20.89 seconds
Started Aug 25 06:30:02 AM UTC 24
Finished Aug 25 06:30:24 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168981085 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.168981085
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.3597325243
Short name T12
Test name
Test status
Simulation time 3289034318 ps
CPU time 4.24 seconds
Started Aug 25 06:30:03 AM UTC 24
Finished Aug 25 06:30:08 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597325243 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.3597325243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2502073941
Short name T77
Test name
Test status
Simulation time 2615413702 ps
CPU time 6.43 seconds
Started Aug 25 06:29:59 AM UTC 24
Finished Aug 25 06:30:06 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502073941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.2502073941
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2972532680
Short name T26
Test name
Test status
Simulation time 2479523309 ps
CPU time 3.25 seconds
Started Aug 25 06:29:56 AM UTC 24
Finished Aug 25 06:30:01 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2972532680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2972532680
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.3137747015
Short name T202
Test name
Test status
Simulation time 2048382267 ps
CPU time 3.48 seconds
Started Aug 25 06:29:59 AM UTC 24
Finished Aug 25 06:30:03 AM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3137747015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.3137747015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.3463069040
Short name T63
Test name
Test status
Simulation time 2509901662 ps
CPU time 12.33 seconds
Started Aug 25 06:29:59 AM UTC 24
Finished Aug 25 06:30:12 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3463069040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.3463069040
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.1808273165
Short name T197
Test name
Test status
Simulation time 42105553528 ps
CPU time 51.37 seconds
Started Aug 25 06:30:05 AM UTC 24
Finished Aug 25 06:30:58 AM UTC 24
Peak memory 240348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808273165 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.1808273165
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3974215775
Short name T80
Test name
Test status
Simulation time 2174293600 ps
CPU time 1.64 seconds
Started Aug 25 06:29:55 AM UTC 24
Finished Aug 25 06:29:58 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974215775 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.3974215775
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.948896478
Short name T71
Test name
Test status
Simulation time 11217992440 ps
CPU time 25.48 seconds
Started Aug 25 06:30:05 AM UTC 24
Finished Aug 25 06:30:31 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948896478 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.948896478
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.4005490865
Short name T310
Test name
Test status
Simulation time 6281798480 ps
CPU time 14.05 seconds
Started Aug 25 06:30:04 AM UTC 24
Finished Aug 25 06:30:20 AM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4005490865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.4005490865
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3578230669
Short name T25
Test name
Test status
Simulation time 438298108558 ps
CPU time 3.2 seconds
Started Aug 25 06:30:03 AM UTC 24
Finished Aug 25 06:30:07 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578230669 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.3578230669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.2369951560
Short name T185
Test name
Test status
Simulation time 2011471461 ps
CPU time 10.21 seconds
Started Aug 25 06:34:38 AM UTC 24
Finished Aug 25 06:34:49 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369951560 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.2369951560
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.379694896
Short name T130
Test name
Test status
Simulation time 3097407997 ps
CPU time 7.8 seconds
Started Aug 25 06:34:32 AM UTC 24
Finished Aug 25 06:34:41 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=379694896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.379694896
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.3540952432
Short name T111
Test name
Test status
Simulation time 96977133676 ps
CPU time 202.18 seconds
Started Aug 25 06:34:33 AM UTC 24
Finished Aug 25 06:37:59 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3540952432 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.3540952432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.1621979471
Short name T110
Test name
Test status
Simulation time 28329656636 ps
CPU time 130.93 seconds
Started Aug 25 06:34:35 AM UTC 24
Finished Aug 25 06:36:49 AM UTC 24
Peak memory 210320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621979471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_with_pre_cond.1621979471
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.2467274214
Short name T501
Test name
Test status
Simulation time 4046902098 ps
CPU time 20.87 seconds
Started Aug 25 06:34:31 AM UTC 24
Finished Aug 25 06:34:53 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2467274214 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.2467274214
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.342512842
Short name T93
Test name
Test status
Simulation time 2695882453 ps
CPU time 3.64 seconds
Started Aug 25 06:34:33 AM UTC 24
Finished Aug 25 06:34:38 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=342512842 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.342512842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.25157334
Short name T133
Test name
Test status
Simulation time 2612654215 ps
CPU time 11.67 seconds
Started Aug 25 06:34:31 AM UTC 24
Finished Aug 25 06:34:44 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=25157334 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.25157334
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.2583970152
Short name T495
Test name
Test status
Simulation time 2492546103 ps
CPU time 3.71 seconds
Started Aug 25 06:34:27 AM UTC 24
Finished Aug 25 06:34:32 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583970152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.2583970152
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.939193075
Short name T131
Test name
Test status
Simulation time 2143830258 ps
CPU time 12.2 seconds
Started Aug 25 06:34:28 AM UTC 24
Finished Aug 25 06:34:42 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=939193075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.939193075
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.1295387448
Short name T497
Test name
Test status
Simulation time 2537728684 ps
CPU time 3.73 seconds
Started Aug 25 06:34:30 AM UTC 24
Finished Aug 25 06:34:35 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295387448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.1295387448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1705103295
Short name T494
Test name
Test status
Simulation time 2169190396 ps
CPU time 2.3 seconds
Started Aug 25 06:34:27 AM UTC 24
Finished Aug 25 06:34:31 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1705103295 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1705103295
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.326793824
Short name T128
Test name
Test status
Simulation time 2796567189 ps
CPU time 2.98 seconds
Started Aug 25 06:34:33 AM UTC 24
Finished Aug 25 06:34:37 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=326793824 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.326793824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.2822967325
Short name T502
Test name
Test status
Simulation time 2037644097 ps
CPU time 3.26 seconds
Started Aug 25 06:34:53 AM UTC 24
Finished Aug 25 06:34:57 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822967325 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.2822967325
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1257806369
Short name T498
Test name
Test status
Simulation time 3411365836 ps
CPU time 5.35 seconds
Started Aug 25 06:34:44 AM UTC 24
Finished Aug 25 06:34:51 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1257806369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.1257806369
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3361268189
Short name T786
Test name
Test status
Simulation time 155710825374 ps
CPU time 705.14 seconds
Started Aug 25 06:34:50 AM UTC 24
Finished Aug 25 06:46:44 AM UTC 24
Peak memory 210108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3361268189 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.3361268189
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.219563674
Short name T279
Test name
Test status
Simulation time 150420561377 ps
CPU time 157.82 seconds
Started Aug 25 06:34:50 AM UTC 24
Finished Aug 25 06:37:30 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=219563674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_with_pre_cond.219563674
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.307235351
Short name T499
Test name
Test status
Simulation time 2953891371 ps
CPU time 7.1 seconds
Started Aug 25 06:34:44 AM UTC 24
Finished Aug 25 06:34:52 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307235351 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.307235351
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.2651796330
Short name T210
Test name
Test status
Simulation time 6360911665 ps
CPU time 15.97 seconds
Started Aug 25 06:34:50 AM UTC 24
Finished Aug 25 06:35:07 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651796330 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.2651796330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.1259581607
Short name T183
Test name
Test status
Simulation time 2630469352 ps
CPU time 3.95 seconds
Started Aug 25 06:34:43 AM UTC 24
Finished Aug 25 06:34:48 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1259581607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.1259581607
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.653110475
Short name T132
Test name
Test status
Simulation time 2473293856 ps
CPU time 3.06 seconds
Started Aug 25 06:34:39 AM UTC 24
Finished Aug 25 06:34:43 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653110475 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.653110475
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1417511813
Short name T500
Test name
Test status
Simulation time 2078322802 ps
CPU time 10.4 seconds
Started Aug 25 06:34:41 AM UTC 24
Finished Aug 25 06:34:53 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417511813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.1417511813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.1128222015
Short name T134
Test name
Test status
Simulation time 2524496714 ps
CPU time 3.49 seconds
Started Aug 25 06:34:42 AM UTC 24
Finished Aug 25 06:34:47 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128222015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.1128222015
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.2171909024
Short name T129
Test name
Test status
Simulation time 2168847953 ps
CPU time 1.42 seconds
Started Aug 25 06:34:38 AM UTC 24
Finished Aug 25 06:34:40 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2171909024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.2171909024
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.2724217387
Short name T503
Test name
Test status
Simulation time 9005691469 ps
CPU time 3.45 seconds
Started Aug 25 06:34:53 AM UTC 24
Finished Aug 25 06:34:57 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724217387 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.2724217387
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.2278271452
Short name T506
Test name
Test status
Simulation time 11852807728 ps
CPU time 8.6 seconds
Started Aug 25 06:34:52 AM UTC 24
Finished Aug 25 06:35:01 AM UTC 24
Peak memory 220536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2278271452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.2278271452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.2953455459
Short name T158
Test name
Test status
Simulation time 1416926285287 ps
CPU time 657.64 seconds
Started Aug 25 06:34:47 AM UTC 24
Finished Aug 25 06:45:53 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2953455459 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.2953455459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.2846357501
Short name T212
Test name
Test status
Simulation time 2038861222 ps
CPU time 2.73 seconds
Started Aug 25 06:35:08 AM UTC 24
Finished Aug 25 06:35:11 AM UTC 24
Peak memory 209816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2846357501 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.2846357501
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.803500210
Short name T476
Test name
Test status
Simulation time 3024763652 ps
CPU time 4.82 seconds
Started Aug 25 06:35:01 AM UTC 24
Finished Aug 25 06:35:07 AM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=803500210 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.803500210
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.3752482035
Short name T369
Test name
Test status
Simulation time 147353178752 ps
CPU time 642.92 seconds
Started Aug 25 06:35:03 AM UTC 24
Finished Aug 25 06:45:54 AM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3752482035 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.3752482035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1884150077
Short name T108
Test name
Test status
Simulation time 29839089910 ps
CPU time 71.02 seconds
Started Aug 25 06:35:04 AM UTC 24
Finished Aug 25 06:36:17 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1884150077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_with_pre_cond.1884150077
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3309794843
Short name T208
Test name
Test status
Simulation time 4348985802 ps
CPU time 5.07 seconds
Started Aug 25 06:35:00 AM UTC 24
Finished Aug 25 06:35:06 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3309794843 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.3309794843
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3944354536
Short name T209
Test name
Test status
Simulation time 2618916552 ps
CPU time 6.63 seconds
Started Aug 25 06:34:59 AM UTC 24
Finished Aug 25 06:35:06 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944354536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3944354536
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.79366166
Short name T207
Test name
Test status
Simulation time 2466935349 ps
CPU time 5.91 seconds
Started Aug 25 06:34:56 AM UTC 24
Finished Aug 25 06:35:03 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=79366166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.79366166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.1521817195
Short name T211
Test name
Test status
Simulation time 2027592149 ps
CPU time 9.64 seconds
Started Aug 25 06:34:56 AM UTC 24
Finished Aug 25 06:35:07 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1521817195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.1521817195
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.331179194
Short name T507
Test name
Test status
Simulation time 2547884064 ps
CPU time 2.56 seconds
Started Aug 25 06:34:58 AM UTC 24
Finished Aug 25 06:35:02 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=331179194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.331179194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.1604770531
Short name T504
Test name
Test status
Simulation time 2134980297 ps
CPU time 3.06 seconds
Started Aug 25 06:34:54 AM UTC 24
Finished Aug 25 06:34:58 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604770531 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1604770531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.132564983
Short name T521
Test name
Test status
Simulation time 12532184827 ps
CPU time 26.19 seconds
Started Aug 25 06:35:06 AM UTC 24
Finished Aug 25 06:35:34 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132564983 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.132564983
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2922598988
Short name T508
Test name
Test status
Simulation time 4590458388 ps
CPU time 7.97 seconds
Started Aug 25 06:35:04 AM UTC 24
Finished Aug 25 06:35:13 AM UTC 24
Peak memory 220176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2922598988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2922598988
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.1437573437
Short name T509
Test name
Test status
Simulation time 3946569490 ps
CPU time 12.11 seconds
Started Aug 25 06:35:03 AM UTC 24
Finished Aug 25 06:35:16 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437573437 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.1437573437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.3324020787
Short name T516
Test name
Test status
Simulation time 2026517058 ps
CPU time 5.19 seconds
Started Aug 25 06:35:18 AM UTC 24
Finished Aug 25 06:35:24 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3324020787 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.3324020787
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.3838061935
Short name T511
Test name
Test status
Simulation time 3618592503 ps
CPU time 2.46 seconds
Started Aug 25 06:35:13 AM UTC 24
Finished Aug 25 06:35:17 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3838061935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.3838061935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.1240831158
Short name T234
Test name
Test status
Simulation time 74755686899 ps
CPU time 294.74 seconds
Started Aug 25 06:35:14 AM UTC 24
Finished Aug 25 06:40:13 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240831158 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.1240831158
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.3273060954
Short name T109
Test name
Test status
Simulation time 25089065813 ps
CPU time 61.05 seconds
Started Aug 25 06:35:15 AM UTC 24
Finished Aug 25 06:36:18 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3273060954 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_with_pre_cond.3273060954
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.211698487
Short name T517
Test name
Test status
Simulation time 2689615607 ps
CPU time 12.28 seconds
Started Aug 25 06:35:13 AM UTC 24
Finished Aug 25 06:35:26 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211698487 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.211698487
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.2889950861
Short name T204
Test name
Test status
Simulation time 5999075301 ps
CPU time 15.84 seconds
Started Aug 25 06:35:14 AM UTC 24
Finished Aug 25 06:35:31 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889950861 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.2889950861
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.1329124846
Short name T518
Test name
Test status
Simulation time 2612282604 ps
CPU time 14.44 seconds
Started Aug 25 06:35:12 AM UTC 24
Finished Aug 25 06:35:27 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329124846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.1329124846
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.590759470
Short name T512
Test name
Test status
Simulation time 2466869880 ps
CPU time 10.33 seconds
Started Aug 25 06:35:08 AM UTC 24
Finished Aug 25 06:35:19 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=590759470 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.590759470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.1432248566
Short name T513
Test name
Test status
Simulation time 2047450304 ps
CPU time 10.47 seconds
Started Aug 25 06:35:08 AM UTC 24
Finished Aug 25 06:35:19 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1432248566 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.1432248566
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.2113677255
Short name T510
Test name
Test status
Simulation time 2523274103 ps
CPU time 3.59 seconds
Started Aug 25 06:35:12 AM UTC 24
Finished Aug 25 06:35:16 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2113677255 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.2113677255
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2665330127
Short name T213
Test name
Test status
Simulation time 2131346715 ps
CPU time 3.4 seconds
Started Aug 25 06:35:08 AM UTC 24
Finished Aug 25 06:35:12 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2665330127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.2665330127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.1284536098
Short name T205
Test name
Test status
Simulation time 12062282476 ps
CPU time 15.51 seconds
Started Aug 25 06:35:18 AM UTC 24
Finished Aug 25 06:35:34 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1284536098 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.1284536098
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2631938308
Short name T332
Test name
Test status
Simulation time 5618494900 ps
CPU time 12.6 seconds
Started Aug 25 06:35:17 AM UTC 24
Finished Aug 25 06:35:30 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2631938308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.2631938308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1595781185
Short name T143
Test name
Test status
Simulation time 12943723033 ps
CPU time 5.51 seconds
Started Aug 25 06:35:14 AM UTC 24
Finished Aug 25 06:35:21 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1595781185 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.1595781185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.4022828706
Short name T529
Test name
Test status
Simulation time 2009566185 ps
CPU time 10.67 seconds
Started Aug 25 06:35:32 AM UTC 24
Finished Aug 25 06:35:44 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4022828706 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.4022828706
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.1639094450
Short name T525
Test name
Test status
Simulation time 3131667192 ps
CPU time 13.97 seconds
Started Aug 25 06:35:25 AM UTC 24
Finished Aug 25 06:35:40 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1639094450 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.1639094450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3776180542
Short name T286
Test name
Test status
Simulation time 41437548566 ps
CPU time 99.75 seconds
Started Aug 25 06:35:29 AM UTC 24
Finished Aug 25 06:37:11 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776180542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_with_pre_cond.3776180542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1978721937
Short name T520
Test name
Test status
Simulation time 4025382771 ps
CPU time 5.15 seconds
Started Aug 25 06:35:24 AM UTC 24
Finished Aug 25 06:35:31 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1978721937 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.1978721937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3987962524
Short name T242
Test name
Test status
Simulation time 2835573536 ps
CPU time 12.19 seconds
Started Aug 25 06:35:29 AM UTC 24
Finished Aug 25 06:35:42 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987962524 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.3987962524
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.118548136
Short name T523
Test name
Test status
Simulation time 2611363464 ps
CPU time 12.25 seconds
Started Aug 25 06:35:23 AM UTC 24
Finished Aug 25 06:35:37 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=118548136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.118548136
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.363922466
Short name T519
Test name
Test status
Simulation time 2462967632 ps
CPU time 6.84 seconds
Started Aug 25 06:35:20 AM UTC 24
Finished Aug 25 06:35:28 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=363922466 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.363922466
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.1643488492
Short name T515
Test name
Test status
Simulation time 2230463057 ps
CPU time 2.75 seconds
Started Aug 25 06:35:20 AM UTC 24
Finished Aug 25 06:35:24 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643488492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.1643488492
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.3669128580
Short name T522
Test name
Test status
Simulation time 2512586243 ps
CPU time 12.91 seconds
Started Aug 25 06:35:22 AM UTC 24
Finished Aug 25 06:35:36 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3669128580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.3669128580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.1928935976
Short name T514
Test name
Test status
Simulation time 2146892823 ps
CPU time 2.62 seconds
Started Aug 25 06:35:19 AM UTC 24
Finished Aug 25 06:35:22 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1928935976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.1928935976
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.3336811529
Short name T350
Test name
Test status
Simulation time 49538216514 ps
CPU time 43.86 seconds
Started Aug 25 06:35:31 AM UTC 24
Finished Aug 25 06:36:17 AM UTC 24
Peak memory 210092 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3336811529 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.3336811529
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2265160695
Short name T544
Test name
Test status
Simulation time 13595652772 ps
CPU time 34.2 seconds
Started Aug 25 06:35:31 AM UTC 24
Finished Aug 25 06:36:07 AM UTC 24
Peak memory 226624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2265160695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.2265160695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.696150571
Short name T157
Test name
Test status
Simulation time 4305579426 ps
CPU time 14.41 seconds
Started Aug 25 06:35:26 AM UTC 24
Finished Aug 25 06:35:41 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=696150571 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.696150571
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.707788387
Short name T535
Test name
Test status
Simulation time 2011000810 ps
CPU time 8.87 seconds
Started Aug 25 06:35:43 AM UTC 24
Finished Aug 25 06:35:53 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=707788387 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.707788387
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2821977429
Short name T528
Test name
Test status
Simulation time 3400034370 ps
CPU time 4.34 seconds
Started Aug 25 06:35:37 AM UTC 24
Finished Aug 25 06:35:43 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821977429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.2821977429
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.3412285110
Short name T292
Test name
Test status
Simulation time 143322552819 ps
CPU time 606.06 seconds
Started Aug 25 06:35:39 AM UTC 24
Finished Aug 25 06:45:54 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412285110 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.3412285110
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.967510636
Short name T532
Test name
Test status
Simulation time 2716991197 ps
CPU time 12.86 seconds
Started Aug 25 06:35:36 AM UTC 24
Finished Aug 25 06:35:50 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=967510636 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.967510636
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.954175415
Short name T187
Test name
Test status
Simulation time 4346485288 ps
CPU time 13.12 seconds
Started Aug 25 06:35:41 AM UTC 24
Finished Aug 25 06:35:56 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=954175415 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.954175415
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.2037087551
Short name T533
Test name
Test status
Simulation time 2613189785 ps
CPU time 13.13 seconds
Started Aug 25 06:35:36 AM UTC 24
Finished Aug 25 06:35:50 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037087551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.2037087551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.2944430277
Short name T527
Test name
Test status
Simulation time 2472175145 ps
CPU time 3.98 seconds
Started Aug 25 06:35:35 AM UTC 24
Finished Aug 25 06:35:40 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2944430277 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.2944430277
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.4232433642
Short name T524
Test name
Test status
Simulation time 2066005360 ps
CPU time 2.1 seconds
Started Aug 25 06:35:35 AM UTC 24
Finished Aug 25 06:35:38 AM UTC 24
Peak memory 209336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4232433642 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.4232433642
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.3149684914
Short name T526
Test name
Test status
Simulation time 2528981635 ps
CPU time 3.32 seconds
Started Aug 25 06:35:35 AM UTC 24
Finished Aug 25 06:35:40 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149684914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.3149684914
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.2718010750
Short name T530
Test name
Test status
Simulation time 2113250818 ps
CPU time 9.14 seconds
Started Aug 25 06:35:35 AM UTC 24
Finished Aug 25 06:35:46 AM UTC 24
Peak memory 210000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2718010750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2718010750
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.2334564620
Short name T392
Test name
Test status
Simulation time 6336265595 ps
CPU time 3.49 seconds
Started Aug 25 06:35:42 AM UTC 24
Finished Aug 25 06:35:47 AM UTC 24
Peak memory 209936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334564620 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.2334564620
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.2122658264
Short name T172
Test name
Test status
Simulation time 190868229764 ps
CPU time 17.33 seconds
Started Aug 25 06:35:41 AM UTC 24
Finished Aug 25 06:36:00 AM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2122658264 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.2122658264
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.162748133
Short name T95
Test name
Test status
Simulation time 544989642817 ps
CPU time 39.04 seconds
Started Aug 25 06:35:37 AM UTC 24
Finished Aug 25 06:36:18 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=162748133 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.162748133
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.1642746697
Short name T540
Test name
Test status
Simulation time 2034839044 ps
CPU time 3.7 seconds
Started Aug 25 06:35:58 AM UTC 24
Finished Aug 25 06:36:03 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642746697 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.1642746697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.4138312827
Short name T548
Test name
Test status
Simulation time 3214293633 ps
CPU time 18.63 seconds
Started Aug 25 06:35:48 AM UTC 24
Finished Aug 25 06:36:08 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138312827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.4138312827
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3987783505
Short name T351
Test name
Test status
Simulation time 59536006624 ps
CPU time 44.52 seconds
Started Aug 25 06:35:51 AM UTC 24
Finished Aug 25 06:36:37 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3987783505 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.3987783505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2888814963
Short name T537
Test name
Test status
Simulation time 2989450269 ps
CPU time 9.03 seconds
Started Aug 25 06:35:48 AM UTC 24
Finished Aug 25 06:35:58 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2888814963 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.2888814963
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.840609675
Short name T188
Test name
Test status
Simulation time 5514229402 ps
CPU time 13.04 seconds
Started Aug 25 06:35:52 AM UTC 24
Finished Aug 25 06:36:06 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840609675 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.840609675
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1148980671
Short name T534
Test name
Test status
Simulation time 2634093626 ps
CPU time 3.99 seconds
Started Aug 25 06:35:47 AM UTC 24
Finished Aug 25 06:35:52 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1148980671 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1148980671
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.121308016
Short name T539
Test name
Test status
Simulation time 2450487844 ps
CPU time 13.36 seconds
Started Aug 25 06:35:44 AM UTC 24
Finished Aug 25 06:35:59 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=121308016 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.121308016
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1220717667
Short name T536
Test name
Test status
Simulation time 2158643718 ps
CPU time 9.61 seconds
Started Aug 25 06:35:45 AM UTC 24
Finished Aug 25 06:35:56 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1220717667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.1220717667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.687847096
Short name T538
Test name
Test status
Simulation time 2508210138 ps
CPU time 11.88 seconds
Started Aug 25 06:35:45 AM UTC 24
Finished Aug 25 06:35:59 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687847096 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.687847096
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.1590228961
Short name T531
Test name
Test status
Simulation time 2135274665 ps
CPU time 3.02 seconds
Started Aug 25 06:35:43 AM UTC 24
Finished Aug 25 06:35:47 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1590228961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.1590228961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.301376614
Short name T793
Test name
Test status
Simulation time 1104398824507 ps
CPU time 876.67 seconds
Started Aug 25 06:35:56 AM UTC 24
Finished Aug 25 06:50:43 AM UTC 24
Peak memory 210332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=301376614 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.301376614
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1254251502
Short name T551
Test name
Test status
Simulation time 4980134502 ps
CPU time 16.8 seconds
Started Aug 25 06:35:54 AM UTC 24
Finished Aug 25 06:36:13 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1254251502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.1254251502
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.340048720
Short name T541
Test name
Test status
Simulation time 6312117293 ps
CPU time 12.17 seconds
Started Aug 25 06:35:51 AM UTC 24
Finished Aug 25 06:36:04 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=340048720 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.340048720
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.2361830419
Short name T553
Test name
Test status
Simulation time 2043508703 ps
CPU time 3.58 seconds
Started Aug 25 06:36:08 AM UTC 24
Finished Aug 25 06:36:13 AM UTC 24
Peak memory 209852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2361830419 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.2361830419
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.1786186857
Short name T545
Test name
Test status
Simulation time 3614145703 ps
CPU time 8.49 seconds
Started Aug 25 06:36:05 AM UTC 24
Finished Aug 25 06:36:15 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1786186857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.1786186857
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.4268965754
Short name T281
Test name
Test status
Simulation time 104147608585 ps
CPU time 252.51 seconds
Started Aug 25 06:36:06 AM UTC 24
Finished Aug 25 06:40:22 AM UTC 24
Peak memory 210492 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4268965754 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.4268965754
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.1229414799
Short name T402
Test name
Test status
Simulation time 261299171528 ps
CPU time 261.98 seconds
Started Aug 25 06:36:07 AM UTC 24
Finished Aug 25 06:40:33 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229414799 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_with_pre_cond.1229414799
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.2193606154
Short name T549
Test name
Test status
Simulation time 2617153585 ps
CPU time 3.61 seconds
Started Aug 25 06:36:03 AM UTC 24
Finished Aug 25 06:36:08 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193606154 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.2193606154
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.4112094867
Short name T790
Test name
Test status
Simulation time 177026667165 ps
CPU time 661.84 seconds
Started Aug 25 06:36:07 AM UTC 24
Finished Aug 25 06:47:16 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4112094867 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.4112094867
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.785632544
Short name T547
Test name
Test status
Simulation time 2618754139 ps
CPU time 5.29 seconds
Started Aug 25 06:36:01 AM UTC 24
Finished Aug 25 06:36:07 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=785632544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.785632544
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.3295476933
Short name T546
Test name
Test status
Simulation time 2468839461 ps
CPU time 6.93 seconds
Started Aug 25 06:35:59 AM UTC 24
Finished Aug 25 06:36:07 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295476933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.3295476933
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.2827091570
Short name T543
Test name
Test status
Simulation time 2117627739 ps
CPU time 3.28 seconds
Started Aug 25 06:36:00 AM UTC 24
Finished Aug 25 06:36:05 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2827091570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.2827091570
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.3859383166
Short name T542
Test name
Test status
Simulation time 2531642228 ps
CPU time 3.22 seconds
Started Aug 25 06:36:00 AM UTC 24
Finished Aug 25 06:36:04 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3859383166 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.3859383166
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.2581289385
Short name T550
Test name
Test status
Simulation time 2114810830 ps
CPU time 11.44 seconds
Started Aug 25 06:35:59 AM UTC 24
Finished Aug 25 06:36:11 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2581289385 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.2581289385
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.65085713
Short name T409
Test name
Test status
Simulation time 2210474670379 ps
CPU time 198.01 seconds
Started Aug 25 06:36:08 AM UTC 24
Finished Aug 25 06:39:29 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=65085713 -assert nopostproc +UVM_TESTNA
ME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.65085713
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.1750716580
Short name T326
Test name
Test status
Simulation time 4190810965 ps
CPU time 11.61 seconds
Started Aug 25 06:36:08 AM UTC 24
Finished Aug 25 06:36:21 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1750716580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.1750716580
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2869584959
Short name T552
Test name
Test status
Simulation time 5525789491 ps
CPU time 6.33 seconds
Started Aug 25 06:36:05 AM UTC 24
Finished Aug 25 06:36:13 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2869584959 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.2869584959
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.3491092647
Short name T563
Test name
Test status
Simulation time 2016482964 ps
CPU time 6.18 seconds
Started Aug 25 06:36:20 AM UTC 24
Finished Aug 25 06:36:27 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491092647 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.3491092647
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3769102599
Short name T689
Test name
Test status
Simulation time 108434258262 ps
CPU time 224.16 seconds
Started Aug 25 06:36:14 AM UTC 24
Finished Aug 25 06:40:02 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3769102599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.3769102599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.1128927320
Short name T271
Test name
Test status
Simulation time 52411838117 ps
CPU time 63.21 seconds
Started Aug 25 06:36:17 AM UTC 24
Finished Aug 25 06:37:22 AM UTC 24
Peak memory 210168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128927320 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.1128927320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.3849703797
Short name T557
Test name
Test status
Simulation time 2679659117 ps
CPU time 3.84 seconds
Started Aug 25 06:36:14 AM UTC 24
Finished Aug 25 06:36:19 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3849703797 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.3849703797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.526660056
Short name T214
Test name
Test status
Simulation time 2468448366 ps
CPU time 3.6 seconds
Started Aug 25 06:36:18 AM UTC 24
Finished Aug 25 06:36:23 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526660056 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.526660056
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.18241130
Short name T555
Test name
Test status
Simulation time 2650413769 ps
CPU time 2.62 seconds
Started Aug 25 06:36:14 AM UTC 24
Finished Aug 25 06:36:18 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18241130 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.18241130
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.417091102
Short name T559
Test name
Test status
Simulation time 2471436706 ps
CPU time 11.9 seconds
Started Aug 25 06:36:09 AM UTC 24
Finished Aug 25 06:36:22 AM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417091102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.417091102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2826080542
Short name T558
Test name
Test status
Simulation time 2224459198 ps
CPU time 5.78 seconds
Started Aug 25 06:36:12 AM UTC 24
Finished Aug 25 06:36:19 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2826080542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2826080542
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.2099157822
Short name T556
Test name
Test status
Simulation time 2529417263 ps
CPU time 3.67 seconds
Started Aug 25 06:36:14 AM UTC 24
Finished Aug 25 06:36:19 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099157822 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.2099157822
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.1839065213
Short name T554
Test name
Test status
Simulation time 2130951169 ps
CPU time 3.85 seconds
Started Aug 25 06:36:08 AM UTC 24
Finished Aug 25 06:36:13 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839065213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.1839065213
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.4174711739
Short name T280
Test name
Test status
Simulation time 70512029693 ps
CPU time 33.53 seconds
Started Aug 25 06:36:20 AM UTC 24
Finished Aug 25 06:36:55 AM UTC 24
Peak memory 210304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4174711739 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.4174711739
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.1538802783
Short name T260
Test name
Test status
Simulation time 27352085532 ps
CPU time 9.14 seconds
Started Aug 25 06:36:18 AM UTC 24
Finished Aug 25 06:36:29 AM UTC 24
Peak memory 210312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1538802783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.1538802783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.54313029
Short name T564
Test name
Test status
Simulation time 6166007760 ps
CPU time 10.17 seconds
Started Aug 25 06:36:16 AM UTC 24
Finished Aug 25 06:36:27 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=54313029 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.54313029
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.4013481027
Short name T569
Test name
Test status
Simulation time 2018420924 ps
CPU time 6.01 seconds
Started Aug 25 06:36:29 AM UTC 24
Finished Aug 25 06:36:37 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4013481027 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.4013481027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.243012323
Short name T570
Test name
Test status
Simulation time 3089560533 ps
CPU time 13.27 seconds
Started Aug 25 06:36:25 AM UTC 24
Finished Aug 25 06:36:39 AM UTC 24
Peak memory 210020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=243012323 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.243012323
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2380564950
Short name T117
Test name
Test status
Simulation time 87341010221 ps
CPU time 382.95 seconds
Started Aug 25 06:36:28 AM UTC 24
Finished Aug 25 06:42:56 AM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380564950 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.2380564950
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3777286715
Short name T356
Test name
Test status
Simulation time 40844167962 ps
CPU time 87.03 seconds
Started Aug 25 06:36:28 AM UTC 24
Finished Aug 25 06:37:57 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777286715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_with_pre_cond.3777286715
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.24288678
Short name T575
Test name
Test status
Simulation time 3355175609 ps
CPU time 21.27 seconds
Started Aug 25 06:36:24 AM UTC 24
Finished Aug 25 06:36:47 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=24288678 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.24288678
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1957418504
Short name T567
Test name
Test status
Simulation time 2663451641 ps
CPU time 3.83 seconds
Started Aug 25 06:36:28 AM UTC 24
Finished Aug 25 06:36:33 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1957418504 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.1957418504
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2653455680
Short name T565
Test name
Test status
Simulation time 2629706271 ps
CPU time 3.05 seconds
Started Aug 25 06:36:23 AM UTC 24
Finished Aug 25 06:36:27 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2653455680 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.2653455680
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.2029689437
Short name T566
Test name
Test status
Simulation time 2458571860 ps
CPU time 6.69 seconds
Started Aug 25 06:36:20 AM UTC 24
Finished Aug 25 06:36:28 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2029689437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2029689437
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1774705035
Short name T561
Test name
Test status
Simulation time 2254565003 ps
CPU time 3.48 seconds
Started Aug 25 06:36:22 AM UTC 24
Finished Aug 25 06:36:27 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1774705035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.1774705035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.3176926282
Short name T562
Test name
Test status
Simulation time 2562177603 ps
CPU time 2.68 seconds
Started Aug 25 06:36:23 AM UTC 24
Finished Aug 25 06:36:27 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3176926282 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.3176926282
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.2536436436
Short name T560
Test name
Test status
Simulation time 2148912213 ps
CPU time 2.42 seconds
Started Aug 25 06:36:20 AM UTC 24
Finished Aug 25 06:36:23 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2536436436 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.2536436436
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.3508877491
Short name T581
Test name
Test status
Simulation time 7124390391 ps
CPU time 23.24 seconds
Started Aug 25 06:36:29 AM UTC 24
Finished Aug 25 06:36:54 AM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3508877491 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.3508877491
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2543052314
Short name T328
Test name
Test status
Simulation time 13076984970 ps
CPU time 14.7 seconds
Started Aug 25 06:36:28 AM UTC 24
Finished Aug 25 06:36:44 AM UTC 24
Peak memory 226540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2543052314 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.2543052314
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.1888737842
Short name T320
Test name
Test status
Simulation time 2027965810 ps
CPU time 3.99 seconds
Started Aug 25 06:30:21 AM UTC 24
Finished Aug 25 06:30:26 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1888737842 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.1888737842
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.3046343432
Short name T55
Test name
Test status
Simulation time 3015392925 ps
CPU time 2.19 seconds
Started Aug 25 06:30:14 AM UTC 24
Finished Aug 25 06:30:17 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046343432 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.3046343432
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3040523691
Short name T364
Test name
Test status
Simulation time 175927256207 ps
CPU time 836.74 seconds
Started Aug 25 06:30:16 AM UTC 24
Finished Aug 25 06:44:24 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3040523691 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.3040523691
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.325849251
Short name T54
Test name
Test status
Simulation time 2217953567 ps
CPU time 5.88 seconds
Started Aug 25 06:30:08 AM UTC 24
Finished Aug 25 06:30:15 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=325849251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.325849251
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3111237918
Short name T56
Test name
Test status
Simulation time 2359272704 ps
CPU time 11.32 seconds
Started Aug 25 06:30:09 AM UTC 24
Finished Aug 25 06:30:22 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3111237918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3111237918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.555557915
Short name T325
Test name
Test status
Simulation time 3392188304 ps
CPU time 8.4 seconds
Started Aug 25 06:30:14 AM UTC 24
Finished Aug 25 06:30:23 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=555557915 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.555557915
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.3009618337
Short name T50
Test name
Test status
Simulation time 3703620755 ps
CPU time 9.12 seconds
Started Aug 25 06:30:16 AM UTC 24
Finished Aug 25 06:30:26 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3009618337 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.3009618337
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.2470932857
Short name T78
Test name
Test status
Simulation time 2640318486 ps
CPU time 3.95 seconds
Started Aug 25 06:30:12 AM UTC 24
Finished Aug 25 06:30:17 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470932857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.2470932857
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.4242056854
Short name T64
Test name
Test status
Simulation time 2484519284 ps
CPU time 3.8 seconds
Started Aug 25 06:30:08 AM UTC 24
Finished Aug 25 06:30:13 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4242056854 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.4242056854
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.214726763
Short name T324
Test name
Test status
Simulation time 2091702666 ps
CPU time 9.67 seconds
Started Aug 25 06:30:11 AM UTC 24
Finished Aug 25 06:30:22 AM UTC 24
Peak memory 209820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=214726763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.214726763
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.1794665046
Short name T122
Test name
Test status
Simulation time 42012317266 ps
CPU time 189.03 seconds
Started Aug 25 06:30:19 AM UTC 24
Finished Aug 25 06:33:32 AM UTC 24
Peak memory 240284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1794665046 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.1794665046
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.2646136870
Short name T323
Test name
Test status
Simulation time 2109334564 ps
CPU time 11.43 seconds
Started Aug 25 06:30:07 AM UTC 24
Finished Aug 25 06:30:19 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2646136870 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2646136870
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1031169
Short name T46
Test name
Test status
Simulation time 7547560026 ps
CPU time 9.12 seconds
Started Aug 25 06:30:18 AM UTC 24
Finished Aug 25 06:30:28 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031169 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.1031169
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.2906362534
Short name T67
Test name
Test status
Simulation time 7595911480 ps
CPU time 10.41 seconds
Started Aug 25 06:30:15 AM UTC 24
Finished Aug 25 06:30:26 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2906362534 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.2906362534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.3362783629
Short name T578
Test name
Test status
Simulation time 2092675641 ps
CPU time 1.64 seconds
Started Aug 25 06:36:48 AM UTC 24
Finished Aug 25 06:36:50 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3362783629 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.3362783629
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1283844448
Short name T577
Test name
Test status
Simulation time 3354746568 ps
CPU time 8.46 seconds
Started Aug 25 06:36:40 AM UTC 24
Finished Aug 25 06:36:50 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283844448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.1283844448
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.1871182783
Short name T787
Test name
Test status
Simulation time 151365795427 ps
CPU time 611.93 seconds
Started Aug 25 06:36:42 AM UTC 24
Finished Aug 25 06:47:02 AM UTC 24
Peak memory 210108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871182783 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.1871182783
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.763809595
Short name T229
Test name
Test status
Simulation time 47599886088 ps
CPU time 57.77 seconds
Started Aug 25 06:36:43 AM UTC 24
Finished Aug 25 06:37:43 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=763809595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_with_pre_cond.763809595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.2317387020
Short name T574
Test name
Test status
Simulation time 3870540747 ps
CPU time 3.94 seconds
Started Aug 25 06:36:38 AM UTC 24
Finished Aug 25 06:36:43 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2317387020 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.2317387020
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.3718506311
Short name T200
Test name
Test status
Simulation time 4244313158 ps
CPU time 2.75 seconds
Started Aug 25 06:36:43 AM UTC 24
Finished Aug 25 06:36:47 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718506311 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.3718506311
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.545059561
Short name T579
Test name
Test status
Simulation time 2610827564 ps
CPU time 11.51 seconds
Started Aug 25 06:36:38 AM UTC 24
Finished Aug 25 06:36:51 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=545059561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.545059561
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.3038894591
Short name T572
Test name
Test status
Simulation time 2441520445 ps
CPU time 7.11 seconds
Started Aug 25 06:36:34 AM UTC 24
Finished Aug 25 06:36:42 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3038894591 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.3038894591
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.2513209114
Short name T571
Test name
Test status
Simulation time 2131813591 ps
CPU time 3.24 seconds
Started Aug 25 06:36:35 AM UTC 24
Finished Aug 25 06:36:39 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2513209114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.2513209114
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.2334732987
Short name T573
Test name
Test status
Simulation time 2522260403 ps
CPU time 5.09 seconds
Started Aug 25 06:36:37 AM UTC 24
Finished Aug 25 06:36:43 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2334732987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.2334732987
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.2674841603
Short name T568
Test name
Test status
Simulation time 2132391592 ps
CPU time 3.29 seconds
Started Aug 25 06:36:29 AM UTC 24
Finished Aug 25 06:36:34 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2674841603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.2674841603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.406154949
Short name T585
Test name
Test status
Simulation time 8324170845 ps
CPU time 7.98 seconds
Started Aug 25 06:36:48 AM UTC 24
Finished Aug 25 06:36:57 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406154949 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.406154949
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.3365294261
Short name T588
Test name
Test status
Simulation time 3163874088 ps
CPU time 14.75 seconds
Started Aug 25 06:36:45 AM UTC 24
Finished Aug 25 06:37:00 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3365294261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.3365294261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.4273848871
Short name T576
Test name
Test status
Simulation time 7254557434 ps
CPU time 6.13 seconds
Started Aug 25 06:36:40 AM UTC 24
Finished Aug 25 06:36:47 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4273848871 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.4273848871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.1147551481
Short name T590
Test name
Test status
Simulation time 2047465687 ps
CPU time 3.34 seconds
Started Aug 25 06:36:59 AM UTC 24
Finished Aug 25 06:37:03 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147551481 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.1147551481
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.1777081532
Short name T589
Test name
Test status
Simulation time 3316201051 ps
CPU time 8.12 seconds
Started Aug 25 06:36:53 AM UTC 24
Finished Aug 25 06:37:03 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777081532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.1777081532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.995689599
Short name T267
Test name
Test status
Simulation time 35783725470 ps
CPU time 72.46 seconds
Started Aug 25 06:36:57 AM UTC 24
Finished Aug 25 06:38:11 AM UTC 24
Peak memory 209996 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=995689599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_with_pre_cond.995689599
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1514850487
Short name T591
Test name
Test status
Simulation time 4371738379 ps
CPU time 10.9 seconds
Started Aug 25 06:36:51 AM UTC 24
Finished Aug 25 06:37:03 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514850487 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.1514850487
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.2319841904
Short name T243
Test name
Test status
Simulation time 4135435034 ps
CPU time 2.25 seconds
Started Aug 25 06:36:57 AM UTC 24
Finished Aug 25 06:37:00 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2319841904 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.2319841904
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.1363749452
Short name T584
Test name
Test status
Simulation time 2624319621 ps
CPU time 3.99 seconds
Started Aug 25 06:36:51 AM UTC 24
Finished Aug 25 06:36:56 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1363749452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.1363749452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.2655508823
Short name T587
Test name
Test status
Simulation time 2461349077 ps
CPU time 7.18 seconds
Started Aug 25 06:36:50 AM UTC 24
Finished Aug 25 06:36:58 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2655508823 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.2655508823
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.974874795
Short name T582
Test name
Test status
Simulation time 2142348280 ps
CPU time 3.42 seconds
Started Aug 25 06:36:51 AM UTC 24
Finished Aug 25 06:36:56 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=974874795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.974874795
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.4024703387
Short name T583
Test name
Test status
Simulation time 2527237050 ps
CPU time 3.52 seconds
Started Aug 25 06:36:51 AM UTC 24
Finished Aug 25 06:36:56 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4024703387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.4024703387
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.3108168290
Short name T580
Test name
Test status
Simulation time 2147633980 ps
CPU time 2.8 seconds
Started Aug 25 06:36:49 AM UTC 24
Finished Aug 25 06:36:53 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3108168290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.3108168290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.1825087777
Short name T595
Test name
Test status
Simulation time 8445645217 ps
CPU time 9.61 seconds
Started Aug 25 06:36:58 AM UTC 24
Finished Aug 25 06:37:09 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825087777 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.1825087777
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.3534091025
Short name T599
Test name
Test status
Simulation time 3743718751 ps
CPU time 19.34 seconds
Started Aug 25 06:36:57 AM UTC 24
Finished Aug 25 06:37:17 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3534091025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.3534091025
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1906052903
Short name T586
Test name
Test status
Simulation time 7397696832 ps
CPU time 2.62 seconds
Started Aug 25 06:36:55 AM UTC 24
Finished Aug 25 06:36:58 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906052903 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.1906052903
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1625443910
Short name T600
Test name
Test status
Simulation time 2040266185 ps
CPU time 3.32 seconds
Started Aug 25 06:37:13 AM UTC 24
Finished Aug 25 06:37:18 AM UTC 24
Peak memory 209816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625443910 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.1625443910
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.248410074
Short name T606
Test name
Test status
Simulation time 3894836983 ps
CPU time 16.23 seconds
Started Aug 25 06:37:07 AM UTC 24
Finished Aug 25 06:37:24 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248410074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.248410074
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2904515735
Short name T227
Test name
Test status
Simulation time 34700655624 ps
CPU time 29.4 seconds
Started Aug 25 06:37:10 AM UTC 24
Finished Aug 25 06:37:41 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2904515735 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_with_pre_cond.2904515735
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.3528658948
Short name T592
Test name
Test status
Simulation time 3242340493 ps
CPU time 1.73 seconds
Started Aug 25 06:37:05 AM UTC 24
Finished Aug 25 06:37:07 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3528658948 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.3528658948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1960056910
Short name T593
Test name
Test status
Simulation time 2702682369 ps
CPU time 1.86 seconds
Started Aug 25 06:37:05 AM UTC 24
Finished Aug 25 06:37:07 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1960056910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.1960056910
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.261250646
Short name T597
Test name
Test status
Simulation time 2470287651 ps
CPU time 10.44 seconds
Started Aug 25 06:37:01 AM UTC 24
Finished Aug 25 06:37:13 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=261250646 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.261250646
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.3172154290
Short name T596
Test name
Test status
Simulation time 2197695554 ps
CPU time 9.83 seconds
Started Aug 25 06:37:01 AM UTC 24
Finished Aug 25 06:37:12 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3172154290 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.3172154290
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.727952430
Short name T594
Test name
Test status
Simulation time 2531417133 ps
CPU time 3.87 seconds
Started Aug 25 06:37:03 AM UTC 24
Finished Aug 25 06:37:08 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=727952430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.727952430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.2235250172
Short name T598
Test name
Test status
Simulation time 2113991055 ps
CPU time 13.13 seconds
Started Aug 25 06:36:59 AM UTC 24
Finished Aug 25 06:37:13 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2235250172 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.2235250172
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.2806644062
Short name T173
Test name
Test status
Simulation time 17150622660 ps
CPU time 6.12 seconds
Started Aug 25 06:37:13 AM UTC 24
Finished Aug 25 06:37:21 AM UTC 24
Peak memory 210480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806644062 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.2806644062
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.1726056333
Short name T613
Test name
Test status
Simulation time 6941975956 ps
CPU time 35.69 seconds
Started Aug 25 06:37:12 AM UTC 24
Finished Aug 25 06:37:49 AM UTC 24
Peak memory 220468 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1726056333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.1726056333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1068848006
Short name T602
Test name
Test status
Simulation time 2565948055 ps
CPU time 10.15 seconds
Started Aug 25 06:37:08 AM UTC 24
Finished Aug 25 06:37:19 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068848006 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.1068848006
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.3536114952
Short name T609
Test name
Test status
Simulation time 2025882531 ps
CPU time 3.45 seconds
Started Aug 25 06:37:28 AM UTC 24
Finished Aug 25 06:37:32 AM UTC 24
Peak memory 209816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3536114952 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.3536114952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.2829070101
Short name T607
Test name
Test status
Simulation time 3545161007 ps
CPU time 5.43 seconds
Started Aug 25 06:37:20 AM UTC 24
Finished Aug 25 06:37:27 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2829070101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.2829070101
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.3115803450
Short name T357
Test name
Test status
Simulation time 153058880683 ps
CPU time 617.96 seconds
Started Aug 25 06:37:21 AM UTC 24
Finished Aug 25 06:47:47 AM UTC 24
Peak memory 210108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3115803450 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.3115803450
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.2563264851
Short name T224
Test name
Test status
Simulation time 3553687650 ps
CPU time 18.25 seconds
Started Aug 25 06:37:20 AM UTC 24
Finished Aug 25 06:37:40 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563264851 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.2563264851
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.4280095151
Short name T608
Test name
Test status
Simulation time 2617384361 ps
CPU time 7.16 seconds
Started Aug 25 06:37:19 AM UTC 24
Finished Aug 25 06:37:27 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280095151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.4280095151
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.1437985836
Short name T603
Test name
Test status
Simulation time 2480860458 ps
CPU time 3.83 seconds
Started Aug 25 06:37:15 AM UTC 24
Finished Aug 25 06:37:19 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437985836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.1437985836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2772216869
Short name T601
Test name
Test status
Simulation time 2117159197 ps
CPU time 2.73 seconds
Started Aug 25 06:37:15 AM UTC 24
Finished Aug 25 06:37:18 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2772216869 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.2772216869
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.1078601945
Short name T610
Test name
Test status
Simulation time 2511436226 ps
CPU time 12.77 seconds
Started Aug 25 06:37:19 AM UTC 24
Finished Aug 25 06:37:33 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1078601945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.1078601945
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.3537744523
Short name T604
Test name
Test status
Simulation time 2114256519 ps
CPU time 5.27 seconds
Started Aug 25 06:37:13 AM UTC 24
Finished Aug 25 06:37:20 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3537744523 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.3537744523
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.623085438
Short name T642
Test name
Test status
Simulation time 12439981459 ps
CPU time 62.36 seconds
Started Aug 25 06:37:25 AM UTC 24
Finished Aug 25 06:38:30 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623085438 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.623085438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.1200568762
Short name T618
Test name
Test status
Simulation time 10374521498 ps
CPU time 28.7 seconds
Started Aug 25 06:37:24 AM UTC 24
Finished Aug 25 06:37:55 AM UTC 24
Peak memory 210624 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1200568762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.1200568762
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1625218452
Short name T605
Test name
Test status
Simulation time 5647616834 ps
CPU time 2.57 seconds
Started Aug 25 06:37:20 AM UTC 24
Finished Aug 25 06:37:24 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1625218452 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.1625218452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.837772947
Short name T612
Test name
Test status
Simulation time 2029769260 ps
CPU time 3.53 seconds
Started Aug 25 06:37:44 AM UTC 24
Finished Aug 25 06:37:48 AM UTC 24
Peak memory 209796 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837772947 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.837772947
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3655558206
Short name T619
Test name
Test status
Simulation time 3026669581 ps
CPU time 16.09 seconds
Started Aug 25 06:37:37 AM UTC 24
Finished Aug 25 06:37:55 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655558206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.3655558206
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.2066077791
Short name T272
Test name
Test status
Simulation time 47998920719 ps
CPU time 45.38 seconds
Started Aug 25 06:37:40 AM UTC 24
Finished Aug 25 06:38:27 AM UTC 24
Peak memory 210504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2066077791 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.2066077791
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2087384862
Short name T622
Test name
Test status
Simulation time 3860986828 ps
CPU time 19.75 seconds
Started Aug 25 06:37:36 AM UTC 24
Finished Aug 25 06:37:57 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087384862 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.2087384862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.2641718939
Short name T231
Test name
Test status
Simulation time 4395771248 ps
CPU time 3.96 seconds
Started Aug 25 06:37:41 AM UTC 24
Finished Aug 25 06:37:46 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641718939 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.2641718939
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.1219502299
Short name T225
Test name
Test status
Simulation time 2672182444 ps
CPU time 2.64 seconds
Started Aug 25 06:37:36 AM UTC 24
Finished Aug 25 06:37:40 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1219502299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.1219502299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.4237231844
Short name T223
Test name
Test status
Simulation time 2496909660 ps
CPU time 4.38 seconds
Started Aug 25 06:37:31 AM UTC 24
Finished Aug 25 06:37:36 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4237231844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.4237231844
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.2488052557
Short name T230
Test name
Test status
Simulation time 2020254975 ps
CPU time 10 seconds
Started Aug 25 06:37:33 AM UTC 24
Finished Aug 25 06:37:45 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2488052557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.2488052557
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.2959541033
Short name T226
Test name
Test status
Simulation time 2529354269 ps
CPU time 4.53 seconds
Started Aug 25 06:37:34 AM UTC 24
Finished Aug 25 06:37:40 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959541033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.2959541033
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.3798594725
Short name T228
Test name
Test status
Simulation time 2107172765 ps
CPU time 11.34 seconds
Started Aug 25 06:37:29 AM UTC 24
Finished Aug 25 06:37:41 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798594725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.3798594725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.1439535613
Short name T625
Test name
Test status
Simulation time 6734290121 ps
CPU time 15.75 seconds
Started Aug 25 06:37:44 AM UTC 24
Finished Aug 25 06:38:01 AM UTC 24
Peak memory 209508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1439535613 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.1439535613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.2420167864
Short name T333
Test name
Test status
Simulation time 93420741605 ps
CPU time 18.81 seconds
Started Aug 25 06:37:43 AM UTC 24
Finished Aug 25 06:38:03 AM UTC 24
Peak memory 222852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2420167864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.2420167864
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1832134403
Short name T615
Test name
Test status
Simulation time 5783584289 ps
CPU time 8.09 seconds
Started Aug 25 06:37:40 AM UTC 24
Finished Aug 25 06:37:49 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1832134403 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.1832134403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.513752662
Short name T626
Test name
Test status
Simulation time 2071777381 ps
CPU time 1.65 seconds
Started Aug 25 06:37:58 AM UTC 24
Finished Aug 25 06:38:01 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=513752662 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.513752662
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.1788672785
Short name T621
Test name
Test status
Simulation time 3593390042 ps
CPU time 3.35 seconds
Started Aug 25 06:37:51 AM UTC 24
Finished Aug 25 06:37:56 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1788672785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.1788672785
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2507911714
Short name T358
Test name
Test status
Simulation time 167781455605 ps
CPU time 629.63 seconds
Started Aug 25 06:37:56 AM UTC 24
Finished Aug 25 06:48:32 AM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2507911714 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.2507911714
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.637045584
Short name T754
Test name
Test status
Simulation time 46364403413 ps
CPU time 236.51 seconds
Started Aug 25 06:37:57 AM UTC 24
Finished Aug 25 06:41:57 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=637045584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_with_pre_cond.637045584
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.3174685218
Short name T623
Test name
Test status
Simulation time 5312857039 ps
CPU time 7.28 seconds
Started Aug 25 06:37:50 AM UTC 24
Finished Aug 25 06:37:59 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3174685218 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.3174685218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.1589250452
Short name T632
Test name
Test status
Simulation time 2833476382 ps
CPU time 14.32 seconds
Started Aug 25 06:37:56 AM UTC 24
Finished Aug 25 06:38:11 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589250452 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.1589250452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3843563439
Short name T624
Test name
Test status
Simulation time 2617429122 ps
CPU time 7.55 seconds
Started Aug 25 06:37:50 AM UTC 24
Finished Aug 25 06:37:59 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3843563439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.3843563439
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.1035790936
Short name T616
Test name
Test status
Simulation time 2504921690 ps
CPU time 2.61 seconds
Started Aug 25 06:37:47 AM UTC 24
Finished Aug 25 06:37:51 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035790936 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.1035790936
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.2538082637
Short name T617
Test name
Test status
Simulation time 2054084679 ps
CPU time 3.88 seconds
Started Aug 25 06:37:49 AM UTC 24
Finished Aug 25 06:37:54 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538082637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.2538082637
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.1460448695
Short name T620
Test name
Test status
Simulation time 2537359419 ps
CPU time 4.14 seconds
Started Aug 25 06:37:50 AM UTC 24
Finished Aug 25 06:37:56 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1460448695 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.1460448695
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.2987245480
Short name T614
Test name
Test status
Simulation time 2134496472 ps
CPU time 3.49 seconds
Started Aug 25 06:37:45 AM UTC 24
Finished Aug 25 06:37:49 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987245480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.2987245480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.1582851134
Short name T664
Test name
Test status
Simulation time 18731719574 ps
CPU time 84.67 seconds
Started Aug 25 06:37:58 AM UTC 24
Finished Aug 25 06:39:25 AM UTC 24
Peak memory 209928 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582851134 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.1582851134
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1019109594
Short name T630
Test name
Test status
Simulation time 3905365546 ps
CPU time 12.73 seconds
Started Aug 25 06:37:57 AM UTC 24
Finished Aug 25 06:38:11 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1019109594 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1019109594
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3477672592
Short name T756
Test name
Test status
Simulation time 1070022494635 ps
CPU time 249.34 seconds
Started Aug 25 06:37:55 AM UTC 24
Finished Aug 25 06:42:08 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477672592 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.3477672592
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.2627077258
Short name T636
Test name
Test status
Simulation time 2040445357 ps
CPU time 2.7 seconds
Started Aug 25 06:38:13 AM UTC 24
Finished Aug 25 06:38:17 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2627077258 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.2627077258
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3392859388
Short name T639
Test name
Test status
Simulation time 3212721245 ps
CPU time 15.7 seconds
Started Aug 25 06:38:06 AM UTC 24
Finished Aug 25 06:38:23 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392859388 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3392859388
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.3572058578
Short name T399
Test name
Test status
Simulation time 48467617159 ps
CPU time 209.76 seconds
Started Aug 25 06:38:10 AM UTC 24
Finished Aug 25 06:41:43 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572058578 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.3572058578
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.330523826
Short name T112
Test name
Test status
Simulation time 60299100089 ps
CPU time 57.32 seconds
Started Aug 25 06:38:12 AM UTC 24
Finished Aug 25 06:39:11 AM UTC 24
Peak memory 210332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=330523826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_with_pre_cond.330523826
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2704362846
Short name T788
Test name
Test status
Simulation time 1065996082259 ps
CPU time 532.31 seconds
Started Aug 25 06:38:04 AM UTC 24
Finished Aug 25 06:47:02 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2704362846 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.2704362846
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.2754168633
Short name T635
Test name
Test status
Simulation time 2695548344 ps
CPU time 3.45 seconds
Started Aug 25 06:38:12 AM UTC 24
Finished Aug 25 06:38:17 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2754168633 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.2754168633
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.283295421
Short name T634
Test name
Test status
Simulation time 2613916240 ps
CPU time 11.45 seconds
Started Aug 25 06:38:01 AM UTC 24
Finished Aug 25 06:38:14 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=283295421 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.283295421
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.1317468632
Short name T627
Test name
Test status
Simulation time 2477466580 ps
CPU time 4.36 seconds
Started Aug 25 06:37:59 AM UTC 24
Finished Aug 25 06:38:05 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317468632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.1317468632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.3999398150
Short name T631
Test name
Test status
Simulation time 2206062514 ps
CPU time 9.6 seconds
Started Aug 25 06:38:00 AM UTC 24
Finished Aug 25 06:38:11 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3999398150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.3999398150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.1453436871
Short name T629
Test name
Test status
Simulation time 2516169122 ps
CPU time 6.79 seconds
Started Aug 25 06:38:01 AM UTC 24
Finished Aug 25 06:38:09 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1453436871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.1453436871
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.1756062704
Short name T628
Test name
Test status
Simulation time 2116650967 ps
CPU time 5.09 seconds
Started Aug 25 06:37:59 AM UTC 24
Finished Aug 25 06:38:05 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1756062704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1756062704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.600723362
Short name T644
Test name
Test status
Simulation time 18284522149 ps
CPU time 20.16 seconds
Started Aug 25 06:38:12 AM UTC 24
Finished Aug 25 06:38:33 AM UTC 24
Peak memory 226868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=600723362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.600723362
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1430377651
Short name T633
Test name
Test status
Simulation time 5246940722 ps
CPU time 4.1 seconds
Started Aug 25 06:38:07 AM UTC 24
Finished Aug 25 06:38:12 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1430377651 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.1430377651
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.2875989669
Short name T647
Test name
Test status
Simulation time 2030118891 ps
CPU time 3.77 seconds
Started Aug 25 06:38:35 AM UTC 24
Finished Aug 25 06:38:40 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2875989669 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.2875989669
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1833633051
Short name T643
Test name
Test status
Simulation time 3499518313 ps
CPU time 8.81 seconds
Started Aug 25 06:38:23 AM UTC 24
Finished Aug 25 06:38:33 AM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833633051 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.1833633051
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.211625266
Short name T99
Test name
Test status
Simulation time 50788936896 ps
CPU time 157.39 seconds
Started Aug 25 06:38:28 AM UTC 24
Finished Aug 25 06:41:09 AM UTC 24
Peak memory 210328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211625266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_with_pre_cond.211625266
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.1072179386
Short name T645
Test name
Test status
Simulation time 4048477108 ps
CPU time 10.05 seconds
Started Aug 25 06:38:23 AM UTC 24
Finished Aug 25 06:38:34 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072179386 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.1072179386
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.754813870
Short name T102
Test name
Test status
Simulation time 3927829481 ps
CPU time 16.86 seconds
Started Aug 25 06:38:27 AM UTC 24
Finished Aug 25 06:38:45 AM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=754813870 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.754813870
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1235361716
Short name T646
Test name
Test status
Simulation time 2611369935 ps
CPU time 13.35 seconds
Started Aug 25 06:38:22 AM UTC 24
Finished Aug 25 06:38:36 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1235361716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.1235361716
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.2353609097
Short name T638
Test name
Test status
Simulation time 2498797990 ps
CPU time 3.55 seconds
Started Aug 25 06:38:18 AM UTC 24
Finished Aug 25 06:38:22 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2353609097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.2353609097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3831645468
Short name T640
Test name
Test status
Simulation time 2234334592 ps
CPU time 5.86 seconds
Started Aug 25 06:38:18 AM UTC 24
Finished Aug 25 06:38:25 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3831645468 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3831645468
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.2597682444
Short name T641
Test name
Test status
Simulation time 2529462552 ps
CPU time 4.26 seconds
Started Aug 25 06:38:21 AM UTC 24
Finished Aug 25 06:38:26 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597682444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.2597682444
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.641189327
Short name T637
Test name
Test status
Simulation time 2136745029 ps
CPU time 3.39 seconds
Started Aug 25 06:38:15 AM UTC 24
Finished Aug 25 06:38:20 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=641189327 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.641189327
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.3847277862
Short name T291
Test name
Test status
Simulation time 53977153044 ps
CPU time 242.29 seconds
Started Aug 25 06:38:34 AM UTC 24
Finished Aug 25 06:42:40 AM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3847277862 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.3847277862
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3043766900
Short name T147
Test name
Test status
Simulation time 2971574830 ps
CPU time 15.38 seconds
Started Aug 25 06:38:31 AM UTC 24
Finished Aug 25 06:38:47 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3043766900 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.3043766900
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.902652961
Short name T152
Test name
Test status
Simulation time 7654207257 ps
CPU time 12.78 seconds
Started Aug 25 06:38:24 AM UTC 24
Finished Aug 25 06:38:38 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=902652961 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.902652961
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.4117966269
Short name T651
Test name
Test status
Simulation time 2024048291 ps
CPU time 6.98 seconds
Started Aug 25 06:38:48 AM UTC 24
Finished Aug 25 06:38:56 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4117966269 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.4117966269
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.97148049
Short name T652
Test name
Test status
Simulation time 3472676652 ps
CPU time 15.51 seconds
Started Aug 25 06:38:44 AM UTC 24
Finished Aug 25 06:39:00 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97148049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.97148049
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.3432692361
Short name T113
Test name
Test status
Simulation time 27136586903 ps
CPU time 32.91 seconds
Started Aug 25 06:38:45 AM UTC 24
Finished Aug 25 06:39:19 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432692361 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.3432692361
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.253032350
Short name T766
Test name
Test status
Simulation time 57974945543 ps
CPU time 263.83 seconds
Started Aug 25 06:38:46 AM UTC 24
Finished Aug 25 06:43:14 AM UTC 24
Peak memory 210244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253032350 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_with_pre_cond.253032350
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.569113366
Short name T148
Test name
Test status
Simulation time 2597657110 ps
CPU time 4.16 seconds
Started Aug 25 06:38:42 AM UTC 24
Finished Aug 25 06:38:48 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569113366 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.569113366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.2773679340
Short name T653
Test name
Test status
Simulation time 3511800302 ps
CPU time 13.14 seconds
Started Aug 25 06:38:46 AM UTC 24
Finished Aug 25 06:39:00 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773679340 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.2773679340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.4040972330
Short name T144
Test name
Test status
Simulation time 2622401839 ps
CPU time 2.56 seconds
Started Aug 25 06:38:40 AM UTC 24
Finished Aug 25 06:38:44 AM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040972330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.4040972330
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.835901604
Short name T150
Test name
Test status
Simulation time 2472455574 ps
CPU time 11.83 seconds
Started Aug 25 06:38:37 AM UTC 24
Finished Aug 25 06:38:50 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=835901604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.835901604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3672578119
Short name T648
Test name
Test status
Simulation time 2140998986 ps
CPU time 3.37 seconds
Started Aug 25 06:38:37 AM UTC 24
Finished Aug 25 06:38:41 AM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672578119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3672578119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.1956874452
Short name T145
Test name
Test status
Simulation time 2532286056 ps
CPU time 4.06 seconds
Started Aug 25 06:38:39 AM UTC 24
Finished Aug 25 06:38:44 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1956874452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.1956874452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2583063316
Short name T146
Test name
Test status
Simulation time 2107921629 ps
CPU time 10.62 seconds
Started Aug 25 06:38:35 AM UTC 24
Finished Aug 25 06:38:47 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2583063316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.2583063316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.2096385509
Short name T668
Test name
Test status
Simulation time 9046008917 ps
CPU time 40.35 seconds
Started Aug 25 06:38:48 AM UTC 24
Finished Aug 25 06:39:30 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2096385509 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.2096385509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.1926795313
Short name T329
Test name
Test status
Simulation time 3533785630 ps
CPU time 12.55 seconds
Started Aug 25 06:38:48 AM UTC 24
Finished Aug 25 06:39:02 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1926795313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.1926795313
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.3740421459
Short name T151
Test name
Test status
Simulation time 7677998918 ps
CPU time 4.22 seconds
Started Aug 25 06:38:45 AM UTC 24
Finished Aug 25 06:38:50 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740421459 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.3740421459
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.1059695026
Short name T663
Test name
Test status
Simulation time 2010481154 ps
CPU time 11.15 seconds
Started Aug 25 06:39:09 AM UTC 24
Finished Aug 25 06:39:22 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1059695026 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.1059695026
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.2355715170
Short name T657
Test name
Test status
Simulation time 3655614396 ps
CPU time 3.07 seconds
Started Aug 25 06:39:02 AM UTC 24
Finished Aug 25 06:39:06 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355715170 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.2355715170
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2421244296
Short name T289
Test name
Test status
Simulation time 102124126007 ps
CPU time 111.67 seconds
Started Aug 25 06:39:03 AM UTC 24
Finished Aug 25 06:40:57 AM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421244296 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.2421244296
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.429653372
Short name T772
Test name
Test status
Simulation time 113262749062 ps
CPU time 267.43 seconds
Started Aug 25 06:39:06 AM UTC 24
Finished Aug 25 06:43:38 AM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=429653372 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_with_pre_cond.429653372
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.1331105463
Short name T656
Test name
Test status
Simulation time 3280730685 ps
CPU time 1.92 seconds
Started Aug 25 06:39:02 AM UTC 24
Finished Aug 25 06:39:05 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1331105463 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.1331105463
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.2783634142
Short name T174
Test name
Test status
Simulation time 4312082493 ps
CPU time 9.56 seconds
Started Aug 25 06:39:03 AM UTC 24
Finished Aug 25 06:39:14 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2783634142 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.2783634142
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3034239918
Short name T655
Test name
Test status
Simulation time 2623080349 ps
CPU time 3.93 seconds
Started Aug 25 06:38:58 AM UTC 24
Finished Aug 25 06:39:03 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3034239918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.3034239918
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.3699063156
Short name T650
Test name
Test status
Simulation time 2479685004 ps
CPU time 3.6 seconds
Started Aug 25 06:38:51 AM UTC 24
Finished Aug 25 06:38:56 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3699063156 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.3699063156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2262766368
Short name T658
Test name
Test status
Simulation time 2077907374 ps
CPU time 10.92 seconds
Started Aug 25 06:38:56 AM UTC 24
Finished Aug 25 06:39:09 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2262766368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2262766368
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.1628190035
Short name T654
Test name
Test status
Simulation time 2540381317 ps
CPU time 3.65 seconds
Started Aug 25 06:38:56 AM UTC 24
Finished Aug 25 06:39:01 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1628190035 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1628190035
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.3829555244
Short name T649
Test name
Test status
Simulation time 2128093647 ps
CPU time 3.29 seconds
Started Aug 25 06:38:51 AM UTC 24
Finished Aug 25 06:38:56 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3829555244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.3829555244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.2432052844
Short name T191
Test name
Test status
Simulation time 13788050601 ps
CPU time 28.89 seconds
Started Aug 25 06:39:07 AM UTC 24
Finished Aug 25 06:39:37 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2432052844 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.2432052844
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.2125980563
Short name T238
Test name
Test status
Simulation time 7551763216 ps
CPU time 29.61 seconds
Started Aug 25 06:39:07 AM UTC 24
Finished Aug 25 06:39:38 AM UTC 24
Peak memory 220392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2125980563 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.2125980563
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.893282449
Short name T660
Test name
Test status
Simulation time 7251084267 ps
CPU time 14.51 seconds
Started Aug 25 06:39:02 AM UTC 24
Finished Aug 25 06:39:18 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=893282449 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.893282449
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.2959451543
Short name T179
Test name
Test status
Simulation time 2093588702 ps
CPU time 1.66 seconds
Started Aug 25 06:30:32 AM UTC 24
Finished Aug 25 06:30:35 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2959451543 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.2959451543
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2274557534
Short name T58
Test name
Test status
Simulation time 3241636659 ps
CPU time 4.96 seconds
Started Aug 25 06:30:28 AM UTC 24
Finished Aug 25 06:30:34 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2274557534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.2274557534
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.1039410552
Short name T57
Test name
Test status
Simulation time 2194179644 ps
CPU time 3.44 seconds
Started Aug 25 06:30:23 AM UTC 24
Finished Aug 25 06:30:27 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1039410552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.1039410552
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4195835613
Short name T82
Test name
Test status
Simulation time 2342111304 ps
CPU time 3.25 seconds
Started Aug 25 06:30:24 AM UTC 24
Finished Aug 25 06:30:28 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4195835613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4195835613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.1611794366
Short name T87
Test name
Test status
Simulation time 89709623917 ps
CPU time 244.55 seconds
Started Aug 25 06:30:29 AM UTC 24
Finished Aug 25 06:34:37 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611794366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_with_pre_cond.1611794366
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1428805804
Short name T416
Test name
Test status
Simulation time 3402891282 ps
CPU time 16.57 seconds
Started Aug 25 06:30:28 AM UTC 24
Finished Aug 25 06:30:45 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428805804 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.1428805804
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.1458192422
Short name T49
Test name
Test status
Simulation time 3245550946 ps
CPU time 3.15 seconds
Started Aug 25 06:30:29 AM UTC 24
Finished Aug 25 06:30:33 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1458192422 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.1458192422
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.1813150549
Short name T156
Test name
Test status
Simulation time 2621286274 ps
CPU time 4.12 seconds
Started Aug 25 06:30:26 AM UTC 24
Finished Aug 25 06:30:32 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813150549 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.1813150549
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.2856814124
Short name T70
Test name
Test status
Simulation time 2572006230 ps
CPU time 1.79 seconds
Started Aug 25 06:30:23 AM UTC 24
Finished Aug 25 06:30:26 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2856814124 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.2856814124
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.4069523600
Short name T294
Test name
Test status
Simulation time 2147511722 ps
CPU time 10.51 seconds
Started Aug 25 06:30:25 AM UTC 24
Finished Aug 25 06:30:37 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4069523600 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.4069523600
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.3517296066
Short name T177
Test name
Test status
Simulation time 2523482388 ps
CPU time 6.13 seconds
Started Aug 25 06:30:26 AM UTC 24
Finished Aug 25 06:30:33 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3517296066 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.3517296066
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.2591011131
Short name T321
Test name
Test status
Simulation time 42009521175 ps
CPU time 189.05 seconds
Started Aug 25 06:30:32 AM UTC 24
Finished Aug 25 06:33:45 AM UTC 24
Peak memory 240212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2591011131 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.2591011131
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.2153622043
Short name T155
Test name
Test status
Simulation time 2109384818 ps
CPU time 8.93 seconds
Started Aug 25 06:30:21 AM UTC 24
Finished Aug 25 06:30:31 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2153622043 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.2153622043
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3158298425
Short name T322
Test name
Test status
Simulation time 5906731450 ps
CPU time 24.03 seconds
Started Aug 25 06:30:29 AM UTC 24
Finished Aug 25 06:30:55 AM UTC 24
Peak memory 220804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3158298425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.3158298425
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.4183231324
Short name T36
Test name
Test status
Simulation time 9126019899 ps
CPU time 3.39 seconds
Started Aug 25 06:30:28 AM UTC 24
Finished Aug 25 06:30:32 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4183231324 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.4183231324
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.1395602689
Short name T670
Test name
Test status
Simulation time 2035482088 ps
CPU time 3.02 seconds
Started Aug 25 06:39:28 AM UTC 24
Finished Aug 25 06:39:32 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395602689 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.1395602689
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.218382438
Short name T665
Test name
Test status
Simulation time 3508955135 ps
CPU time 4.71 seconds
Started Aug 25 06:39:20 AM UTC 24
Finished Aug 25 06:39:26 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=218382438 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.218382438
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.154315850
Short name T366
Test name
Test status
Simulation time 104894901210 ps
CPU time 427.36 seconds
Started Aug 25 06:39:22 AM UTC 24
Finished Aug 25 06:46:35 AM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=154315850 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_with_pre_cond.154315850
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.4180330218
Short name T667
Test name
Test status
Simulation time 3185583766 ps
CPU time 8.43 seconds
Started Aug 25 06:39:19 AM UTC 24
Finished Aug 25 06:39:29 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4180330218 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.4180330218
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3794598813
Short name T235
Test name
Test status
Simulation time 2613761955 ps
CPU time 14.25 seconds
Started Aug 25 06:39:19 AM UTC 24
Finished Aug 25 06:39:34 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794598813 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3794598813
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.3184553923
Short name T666
Test name
Test status
Simulation time 2453407114 ps
CPU time 14.46 seconds
Started Aug 25 06:39:12 AM UTC 24
Finished Aug 25 06:39:27 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3184553923 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.3184553923
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.1217173333
Short name T662
Test name
Test status
Simulation time 2151077253 ps
CPU time 5.5 seconds
Started Aug 25 06:39:15 AM UTC 24
Finished Aug 25 06:39:21 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1217173333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.1217173333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2315341333
Short name T661
Test name
Test status
Simulation time 2538941501 ps
CPU time 3.24 seconds
Started Aug 25 06:39:15 AM UTC 24
Finished Aug 25 06:39:19 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315341333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.2315341333
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.710793480
Short name T659
Test name
Test status
Simulation time 2157897136 ps
CPU time 1.97 seconds
Started Aug 25 06:39:10 AM UTC 24
Finished Aug 25 06:39:13 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=710793480 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.710793480
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.2229323316
Short name T669
Test name
Test status
Simulation time 6333000186 ps
CPU time 3.68 seconds
Started Aug 25 06:39:27 AM UTC 24
Finished Aug 25 06:39:31 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2229323316 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.2229323316
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.911507383
Short name T239
Test name
Test status
Simulation time 10854831331 ps
CPU time 11.9 seconds
Started Aug 25 06:39:26 AM UTC 24
Finished Aug 25 06:39:39 AM UTC 24
Peak memory 226328 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=911507383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.911507383
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.1949095993
Short name T681
Test name
Test status
Simulation time 2010770829 ps
CPU time 10.3 seconds
Started Aug 25 06:39:40 AM UTC 24
Finished Aug 25 06:39:51 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1949095993 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.1949095993
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.4001352460
Short name T241
Test name
Test status
Simulation time 3226254220 ps
CPU time 4.33 seconds
Started Aug 25 06:39:35 AM UTC 24
Finished Aug 25 06:39:41 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001352460 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.4001352460
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.1971109979
Short name T391
Test name
Test status
Simulation time 56522312072 ps
CPU time 136.98 seconds
Started Aug 25 06:39:37 AM UTC 24
Finished Aug 25 06:41:56 AM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971109979 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.1971109979
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2277363664
Short name T114
Test name
Test status
Simulation time 27351897243 ps
CPU time 30.85 seconds
Started Aug 25 06:39:39 AM UTC 24
Finished Aug 25 06:40:11 AM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2277363664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_with_pre_cond.2277363664
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.4175468872
Short name T240
Test name
Test status
Simulation time 5146692618 ps
CPU time 6.1 seconds
Started Aug 25 06:39:33 AM UTC 24
Finished Aug 25 06:39:41 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4175468872 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.4175468872
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.2183351977
Short name T672
Test name
Test status
Simulation time 2652344289 ps
CPU time 3.46 seconds
Started Aug 25 06:39:38 AM UTC 24
Finished Aug 25 06:39:42 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2183351977 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.2183351977
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1386419535
Short name T671
Test name
Test status
Simulation time 2619449504 ps
CPU time 7.75 seconds
Started Aug 25 06:39:32 AM UTC 24
Finished Aug 25 06:39:41 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386419535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.1386419535
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.397156455
Short name T673
Test name
Test status
Simulation time 2462376998 ps
CPU time 11.67 seconds
Started Aug 25 06:39:30 AM UTC 24
Finished Aug 25 06:39:43 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397156455 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.397156455
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1122974121
Short name T236
Test name
Test status
Simulation time 2122792718 ps
CPU time 3.27 seconds
Started Aug 25 06:39:31 AM UTC 24
Finished Aug 25 06:39:35 AM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122974121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1122974121
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.717924663
Short name T677
Test name
Test status
Simulation time 2510903398 ps
CPU time 12.46 seconds
Started Aug 25 06:39:32 AM UTC 24
Finished Aug 25 06:39:46 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717924663 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.717924663
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.3383087389
Short name T674
Test name
Test status
Simulation time 2111542228 ps
CPU time 11.85 seconds
Started Aug 25 06:39:30 AM UTC 24
Finished Aug 25 06:39:43 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383087389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.3383087389
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.1712035465
Short name T176
Test name
Test status
Simulation time 19417216997 ps
CPU time 19.37 seconds
Started Aug 25 06:39:40 AM UTC 24
Finished Aug 25 06:40:01 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1712035465 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.1712035465
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.1907135088
Short name T693
Test name
Test status
Simulation time 5514282127 ps
CPU time 26.05 seconds
Started Aug 25 06:39:39 AM UTC 24
Finished Aug 25 06:40:06 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1907135088 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.1907135088
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.850979293
Short name T680
Test name
Test status
Simulation time 6798680528 ps
CPU time 14.48 seconds
Started Aug 25 06:39:35 AM UTC 24
Finished Aug 25 06:39:51 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850979293 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.850979293
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.2107006603
Short name T688
Test name
Test status
Simulation time 2019641997 ps
CPU time 6.77 seconds
Started Aug 25 06:39:52 AM UTC 24
Finished Aug 25 06:40:00 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2107006603 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.2107006603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.4283333446
Short name T683
Test name
Test status
Simulation time 3526115919 ps
CPU time 6.25 seconds
Started Aug 25 06:39:46 AM UTC 24
Finished Aug 25 06:39:53 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283333446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.4283333446
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.1218630445
Short name T283
Test name
Test status
Simulation time 59858940258 ps
CPU time 213.29 seconds
Started Aug 25 06:39:47 AM UTC 24
Finished Aug 25 06:43:23 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218630445 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.1218630445
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.2306355613
Short name T268
Test name
Test status
Simulation time 27862743874 ps
CPU time 29.97 seconds
Started Aug 25 06:39:51 AM UTC 24
Finished Aug 25 06:40:22 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306355613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_with_pre_cond.2306355613
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3141742175
Short name T687
Test name
Test status
Simulation time 4660631914 ps
CPU time 15.14 seconds
Started Aug 25 06:39:44 AM UTC 24
Finished Aug 25 06:40:00 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3141742175 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.3141742175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.2857389697
Short name T252
Test name
Test status
Simulation time 4354305705 ps
CPU time 8.37 seconds
Started Aug 25 06:39:48 AM UTC 24
Finished Aug 25 06:39:57 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2857389697 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.2857389697
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2964224846
Short name T682
Test name
Test status
Simulation time 2616994225 ps
CPU time 7 seconds
Started Aug 25 06:39:44 AM UTC 24
Finished Aug 25 06:39:52 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2964224846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.2964224846
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.3924392113
Short name T675
Test name
Test status
Simulation time 2494186025 ps
CPU time 1.99 seconds
Started Aug 25 06:39:42 AM UTC 24
Finished Aug 25 06:39:45 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3924392113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.3924392113
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.2374270129
Short name T678
Test name
Test status
Simulation time 2138481352 ps
CPU time 3.31 seconds
Started Aug 25 06:39:42 AM UTC 24
Finished Aug 25 06:39:47 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374270129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.2374270129
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.2574400304
Short name T684
Test name
Test status
Simulation time 2512398901 ps
CPU time 10.21 seconds
Started Aug 25 06:39:43 AM UTC 24
Finished Aug 25 06:39:55 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2574400304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.2574400304
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.2840455551
Short name T676
Test name
Test status
Simulation time 2124061813 ps
CPU time 3.16 seconds
Started Aug 25 06:39:41 AM UTC 24
Finished Aug 25 06:39:45 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840455551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2840455551
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.2527968531
Short name T410
Test name
Test status
Simulation time 11955791759 ps
CPU time 27.69 seconds
Started Aug 25 06:39:52 AM UTC 24
Finished Aug 25 06:40:21 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2527968531 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.2527968531
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.1323946505
Short name T679
Test name
Test status
Simulation time 7298682403 ps
CPU time 2.48 seconds
Started Aug 25 06:39:47 AM UTC 24
Finished Aug 25 06:39:50 AM UTC 24
Peak memory 209744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323946505 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.1323946505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.1932581373
Short name T149
Test name
Test status
Simulation time 2014682926 ps
CPU time 8.31 seconds
Started Aug 25 06:40:07 AM UTC 24
Finished Aug 25 06:40:16 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1932581373 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.1932581373
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2278559244
Short name T256
Test name
Test status
Simulation time 3450675370 ps
CPU time 10.4 seconds
Started Aug 25 06:40:00 AM UTC 24
Finished Aug 25 06:40:12 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278559244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.2278559244
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.181429567
Short name T359
Test name
Test status
Simulation time 115178398144 ps
CPU time 250.82 seconds
Started Aug 25 06:40:01 AM UTC 24
Finished Aug 25 06:44:16 AM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=181429567 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.181429567
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.2673511708
Short name T765
Test name
Test status
Simulation time 43584789725 ps
CPU time 186.99 seconds
Started Aug 25 06:40:02 AM UTC 24
Finished Aug 25 06:43:13 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2673511708 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_with_pre_cond.2673511708
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.3298389342
Short name T701
Test name
Test status
Simulation time 4228998885 ps
CPU time 22.92 seconds
Started Aug 25 06:39:58 AM UTC 24
Finished Aug 25 06:40:22 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3298389342 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.3298389342
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.2804844031
Short name T690
Test name
Test status
Simulation time 2616690974 ps
CPU time 7.06 seconds
Started Aug 25 06:39:57 AM UTC 24
Finished Aug 25 06:40:05 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2804844031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.2804844031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.1739677911
Short name T692
Test name
Test status
Simulation time 2454221650 ps
CPU time 10.98 seconds
Started Aug 25 06:39:54 AM UTC 24
Finished Aug 25 06:40:06 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1739677911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.1739677911
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.225653068
Short name T691
Test name
Test status
Simulation time 2027809800 ps
CPU time 10.54 seconds
Started Aug 25 06:39:54 AM UTC 24
Finished Aug 25 06:40:05 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225653068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.225653068
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.3880087723
Short name T686
Test name
Test status
Simulation time 2601063092 ps
CPU time 2.01 seconds
Started Aug 25 06:39:56 AM UTC 24
Finished Aug 25 06:39:59 AM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3880087723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.3880087723
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2006827901
Short name T685
Test name
Test status
Simulation time 2132008525 ps
CPU time 2.9 seconds
Started Aug 25 06:39:52 AM UTC 24
Finished Aug 25 06:39:56 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2006827901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2006827901
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.3220774299
Short name T255
Test name
Test status
Simulation time 7437765671 ps
CPU time 3.54 seconds
Started Aug 25 06:40:07 AM UTC 24
Finished Aug 25 06:40:11 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220774299 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.3220774299
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2342081190
Short name T330
Test name
Test status
Simulation time 6541700639 ps
CPU time 22.94 seconds
Started Aug 25 06:40:06 AM UTC 24
Finished Aug 25 06:40:30 AM UTC 24
Peak memory 220416 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2342081190 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.2342081190
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2815978604
Short name T96
Test name
Test status
Simulation time 140729847960 ps
CPU time 63.25 seconds
Started Aug 25 06:40:01 AM UTC 24
Finished Aug 25 06:41:06 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815978604 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.2815978604
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.3649899789
Short name T699
Test name
Test status
Simulation time 2039422695 ps
CPU time 2.44 seconds
Started Aug 25 06:40:17 AM UTC 24
Finished Aug 25 06:40:21 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649899789 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.3649899789
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.97427568
Short name T702
Test name
Test status
Simulation time 3782480304 ps
CPU time 9.46 seconds
Started Aug 25 06:40:12 AM UTC 24
Finished Aug 25 06:40:23 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=97427568 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0
8_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.97427568
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.2602131156
Short name T784
Test name
Test status
Simulation time 116794317439 ps
CPU time 367.02 seconds
Started Aug 25 06:40:13 AM UTC 24
Finished Aug 25 06:46:25 AM UTC 24
Peak memory 210484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2602131156 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.2602131156
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.1102939718
Short name T262
Test name
Test status
Simulation time 49445999532 ps
CPU time 221.3 seconds
Started Aug 25 06:40:15 AM UTC 24
Finished Aug 25 06:44:00 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1102939718 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_with_pre_cond.1102939718
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1771265548
Short name T698
Test name
Test status
Simulation time 3481006888 ps
CPU time 5.18 seconds
Started Aug 25 06:40:12 AM UTC 24
Finished Aug 25 06:40:19 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1771265548 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.1771265548
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.217318577
Short name T695
Test name
Test status
Simulation time 2625494303 ps
CPU time 3.83 seconds
Started Aug 25 06:40:12 AM UTC 24
Finished Aug 25 06:40:18 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217318577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.217318577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.3895262054
Short name T237
Test name
Test status
Simulation time 2491669498 ps
CPU time 3.65 seconds
Started Aug 25 06:40:09 AM UTC 24
Finished Aug 25 06:40:14 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3895262054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.3895262054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.3289732319
Short name T258
Test name
Test status
Simulation time 2168022029 ps
CPU time 3.06 seconds
Started Aug 25 06:40:10 AM UTC 24
Finished Aug 25 06:40:14 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3289732319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.3289732319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.1061139182
Short name T694
Test name
Test status
Simulation time 2535720419 ps
CPU time 4.51 seconds
Started Aug 25 06:40:11 AM UTC 24
Finished Aug 25 06:40:17 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1061139182 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.1061139182
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.569581326
Short name T697
Test name
Test status
Simulation time 2111750446 ps
CPU time 11.06 seconds
Started Aug 25 06:40:07 AM UTC 24
Finished Aug 25 06:40:19 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=569581326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.569581326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.1292362933
Short name T791
Test name
Test status
Simulation time 307075318648 ps
CPU time 537.69 seconds
Started Aug 25 06:40:17 AM UTC 24
Finished Aug 25 06:49:22 AM UTC 24
Peak memory 210296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1292362933 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.1292362933
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.55123632
Short name T707
Test name
Test status
Simulation time 3288837283 ps
CPU time 10.25 seconds
Started Aug 25 06:40:15 AM UTC 24
Finished Aug 25 06:40:26 AM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=55123632 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.55123632
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4239239778
Short name T259
Test name
Test status
Simulation time 7266677694 ps
CPU time 2.23 seconds
Started Aug 25 06:40:13 AM UTC 24
Finished Aug 25 06:40:16 AM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4239239778 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.4239239778
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.93174648
Short name T708
Test name
Test status
Simulation time 2031391774 ps
CPU time 3.42 seconds
Started Aug 25 06:40:25 AM UTC 24
Finished Aug 25 06:40:30 AM UTC 24
Peak memory 209552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=93174648 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.93174648
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3974312853
Short name T717
Test name
Test status
Simulation time 3524452712 ps
CPU time 15.1 seconds
Started Aug 25 06:40:22 AM UTC 24
Finished Aug 25 06:40:38 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3974312853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.3974312853
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.15507924
Short name T759
Test name
Test status
Simulation time 119479265450 ps
CPU time 124.11 seconds
Started Aug 25 06:40:23 AM UTC 24
Finished Aug 25 06:42:30 AM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=15507924 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.15507924
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.885654991
Short name T269
Test name
Test status
Simulation time 73721766527 ps
CPU time 59.54 seconds
Started Aug 25 06:40:23 AM UTC 24
Finished Aug 25 06:41:25 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885654991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_with_pre_cond.885654991
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3923901825
Short name T704
Test name
Test status
Simulation time 2610813934 ps
CPU time 3.45 seconds
Started Aug 25 06:40:20 AM UTC 24
Finished Aug 25 06:40:25 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3923901825 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.3923901825
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.885079980
Short name T709
Test name
Test status
Simulation time 4106149607 ps
CPU time 7.31 seconds
Started Aug 25 06:40:23 AM UTC 24
Finished Aug 25 06:40:32 AM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=885079980 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.885079980
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.4000474103
Short name T703
Test name
Test status
Simulation time 2637359789 ps
CPU time 3.23 seconds
Started Aug 25 06:40:20 AM UTC 24
Finished Aug 25 06:40:25 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4000474103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.4000474103
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.3255424505
Short name T711
Test name
Test status
Simulation time 2476117131 ps
CPU time 12.59 seconds
Started Aug 25 06:40:18 AM UTC 24
Finished Aug 25 06:40:33 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3255424505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3255424505
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.2902137407
Short name T706
Test name
Test status
Simulation time 2036362339 ps
CPU time 5.48 seconds
Started Aug 25 06:40:19 AM UTC 24
Finished Aug 25 06:40:26 AM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2902137407 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2902137407
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.1194599211
Short name T713
Test name
Test status
Simulation time 2510851281 ps
CPU time 12.73 seconds
Started Aug 25 06:40:20 AM UTC 24
Finished Aug 25 06:40:35 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1194599211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.1194599211
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.348959944
Short name T700
Test name
Test status
Simulation time 2208697073 ps
CPU time 1.47 seconds
Started Aug 25 06:40:18 AM UTC 24
Finished Aug 25 06:40:21 AM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=348959944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.348959944
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.586434185
Short name T773
Test name
Test status
Simulation time 209932986850 ps
CPU time 197.91 seconds
Started Aug 25 06:40:24 AM UTC 24
Finished Aug 25 06:43:45 AM UTC 24
Peak memory 210504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=586434185 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.586434185
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3777401287
Short name T721
Test name
Test status
Simulation time 10844251153 ps
CPU time 15.35 seconds
Started Aug 25 06:40:23 AM UTC 24
Finished Aug 25 06:40:40 AM UTC 24
Peak memory 220776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3777401287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.3777401287
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.2390700470
Short name T705
Test name
Test status
Simulation time 6822154716 ps
CPU time 1.89 seconds
Started Aug 25 06:40:23 AM UTC 24
Finished Aug 25 06:40:26 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2390700470 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.2390700470
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.4120356147
Short name T723
Test name
Test status
Simulation time 2020951226 ps
CPU time 5.61 seconds
Started Aug 25 06:40:34 AM UTC 24
Finished Aug 25 06:40:41 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4120356147 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.4120356147
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.3025260059
Short name T734
Test name
Test status
Simulation time 3934982214 ps
CPU time 20.93 seconds
Started Aug 25 06:40:31 AM UTC 24
Finished Aug 25 06:40:54 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3025260059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.3025260059
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.2766148948
Short name T116
Test name
Test status
Simulation time 92747925338 ps
CPU time 105.19 seconds
Started Aug 25 06:40:31 AM UTC 24
Finished Aug 25 06:42:19 AM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2766148948 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.2766148948
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2159624059
Short name T714
Test name
Test status
Simulation time 3201998557 ps
CPU time 3.79 seconds
Started Aug 25 06:40:31 AM UTC 24
Finished Aug 25 06:40:36 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2159624059 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.2159624059
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.3441234970
Short name T716
Test name
Test status
Simulation time 2935487890 ps
CPU time 3.56 seconds
Started Aug 25 06:40:32 AM UTC 24
Finished Aug 25 06:40:37 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3441234970 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.3441234970
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1254961428
Short name T718
Test name
Test status
Simulation time 2610776810 ps
CPU time 9.48 seconds
Started Aug 25 06:40:28 AM UTC 24
Finished Aug 25 06:40:39 AM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1254961428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.1254961428
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1740552623
Short name T710
Test name
Test status
Simulation time 2469310322 ps
CPU time 3.68 seconds
Started Aug 25 06:40:27 AM UTC 24
Finished Aug 25 06:40:32 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1740552623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.1740552623
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3690297353
Short name T719
Test name
Test status
Simulation time 2055783734 ps
CPU time 10.73 seconds
Started Aug 25 06:40:27 AM UTC 24
Finished Aug 25 06:40:39 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690297353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.3690297353
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.1122888486
Short name T712
Test name
Test status
Simulation time 2531989795 ps
CPU time 4.19 seconds
Started Aug 25 06:40:28 AM UTC 24
Finished Aug 25 06:40:33 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1122888486 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.1122888486
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.4041359725
Short name T715
Test name
Test status
Simulation time 2110896684 ps
CPU time 10.24 seconds
Started Aug 25 06:40:25 AM UTC 24
Finished Aug 25 06:40:37 AM UTC 24
Peak memory 209588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4041359725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.4041359725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.920012478
Short name T193
Test name
Test status
Simulation time 9290610749 ps
CPU time 10.76 seconds
Started Aug 25 06:40:34 AM UTC 24
Finished Aug 25 06:40:46 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=920012478 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.920012478
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2672819326
Short name T726
Test name
Test status
Simulation time 6128589809 ps
CPU time 10.23 seconds
Started Aug 25 06:40:34 AM UTC 24
Finished Aug 25 06:40:46 AM UTC 24
Peak memory 209980 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2672819326 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.2672819326
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.577467479
Short name T720
Test name
Test status
Simulation time 4349290050 ps
CPU time 6.26 seconds
Started Aug 25 06:40:31 AM UTC 24
Finished Aug 25 06:40:39 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=577467479 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.577467479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.1269093030
Short name T731
Test name
Test status
Simulation time 2037743803 ps
CPU time 4 seconds
Started Aug 25 06:40:46 AM UTC 24
Finished Aug 25 06:40:51 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1269093030 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.1269093030
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.3467886515
Short name T779
Test name
Test status
Simulation time 58926414457 ps
CPU time 270.27 seconds
Started Aug 25 06:40:40 AM UTC 24
Finished Aug 25 06:45:14 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3467886515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.3467886515
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.4213193521
Short name T115
Test name
Test status
Simulation time 60544388398 ps
CPU time 85.64 seconds
Started Aug 25 06:40:40 AM UTC 24
Finished Aug 25 06:42:07 AM UTC 24
Peak memory 210236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213193521 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.4213193521
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.3033646924
Short name T400
Test name
Test status
Simulation time 46488101921 ps
CPU time 16.98 seconds
Started Aug 25 06:40:42 AM UTC 24
Finished Aug 25 06:41:00 AM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033646924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_with_pre_cond.3033646924
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2021990162
Short name T730
Test name
Test status
Simulation time 3798928715 ps
CPU time 9.02 seconds
Started Aug 25 06:40:39 AM UTC 24
Finished Aug 25 06:40:50 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2021990162 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.2021990162
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.138190054
Short name T725
Test name
Test status
Simulation time 3123232157 ps
CPU time 3.56 seconds
Started Aug 25 06:40:41 AM UTC 24
Finished Aug 25 06:40:46 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=138190054 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.138190054
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.1833358589
Short name T724
Test name
Test status
Simulation time 2639667201 ps
CPU time 2.59 seconds
Started Aug 25 06:40:38 AM UTC 24
Finished Aug 25 06:40:42 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833358589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.1833358589
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.4194498736
Short name T722
Test name
Test status
Simulation time 2470469622 ps
CPU time 3.97 seconds
Started Aug 25 06:40:35 AM UTC 24
Finished Aug 25 06:40:41 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4194498736 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.4194498736
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.3237703003
Short name T729
Test name
Test status
Simulation time 2046168809 ps
CPU time 9.92 seconds
Started Aug 25 06:40:37 AM UTC 24
Finished Aug 25 06:40:49 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3237703003 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.3237703003
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.1717332340
Short name T728
Test name
Test status
Simulation time 2523725584 ps
CPU time 6.85 seconds
Started Aug 25 06:40:38 AM UTC 24
Finished Aug 25 06:40:47 AM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1717332340 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.1717332340
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.2548962036
Short name T727
Test name
Test status
Simulation time 2112527211 ps
CPU time 9.63 seconds
Started Aug 25 06:40:35 AM UTC 24
Finished Aug 25 06:40:46 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548962036 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.2548962036
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.3387834087
Short name T794
Test name
Test status
Simulation time 203505772233 ps
CPU time 613.37 seconds
Started Aug 25 06:40:43 AM UTC 24
Finished Aug 25 06:51:03 AM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387834087 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.3387834087
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.17062706
Short name T736
Test name
Test status
Simulation time 7411273679 ps
CPU time 11.46 seconds
Started Aug 25 06:40:42 AM UTC 24
Finished Aug 25 06:40:54 AM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=17062706 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev
/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.17062706
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.3897308920
Short name T407
Test name
Test status
Simulation time 1891266561695 ps
CPU time 268.33 seconds
Started Aug 25 06:40:40 AM UTC 24
Finished Aug 25 06:45:12 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3897308920 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.3897308920
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.1248298216
Short name T740
Test name
Test status
Simulation time 2035132109 ps
CPU time 3.51 seconds
Started Aug 25 06:40:57 AM UTC 24
Finished Aug 25 06:41:02 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248298216 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.1248298216
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.168145836
Short name T743
Test name
Test status
Simulation time 3431350031 ps
CPU time 15.43 seconds
Started Aug 25 06:40:51 AM UTC 24
Finished Aug 25 06:41:07 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=168145836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.168145836
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.3991450069
Short name T361
Test name
Test status
Simulation time 86797306343 ps
CPU time 197.98 seconds
Started Aug 25 06:40:53 AM UTC 24
Finished Aug 25 06:44:14 AM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3991450069 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.3991450069
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.4159384335
Short name T747
Test name
Test status
Simulation time 2973858440 ps
CPU time 17.1 seconds
Started Aug 25 06:40:50 AM UTC 24
Finished Aug 25 06:41:08 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4159384335 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.4159384335
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.2817803657
Short name T745
Test name
Test status
Simulation time 2696735885 ps
CPU time 13.6 seconds
Started Aug 25 06:40:53 AM UTC 24
Finished Aug 25 06:41:08 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817803657 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.2817803657
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.3529612667
Short name T738
Test name
Test status
Simulation time 2621964638 ps
CPU time 7.97 seconds
Started Aug 25 06:40:48 AM UTC 24
Finished Aug 25 06:40:57 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3529612667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.3529612667
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.1607494621
Short name T735
Test name
Test status
Simulation time 2475216825 ps
CPU time 6.26 seconds
Started Aug 25 06:40:46 AM UTC 24
Finished Aug 25 06:40:54 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1607494621 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.1607494621
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.3531192184
Short name T732
Test name
Test status
Simulation time 2109935075 ps
CPU time 3.22 seconds
Started Aug 25 06:40:48 AM UTC 24
Finished Aug 25 06:40:52 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3531192184 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.3531192184
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3067212097
Short name T733
Test name
Test status
Simulation time 2536328431 ps
CPU time 3.78 seconds
Started Aug 25 06:40:48 AM UTC 24
Finished Aug 25 06:40:52 AM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3067212097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.3067212097
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.662905095
Short name T737
Test name
Test status
Simulation time 2113434199 ps
CPU time 8.67 seconds
Started Aug 25 06:40:46 AM UTC 24
Finished Aug 25 06:40:56 AM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=662905095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.662905095
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.973898858
Short name T233
Test name
Test status
Simulation time 11760875448 ps
CPU time 57.18 seconds
Started Aug 25 06:40:55 AM UTC 24
Finished Aug 25 06:41:54 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=973898858 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.973898858
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.1797219772
Short name T750
Test name
Test status
Simulation time 5013286929 ps
CPU time 26.12 seconds
Started Aug 25 06:40:54 AM UTC 24
Finished Aug 25 06:41:22 AM UTC 24
Peak memory 220736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1797219772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.1797219772
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3077094082
Short name T154
Test name
Test status
Simulation time 5122679144 ps
CPU time 11.18 seconds
Started Aug 25 06:40:52 AM UTC 24
Finished Aug 25 06:41:04 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3077094082 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.3077094082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.1425790782
Short name T749
Test name
Test status
Simulation time 2014405641 ps
CPU time 4.96 seconds
Started Aug 25 06:41:10 AM UTC 24
Finished Aug 25 06:41:16 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1425790782 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.1425790782
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.472410532
Short name T739
Test name
Test status
Simulation time 3581301231 ps
CPU time 18.13 seconds
Started Aug 25 06:41:05 AM UTC 24
Finished Aug 25 06:41:24 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=472410532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.472410532
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.1940055464
Short name T763
Test name
Test status
Simulation time 89194954545 ps
CPU time 108.46 seconds
Started Aug 25 06:41:08 AM UTC 24
Finished Aug 25 06:42:59 AM UTC 24
Peak memory 210108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1940055464 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.1940055464
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.698312424
Short name T696
Test name
Test status
Simulation time 4676814226 ps
CPU time 12.74 seconds
Started Aug 25 06:41:04 AM UTC 24
Finished Aug 25 06:41:18 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=698312424 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.698312424
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.3275390384
Short name T752
Test name
Test status
Simulation time 3109113585 ps
CPU time 18.33 seconds
Started Aug 25 06:41:08 AM UTC 24
Finished Aug 25 06:41:28 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3275390384 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.3275390384
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.1433820935
Short name T744
Test name
Test status
Simulation time 2640262770 ps
CPU time 3.59 seconds
Started Aug 25 06:41:03 AM UTC 24
Finished Aug 25 06:41:08 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1433820935 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.1433820935
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.2508076686
Short name T741
Test name
Test status
Simulation time 2461162100 ps
CPU time 3.5 seconds
Started Aug 25 06:40:59 AM UTC 24
Finished Aug 25 06:41:03 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508076686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.2508076686
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.989226194
Short name T742
Test name
Test status
Simulation time 2119517205 ps
CPU time 5.25 seconds
Started Aug 25 06:41:01 AM UTC 24
Finished Aug 25 06:41:07 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=989226194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.989226194
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.4204502213
Short name T748
Test name
Test status
Simulation time 2508347229 ps
CPU time 13.28 seconds
Started Aug 25 06:41:01 AM UTC 24
Finished Aug 25 06:41:15 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4204502213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.4204502213
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.1437499967
Short name T746
Test name
Test status
Simulation time 2112649846 ps
CPU time 9.35 seconds
Started Aug 25 06:40:57 AM UTC 24
Finished Aug 25 06:41:08 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1437499967 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.1437499967
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.764687243
Short name T261
Test name
Test status
Simulation time 956642069994 ps
CPU time 415.69 seconds
Started Aug 25 06:41:08 AM UTC 24
Finished Aug 25 06:48:10 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=764687243 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.764687243
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2494233127
Short name T751
Test name
Test status
Simulation time 3326708509 ps
CPU time 15.02 seconds
Started Aug 25 06:41:08 AM UTC 24
Finished Aug 25 06:41:25 AM UTC 24
Peak memory 210284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2494233127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.2494233127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.2028941224
Short name T196
Test name
Test status
Simulation time 2012393099 ps
CPU time 12.74 seconds
Started Aug 25 06:30:43 AM UTC 24
Finished Aug 25 06:30:57 AM UTC 24
Peak memory 210068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2028941224 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.2028941224
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1006037952
Short name T59
Test name
Test status
Simulation time 3654608514 ps
CPU time 15.16 seconds
Started Aug 25 06:30:37 AM UTC 24
Finished Aug 25 06:30:53 AM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1006037952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.1006037952
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2640632111
Short name T298
Test name
Test status
Simulation time 2604079244 ps
CPU time 8.44 seconds
Started Aug 25 06:30:36 AM UTC 24
Finished Aug 25 06:30:45 AM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2640632111 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.2640632111
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3888738760
Short name T6
Test name
Test status
Simulation time 4246685153 ps
CPU time 3.33 seconds
Started Aug 25 06:30:37 AM UTC 24
Finished Aug 25 06:30:42 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3888738760 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.3888738760
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.3555663217
Short name T296
Test name
Test status
Simulation time 2632217981 ps
CPU time 4.91 seconds
Started Aug 25 06:30:36 AM UTC 24
Finished Aug 25 06:30:42 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555663217 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.3555663217
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3432855060
Short name T73
Test name
Test status
Simulation time 2464351900 ps
CPU time 8.08 seconds
Started Aug 25 06:30:35 AM UTC 24
Finished Aug 25 06:30:44 AM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3432855060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.3432855060
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.1933612168
Short name T297
Test name
Test status
Simulation time 2122935790 ps
CPU time 9.18 seconds
Started Aug 25 06:30:35 AM UTC 24
Finished Aug 25 06:30:45 AM UTC 24
Peak memory 209788 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1933612168 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.1933612168
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.1180498797
Short name T295
Test name
Test status
Simulation time 2526429622 ps
CPU time 3.2 seconds
Started Aug 25 06:30:35 AM UTC 24
Finished Aug 25 06:30:39 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1180498797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.1180498797
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.1053086031
Short name T293
Test name
Test status
Simulation time 2181719189 ps
CPU time 1.7 seconds
Started Aug 25 06:30:33 AM UTC 24
Finished Aug 25 06:30:36 AM UTC 24
Peak memory 208248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1053086031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1053086031
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.562387937
Short name T68
Test name
Test status
Simulation time 2979621181 ps
CPU time 3.11 seconds
Started Aug 25 06:30:37 AM UTC 24
Finished Aug 25 06:30:41 AM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=562387937 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.562387937
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.682545119
Short name T755
Test name
Test status
Simulation time 22834324423 ps
CPU time 52.16 seconds
Started Aug 25 06:41:10 AM UTC 24
Finished Aug 25 06:42:03 AM UTC 24
Peak memory 210188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=682545119 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_with_pre_cond.682545119
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3547588076
Short name T385
Test name
Test status
Simulation time 67572282654 ps
CPU time 278.6 seconds
Started Aug 25 06:41:16 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3547588076 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_with_pre_cond.3547588076
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.1855047577
Short name T770
Test name
Test status
Simulation time 25830633127 ps
CPU time 130.72 seconds
Started Aug 25 06:41:19 AM UTC 24
Finished Aug 25 06:43:32 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1855047577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_with_pre_cond.1855047577
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2387803670
Short name T761
Test name
Test status
Simulation time 66674389353 ps
CPU time 83.9 seconds
Started Aug 25 06:41:22 AM UTC 24
Finished Aug 25 06:42:48 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387803670 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_with_pre_cond.2387803670
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2563135990
Short name T753
Test name
Test status
Simulation time 24416409135 ps
CPU time 8.89 seconds
Started Aug 25 06:41:22 AM UTC 24
Finished Aug 25 06:41:33 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2563135990 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_with_pre_cond.2563135990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.230943592
Short name T771
Test name
Test status
Simulation time 27083317646 ps
CPU time 124.47 seconds
Started Aug 25 06:41:26 AM UTC 24
Finished Aug 25 06:43:33 AM UTC 24
Peak memory 210588 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230943592 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_with_pre_cond.230943592
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.3733138289
Short name T251
Test name
Test status
Simulation time 2015265200 ps
CPU time 11.75 seconds
Started Aug 25 06:30:59 AM UTC 24
Finished Aug 25 06:31:12 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3733138289 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.3733138289
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.1502263196
Short name T60
Test name
Test status
Simulation time 3453013757 ps
CPU time 2.8 seconds
Started Aug 25 06:30:55 AM UTC 24
Finished Aug 25 06:30:59 AM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1502263196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.1502263196
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4176724816
Short name T40
Test name
Test status
Simulation time 144179016221 ps
CPU time 69.23 seconds
Started Aug 25 06:30:57 AM UTC 24
Finished Aug 25 06:32:08 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4176724816 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.4176724816
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.897770402
Short name T199
Test name
Test status
Simulation time 3771500829 ps
CPU time 5.27 seconds
Started Aug 25 06:30:55 AM UTC 24
Finished Aug 25 06:31:01 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=897770402 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.897770402
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.1474531127
Short name T194
Test name
Test status
Simulation time 3529058773 ps
CPU time 6.95 seconds
Started Aug 25 06:30:57 AM UTC 24
Finished Aug 25 06:31:05 AM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1474531127 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.1474531127
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.4147419687
Short name T198
Test name
Test status
Simulation time 2616313202 ps
CPU time 5.63 seconds
Started Aug 25 06:30:53 AM UTC 24
Finished Aug 25 06:31:00 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147419687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.4147419687
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.4156579121
Short name T74
Test name
Test status
Simulation time 2456031717 ps
CPU time 11.04 seconds
Started Aug 25 06:30:46 AM UTC 24
Finished Aug 25 06:30:58 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4156579121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.4156579121
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.4246594125
Short name T415
Test name
Test status
Simulation time 2132464123 ps
CPU time 5 seconds
Started Aug 25 06:30:46 AM UTC 24
Finished Aug 25 06:30:52 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4246594125 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.4246594125
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.3821076320
Short name T412
Test name
Test status
Simulation time 2523016131 ps
CPU time 6.23 seconds
Started Aug 25 06:30:46 AM UTC 24
Finished Aug 25 06:30:54 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821076320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.3821076320
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.3594548518
Short name T195
Test name
Test status
Simulation time 2109015191 ps
CPU time 10.31 seconds
Started Aug 25 06:30:45 AM UTC 24
Finished Aug 25 06:30:57 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594548518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3594548518
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.3318522175
Short name T248
Test name
Test status
Simulation time 6705020966 ps
CPU time 10.33 seconds
Started Aug 25 06:30:59 AM UTC 24
Finished Aug 25 06:31:11 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3318522175 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.3318522175
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.2813736082
Short name T250
Test name
Test status
Simulation time 3759264259 ps
CPU time 12.33 seconds
Started Aug 25 06:30:58 AM UTC 24
Finished Aug 25 06:31:12 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2813736082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.2813736082
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.2009233501
Short name T153
Test name
Test status
Simulation time 1225271527592 ps
CPU time 570.84 seconds
Started Aug 25 06:30:56 AM UTC 24
Finished Aug 25 06:40:34 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009233501 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.2009233501
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3291095403
Short name T757
Test name
Test status
Simulation time 25348019127 ps
CPU time 40.74 seconds
Started Aug 25 06:41:28 AM UTC 24
Finished Aug 25 06:42:10 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291095403 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_with_pre_cond.3291095403
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2192844526
Short name T379
Test name
Test status
Simulation time 106015377491 ps
CPU time 236.99 seconds
Started Aug 25 06:41:33 AM UTC 24
Finished Aug 25 06:45:34 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2192844526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_with_pre_cond.2192844526
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.3778408221
Short name T362
Test name
Test status
Simulation time 49729824735 ps
CPU time 58.46 seconds
Started Aug 25 06:41:44 AM UTC 24
Finished Aug 25 06:42:44 AM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3778408221 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_with_pre_cond.3778408221
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.736278382
Short name T758
Test name
Test status
Simulation time 53445227580 ps
CPU time 27.37 seconds
Started Aug 25 06:41:55 AM UTC 24
Finished Aug 25 06:42:24 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736278382 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_with_pre_cond.736278382
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.874609207
Short name T290
Test name
Test status
Simulation time 40252058484 ps
CPU time 9.89 seconds
Started Aug 25 06:41:58 AM UTC 24
Finished Aug 25 06:42:09 AM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=874609207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_with_pre_cond.874609207
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.241423248
Short name T401
Test name
Test status
Simulation time 123599026883 ps
CPU time 131.27 seconds
Started Aug 25 06:41:59 AM UTC 24
Finished Aug 25 06:44:13 AM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241423248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_with_pre_cond.241423248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.3544859430
Short name T419
Test name
Test status
Simulation time 2034156075 ps
CPU time 3.91 seconds
Started Aug 25 06:31:13 AM UTC 24
Finished Aug 25 06:31:18 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3544859430 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.3544859430
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.3383812027
Short name T61
Test name
Test status
Simulation time 3339485896 ps
CPU time 14.93 seconds
Started Aug 25 06:31:07 AM UTC 24
Finished Aug 25 06:31:24 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3383812027 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.3383812027
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.2998073474
Short name T349
Test name
Test status
Simulation time 73950284489 ps
CPU time 278.33 seconds
Started Aug 25 06:31:10 AM UTC 24
Finished Aug 25 06:35:52 AM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2998073474 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.2998073474
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.1697309617
Short name T263
Test name
Test status
Simulation time 46701800763 ps
CPU time 220.81 seconds
Started Aug 25 06:31:11 AM UTC 24
Finished Aug 25 06:34:55 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697309617 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_with_pre_cond.1697309617
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.704802261
Short name T247
Test name
Test status
Simulation time 2832628190 ps
CPU time 2.74 seconds
Started Aug 25 06:31:06 AM UTC 24
Finished Aug 25 06:31:10 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=704802261 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.704802261
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.142656576
Short name T47
Test name
Test status
Simulation time 3565819238 ps
CPU time 15.02 seconds
Started Aug 25 06:31:10 AM UTC 24
Finished Aug 25 06:31:26 AM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=142656576 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.142656576
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.274194527
Short name T244
Test name
Test status
Simulation time 2743794050 ps
CPU time 1.76 seconds
Started Aug 25 06:31:04 AM UTC 24
Finished Aug 25 06:31:07 AM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=274194527 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.274194527
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.3014521061
Short name T249
Test name
Test status
Simulation time 2457684238 ps
CPU time 7.22 seconds
Started Aug 25 06:31:03 AM UTC 24
Finished Aug 25 06:31:11 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3014521061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.3014521061
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.1662782153
Short name T417
Test name
Test status
Simulation time 2080322160 ps
CPU time 9.41 seconds
Started Aug 25 06:31:03 AM UTC 24
Finished Aug 25 06:31:13 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1662782153 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.1662782153
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.3044492747
Short name T245
Test name
Test status
Simulation time 2535320531 ps
CPU time 3.75 seconds
Started Aug 25 06:31:04 AM UTC 24
Finished Aug 25 06:31:09 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044492747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.3044492747
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.2705070401
Short name T246
Test name
Test status
Simulation time 2120063673 ps
CPU time 6.17 seconds
Started Aug 25 06:31:01 AM UTC 24
Finished Aug 25 06:31:09 AM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2705070401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.2705070401
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.3335367498
Short name T219
Test name
Test status
Simulation time 4584448028 ps
CPU time 22.44 seconds
Started Aug 25 06:31:12 AM UTC 24
Finished Aug 25 06:31:36 AM UTC 24
Peak memory 226728 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3335367498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.3335367498
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3665456699
Short name T69
Test name
Test status
Simulation time 2962800752 ps
CPU time 6.09 seconds
Started Aug 25 06:31:07 AM UTC 24
Finished Aug 25 06:31:15 AM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3665456699 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.3665456699
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.3814678248
Short name T390
Test name
Test status
Simulation time 147111979930 ps
CPU time 174.35 seconds
Started Aug 25 06:42:02 AM UTC 24
Finished Aug 25 06:44:59 AM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814678248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_with_pre_cond.3814678248
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2169314589
Short name T781
Test name
Test status
Simulation time 49446223632 ps
CPU time 220.5 seconds
Started Aug 25 06:42:08 AM UTC 24
Finished Aug 25 06:45:52 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2169314589 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_with_pre_cond.2169314589
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2690576228
Short name T792
Test name
Test status
Simulation time 139928559861 ps
CPU time 435.62 seconds
Started Aug 25 06:42:09 AM UTC 24
Finished Aug 25 06:49:30 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690576228 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_with_pre_cond.2690576228
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2242495767
Short name T760
Test name
Test status
Simulation time 23365995735 ps
CPU time 24.07 seconds
Started Aug 25 06:42:11 AM UTC 24
Finished Aug 25 06:42:36 AM UTC 24
Peak memory 210512 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242495767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_with_pre_cond.2242495767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.4036491122
Short name T762
Test name
Test status
Simulation time 25358421103 ps
CPU time 32.33 seconds
Started Aug 25 06:42:20 AM UTC 24
Finished Aug 25 06:42:54 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4036491122 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_with_pre_cond.4036491122
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.404335603
Short name T218
Test name
Test status
Simulation time 2027811080 ps
CPU time 3.87 seconds
Started Aug 25 06:31:30 AM UTC 24
Finished Aug 25 06:31:35 AM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=404335603 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.404335603
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1274928889
Short name T135
Test name
Test status
Simulation time 3588805919 ps
CPU time 1.47 seconds
Started Aug 25 06:31:24 AM UTC 24
Finished Aug 25 06:31:26 AM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1274928889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.1274928889
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.4028053704
Short name T44
Test name
Test status
Simulation time 52753005651 ps
CPU time 122.27 seconds
Started Aug 25 06:31:25 AM UTC 24
Finished Aug 25 06:33:30 AM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4028053704 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.4028053704
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.362932102
Short name T253
Test name
Test status
Simulation time 119338441273 ps
CPU time 515.96 seconds
Started Aug 25 06:31:27 AM UTC 24
Finished Aug 25 06:40:10 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=362932102 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_with_pre_cond.362932102
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.3694773201
Short name T216
Test name
Test status
Simulation time 4359783036 ps
CPU time 6.67 seconds
Started Aug 25 06:31:20 AM UTC 24
Finished Aug 25 06:31:28 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3694773201 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.3694773201
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.2310834990
Short name T168
Test name
Test status
Simulation time 3152489975 ps
CPU time 1.5 seconds
Started Aug 25 06:31:26 AM UTC 24
Finished Aug 25 06:31:29 AM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2310834990 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.2310834990
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.2529870721
Short name T421
Test name
Test status
Simulation time 2643398919 ps
CPU time 3.17 seconds
Started Aug 25 06:31:19 AM UTC 24
Finished Aug 25 06:31:23 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529870721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.2529870721
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.156320873
Short name T420
Test name
Test status
Simulation time 2489561789 ps
CPU time 3.92 seconds
Started Aug 25 06:31:14 AM UTC 24
Finished Aug 25 06:31:19 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156320873 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
4/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.156320873
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.1489739267
Short name T422
Test name
Test status
Simulation time 2121176498 ps
CPU time 8.74 seconds
Started Aug 25 06:31:15 AM UTC 24
Finished Aug 25 06:31:26 AM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1489739267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.1489739267
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1183451413
Short name T217
Test name
Test status
Simulation time 2510123312 ps
CPU time 13.67 seconds
Started Aug 25 06:31:18 AM UTC 24
Finished Aug 25 06:31:33 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1183451413 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1183451413
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.271315005
Short name T418
Test name
Test status
Simulation time 2139193111 ps
CPU time 2.72 seconds
Started Aug 25 06:31:13 AM UTC 24
Finished Aug 25 06:31:17 AM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271315005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.271315005
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.3335694792
Short name T277
Test name
Test status
Simulation time 3897877647 ps
CPU time 18.24 seconds
Started Aug 25 06:31:28 AM UTC 24
Finished Aug 25 06:31:47 AM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3335694792 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.3335694792
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.1267919824
Short name T266
Test name
Test status
Simulation time 218172204228 ps
CPU time 156.05 seconds
Started Aug 25 06:42:25 AM UTC 24
Finished Aug 25 06:45:04 AM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267919824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_with_pre_cond.1267919824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.64740391
Short name T778
Test name
Test status
Simulation time 65312539963 ps
CPU time 155.17 seconds
Started Aug 25 06:42:31 AM UTC 24
Finished Aug 25 06:45:09 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64740391 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_with_pre_cond.64740391
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.3133898767
Short name T776
Test name
Test status
Simulation time 33593069874 ps
CPU time 90.51 seconds
Started Aug 25 06:42:32 AM UTC 24
Finished Aug 25 06:44:05 AM UTC 24
Peak memory 210580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3133898767 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_with_pre_cond.3133898767
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2641434672
Short name T768
Test name
Test status
Simulation time 29601890308 ps
CPU time 35.45 seconds
Started Aug 25 06:42:44 AM UTC 24
Finished Aug 25 06:43:21 AM UTC 24
Peak memory 210448 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2641434672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_with_pre_cond.2641434672
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.765897693
Short name T789
Test name
Test status
Simulation time 69667507804 ps
CPU time 254.11 seconds
Started Aug 25 06:42:45 AM UTC 24
Finished Aug 25 06:47:03 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=765897693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_with_pre_cond.765897693
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.1241723824
Short name T388
Test name
Test status
Simulation time 43503577129 ps
CPU time 32.13 seconds
Started Aug 25 06:42:46 AM UTC 24
Finished Aug 25 06:43:19 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241723824 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_with_pre_cond.1241723824
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.3776485724
Short name T769
Test name
Test status
Simulation time 25600257224 ps
CPU time 32.26 seconds
Started Aug 25 06:42:55 AM UTC 24
Finished Aug 25 06:43:28 AM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776485724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_with_pre_cond.3776485724
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.1701818595
Short name T165
Test name
Test status
Simulation time 2016580169 ps
CPU time 10.41 seconds
Started Aug 25 06:31:48 AM UTC 24
Finished Aug 25 06:32:00 AM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701818595 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.1701818595
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.4055172319
Short name T775
Test name
Test status
Simulation time 177465824243 ps
CPU time 736.13 seconds
Started Aug 25 06:31:39 AM UTC 24
Finished Aug 25 06:44:04 AM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055172319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.4055172319
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.1883868856
Short name T348
Test name
Test status
Simulation time 111581610069 ps
CPU time 484.14 seconds
Started Aug 25 06:31:41 AM UTC 24
Finished Aug 25 06:39:52 AM UTC 24
Peak memory 210096 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1883868856 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.1883868856
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3736016479
Short name T264
Test name
Test status
Simulation time 41415303275 ps
CPU time 207.87 seconds
Started Aug 25 06:31:47 AM UTC 24
Finished Aug 25 06:35:18 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736016479 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_with_pre_cond.3736016479
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.4001222635
Short name T160
Test name
Test status
Simulation time 3892620494 ps
CPU time 12.33 seconds
Started Aug 25 06:31:39 AM UTC 24
Finished Aug 25 06:31:52 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4001222635 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.4001222635
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.949017411
Short name T159
Test name
Test status
Simulation time 3931325507 ps
CPU time 6.54 seconds
Started Aug 25 06:31:41 AM UTC 24
Finished Aug 25 06:31:49 AM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=949017411 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.949017411
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.2287394509
Short name T276
Test name
Test status
Simulation time 2616817945 ps
CPU time 7 seconds
Started Aug 25 06:31:39 AM UTC 24
Finished Aug 25 06:31:47 AM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2287394509 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.2287394509
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.4116908694
Short name T220
Test name
Test status
Simulation time 2468582059 ps
CPU time 3.58 seconds
Started Aug 25 06:31:33 AM UTC 24
Finished Aug 25 06:31:38 AM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116908694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.4116908694
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.865150998
Short name T221
Test name
Test status
Simulation time 2090522313 ps
CPU time 3.15 seconds
Started Aug 25 06:31:35 AM UTC 24
Finished Aug 25 06:31:40 AM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=865150998 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.865150998
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.2387786135
Short name T274
Test name
Test status
Simulation time 2565746440 ps
CPU time 2.44 seconds
Started Aug 25 06:31:36 AM UTC 24
Finished Aug 25 06:31:40 AM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387786135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.2387786135
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.3033638452
Short name T275
Test name
Test status
Simulation time 2118269426 ps
CPU time 6.79 seconds
Started Aug 25 06:31:32 AM UTC 24
Finished Aug 25 06:31:40 AM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3033638452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.3033638452
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2013419308
Short name T767
Test name
Test status
Simulation time 28867333033 ps
CPU time 19.52 seconds
Started Aug 25 06:42:57 AM UTC 24
Finished Aug 25 06:43:18 AM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2013419308 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_with_pre_cond.2013419308
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.2374896150
Short name T782
Test name
Test status
Simulation time 40455749238 ps
CPU time 176.4 seconds
Started Aug 25 06:43:00 AM UTC 24
Finished Aug 25 06:45:59 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374896150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_with_pre_cond.2374896150
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.1286966725
Short name T764
Test name
Test status
Simulation time 27125045622 ps
CPU time 7.78 seconds
Started Aug 25 06:43:01 AM UTC 24
Finished Aug 25 06:43:10 AM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286966725 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_with_pre_cond.1286966725
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.1856866995
Short name T387
Test name
Test status
Simulation time 134068860750 ps
CPU time 83.79 seconds
Started Aug 25 06:43:09 AM UTC 24
Finished Aug 25 06:44:35 AM UTC 24
Peak memory 210240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1856866995 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_with_pre_cond.1856866995
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3063962776
Short name T381
Test name
Test status
Simulation time 129643748694 ps
CPU time 379.4 seconds
Started Aug 25 06:43:11 AM UTC 24
Finished Aug 25 06:49:35 AM UTC 24
Peak memory 210312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3063962776 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_with_pre_cond.3063962776
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.294878240
Short name T365
Test name
Test status
Simulation time 143195653448 ps
CPU time 117.83 seconds
Started Aug 25 06:43:14 AM UTC 24
Finished Aug 25 06:45:14 AM UTC 24
Peak memory 210584 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=294878240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_with_pre_cond.294878240
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.3826811091
Short name T774
Test name
Test status
Simulation time 25861117791 ps
CPU time 34.59 seconds
Started Aug 25 06:43:14 AM UTC 24
Finished Aug 25 06:43:50 AM UTC 24
Peak memory 210644 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826811091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_with_pre_cond.3826811091
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.1650196187
Short name T783
Test name
Test status
Simulation time 43721577048 ps
CPU time 181.96 seconds
Started Aug 25 06:43:15 AM UTC 24
Finished Aug 25 06:46:20 AM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650196187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_24/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_with_pre_cond.1650196187
Directory /workspaces/repo/scratch/os_regression_2024_08_24/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest
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