Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.89	100.00	94.44		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T6 T26 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T28 T29 T30 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T28 T29 T30 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T28 T29 T30 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T28 T29 T30 
149        1/1                    cnt_en = 1'b1;
           Tests:       T28 T29 T30 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T28 T29 T30 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T28 T29 T30 
163        1/1                    state_d = IdleSt;
           Tests:       T44 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 
165        1/1                  end else if (cnt_done) begin
           Tests:       T28 T29 T30 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T29 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T28 T29 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T28 T29 T30 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T70 T55 T141 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T28 T29 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T28 T29 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T28 T29 T30 
186        1/1                    state_d = IdleSt;
           Tests:       T48 T122 T125 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T48 T122 T125 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T28 T29 T30 
191        1/1                      state_d = StableSt;
           Tests:       T28 T29 T30 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T28 T29 T30 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T28 T29 T30 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T28 T29 T30 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T28 T29 T30 
206        1/1                    state_d = IdleSt;
           Tests:       T28 T29 T30 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T28 T29 T30 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T26
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T28,T29,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T28,T29,T30

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T28,T29,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T28,T29,T30
1	0	Covered	T4,T6,T26
1	1	Covered	T28,T29,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Covered	T48,T122,T125
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T28,T29,T30
0	1	Covered	T28,T29,T30
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T28,T29,T30
1	-	Covered	T28,T29,T30

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T28,T29,T30
DetectSt	168	Covered	T28,T29,T30
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T28,T29,T30

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T28,T29,T30
DebounceSt->IdleSt	163	Covered	T44,T70,T55
DetectSt->IdleSt	186	Covered	T48,T122,T125
DetectSt->StableSt	191	Covered	T28,T29,T30
IdleSt->DebounceSt	148	Covered	T28,T29,T30
StableSt->IdleSt	206	Covered	T28,T29,T30

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T28,T29,T30
0	1	Covered	T28,T29,T30
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T28,T29,T30
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T28,T29,T30
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T44
DebounceSt	-	0	1	1	-	-	-	Covered	T28,T29,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T70,T55,T141
DebounceSt	-	0	0	-	-	-	-	Covered	T28,T29,T30
DetectSt	-	-	-	-	1	-	-	Covered	T48,T122,T125
DetectSt	-	-	-	-	0	1	-	Covered	T28,T29,T30
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T28,T29,T30
StableSt	-	-	-	-	-	-	0	Covered	T28,T29,T30
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	217	0	0
CntIncr_A	6668985	72425	0	0
CntNoWrap_A	6668985	6186791	0	0
DetectStDropOut_A	6668985	4	0	0
DetectedOut_A	6668985	659	0	0
DetectedPulseOut_A	6668985	97	0	0
DisabledIdleSt_A	6668985	6109595	0	0
DisabledNoDetection_A	6668985	6111490	0	0
EnterDebounceSt_A	6668985	117	0	0
EnterDetectSt_A	6668985	101	0	0
EnterStableSt_A	6668985	97	0	0
PulseIsPulse_A	6668985	97	0	0
StayInStableSt	6668985	562	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6668985	5738	0	0
gen_low_level_sva.LowLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	96	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	217	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T25	490	0	0	0
T28	832	6	0	0
T29	2392	6	0	0
T30	0	4	0	0
T31	471	0	0	0
T44	0	1	0	0
T48	0	4	0	0
T60	4539	0	0	0
T65	444	0	0	0
T66	0	4	0	0
T67	0	4	0	0
T68	0	2	0	0
T69	0	2	0	0
T70	0	3	0	0
T71	423	0	0	0
T72	428	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	72425	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T25	490	0	0	0
T28	832	288	0	0
T29	2392	131	0	0
T30	0	94	0	0
T31	471	0	0	0
T44	0	33	0	0
T48	0	173	0	0
T60	4539	0	0	0
T65	444	0	0	0
T66	0	194	0	0
T67	0	104	0	0
T68	0	78	0	0
T69	0	25	0	0
T70	0	184	0	0
T71	423	0	0	0
T72	428	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186791	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	4	0	0
T39	19202	0	0	0
T48	8274	1	0	0
T64	8518	0	0	0
T74	1932	0	0	0
T122	0	1	0	0
T125	0	1	0	0
T126	0	1	0	0
T128	1040	0	0	0
T129	502	0	0	0
T130	709	0	0	0
T131	521	0	0	0
T132	428	0	0	0
T133	451	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	659	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T25	490	0	0	0
T28	832	24	0	0
T29	2392	21	0	0
T30	0	15	0	0
T31	471	0	0	0
T48	0	4	0	0
T60	4539	0	0	0
T65	444	0	0	0
T66	0	21	0	0
T67	0	13	0	0
T68	0	7	0	0
T69	0	1	0	0
T70	0	12	0	0
T71	423	0	0	0
T72	428	0	0	0
T130	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	97	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T25	490	0	0	0
T28	832	3	0	0
T29	2392	3	0	0
T30	0	2	0	0
T31	471	0	0	0
T48	0	1	0	0
T60	4539	0	0	0
T65	444	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	423	0	0	0
T72	428	0	0	0
T130	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6109595	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6111490	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	117	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T25	490	0	0	0
T28	832	3	0	0
T29	2392	3	0	0
T30	0	2	0	0
T31	471	0	0	0
T44	0	1	0	0
T48	0	2	0	0
T60	4539	0	0	0
T65	444	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	423	0	0	0
T72	428	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	101	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T25	490	0	0	0
T28	832	3	0	0
T29	2392	3	0	0
T30	0	2	0	0
T31	471	0	0	0
T48	0	2	0	0
T60	4539	0	0	0
T65	444	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	423	0	0	0
T72	428	0	0	0
T130	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	97	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T25	490	0	0	0
T28	832	3	0	0
T29	2392	3	0	0
T30	0	2	0	0
T31	471	0	0	0
T48	0	1	0	0
T60	4539	0	0	0
T65	444	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	423	0	0	0
T72	428	0	0	0
T130	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	97	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T25	490	0	0	0
T28	832	3	0	0
T29	2392	3	0	0
T30	0	2	0	0
T31	471	0	0	0
T48	0	1	0	0
T60	4539	0	0	0
T65	444	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	423	0	0	0
T72	428	0	0	0
T130	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	562	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T25	490	0	0	0
T28	832	21	0	0
T29	2392	18	0	0
T30	0	13	0	0
T31	471	0	0	0
T48	0	3	0	0
T60	4539	0	0	0
T64	0	11	0	0
T65	444	0	0	0
T66	0	19	0	0
T67	0	11	0	0
T68	0	6	0	0
T70	0	11	0	0
T71	423	0	0	0
T72	428	0	0	0
T130	0	6	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5738	0	0
T1	822	0	0	0
T2	0	12	0	0
T4	513	4	0	0
T5	442	0	0	0
T6	429	4	0	0
T14	453	0	0	0
T15	489	8	0	0
T16	487	0	0	0
T17	0	6	0	0
T18	0	5	0	0
T21	0	2	0	0
T22	1040	0	0	0
T26	527	7	0	0
T27	0	7	0	0
T36	423	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	96	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T25	490	0	0	0
T28	832	3	0	0
T29	2392	3	0	0
T30	0	2	0	0
T31	471	0	0	0
T48	0	1	0	0
T60	4539	0	0	0
T65	444	0	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	1	0	0
T70	0	1	0	0
T71	423	0	0	0
T72	428	0	0	0
T130	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T6 T26 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T3 T24 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T3 T23 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T3 T23 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T3 T24 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T3 T24 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T3 T24 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T3 T24 
163        1/1                    state_d = IdleSt;
           Tests:       T44 T64 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T3 T24 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T24 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T3 T24 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T24 T74 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T2 T73 T115 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T24 T74 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T24 T74 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T24 T74 
186        1/1                    state_d = IdleSt;
           Tests:       T103 T107 T115 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T103 T107 T115 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T24 T74 
191        1/1                      state_d = StableSt;
           Tests:       T3 T24 T74 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T24 T74 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T24 T74 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T24 T74 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T24 T74 
206        1/1                    state_d = IdleSt;
           Tests:       T3 T24 T74 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T24 T74 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T26
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T3,T24,T74

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T24
1	0	Covered	T4,T6,T26
1	1	Covered	T2,T3,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T24,T74
0	1	Covered	T103,T107,T115
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T24,T74
0	1	Unreachable
1	0	Covered	T3,T24,T74

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T24
DetectSt	168	Covered	T3,T24,T74
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T3,T24,T74

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T24,T74
DebounceSt->IdleSt	163	Covered	T2,T73,T44
DetectSt->IdleSt	186	Covered	T103,T107,T115
DetectSt->StableSt	191	Covered	T3,T24,T74
IdleSt->DebounceSt	148	Covered	T2,T3,T24
StableSt->IdleSt	206	Covered	T3,T24,T74

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T24
0	1	Covered	T2,T3,T24
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T24,T74
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T44,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T24,T74
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T73,T115
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T24
DetectSt	-	-	-	-	1	-	-	Covered	T103,T107,T115
DetectSt	-	-	-	-	0	1	-	Covered	T3,T24,T74
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T3,T24,T74
StableSt	-	-	-	-	-	-	0	Covered	T3,T24,T74
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	145	0	0
CntIncr_A	6668985	83818	0	0
CntNoWrap_A	6668985	6186863	0	0
DetectStDropOut_A	6668985	15	0	0
DetectedOut_A	6668985	167117	0	0
DetectedPulseOut_A	6668985	35	0	0
DisabledIdleSt_A	6668985	5192499	0	0
DisabledNoDetection_A	6668985	5194435	0	0
EnterDebounceSt_A	6668985	97	0	0
EnterDetectSt_A	6668985	50	0	0
EnterStableSt_A	6668985	35	0	0
PulseIsPulse_A	6668985	35	0	0
StayInStableSt	6668985	167082	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6668985	5738	0	0
gen_low_level_sva.LowLevelEvent_A	6668985	6188948	0	0
gen_sticky_sva.StableStDropOut_A	6668985	532130	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	145	0	0
T2	2239	4	0	0
T3	1035	2	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	4	0	0
T27	522	0	0	0
T28	832	0	0	0
T44	0	1	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T64	0	1	0	0
T73	0	3	0	0
T74	0	2	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	83818	0	0
T2	2239	232	0	0
T3	1035	53	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	62	0	0
T27	522	0	0	0
T28	832	0	0	0
T44	0	10	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T64	0	51	0	0
T73	0	96	0	0
T74	0	100	0	0
T99	0	50	0	0
T100	0	30	0	0
T101	0	98	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186863	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	15	0	0
T103	1836	3	0	0
T105	13512	0	0	0
T107	0	2	0	0
T115	0	3	0	0
T120	19115	0	0	0
T142	0	2	0	0
T143	0	2	0	0
T144	0	3	0	0
T145	932	0	0	0
T146	490	0	0	0
T147	522	0	0	0
T148	403	0	0	0
T149	535	0	0	0
T150	709	0	0	0
T151	427	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	167117	0	0
T3	1035	70	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T24	0	298	0	0
T25	490	0	0	0
T28	832	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T56	405	0	0	0
T65	444	0	0	0
T71	423	0	0	0
T74	0	656	0	0
T99	0	114	0	0
T100	0	6	0	0
T101	0	519	0	0
T105	0	32	0	0
T106	0	355	0	0
T107	0	29	0	0
T140	0	163	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	35	0	0
T3	1035	1	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T24	0	2	0	0
T25	490	0	0	0
T28	832	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T56	405	0	0	0
T65	444	0	0	0
T71	423	0	0	0
T74	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5192499	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5194435	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	97	0	0
T2	2239	4	0	0
T3	1035	1	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	2	0	0
T27	522	0	0	0
T28	832	0	0	0
T44	0	2	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T64	0	2	0	0
T73	0	3	0	0
T74	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	50	0	0
T3	1035	1	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T24	0	2	0	0
T25	490	0	0	0
T28	832	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T56	405	0	0	0
T65	444	0	0	0
T71	423	0	0	0
T74	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T103	0	3	0	0
T105	0	1	0	0
T106	0	1	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	35	0	0
T3	1035	1	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T24	0	2	0	0
T25	490	0	0	0
T28	832	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T56	405	0	0	0
T65	444	0	0	0
T71	423	0	0	0
T74	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	35	0	0
T3	1035	1	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T24	0	2	0	0
T25	490	0	0	0
T28	832	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T56	405	0	0	0
T65	444	0	0	0
T71	423	0	0	0
T74	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T105	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	167082	0	0
T3	1035	69	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T24	0	296	0	0
T25	490	0	0	0
T28	832	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T56	405	0	0	0
T65	444	0	0	0
T71	423	0	0	0
T74	0	655	0	0
T99	0	113	0	0
T100	0	5	0	0
T101	0	518	0	0
T105	0	31	0	0
T106	0	354	0	0
T107	0	28	0	0
T140	0	162	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5738	0	0
T1	822	0	0	0
T2	0	12	0	0
T4	513	4	0	0
T5	442	0	0	0
T6	429	4	0	0
T14	453	0	0	0
T15	489	8	0	0
T16	487	0	0	0
T17	0	6	0	0
T18	0	5	0	0
T21	0	2	0	0
T22	1040	0	0	0
T26	527	7	0	0
T27	0	7	0	0
T36	423	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	532130	0	0
T3	1035	44	0	0
T7	3077	0	0	0
T8	1171	0	0	0
T24	0	311	0	0
T25	490	0	0	0
T28	832	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T56	405	0	0	0
T65	444	0	0	0
T71	423	0	0	0
T74	0	90	0	0
T99	0	517	0	0
T100	0	64	0	0
T101	0	86	0	0
T105	0	58	0	0
T106	0	145	0	0
T107	0	133	0	0
T140	0	380	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T6 T26 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T6 T26 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T3 T24 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T3 T23 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T3 T23 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T6 T26 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T6 T26 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T6 T26 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T6 T26 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T6 T26 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T6 T26 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T6 T26 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T6 T26 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T3 T24 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T3 T24 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T3 T24 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T3 T24 
163        1/1                    state_d = IdleSt;
           Tests:       T44 T64 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T3 T24 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T24 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T3 T24 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T3 T24 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T99 T100 T106 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T3 T24 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T3 T24 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T3 T24 
186        1/1                    state_d = IdleSt;
           Tests:       T73 T113 T114 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T73 T113 T114 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T3 T24 
191        1/1                      state_d = StableSt;
           Tests:       T2 T3 T24 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T3 T24 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T3 T24 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T3 T24 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T3 T24 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T3 T24 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T3 T24 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	18	17	94.44
Logical	18	17	94.44
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T26
1	1	Covered	T4,T6,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T24

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T24
1	0	Covered	T4,T6,T26
1	1	Covered	T2,T3,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T24
0	1	Covered	T73,T113,T114
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T24
0	1	Unreachable
1	0	Covered	T2,T3,T24

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T24
DetectSt	168	Covered	T2,T3,T24
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T24

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T24
DebounceSt->IdleSt	163	Covered	T44,T64,T99
DetectSt->IdleSt	186	Covered	T73,T113,T114
DetectSt->StableSt	191	Covered	T2,T3,T24
IdleSt->DebounceSt	148	Covered	T2,T3,T24
StableSt->IdleSt	206	Covered	T2,T3,T24

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T24
0	1	Covered	T2,T3,T24
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T24
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T44,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T24
DebounceSt	-	0	1	0	-	-	-	Covered	T99,T100,T106
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T24
DetectSt	-	-	-	-	1	-	-	Covered	T73,T113,T114
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T24
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T24
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T24
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	134	0	0
CntIncr_A	6668985	125815	0	0
CntNoWrap_A	6668985	6186874	0	0
DetectStDropOut_A	6668985	9	0	0
DetectedOut_A	6668985	6110	0	0
DetectedPulseOut_A	6668985	32	0	0
DisabledIdleSt_A	6668985	5192499	0	0
DisabledNoDetection_A	6668985	5194435	0	0
EnterDebounceSt_A	6668985	95	0	0
EnterDetectSt_A	6668985	41	0	0
EnterStableSt_A	6668985	32	0	0
PulseIsPulse_A	6668985	32	0	0
StayInStableSt	6668985	6078	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_sticky_sva.StableStDropOut_A	6668985	845024	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	134	0	0
T2	2239	2	0	0
T3	1035	2	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	4	0	0
T27	522	0	0	0
T28	832	0	0	0
T44	0	1	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T64	0	1	0	0
T73	0	6	0	0
T74	0	2	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	125815	0	0
T2	2239	76	0	0
T3	1035	39	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	82	0	0
T27	522	0	0	0
T28	832	0	0	0
T44	0	12	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T64	0	50	0	0
T73	0	102	0	0
T74	0	44	0	0
T99	0	291	0	0
T100	0	77	0	0
T101	0	89	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186874	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	9	0	0
T33	9264	0	0	0
T34	4765	0	0	0
T44	7695	0	0	0
T46	808	0	0	0
T53	8402	0	0	0
T68	1591	0	0	0
T73	1389	3	0	0
T113	0	2	0	0
T114	0	2	0	0
T152	0	1	0	0
T153	0	1	0	0
T154	885	0	0	0
T155	424	0	0	0
T156	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6110	0	0
T2	2239	398	0	0
T3	1035	63	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	341	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T74	0	239	0	0
T101	0	373	0	0
T103	0	252	0	0
T105	0	48	0	0
T107	0	144	0	0
T115	0	1167	0	0
T140	0	167	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	32	0	0
T2	2239	1	0	0
T3	1035	1	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	2	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T74	0	1	0	0
T101	0	1	0	0
T103	0	1	0	0
T105	0	1	0	0
T107	0	2	0	0
T115	0	3	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5192499	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5194435	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	95	0	0
T2	2239	1	0	0
T3	1035	1	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	2	0	0
T27	522	0	0	0
T28	832	0	0	0
T44	0	2	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T64	0	2	0	0
T73	0	3	0	0
T74	0	1	0	0
T99	0	3	0	0
T100	0	1	0	0
T101	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	41	0	0
T2	2239	1	0	0
T3	1035	1	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	2	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T73	0	3	0	0
T74	0	1	0	0
T101	0	1	0	0
T103	0	1	0	0
T105	0	1	0	0
T107	0	2	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	32	0	0
T2	2239	1	0	0
T3	1035	1	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	2	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T74	0	1	0	0
T101	0	1	0	0
T103	0	1	0	0
T105	0	1	0	0
T107	0	2	0	0
T115	0	3	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	32	0	0
T2	2239	1	0	0
T3	1035	1	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	2	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T74	0	1	0	0
T101	0	1	0	0
T103	0	1	0	0
T105	0	1	0	0
T107	0	2	0	0
T115	0	3	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6078	0	0
T2	2239	397	0	0
T3	1035	62	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	339	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T74	0	238	0	0
T101	0	372	0	0
T103	0	251	0	0
T105	0	47	0	0
T107	0	142	0	0
T115	0	1164	0	0
T140	0	166	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	845024	0	0
T2	2239	126	0	0
T3	1035	79	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	221	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T74	0	549	0	0
T101	0	238	0	0
T103	0	83	0	0
T105	0	27	0	0
T107	0	156	0	0
T115	0	494925	0	0
T140	0	373	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T6 T26 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T4 T6 T26 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T3 T24 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T3 T23 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T3 T23 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T6 T26 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T6 T26 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T6 T26 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T6 T26 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T6 T26 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T6 T26 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T6 T26 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T6 T26 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T3 T24 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T3 T24 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T3 T24 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T3 T24 
163        1/1                    state_d = IdleSt;
           Tests:       T44 T64 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T3 T24 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T3 T24 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T3 T24 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T3 T73 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T24 T106 T103 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T3 T73 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T3 T73 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T3 T73 
186        1/1                    state_d = IdleSt;
           Tests:       T106 T105 T107 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T106 T105 T107 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T3 T73 
191        1/1                      state_d = StableSt;
           Tests:       T2 T3 T73 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T3 T73 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T3 T73 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T3 T73 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T3 T73 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T3 T73 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T3 T73 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	15	14	93.33
Logical	15	14	93.33
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T24

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T2,T3,T24

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T73

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T24
1	0	Covered	T4,T6,T26
1	1	Covered	T2,T3,T24

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T73
0	1	Covered	T106,T105,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T73
0	1	Unreachable
1	0	Covered	T2,T3,T73

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T3,T24
DetectSt	168	Covered	T2,T3,T73
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T73

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T73
DebounceSt->IdleSt	163	Covered	T24,T44,T64
DetectSt->IdleSt	186	Covered	T106,T105,T107
DetectSt->StableSt	191	Covered	T2,T3,T73
IdleSt->DebounceSt	148	Covered	T2,T3,T24
StableSt->IdleSt	206	Covered	T2,T3,T73

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		18	18	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T2,T3,T24
0	1	Covered	T2,T3,T24
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T73
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T3,T24
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T26
DebounceSt	-	1	-	-	-	-	-	Covered	T44,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T73
DebounceSt	-	0	1	0	-	-	-	Covered	T24,T106,T103
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T3,T24
DetectSt	-	-	-	-	1	-	-	Covered	T106,T105,T107
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T73
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T73
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T73
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	129	0	0
CntIncr_A	6668985	160523	0	0
CntNoWrap_A	6668985	6186879	0	0
DetectStDropOut_A	6668985	6	0	0
DetectedOut_A	6668985	682814	0	0
DetectedPulseOut_A	6668985	42	0	0
DisabledIdleSt_A	6668985	5192499	0	0
DisabledNoDetection_A	6668985	5194435	0	0
EnterDebounceSt_A	6668985	83	0	0
EnterDetectSt_A	6668985	48	0	0
EnterStableSt_A	6668985	42	0	0
PulseIsPulse_A	6668985	42	0	0
StayInStableSt	6668985	682772	0	0
gen_high_event_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_sticky_sva.StableStDropOut_A	6668985	147970	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	129	0	0
T2	2239	2	0	0
T3	1035	2	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	8	0	0
T27	522	0	0	0
T28	832	0	0	0
T44	0	1	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T64	0	1	0	0
T73	0	2	0	0
T74	0	2	0	0
T99	0	2	0	0
T100	0	2	0	0
T101	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	160523	0	0
T2	2239	51	0	0
T3	1035	52	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	576	0	0
T27	522	0	0	0
T28	832	0	0	0
T44	0	13	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T64	0	51	0	0
T73	0	27	0	0
T74	0	59	0	0
T99	0	89	0	0
T100	0	24	0	0
T101	0	72	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186879	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6	0	0
T105	0	1	0	0
T106	3583	2	0	0
T107	0	2	0	0
T157	0	1	0	0
T158	16760	0	0	0
T159	1007	0	0	0
T160	525	0	0	0
T161	502	0	0	0
T162	415	0	0	0
T163	747	0	0	0
T164	574	0	0	0
T165	4816	0	0	0
T166	406	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	682814	0	0
T2	2239	214	0	0
T3	1035	75	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T73	0	118	0	0
T74	0	240	0	0
T99	0	425	0	0
T100	0	21	0	0
T101	0	313	0	0
T106	0	61	0	0
T107	0	1	0	0
T140	0	453	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	42	0	0
T2	2239	1	0	0
T3	1035	1	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5192499	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5194435	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	83	0	0
T2	2239	1	0	0
T3	1035	1	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T24	0	8	0	0
T27	522	0	0	0
T28	832	0	0	0
T44	0	2	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T64	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	48	0	0
T2	2239	1	0	0
T3	1035	1	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T105	0	1	0	0
T106	0	3	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	42	0	0
T2	2239	1	0	0
T3	1035	1	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	42	0	0
T2	2239	1	0	0
T3	1035	1	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T99	0	1	0	0
T100	0	1	0	0
T101	0	1	0	0
T106	0	1	0	0
T107	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	682772	0	0
T2	2239	213	0	0
T3	1035	74	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T73	0	117	0	0
T74	0	239	0	0
T99	0	424	0	0
T100	0	20	0	0
T101	0	312	0	0
T106	0	60	0	0
T115	0	427926	0	0
T140	0	452	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	147970	0	0
T2	2239	339	0	0
T3	1035	56	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T28	832	0	0	0
T56	405	0	0	0
T62	502	0	0	0
T63	651	0	0	0
T73	0	102	0	0
T74	0	551	0	0
T99	0	185	0	0
T100	0	65	0	0
T101	0	334	0	0
T106	0	121	0	0
T107	0	27	0	0
T140	0	45	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T9 T50 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T9 T50 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T9 T50 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T50 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T9 T50 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T9 T50 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T9 T50 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T9 T50 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T9 T50 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T48 T167 T168 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T9 T50 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T50 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T9 T50 
186        1/1                    state_d = IdleSt;
           Tests:       T169 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T169 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T9 T50 
191        1/1                      state_d = StableSt;
           Tests:       T8 T9 T50 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T9 T50 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T9 T50 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T9 T50 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T9 T50 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T9 T44 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T9 T50 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T12
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T9,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T50
0	1	Covered	T169
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T50
0	1	Covered	T8,T9,T46
1	0	Covered	T44,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T50
1	-	Covered	T8,T9,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T50
DetectSt	168	Covered	T8,T9,T50
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T9,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T50
DebounceSt->IdleSt	163	Covered	T48,T167,T168
DetectSt->IdleSt	186	Covered	T169
DetectSt->StableSt	191	Covered	T8,T9,T50
IdleSt->DebounceSt	148	Covered	T8,T9,T50
StableSt->IdleSt	206	Covered	T8,T9,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T50
0	1	Covered	T8,T9,T50
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T50
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T50
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T48,T167,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T50
DetectSt	-	-	-	-	1	-	-	Covered	T169
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T44
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	101	0	0
CntIncr_A	6668985	125895	0	0
CntNoWrap_A	6668985	6186907	0	0
DetectStDropOut_A	6668985	1	0	0
DetectedOut_A	6668985	10466	0	0
DetectedPulseOut_A	6668985	48	0	0
DisabledIdleSt_A	6668985	5863992	0	0
DisabledNoDetection_A	6668985	5865891	0	0
EnterDebounceSt_A	6668985	52	0	0
EnterDetectSt_A	6668985	49	0	0
EnterStableSt_A	6668985	48	0	0
PulseIsPulse_A	6668985	48	0	0
StayInStableSt	6668985	10395	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	101	0	0
T8	1171	4	0	0
T9	943	6	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	2	0	0
T46	0	4	0	0
T48	0	3	0	0
T50	0	2	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	2	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	6	0	0
T139	713	0	0	0
T170	0	4	0	0
T171	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	125895	0	0
T8	1171	160	0	0
T9	943	150	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	15	0	0
T46	0	76	0	0
T48	0	45	0	0
T50	0	97	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	22	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	132	0	0
T139	713	0	0	0
T170	0	142	0	0
T171	0	126	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186907	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1	0	0
T169	594	1	0	0
T172	1030	0	0	0
T173	426	0	0	0
T174	402	0	0	0
T175	1009	0	0	0
T176	498	0	0	0
T177	505	0	0	0
T178	3382	0	0	0
T179	2383	0	0	0
T180	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	10466	0	0
T8	1171	99	0	0
T9	943	134	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	22	0	0
T46	0	128	0	0
T48	0	52	0	0
T50	0	41	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	24	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	135	0	0
T139	713	0	0	0
T170	0	81	0	0
T171	0	72	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	48	0	0
T8	1171	2	0	0
T9	943	3	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	3	0	0
T139	713	0	0	0
T170	0	2	0	0
T171	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5863992	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5865891	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	52	0	0
T8	1171	2	0	0
T9	943	3	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	2	0	0
T50	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	3	0	0
T139	713	0	0	0
T170	0	2	0	0
T171	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	49	0	0
T8	1171	2	0	0
T9	943	3	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	3	0	0
T139	713	0	0	0
T170	0	2	0	0
T171	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	48	0	0
T8	1171	2	0	0
T9	943	3	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	3	0	0
T139	713	0	0	0
T170	0	2	0	0
T171	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	48	0	0
T8	1171	2	0	0
T9	943	3	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T50	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	3	0	0
T139	713	0	0	0
T170	0	2	0	0
T171	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	10395	0	0
T8	1171	96	0	0
T9	943	130	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	21	0	0
T46	0	125	0	0
T48	0	50	0	0
T50	0	39	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	23	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	131	0	0
T139	713	0	0	0
T170	0	78	0	0
T171	0	69	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	23	0	0
T8	1171	1	0	0
T9	943	2	0	0
T10	12010	0	0	0
T23	959	0	0	0
T46	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	2	0	0
T105	0	1	0	0
T139	713	0	0	0
T170	0	1	0	0
T171	0	1	0	0
T181	0	1	0	0
T182	0	1	0	0
T183	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T8 T9 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T8 T9 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T8 T9 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T8 T9 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T8 T9 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T8 T9 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T8 T9 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T8 T9 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T8 T9 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T102 T105 T184 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T8 T9 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T8 T9 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T8 T9 
186        1/1                    state_d = IdleSt;
           Tests:       T185 T186 T187 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T185 T186 T187 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T8 T9 
191        1/1                      state_d = StableSt;
           Tests:       T1 T8 T9 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T8 T9 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T8 T9 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T8 T9 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T8 T9 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T8 T9 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T8 T9 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T4,T6,T26
1	1	Covered	T1,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T185,T186,T187
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
1	0	Covered	T44,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T9
1	-	Covered	T1,T8,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T9
DetectSt	168	Covered	T1,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T9
DebounceSt->IdleSt	163	Covered	T102,T105,T184
DetectSt->IdleSt	186	Covered	T185,T186,T187
DetectSt->StableSt	191	Covered	T1,T8,T9
IdleSt->DebounceSt	148	Covered	T1,T8,T9
StableSt->IdleSt	206	Covered	T1,T8,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T102,T105,T184
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T185,T186,T187
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T8,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	99	0	0
CntIncr_A	6668985	117440	0	0
CntNoWrap_A	6668985	6186909	0	0
DetectStDropOut_A	6668985	3	0	0
DetectedOut_A	6668985	8430	0	0
DetectedPulseOut_A	6668985	44	0	0
DisabledIdleSt_A	6668985	5938667	0	0
DisabledNoDetection_A	6668985	5940569	0	0
EnterDebounceSt_A	6668985	52	0	0
EnterDetectSt_A	6668985	47	0	0
EnterStableSt_A	6668985	44	0	0
PulseIsPulse_A	6668985	44	0	0
StayInStableSt	6668985	8371	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6668985	1759	0	0
gen_low_level_sva.LowLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	99	0	0
T1	822	2	0	0
T2	2239	0	0	0
T8	0	4	0	0
T9	0	6	0	0
T12	0	2	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	2	0	0
T46	0	4	0	0
T47	0	2	0	0
T48	0	2	0	0
T50	0	2	0	0
T64	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	117440	0	0
T1	822	83	0	0
T2	2239	0	0	0
T8	0	160	0	0
T9	0	150	0	0
T12	0	16	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	15	0	0
T46	0	76	0	0
T47	0	96	0	0
T48	0	16	0	0
T50	0	97	0	0
T64	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186909	0	0
T1	822	419	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	3	0	0
T142	1719	0	0	0
T185	994	1	0	0
T186	235340	1	0	0
T187	0	1	0	0
T188	432	0	0	0
T189	508	0	0	0
T190	426	0	0	0
T191	526	0	0	0
T192	439	0	0	0
T193	726	0	0	0
T194	1745	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	8430	0	0
T1	822	128	0	0
T2	2239	0	0	0
T8	0	203	0	0
T9	0	94	0	0
T12	0	44	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	23	0	0
T46	0	116	0	0
T47	0	243	0	0
T48	0	15	0	0
T50	0	64	0	0
T64	0	24	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	44	0	0
T1	822	1	0	0
T2	2239	0	0	0
T8	0	2	0	0
T9	0	3	0	0
T12	0	1	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T64	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5938667	0	0
T1	822	3	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5940569	0	0
T1	822	3	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	52	0	0
T1	822	1	0	0
T2	2239	0	0	0
T8	0	2	0	0
T9	0	3	0	0
T12	0	1	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T64	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	47	0	0
T1	822	1	0	0
T2	2239	0	0	0
T8	0	2	0	0
T9	0	3	0	0
T12	0	1	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T64	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	44	0	0
T1	822	1	0	0
T2	2239	0	0	0
T8	0	2	0	0
T9	0	3	0	0
T12	0	1	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T64	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	44	0	0
T1	822	1	0	0
T2	2239	0	0	0
T8	0	2	0	0
T9	0	3	0	0
T12	0	1	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T64	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	8371	0	0
T1	822	127	0	0
T2	2239	0	0	0
T8	0	201	0	0
T9	0	91	0	0
T12	0	42	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	22	0	0
T46	0	114	0	0
T47	0	242	0	0
T48	0	14	0	0
T50	0	63	0	0
T64	0	23	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1759	0	0
T1	822	1	0	0
T4	513	5	0	0
T5	442	0	0	0
T6	429	3	0	0
T14	453	0	0	0
T15	489	5	0	0
T16	487	0	0	0
T17	0	5	0	0
T18	0	3	0	0
T21	0	3	0	0
T22	1040	0	0	0
T26	527	5	0	0
T27	0	6	0	0
T36	423	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	27	0	0
T1	822	1	0	0
T2	2239	0	0	0
T8	0	2	0	0
T9	0	3	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T46	0	2	0	0
T47	0	1	0	0
T48	0	1	0	0
T50	0	1	0	0
T102	0	1	0	0
T116	0	1	0	0
T183	0	2	0	0