Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T4 T5 T6
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T2 T3
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T5 T1 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T5 T1 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T1 T2 T3
149 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T2 T3
163 1/1 state_d = IdleSt;
Tests: T44 T64
164 1/1 cnt_clr = 1'b1;
Tests: T44 T64
165 1/1 end else if (cnt_done) begin
Tests: T1 T2 T3
166 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
167 1/1 if (trigger_active) begin
Tests: T1 T2 T3
168 1/1 state_d = DetectSt;
Tests: T1 T3 T28
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T2 T73 T70
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T3 T28
182 1/1 cnt_en = 1'b1;
Tests: T1 T3 T28
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T3 T28
186 1/1 state_d = IdleSt;
Tests: T48 T102 T103
187 1/1 cnt_clr = 1'b1;
Tests: T48 T102 T103
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T3 T28
191 1/1 state_d = StableSt;
Tests: T1 T3 T28
192 1/1 cnt_clr = 1'b1;
Tests: T1 T3 T28
193 1/1 event_detected_o = 1'b1;
Tests: T1 T3 T28
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T3 T28
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T3 T28
206 1/1 state_d = IdleSt;
Tests: T1 T3 T28
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T3 T28
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T6
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T2 T3
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T5 T1 T14
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T5 T1 T14
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T1 T2 T3
149 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T2 T3
163 1/1 state_d = IdleSt;
Tests: T44 T64
164 1/1 cnt_clr = 1'b1;
Tests: T44 T64
165 1/1 end else if (cnt_done) begin
Tests: T1 T2 T3
166 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
167 1/1 if (trigger_active) begin
Tests: T1 T2 T3
168 1/1 state_d = DetectSt;
Tests: T1 T2 T3
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T47 T48 T99
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T2 T3
182 1/1 cnt_en = 1'b1;
Tests: T1 T2 T3
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T2 T3
186 1/1 state_d = IdleSt;
Tests: T73 T104 T105
187 1/1 cnt_clr = 1'b1;
Tests: T73 T104 T105
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T2 T3
191 1/1 state_d = StableSt;
Tests: T1 T2 T3
192 1/1 cnt_clr = 1'b1;
Tests: T1 T2 T3
193 1/1 event_detected_o = 1'b1;
Tests: T1 T2 T3
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T2 T3
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T2 T3
206 1/1 state_d = IdleSt;
Tests: T2 T3 T8
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T2 T3
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T6 T26
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T4 T6 T26
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T3 T24
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T2 T3 T23
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T2 T3 T23
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T6 T26
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T6 T26
129 1/1 cnt_en = 1'b0;
Tests: T4 T6 T26
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T6 T26
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T6 T26
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T6 T26
139
140 1/1 unique case (state_q)
Tests: T4 T6 T26
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T6 T26
148 1/1 state_d = DebounceSt;
Tests: T2 T3 T24
149 1/1 cnt_en = 1'b1;
Tests: T2 T3 T24
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T3 T24
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T3 T24
163 1/1 state_d = IdleSt;
Tests: T44 T64
164 1/1 cnt_clr = 1'b1;
Tests: T44 T64
165 1/1 end else if (cnt_done) begin
Tests: T2 T3 T24
166 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T24
167 1/1 if (trigger_active) begin
Tests: T2 T3 T24
168 1/1 state_d = DetectSt;
Tests: T2 T3 T73
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T24 T106 T103
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T3 T73
182 1/1 cnt_en = 1'b1;
Tests: T2 T3 T73
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T3 T73
186 1/1 state_d = IdleSt;
Tests: T106 T105 T107
187 1/1 cnt_clr = 1'b1;
Tests: T106 T105 T107
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T3 T73
191 1/1 state_d = StableSt;
Tests: T2 T3 T73
192 1/1 cnt_clr = 1'b1;
Tests: T2 T3 T73
193 1/1 event_detected_o = 1'b1;
Tests: T2 T3 T73
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T3 T73
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T3 T73
206 1/1 state_d = IdleSt;
Tests: T2 T3 T73
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T3 T73
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T32 T33 T34
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T32 T33 T34
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T14 T16 T31
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T5 T1 T14
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T5 T1 T14
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T14 T16 T31
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T14 T16 T31
129 1/1 cnt_en = 1'b0;
Tests: T14 T16 T31
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T14 T16 T31
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T14 T16 T31
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T14 T16 T31
139
140 1/1 unique case (state_q)
Tests: T14 T16 T31
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T14 T16 T31
148 1/1 state_d = DebounceSt;
Tests: T14 T16 T31
149 1/1 cnt_en = 1'b1;
Tests: T14 T16 T31
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T14 T16 T31
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T14 T16 T31
163 1/1 state_d = IdleSt;
Tests: T44 T64
164 1/1 cnt_clr = 1'b1;
Tests: T44 T64
165 1/1 end else if (cnt_done) begin
Tests: T14 T16 T31
166 1/1 cnt_clr = 1'b1;
Tests: T14 T16 T31
167 1/1 if (trigger_active) begin
Tests: T14 T16 T31
168 1/1 state_d = DetectSt;
Tests: T14 T16 T31
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T34 T44 T64
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T14 T16 T31
182 1/1 cnt_en = 1'b1;
Tests: T14 T16 T31
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T14 T16 T31
186 1/1 state_d = IdleSt;
Tests: T32 T33 T34
187 1/1 cnt_clr = 1'b1;
Tests: T32 T33 T34
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T14 T16 T31
191 1/1 state_d = StableSt;
Tests: T14 T16 T31
192 1/1 cnt_clr = 1'b1;
Tests: T14 T16 T31
193 1/1 event_detected_o = 1'b1;
Tests: T14 T16 T31
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T14 T16 T31
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T14 T16 T31
206 1/1 state_d = IdleSt;
Tests: T32 T33 T34
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T14 T16 T31
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T5 T14 T16
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T5 T14 T16
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T5 T1 T14
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T5 T1 T14
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T5 T14 T16
149 1/1 cnt_en = 1'b1;
Tests: T5 T14 T16
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T5 T14 T16
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T5 T14 T16
163 1/1 state_d = IdleSt;
Tests: T44 T64
164 1/1 cnt_clr = 1'b1;
Tests: T44 T64
165 1/1 end else if (cnt_done) begin
Tests: T5 T14 T16
166 1/1 cnt_clr = 1'b1;
Tests: T5 T14 T16
167 1/1 if (trigger_active) begin
Tests: T5 T14 T16
168 1/1 state_d = DetectSt;
Tests: T7 T10 T11
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T5 T14 T16
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T7 T10 T11
182 1/1 cnt_en = 1'b1;
Tests: T7 T10 T11
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T7 T10 T11
186 1/1 state_d = IdleSt;
Tests: T35 T44 T64
187 1/1 cnt_clr = 1'b1;
Tests: T35 T44 T64
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T7 T10 T11
191 1/1 state_d = StableSt;
Tests: T7 T10 T11
192 1/1 cnt_clr = 1'b1;
Tests: T7 T10 T11
193 1/1 event_detected_o = 1'b1;
Tests: T7 T10 T11
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T7 T10 T11
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T7 T10 T11
206 1/1 state_d = IdleSt;
Tests: T7 T10 T11
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T7 T10 T11
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T5,T14,T16 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T14,T16 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T14,T16 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T5,T14,T16 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T7,T10,T11 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T5,T14,T16 |
| 1 | 0 | Covered | T7,T29,T60 |
| 1 | 1 | Covered | T5,T14,T16 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T10,T11 |
| 0 | 1 | Covered | T108,T109,T43 |
| 1 | 0 | Covered | T44,T64 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T10,T11 |
| 0 | 1 | Covered | T7,T10,T11 |
| 1 | 0 | Covered | T44,T64,T110 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T7,T10,T11 |
| 1 | - | Covered | T7,T10,T11 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T28,T29 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T28,T29 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T28,T29 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T28,T29 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T1,T28,T29 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T28,T29 |
| 0 | 1 | Covered | T48,T102,T105 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T28,T29 |
| 0 | 1 | Covered | T1,T28,T29 |
| 1 | 0 | Covered | T44,T64 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T28,T29 |
| 1 | - | Covered | T1,T28,T29 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T32,T33,T34 |
| 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T14,T16,T31 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T14,T16,T31 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T14,T16,T31 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T32,T33,T34 |
| 1 | 0 | Covered | T32,T33,T44 |
| 1 | 1 | Covered | T14,T16,T31 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T14,T16,T31 |
| 0 | 1 | Covered | T32,T33,T34 |
| 1 | 0 | Covered | T32,T33,T44 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T14,T16,T31 |
| 0 | 1 | Covered | T32,T33,T34 |
| 1 | 0 | Covered | T41,T64,T111 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T14,T16,T31 |
| 1 | - | Covered | T32,T33,T34 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T6,T26 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T3,T24 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T3,T24 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T3,T73 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T24 |
| 1 | 0 | Covered | T4,T6,T26 |
| 1 | 1 | Covered | T2,T3,T24 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T3,T73 |
| 0 | 1 | Covered | T106,T105,T107 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T3,T73 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T3,T73 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T8,T9 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T8,T9 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T8,T9 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T8,T9 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T1,T8,T9 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T8,T9 |
| 0 | 1 | Covered | T104,T105,T112 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T8,T9 |
| 0 | 1 | Covered | T8,T9,T12 |
| 1 | 0 | Covered | T44,T64 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T8,T9 |
| 1 | - | Covered | T8,T9,T12 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T6,T26 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T6,T26 |
| 1 | 1 | Covered | T4,T6,T26 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T3,T24 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T3,T24 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T3,T24 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T24 |
| 1 | 0 | Covered | T4,T6,T26 |
| 1 | 1 | Covered | T2,T3,T24 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T3,T24 |
| 0 | 1 | Covered | T73,T113,T114 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T3,T24 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T3,T24 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T6,T26 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T6,T26 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T3,T24 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T3,T24 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T3,T24,T74 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T3,T24 |
| 1 | 0 | Covered | T4,T6,T26 |
| 1 | 1 | Covered | T2,T3,T24 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T24,T74 |
| 0 | 1 | Covered | T103,T107,T115 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T24,T74 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T3,T24,T74 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DebounceSt |
148 |
Covered |
T1,T28,T29 |
| DetectSt |
168 |
Covered |
T1,T28,T29 |
| IdleSt |
163 |
Covered |
T4,T5,T6 |
| StableSt |
191 |
Covered |
T1,T28,T29 |
| transitions | Line No. | Covered | Tests |
| DebounceSt->DetectSt |
168 |
Covered |
T1,T28,T29 |
| DebounceSt->IdleSt |
163 |
Covered |
T44,T70,T55 |
| DetectSt->IdleSt |
186 |
Covered |
T73,T48,T102 |
| DetectSt->StableSt |
191 |
Covered |
T1,T28,T29 |
| IdleSt->DebounceSt |
148 |
Covered |
T1,T28,T29 |
| StableSt->IdleSt |
206 |
Covered |
T1,T28,T29 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T28,T29 |
| 0 |
1 |
Covered |
T1,T28,T29 |
| 0 |
0 |
Covered |
T4,T5,T6 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T28,T29 |
| 0 |
Covered |
T4,T5,T6 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T28,T29 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T44,T64 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T1,T28,T29 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T70,T55,T116 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T28,T29 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T73,T48,T102 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T1,T28,T29 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T7,T10,T11 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T1,T28,T29 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T28,T29 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T14,T16,T2 |
| 0 |
1 |
Covered |
T14,T16,T2 |
| 0 |
0 |
Covered |
T4,T5,T6 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T14,T16,T2 |
| 0 |
Covered |
T4,T5,T6 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T14,T16,T2 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T6,T26 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T44,T64 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T14,T16,T2 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T24,T34,T44 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T14,T16,T2 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T32,T33,T34 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T14,T16,T2 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T14,T16,T31 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T2,T3,T32 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T14,T16,T2 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
17257 |
0 |
0 |
| T1 |
822 |
0 |
0 |
0 |
| T5 |
442 |
1 |
0 |
0 |
| T6 |
429 |
0 |
0 |
0 |
| T7 |
3077 |
4 |
0 |
0 |
| T8 |
1171 |
0 |
0 |
0 |
| T10 |
0 |
5 |
0 |
0 |
| T11 |
0 |
4 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T14 |
906 |
3 |
0 |
0 |
| T15 |
978 |
0 |
0 |
0 |
| T16 |
974 |
3 |
0 |
0 |
| T17 |
994 |
0 |
0 |
0 |
| T18 |
441 |
0 |
0 |
0 |
| T19 |
0 |
1 |
0 |
0 |
| T22 |
1040 |
0 |
0 |
0 |
| T25 |
490 |
0 |
0 |
0 |
| T26 |
527 |
0 |
0 |
0 |
| T28 |
832 |
6 |
0 |
0 |
| T29 |
2392 |
6 |
0 |
0 |
| T30 |
0 |
4 |
0 |
0 |
| T31 |
471 |
3 |
0 |
0 |
| T36 |
423 |
0 |
0 |
0 |
| T44 |
0 |
17 |
0 |
0 |
| T48 |
0 |
4 |
0 |
0 |
| T60 |
4539 |
0 |
0 |
0 |
| T65 |
444 |
1 |
0 |
0 |
| T66 |
0 |
4 |
0 |
0 |
| T67 |
0 |
4 |
0 |
0 |
| T68 |
0 |
2 |
0 |
0 |
| T69 |
0 |
2 |
0 |
0 |
| T70 |
0 |
3 |
0 |
0 |
| T71 |
423 |
0 |
0 |
0 |
| T72 |
428 |
0 |
0 |
0 |
| T89 |
0 |
2 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
2073582 |
0 |
0 |
| T1 |
822 |
0 |
0 |
0 |
| T5 |
442 |
20 |
0 |
0 |
| T6 |
429 |
0 |
0 |
0 |
| T7 |
3077 |
50 |
0 |
0 |
| T8 |
1171 |
0 |
0 |
0 |
| T10 |
0 |
240 |
0 |
0 |
| T11 |
0 |
46 |
0 |
0 |
| T13 |
0 |
25 |
0 |
0 |
| T14 |
906 |
41 |
0 |
0 |
| T15 |
978 |
0 |
0 |
0 |
| T16 |
974 |
41 |
0 |
0 |
| T17 |
994 |
0 |
0 |
0 |
| T18 |
441 |
0 |
0 |
0 |
| T19 |
0 |
20 |
0 |
0 |
| T22 |
1040 |
0 |
0 |
0 |
| T25 |
490 |
0 |
0 |
0 |
| T26 |
527 |
0 |
0 |
0 |
| T28 |
832 |
288 |
0 |
0 |
| T29 |
2392 |
131 |
0 |
0 |
| T30 |
0 |
94 |
0 |
0 |
| T31 |
471 |
41 |
0 |
0 |
| T36 |
423 |
0 |
0 |
0 |
| T44 |
0 |
609 |
0 |
0 |
| T48 |
0 |
173 |
0 |
0 |
| T60 |
4539 |
0 |
0 |
0 |
| T65 |
444 |
20 |
0 |
0 |
| T66 |
0 |
194 |
0 |
0 |
| T67 |
0 |
104 |
0 |
0 |
| T68 |
0 |
78 |
0 |
0 |
| T69 |
0 |
25 |
0 |
0 |
| T70 |
0 |
184 |
0 |
0 |
| T71 |
423 |
0 |
0 |
0 |
| T72 |
428 |
0 |
0 |
0 |
| T89 |
0 |
21 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
160844951 |
0 |
0 |
| T1 |
21372 |
10930 |
0 |
0 |
| T4 |
13338 |
2912 |
0 |
0 |
| T5 |
11492 |
1065 |
0 |
0 |
| T6 |
11154 |
728 |
0 |
0 |
| T14 |
11778 |
1349 |
0 |
0 |
| T15 |
12714 |
2288 |
0 |
0 |
| T16 |
12662 |
2233 |
0 |
0 |
| T22 |
27040 |
16614 |
0 |
0 |
| T26 |
13702 |
3276 |
0 |
0 |
| T36 |
10998 |
572 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
1971 |
0 |
0 |
| T33 |
9264 |
2 |
0 |
0 |
| T39 |
19202 |
17 |
0 |
0 |
| T41 |
0 |
11 |
0 |
0 |
| T43 |
0 |
9 |
0 |
0 |
| T44 |
0 |
1 |
0 |
0 |
| T48 |
8274 |
1 |
0 |
0 |
| T55 |
3079 |
0 |
0 |
0 |
| T64 |
8518 |
1 |
0 |
0 |
| T74 |
1932 |
0 |
0 |
0 |
| T90 |
0 |
24 |
0 |
0 |
| T92 |
0 |
22 |
0 |
0 |
| T99 |
1136 |
0 |
0 |
0 |
| T102 |
8582 |
0 |
0 |
0 |
| T108 |
6599 |
5 |
0 |
0 |
| T116 |
625 |
0 |
0 |
0 |
| T117 |
0 |
2 |
0 |
0 |
| T118 |
0 |
5 |
0 |
0 |
| T119 |
0 |
5 |
0 |
0 |
| T120 |
0 |
2 |
0 |
0 |
| T121 |
0 |
16 |
0 |
0 |
| T122 |
0 |
1 |
0 |
0 |
| T123 |
0 |
6 |
0 |
0 |
| T124 |
0 |
3 |
0 |
0 |
| T125 |
0 |
1 |
0 |
0 |
| T126 |
0 |
1 |
0 |
0 |
| T127 |
0 |
4 |
0 |
0 |
| T128 |
1040 |
0 |
0 |
0 |
| T129 |
502 |
0 |
0 |
0 |
| T130 |
709 |
0 |
0 |
0 |
| T131 |
521 |
0 |
0 |
0 |
| T132 |
428 |
0 |
0 |
0 |
| T133 |
451 |
0 |
0 |
0 |
| T134 |
402 |
0 |
0 |
0 |
| T135 |
504 |
0 |
0 |
0 |
| T136 |
426 |
0 |
0 |
0 |
| T137 |
414 |
0 |
0 |
0 |
| T138 |
506 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
1650004 |
0 |
0 |
| T2 |
2239 |
0 |
0 |
0 |
| T7 |
6154 |
6 |
0 |
0 |
| T8 |
2342 |
0 |
0 |
0 |
| T9 |
943 |
0 |
0 |
0 |
| T10 |
0 |
15 |
0 |
0 |
| T11 |
0 |
87 |
0 |
0 |
| T13 |
0 |
3 |
0 |
0 |
| T14 |
453 |
27 |
0 |
0 |
| T15 |
489 |
0 |
0 |
0 |
| T16 |
487 |
61 |
0 |
0 |
| T17 |
497 |
0 |
0 |
0 |
| T18 |
441 |
0 |
0 |
0 |
| T19 |
428 |
0 |
0 |
0 |
| T23 |
959 |
0 |
0 |
0 |
| T25 |
490 |
0 |
0 |
0 |
| T28 |
832 |
24 |
0 |
0 |
| T29 |
4784 |
21 |
0 |
0 |
| T30 |
0 |
15 |
0 |
0 |
| T31 |
942 |
0 |
0 |
0 |
| T32 |
0 |
2346 |
0 |
0 |
| T35 |
0 |
102 |
0 |
0 |
| T38 |
0 |
108 |
0 |
0 |
| T44 |
0 |
431 |
0 |
0 |
| T48 |
0 |
11 |
0 |
0 |
| T60 |
9078 |
0 |
0 |
0 |
| T64 |
0 |
604 |
0 |
0 |
| T65 |
444 |
0 |
0 |
0 |
| T66 |
0 |
21 |
0 |
0 |
| T67 |
0 |
13 |
0 |
0 |
| T68 |
0 |
7 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
12 |
0 |
0 |
| T71 |
423 |
0 |
0 |
0 |
| T72 |
856 |
0 |
0 |
0 |
| T83 |
502 |
0 |
0 |
0 |
| T130 |
0 |
8 |
0 |
0 |
| T139 |
713 |
0 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
5504 |
0 |
0 |
| T2 |
2239 |
0 |
0 |
0 |
| T7 |
6154 |
2 |
0 |
0 |
| T8 |
2342 |
0 |
0 |
0 |
| T9 |
943 |
0 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
0 |
2 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
453 |
1 |
0 |
0 |
| T15 |
489 |
0 |
0 |
0 |
| T16 |
487 |
1 |
0 |
0 |
| T17 |
497 |
0 |
0 |
0 |
| T18 |
441 |
0 |
0 |
0 |
| T19 |
428 |
0 |
0 |
0 |
| T23 |
959 |
0 |
0 |
0 |
| T25 |
490 |
0 |
0 |
0 |
| T28 |
832 |
3 |
0 |
0 |
| T29 |
4784 |
3 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T31 |
942 |
0 |
0 |
0 |
| T32 |
0 |
14 |
0 |
0 |
| T35 |
0 |
8 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T44 |
0 |
6 |
0 |
0 |
| T48 |
0 |
3 |
0 |
0 |
| T60 |
9078 |
0 |
0 |
0 |
| T64 |
0 |
6 |
0 |
0 |
| T65 |
444 |
0 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
1 |
0 |
0 |
| T71 |
423 |
0 |
0 |
0 |
| T72 |
856 |
0 |
0 |
0 |
| T83 |
502 |
0 |
0 |
0 |
| T130 |
0 |
2 |
0 |
0 |
| T139 |
713 |
0 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
151033174 |
0 |
0 |
| T1 |
21372 |
7602 |
0 |
0 |
| T4 |
13338 |
2912 |
0 |
0 |
| T5 |
11492 |
1028 |
0 |
0 |
| T6 |
11154 |
728 |
0 |
0 |
| T14 |
11778 |
1278 |
0 |
0 |
| T15 |
12714 |
2288 |
0 |
0 |
| T16 |
12662 |
2094 |
0 |
0 |
| T22 |
27040 |
16614 |
0 |
0 |
| T26 |
13702 |
3276 |
0 |
0 |
| T36 |
10998 |
572 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
151079655 |
0 |
0 |
| T1 |
21372 |
7620 |
0 |
0 |
| T4 |
13338 |
2938 |
0 |
0 |
| T5 |
11492 |
1053 |
0 |
0 |
| T6 |
11154 |
754 |
0 |
0 |
| T14 |
11778 |
1302 |
0 |
0 |
| T15 |
12714 |
2314 |
0 |
0 |
| T16 |
12662 |
2118 |
0 |
0 |
| T22 |
27040 |
16640 |
0 |
0 |
| T26 |
13702 |
3302 |
0 |
0 |
| T36 |
10998 |
598 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
9000 |
0 |
0 |
| T1 |
822 |
0 |
0 |
0 |
| T5 |
442 |
1 |
0 |
0 |
| T6 |
429 |
0 |
0 |
0 |
| T7 |
3077 |
2 |
0 |
0 |
| T8 |
1171 |
0 |
0 |
0 |
| T10 |
0 |
3 |
0 |
0 |
| T11 |
0 |
2 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
906 |
2 |
0 |
0 |
| T15 |
978 |
0 |
0 |
0 |
| T16 |
974 |
2 |
0 |
0 |
| T17 |
994 |
0 |
0 |
0 |
| T18 |
441 |
0 |
0 |
0 |
| T19 |
0 |
1 |
0 |
0 |
| T22 |
1040 |
0 |
0 |
0 |
| T25 |
490 |
0 |
0 |
0 |
| T26 |
527 |
0 |
0 |
0 |
| T28 |
832 |
3 |
0 |
0 |
| T29 |
2392 |
3 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T31 |
471 |
2 |
0 |
0 |
| T36 |
423 |
0 |
0 |
0 |
| T44 |
0 |
10 |
0 |
0 |
| T48 |
0 |
2 |
0 |
0 |
| T60 |
4539 |
0 |
0 |
0 |
| T65 |
444 |
1 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T71 |
423 |
0 |
0 |
0 |
| T72 |
428 |
0 |
0 |
0 |
| T89 |
0 |
1 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
8278 |
0 |
0 |
| T2 |
2239 |
0 |
0 |
0 |
| T7 |
6154 |
2 |
0 |
0 |
| T8 |
2342 |
0 |
0 |
0 |
| T9 |
943 |
0 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
0 |
2 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
453 |
1 |
0 |
0 |
| T15 |
489 |
0 |
0 |
0 |
| T16 |
487 |
1 |
0 |
0 |
| T17 |
497 |
0 |
0 |
0 |
| T18 |
441 |
0 |
0 |
0 |
| T19 |
428 |
0 |
0 |
0 |
| T23 |
959 |
0 |
0 |
0 |
| T25 |
490 |
0 |
0 |
0 |
| T28 |
832 |
3 |
0 |
0 |
| T29 |
4784 |
3 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T31 |
942 |
0 |
0 |
0 |
| T32 |
0 |
14 |
0 |
0 |
| T35 |
0 |
8 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T44 |
0 |
9 |
0 |
0 |
| T48 |
0 |
4 |
0 |
0 |
| T60 |
9078 |
0 |
0 |
0 |
| T64 |
0 |
3 |
0 |
0 |
| T65 |
444 |
0 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
1 |
0 |
0 |
| T71 |
423 |
0 |
0 |
0 |
| T72 |
856 |
0 |
0 |
0 |
| T83 |
502 |
0 |
0 |
0 |
| T130 |
0 |
2 |
0 |
0 |
| T139 |
713 |
0 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
5504 |
0 |
0 |
| T2 |
2239 |
0 |
0 |
0 |
| T7 |
6154 |
2 |
0 |
0 |
| T8 |
2342 |
0 |
0 |
0 |
| T9 |
943 |
0 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
0 |
2 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
453 |
1 |
0 |
0 |
| T15 |
489 |
0 |
0 |
0 |
| T16 |
487 |
1 |
0 |
0 |
| T17 |
497 |
0 |
0 |
0 |
| T18 |
441 |
0 |
0 |
0 |
| T19 |
428 |
0 |
0 |
0 |
| T23 |
959 |
0 |
0 |
0 |
| T25 |
490 |
0 |
0 |
0 |
| T28 |
832 |
3 |
0 |
0 |
| T29 |
4784 |
3 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T31 |
942 |
0 |
0 |
0 |
| T32 |
0 |
14 |
0 |
0 |
| T35 |
0 |
8 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T44 |
0 |
6 |
0 |
0 |
| T48 |
0 |
3 |
0 |
0 |
| T60 |
9078 |
0 |
0 |
0 |
| T64 |
0 |
6 |
0 |
0 |
| T65 |
444 |
0 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
1 |
0 |
0 |
| T71 |
423 |
0 |
0 |
0 |
| T72 |
856 |
0 |
0 |
0 |
| T83 |
502 |
0 |
0 |
0 |
| T130 |
0 |
2 |
0 |
0 |
| T139 |
713 |
0 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
5504 |
0 |
0 |
| T2 |
2239 |
0 |
0 |
0 |
| T7 |
6154 |
2 |
0 |
0 |
| T8 |
2342 |
0 |
0 |
0 |
| T9 |
943 |
0 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
0 |
2 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T14 |
453 |
1 |
0 |
0 |
| T15 |
489 |
0 |
0 |
0 |
| T16 |
487 |
1 |
0 |
0 |
| T17 |
497 |
0 |
0 |
0 |
| T18 |
441 |
0 |
0 |
0 |
| T19 |
428 |
0 |
0 |
0 |
| T23 |
959 |
0 |
0 |
0 |
| T25 |
490 |
0 |
0 |
0 |
| T28 |
832 |
3 |
0 |
0 |
| T29 |
4784 |
3 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T31 |
942 |
0 |
0 |
0 |
| T32 |
0 |
14 |
0 |
0 |
| T35 |
0 |
8 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T44 |
0 |
6 |
0 |
0 |
| T48 |
0 |
3 |
0 |
0 |
| T60 |
9078 |
0 |
0 |
0 |
| T64 |
0 |
6 |
0 |
0 |
| T65 |
444 |
0 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
1 |
0 |
0 |
| T71 |
423 |
0 |
0 |
0 |
| T72 |
856 |
0 |
0 |
0 |
| T83 |
502 |
0 |
0 |
0 |
| T130 |
0 |
2 |
0 |
0 |
| T139 |
713 |
0 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
173393610 |
1643682 |
0 |
0 |
| T2 |
2239 |
0 |
0 |
0 |
| T7 |
6154 |
4 |
0 |
0 |
| T8 |
2342 |
0 |
0 |
0 |
| T9 |
943 |
0 |
0 |
0 |
| T10 |
0 |
13 |
0 |
0 |
| T11 |
0 |
84 |
0 |
0 |
| T13 |
0 |
2 |
0 |
0 |
| T14 |
453 |
25 |
0 |
0 |
| T15 |
489 |
0 |
0 |
0 |
| T16 |
487 |
59 |
0 |
0 |
| T17 |
497 |
0 |
0 |
0 |
| T18 |
441 |
0 |
0 |
0 |
| T19 |
428 |
0 |
0 |
0 |
| T23 |
959 |
0 |
0 |
0 |
| T25 |
490 |
0 |
0 |
0 |
| T28 |
832 |
21 |
0 |
0 |
| T29 |
4784 |
18 |
0 |
0 |
| T30 |
0 |
13 |
0 |
0 |
| T31 |
942 |
44 |
0 |
0 |
| T32 |
0 |
2329 |
0 |
0 |
| T35 |
0 |
94 |
0 |
0 |
| T38 |
0 |
107 |
0 |
0 |
| T44 |
0 |
425 |
0 |
0 |
| T48 |
0 |
8 |
0 |
0 |
| T60 |
9078 |
0 |
0 |
0 |
| T64 |
0 |
609 |
0 |
0 |
| T65 |
444 |
0 |
0 |
0 |
| T66 |
0 |
19 |
0 |
0 |
| T67 |
0 |
11 |
0 |
0 |
| T68 |
0 |
6 |
0 |
0 |
| T70 |
0 |
11 |
0 |
0 |
| T71 |
423 |
0 |
0 |
0 |
| T72 |
856 |
0 |
0 |
0 |
| T83 |
502 |
0 |
0 |
0 |
| T130 |
0 |
6 |
0 |
0 |
| T139 |
713 |
0 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
60020865 |
42376 |
0 |
0 |
| T1 |
7398 |
6 |
0 |
0 |
| T2 |
0 |
48 |
0 |
0 |
| T4 |
4617 |
37 |
0 |
0 |
| T5 |
3978 |
3 |
0 |
0 |
| T6 |
3861 |
24 |
0 |
0 |
| T14 |
4077 |
3 |
0 |
0 |
| T15 |
4401 |
66 |
0 |
0 |
| T16 |
4383 |
3 |
0 |
0 |
| T17 |
0 |
65 |
0 |
0 |
| T18 |
0 |
27 |
0 |
0 |
| T21 |
0 |
13 |
0 |
0 |
| T22 |
9360 |
6 |
0 |
0 |
| T26 |
4743 |
52 |
0 |
0 |
| T27 |
0 |
32 |
0 |
0 |
| T36 |
3807 |
20 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
33344925 |
30944740 |
0 |
0 |
| T1 |
4110 |
2110 |
0 |
0 |
| T4 |
2565 |
565 |
0 |
0 |
| T5 |
2210 |
210 |
0 |
0 |
| T6 |
2145 |
145 |
0 |
0 |
| T14 |
2265 |
265 |
0 |
0 |
| T15 |
2445 |
445 |
0 |
0 |
| T16 |
2435 |
435 |
0 |
0 |
| T22 |
5200 |
3200 |
0 |
0 |
| T26 |
2635 |
635 |
0 |
0 |
| T36 |
2115 |
115 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
113372745 |
105212116 |
0 |
0 |
| T1 |
13974 |
7174 |
0 |
0 |
| T4 |
8721 |
1921 |
0 |
0 |
| T5 |
7514 |
714 |
0 |
0 |
| T6 |
7293 |
493 |
0 |
0 |
| T14 |
7701 |
901 |
0 |
0 |
| T15 |
8313 |
1513 |
0 |
0 |
| T16 |
8279 |
1479 |
0 |
0 |
| T22 |
17680 |
10880 |
0 |
0 |
| T26 |
8959 |
2159 |
0 |
0 |
| T36 |
7191 |
391 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
60020865 |
55700532 |
0 |
0 |
| T1 |
7398 |
3798 |
0 |
0 |
| T4 |
4617 |
1017 |
0 |
0 |
| T5 |
3978 |
378 |
0 |
0 |
| T6 |
3861 |
261 |
0 |
0 |
| T14 |
4077 |
477 |
0 |
0 |
| T15 |
4401 |
801 |
0 |
0 |
| T16 |
4383 |
783 |
0 |
0 |
| T22 |
9360 |
5760 |
0 |
0 |
| T26 |
4743 |
1143 |
0 |
0 |
| T36 |
3807 |
207 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
153386655 |
4510 |
0 |
0 |
| T7 |
6154 |
2 |
0 |
0 |
| T8 |
2342 |
0 |
0 |
0 |
| T9 |
943 |
0 |
0 |
0 |
| T10 |
0 |
2 |
0 |
0 |
| T11 |
0 |
1 |
0 |
0 |
| T13 |
0 |
1 |
0 |
0 |
| T23 |
959 |
0 |
0 |
0 |
| T24 |
1142 |
0 |
0 |
0 |
| T25 |
490 |
0 |
0 |
0 |
| T28 |
832 |
3 |
0 |
0 |
| T29 |
4784 |
3 |
0 |
0 |
| T30 |
0 |
2 |
0 |
0 |
| T31 |
942 |
0 |
0 |
0 |
| T32 |
14266 |
11 |
0 |
0 |
| T34 |
0 |
3 |
0 |
0 |
| T35 |
0 |
8 |
0 |
0 |
| T38 |
0 |
1 |
0 |
0 |
| T42 |
0 |
2 |
0 |
0 |
| T44 |
0 |
5 |
0 |
0 |
| T48 |
0 |
3 |
0 |
0 |
| T58 |
1031 |
0 |
0 |
0 |
| T60 |
9078 |
0 |
0 |
0 |
| T65 |
444 |
0 |
0 |
0 |
| T66 |
775 |
2 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T68 |
0 |
1 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
1 |
0 |
0 |
| T71 |
423 |
0 |
0 |
0 |
| T72 |
856 |
0 |
0 |
0 |
| T83 |
502 |
0 |
0 |
0 |
| T87 |
527 |
0 |
0 |
0 |
| T88 |
502 |
0 |
0 |
0 |
| T93 |
502 |
0 |
0 |
0 |
| T102 |
0 |
1 |
0 |
0 |
| T130 |
0 |
2 |
0 |
0 |
| T139 |
713 |
0 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
20006955 |
1525124 |
0 |
0 |
| T2 |
4478 |
465 |
0 |
0 |
| T3 |
3105 |
179 |
0 |
0 |
| T7 |
3077 |
0 |
0 |
0 |
| T8 |
1171 |
0 |
0 |
0 |
| T19 |
856 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T21 |
844 |
0 |
0 |
0 |
| T24 |
0 |
532 |
0 |
0 |
| T25 |
490 |
0 |
0 |
0 |
| T27 |
1044 |
0 |
0 |
0 |
| T28 |
2496 |
0 |
0 |
0 |
| T29 |
2392 |
0 |
0 |
0 |
| T31 |
471 |
0 |
0 |
0 |
| T56 |
1215 |
0 |
0 |
0 |
| T62 |
1004 |
0 |
0 |
0 |
| T63 |
1302 |
0 |
0 |
0 |
| T65 |
444 |
0 |
0 |
0 |
| T71 |
423 |
0 |
0 |
0 |
| T73 |
0 |
102 |
0 |
0 |
| T74 |
0 |
1190 |
0 |
0 |
| T99 |
0 |
702 |
0 |
0 |
| T100 |
0 |
129 |
0 |
0 |
| T101 |
0 |
658 |
0 |
0 |
| T103 |
0 |
83 |
0 |
0 |
| T105 |
0 |
85 |
0 |
0 |
| T106 |
0 |
266 |
0 |
0 |
| T107 |
0 |
316 |
0 |
0 |
| T115 |
0 |
494925 |
0 |
0 |
| T140 |
0 |
798 |
0 |
0 |
