Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.69	91.30	90.48		83.33	90.00	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.77	91.30	90.48		83.33	90.00	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.18	95.65	95.24		100.00	95.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T44 T46 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T44 T46 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T44 T46 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T44 T46 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T44 T46 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T44 T46 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T44 T46 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T44 T46 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T44 T46 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T195 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T44 T46 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T44 T46 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T44 T46 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T44 T46 
191        1/1                      state_d = StableSt;
           Tests:       T1 T44 T46 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T44 T46 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T44 T46 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T44 T46 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T44 T46 
206        1/1                    state_d = IdleSt;
           Tests:       T44 T46 T48 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T44 T46 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T44,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T44,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T44,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T44
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T44,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T44,T46
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T44,T46
0	1	Covered	T46,T48,T171
1	0	Covered	T44,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T44,T46
1	-	Covered	T46,T48,T171

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T44,T46
DetectSt	168	Covered	T1,T44,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T44,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T44,T46
DebounceSt->IdleSt	163	Covered	T195
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T44,T46
IdleSt->DebounceSt	148	Covered	T1,T44,T46
StableSt->IdleSt	206	Covered	T44,T46,T48

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T44,T46
0	1	Covered	T1,T44,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T44,T46
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T44,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T44,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T195
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T44,T46
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T44,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T44,T46,T48
StableSt	-	-	-	-	-	-	0	Covered	T1,T44,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	55	0	0
CntIncr_A	6668985	1365	0	0
CntNoWrap_A	6668985	6186953	0	0
DetectStDropOut_A	6668985	0	0	0
DetectedOut_A	6668985	1663	0	0
DetectedPulseOut_A	6668985	27	0	0
DisabledIdleSt_A	6668985	6176372	0	0
DisabledNoDetection_A	6668985	6178279	0	0
EnterDebounceSt_A	6668985	28	0	0
EnterDetectSt_A	6668985	27	0	0
EnterStableSt_A	6668985	27	0	0
PulseIsPulse_A	6668985	27	0	0
StayInStableSt	6668985	1623	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	12	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	55	0	0
T1	822	2	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	2	0	0
T46	0	2	0	0
T48	0	4	0	0
T64	0	2	0	0
T105	0	4	0	0
T112	0	4	0	0
T116	0	2	0	0
T171	0	2	0	0
T196	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1365	0	0
T1	822	83	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	15	0	0
T46	0	38	0	0
T48	0	58	0	0
T64	0	22	0	0
T105	0	90	0	0
T112	0	48	0	0
T116	0	87	0	0
T171	0	63	0	0
T196	0	32	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186953	0	0
T1	822	419	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1663	0	0
T1	822	240	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	23	0	0
T46	0	157	0	0
T48	0	61	0	0
T64	0	23	0	0
T105	0	181	0	0
T112	0	19	0	0
T116	0	41	0	0
T171	0	7	0	0
T196	0	106	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	27	0	0
T1	822	1	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T64	0	1	0	0
T105	0	2	0	0
T112	0	2	0	0
T116	0	1	0	0
T171	0	1	0	0
T196	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6176372	0	0
T1	822	3	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6178279	0	0
T1	822	3	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	28	0	0
T1	822	1	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T64	0	1	0	0
T105	0	2	0	0
T112	0	2	0	0
T116	0	1	0	0
T171	0	1	0	0
T196	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	27	0	0
T1	822	1	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T64	0	1	0	0
T105	0	2	0	0
T112	0	2	0	0
T116	0	1	0	0
T171	0	1	0	0
T196	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	27	0	0
T1	822	1	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T64	0	1	0	0
T105	0	2	0	0
T112	0	2	0	0
T116	0	1	0	0
T171	0	1	0	0
T196	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	27	0	0
T1	822	1	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T46	0	1	0	0
T48	0	2	0	0
T64	0	1	0	0
T105	0	2	0	0
T112	0	2	0	0
T116	0	1	0	0
T171	0	1	0	0
T196	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1623	0	0
T1	822	238	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	22	0	0
T46	0	156	0	0
T48	0	58	0	0
T64	0	22	0	0
T105	0	178	0	0
T112	0	17	0	0
T116	0	39	0	0
T171	0	6	0	0
T196	0	105	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	12	0	0
T38	30851	0	0	0
T46	808	1	0	0
T48	0	1	0	0
T54	4402	0	0	0
T69	664	0	0	0
T81	499	0	0	0
T105	0	1	0	0
T112	0	2	0	0
T155	424	0	0	0
T156	402	0	0	0
T167	0	2	0	0
T168	0	1	0	0
T171	0	1	0	0
T184	0	1	0	0
T187	0	1	0	0
T196	0	1	0	0
T197	419	0	0	0
T198	524	0	0	0
T199	794	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T12 T50 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T12 T50 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T12 T50 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T12 T50 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T12 T50 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T12 T50 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T12 T50 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T12 T50 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T12 T50 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T116 T102 T105 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T12 T50 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T12 T50 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T12 T50 
186        1/1                    state_d = IdleSt;
           Tests:       T102 T200 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T102 T200 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T12 T50 
191        1/1                      state_d = StableSt;
           Tests:       T8 T12 T50 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T12 T50 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T12 T50 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T12 T50 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T12 T50 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T50 T44 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T12 T50 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T12,T50

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T12,T50

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T12,T50

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T12,T50
1	0	Covered	T4,T6,T26
1	1	Covered	T8,T12,T50

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T12,T50
0	1	Covered	T102,T200
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T12,T50
0	1	Covered	T8,T50,T51
1	0	Covered	T44,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T12,T50
1	-	Covered	T8,T50,T51

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T12,T50
DetectSt	168	Covered	T8,T12,T50
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T12,T50

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T12,T50
DebounceSt->IdleSt	163	Covered	T116,T102,T105
DetectSt->IdleSt	186	Covered	T102,T200
DetectSt->StableSt	191	Covered	T8,T12,T50
IdleSt->DebounceSt	148	Covered	T8,T12,T50
StableSt->IdleSt	206	Covered	T8,T50,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T12,T50
0	1	Covered	T8,T12,T50
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T12,T50
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T12,T50
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T12,T50
DebounceSt	-	0	1	0	-	-	-	Covered	T116,T102,T105
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T12,T50
DetectSt	-	-	-	-	1	-	-	Covered	T102,T200
DetectSt	-	-	-	-	0	1	-	Covered	T8,T12,T50
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T50,T44
StableSt	-	-	-	-	-	-	0	Covered	T8,T12,T50
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	102	0	0
CntIncr_A	6668985	31888	0	0
CntNoWrap_A	6668985	6186906	0	0
DetectStDropOut_A	6668985	2	0	0
DetectedOut_A	6668985	71576	0	0
DetectedPulseOut_A	6668985	46	0	0
DisabledIdleSt_A	6668985	6034109	0	0
DisabledNoDetection_A	6668985	6036012	0	0
EnterDebounceSt_A	6668985	54	0	0
EnterDetectSt_A	6668985	48	0	0
EnterStableSt_A	6668985	46	0	0
PulseIsPulse_A	6668985	46	0	0
StayInStableSt	6668985	71513	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6668985	1939	0	0
gen_low_level_sva.LowLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	102	0	0
T8	1171	6	0	0
T9	943	0	0	0
T10	12010	0	0	0
T12	0	2	0	0
T23	959	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T50	0	2	0	0
T51	0	4	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	2	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	3	0	0
T104	0	2	0	0
T116	0	1	0	0
T139	713	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	31888	0	0
T8	1171	240	0	0
T9	943	0	0	0
T10	12010	0	0	0
T12	0	16	0	0
T23	959	0	0	0
T44	0	15	0	0
T45	0	89	0	0
T50	0	97	0	0
T51	0	198	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	22	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	88	0	0
T104	0	11364	0	0
T116	0	87	0	0
T139	713	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186906	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	2	0	0
T40	14964	0	0	0
T59	946	0	0	0
T102	8582	1	0	0
T109	12673	0	0	0
T200	0	1	0	0
T201	527	0	0	0
T202	634	0	0	0
T203	633	0	0	0
T204	405	0	0	0
T205	427	0	0	0
T206	505	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	71576	0	0
T8	1171	156	0	0
T9	943	0	0	0
T10	12010	0	0	0
T12	0	44	0	0
T23	959	0	0	0
T44	0	24	0	0
T45	0	431	0	0
T50	0	65	0	0
T51	0	81	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	23	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	44789	0	0
T105	0	55	0	0
T112	0	124	0	0
T139	713	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	46	0	0
T8	1171	3	0	0
T9	943	0	0	0
T10	12010	0	0	0
T12	0	1	0	0
T23	959	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	1	0	0
T105	0	1	0	0
T112	0	3	0	0
T139	713	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6034109	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6036012	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	54	0	0
T8	1171	3	0	0
T9	943	0	0	0
T10	12010	0	0	0
T12	0	1	0	0
T23	959	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	2	0	0
T104	0	1	0	0
T116	0	1	0	0
T139	713	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	48	0	0
T8	1171	3	0	0
T9	943	0	0	0
T10	12010	0	0	0
T12	0	1	0	0
T23	959	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T139	713	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	46	0	0
T8	1171	3	0	0
T9	943	0	0	0
T10	12010	0	0	0
T12	0	1	0	0
T23	959	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	1	0	0
T105	0	1	0	0
T112	0	3	0	0
T139	713	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	46	0	0
T8	1171	3	0	0
T9	943	0	0	0
T10	12010	0	0	0
T12	0	1	0	0
T23	959	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T50	0	1	0	0
T51	0	2	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	1	0	0
T105	0	1	0	0
T112	0	3	0	0
T139	713	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	71513	0	0
T8	1171	152	0	0
T9	943	0	0	0
T10	12010	0	0	0
T12	0	42	0	0
T23	959	0	0	0
T44	0	23	0	0
T45	0	429	0	0
T50	0	64	0	0
T51	0	78	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	22	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	44788	0	0
T105	0	53	0	0
T112	0	120	0	0
T139	713	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1939	0	0
T1	822	1	0	0
T4	513	4	0	0
T5	442	0	0	0
T6	429	2	0	0
T14	453	0	0	0
T15	489	4	0	0
T16	487	0	0	0
T17	0	4	0	0
T18	0	6	0	0
T21	0	2	0	0
T22	1040	6	0	0
T26	527	5	0	0
T36	423	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	27	0	0
T8	1171	2	0	0
T9	943	0	0	0
T10	12010	0	0	0
T23	959	0	0	0
T50	0	1	0	0
T51	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	1	0	0
T112	0	2	0	0
T139	713	0	0	0
T167	0	1	0	0
T185	0	1	0	0
T207	0	1	0	0
T208	0	1	0	0
T209	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T6 T26 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T6 T26 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T8 T9 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T6 T26 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T6 T26 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T6 T26 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T6 T26 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T6 T26 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T6 T26 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T6 T26 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T6 T26 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T8 T9 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T8 T9 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T8 T9 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T8 T9 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T8 T9 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T8 T9 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T8 T9 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T8 T9 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T47 T210 T211 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T8 T9 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T8 T9 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T8 T9 
186        1/1                    state_d = IdleSt;
           Tests:       T185 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T185 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T8 T9 
191        1/1                      state_d = StableSt;
           Tests:       T1 T8 T9 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T8 T9 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T8 T9 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T8 T9 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T8 T9 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T9 T12 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T8 T9 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T6,T26

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T6,T26
1	1	Covered	T4,T6,T26

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T9

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T8,T9

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T8,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T4,T6,T26
1	1	Covered	T1,T8,T9

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T185
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T8,T9
0	1	Covered	T8,T9,T12
1	0	Covered	T44,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T8,T9
1	-	Covered	T8,T9,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T8,T9
DetectSt	168	Covered	T1,T8,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T8,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T8,T9
DebounceSt->IdleSt	163	Covered	T47,T210,T211
DetectSt->IdleSt	186	Covered	T185
DetectSt->StableSt	191	Covered	T1,T8,T9
IdleSt->DebounceSt	148	Covered	T1,T8,T9
StableSt->IdleSt	206	Covered	T8,T9,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T8,T9
0	1	Covered	T1,T8,T9
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T8,T9
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T8,T9
IdleSt	0	-	-	-	-	-	-	Covered	T4,T6,T26
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T8,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T47,T210,T211
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	1	-	-	Covered	T185
DetectSt	-	-	-	-	0	1	-	Covered	T1,T8,T9
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T12
StableSt	-	-	-	-	-	-	0	Covered	T1,T8,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	97	0	0
CntIncr_A	6668985	71346	0	0
CntNoWrap_A	6668985	6186911	0	0
DetectStDropOut_A	6668985	1	0	0
DetectedOut_A	6668985	146423	0	0
DetectedPulseOut_A	6668985	45	0	0
DisabledIdleSt_A	6668985	5871921	0	0
DisabledNoDetection_A	6668985	5873822	0	0
EnterDebounceSt_A	6668985	52	0	0
EnterDetectSt_A	6668985	46	0	0
EnterStableSt_A	6668985	45	0	0
PulseIsPulse_A	6668985	45	0	0
StayInStableSt	6668985	146355	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	97	0	0
T1	822	2	0	0
T2	2239	0	0	0
T8	0	2	0	0
T9	0	4	0	0
T12	0	2	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	2	0	0
T47	0	1	0	0
T51	0	4	0	0
T64	0	2	0	0
T102	0	4	0	0
T171	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	71346	0	0
T1	822	83	0	0
T2	2239	0	0	0
T8	0	80	0	0
T9	0	100	0	0
T12	0	16	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	15	0	0
T47	0	96	0	0
T51	0	198	0	0
T64	0	22	0	0
T102	0	88	0	0
T171	0	126	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186911	0	0
T1	822	419	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1	0	0
T142	1719	0	0	0
T185	994	1	0	0
T186	235340	0	0	0
T188	432	0	0	0
T189	508	0	0	0
T190	426	0	0	0
T191	526	0	0	0
T192	439	0	0	0
T193	726	0	0	0
T194	1745	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	146423	0	0
T1	822	240	0	0
T2	2239	0	0	0
T8	0	318	0	0
T9	0	333	0	0
T12	0	9	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	23	0	0
T51	0	141	0	0
T64	0	22	0	0
T102	0	130	0	0
T104	0	22815	0	0
T171	0	211	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	45	0	0
T1	822	1	0	0
T2	2239	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	0	1	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T51	0	2	0	0
T64	0	1	0	0
T102	0	2	0	0
T104	0	1	0	0
T171	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5871921	0	0
T1	822	3	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5873822	0	0
T1	822	3	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	52	0	0
T1	822	1	0	0
T2	2239	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	0	1	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T47	0	1	0	0
T51	0	2	0	0
T64	0	1	0	0
T102	0	2	0	0
T171	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	46	0	0
T1	822	1	0	0
T2	2239	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	0	1	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T51	0	2	0	0
T64	0	1	0	0
T102	0	2	0	0
T104	0	1	0	0
T171	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	45	0	0
T1	822	1	0	0
T2	2239	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	0	1	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T51	0	2	0	0
T64	0	1	0	0
T102	0	2	0	0
T104	0	1	0	0
T171	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	45	0	0
T1	822	1	0	0
T2	2239	0	0	0
T8	0	1	0	0
T9	0	2	0	0
T12	0	1	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T51	0	2	0	0
T64	0	1	0	0
T102	0	2	0	0
T104	0	1	0	0
T171	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	146355	0	0
T1	822	238	0	0
T2	2239	0	0	0
T8	0	317	0	0
T9	0	330	0	0
T12	0	8	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	22	0	0
T51	0	138	0	0
T64	0	21	0	0
T102	0	127	0	0
T104	0	22814	0	0
T171	0	208	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	20	0	0
T8	1171	1	0	0
T9	943	1	0	0
T10	12010	0	0	0
T12	0	1	0	0
T23	959	0	0	0
T51	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T112	0	1	0	0
T139	713	0	0	0
T159	0	1	0	0
T171	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T6 T26 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T9 T12 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T9 T12 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T9 T12 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T12 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T9 T12 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T9 T12 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T9 T12 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T9 T12 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T9 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T212 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T9 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T9 T12 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T9 T12 
191        1/1                      state_d = StableSt;
           Tests:       T8 T9 T12 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T9 T12 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T9 T12 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T9 T12 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T9 T12 
206        1/1                    state_d = IdleSt;
           Tests:       T9 T44 T64 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T9 T12 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	19	90.48
Logical	21	19	90.48
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T6,T26
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T6,T26
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T12

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T8,T9
1	0	Covered	T4,T6,T26
1	1	Covered	T8,T9,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T12
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T12
0	1	Covered	T9,T102,T159
1	0	Covered	T44,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T12
1	-	Covered	T9,T102,T159

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T12
DetectSt	168	Covered	T8,T9,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T9,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T12
DebounceSt->IdleSt	163	Covered	T212
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T8,T9,T12
IdleSt->DebounceSt	148	Covered	T8,T9,T12
StableSt->IdleSt	206	Covered	T9,T44,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	18	90.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T12
0	1	Covered	T8,T9,T12
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T12
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T12
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T212
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T12
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T44,T64
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	63	0	0
CntIncr_A	6668985	12787	0	0
CntNoWrap_A	6668985	6186945	0	0
DetectStDropOut_A	6668985	0	0	0
DetectedOut_A	6668985	5266	0	0
DetectedPulseOut_A	6668985	31	0	0
DisabledIdleSt_A	6668985	6105904	0	0
DisabledNoDetection_A	6668985	6107807	0	0
EnterDebounceSt_A	6668985	32	0	0
EnterDetectSt_A	6668985	31	0	0
EnterStableSt_A	6668985	31	0	0
PulseIsPulse_A	6668985	31	0	0
StayInStableSt	6668985	5222	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6668985	5574	0	0
gen_low_level_sva.LowLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	16	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	63	0	0
T8	1171	2	0	0
T9	943	2	0	0
T10	12010	0	0	0
T12	0	2	0	0
T23	959	0	0	0
T44	0	2	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	2	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	2	0	0
T104	0	2	0	0
T105	0	2	0	0
T139	713	0	0	0
T159	0	2	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	12787	0	0
T8	1171	80	0	0
T9	943	50	0	0
T10	12010	0	0	0
T12	0	16	0	0
T23	959	0	0	0
T44	0	15	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	22	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	44	0	0
T104	0	11364	0	0
T105	0	40	0	0
T139	713	0	0	0
T159	0	71	0	0
T170	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186945	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5266	0	0
T8	1171	282	0	0
T9	943	49	0	0
T10	12010	0	0	0
T12	0	44	0	0
T23	959	0	0	0
T44	0	23	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	23	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	130	0	0
T104	0	2918	0	0
T105	0	42	0	0
T139	713	0	0	0
T159	0	317	0	0
T170	0	38	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	31	0	0
T8	1171	1	0	0
T9	943	1	0	0
T10	12010	0	0	0
T12	0	1	0	0
T23	959	0	0	0
T44	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T139	713	0	0	0
T159	0	1	0	0
T170	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6105904	0	0
T1	822	3	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6107807	0	0
T1	822	3	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	32	0	0
T8	1171	1	0	0
T9	943	1	0	0
T10	12010	0	0	0
T12	0	1	0	0
T23	959	0	0	0
T44	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T139	713	0	0	0
T159	0	1	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	31	0	0
T8	1171	1	0	0
T9	943	1	0	0
T10	12010	0	0	0
T12	0	1	0	0
T23	959	0	0	0
T44	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T139	713	0	0	0
T159	0	1	0	0
T170	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	31	0	0
T8	1171	1	0	0
T9	943	1	0	0
T10	12010	0	0	0
T12	0	1	0	0
T23	959	0	0	0
T44	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T139	713	0	0	0
T159	0	1	0	0
T170	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	31	0	0
T8	1171	1	0	0
T9	943	1	0	0
T10	12010	0	0	0
T12	0	1	0	0
T23	959	0	0	0
T44	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	1	0	0
T104	0	1	0	0
T105	0	1	0	0
T139	713	0	0	0
T159	0	1	0	0
T170	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5222	0	0
T8	1171	280	0	0
T9	943	48	0	0
T10	12010	0	0	0
T12	0	42	0	0
T23	959	0	0	0
T44	0	22	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	22	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T102	0	129	0	0
T104	0	2916	0	0
T105	0	41	0	0
T139	713	0	0	0
T159	0	316	0	0
T170	0	36	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5574	0	0
T1	822	0	0	0
T2	0	12	0	0
T4	513	5	0	0
T5	442	0	0	0
T6	429	1	0	0
T14	453	0	0	0
T15	489	7	0	0
T16	487	0	0	0
T17	0	8	0	0
T18	0	3	0	0
T21	0	2	0	0
T22	1040	0	0	0
T26	527	7	0	0
T27	0	5	0	0
T36	423	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	16	0	0
T9	943	1	0	0
T10	12010	0	0	0
T11	510	0	0	0
T57	408	0	0	0
T61	743	0	0	0
T78	495	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T96	421	0	0	0
T97	430	0	0	0
T102	0	1	0	0
T105	0	1	0	0
T159	0	1	0	0
T185	0	1	0	0
T195	0	1	0	0
T208	0	1	0	0
T211	0	2	0	0
T213	0	1	0	0
T214	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T9 T44 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T9 T44 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T9 T44 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T44 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T9 T44 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T9 T44 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T9 T44 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T9 T44 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T9 T44 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T116 T104 T215 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T9 T44 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T44 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T9 T44 
186        1/1                    state_d = IdleSt;
           Tests:       T112 T216 T215 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T112 T216 T215 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T9 T44 
191        1/1                      state_d = StableSt;
           Tests:       T8 T9 T44 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T9 T44 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T9 T44 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T9 T44 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T9 T44 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T9 T44 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T9 T44 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T8,T9,T44

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T50
1	0	Covered	T4,T5,T6
1	1	Covered	T8,T9,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T44
0	1	Covered	T112,T216,T215
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T44
0	1	Covered	T8,T9,T46
1	0	Covered	T44,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T8,T9,T44
1	-	Covered	T8,T9,T46

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T44
DetectSt	168	Covered	T8,T9,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T9,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T44
DebounceSt->IdleSt	163	Covered	T116,T104,T215
DetectSt->IdleSt	186	Covered	T112,T216,T215
DetectSt->StableSt	191	Covered	T8,T9,T44
IdleSt->DebounceSt	148	Covered	T8,T9,T44
StableSt->IdleSt	206	Covered	T8,T9,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T8,T9,T44
0	1	Covered	T8,T9,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T44
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T116,T104,T215
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T44
DetectSt	-	-	-	-	1	-	-	Covered	T112,T216,T215
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T44
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T44
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	104	0	0
CntIncr_A	6668985	82940	0	0
CntNoWrap_A	6668985	6186904	0	0
DetectStDropOut_A	6668985	3	0	0
DetectedOut_A	6668985	34428	0	0
DetectedPulseOut_A	6668985	47	0	0
DisabledIdleSt_A	6668985	5871004	0	0
DisabledNoDetection_A	6668985	5872906	0	0
EnterDebounceSt_A	6668985	54	0	0
EnterDetectSt_A	6668985	50	0	0
EnterStableSt_A	6668985	47	0	0
PulseIsPulse_A	6668985	47	0	0
StayInStableSt	6668985	34363	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	27	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	104	0	0
T8	1171	4	0	0
T9	943	2	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	2	0	0
T46	0	4	0	0
T48	0	2	0	0
T49	0	4	0	0
T51	0	2	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	2	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T116	0	1	0	0
T139	713	0	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	82940	0	0
T8	1171	160	0	0
T9	943	50	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	15	0	0
T46	0	76	0	0
T48	0	16	0	0
T49	0	188	0	0
T51	0	99	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	22	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T116	0	87	0	0
T139	713	0	0	0
T170	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186904	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	3	0	0
T112	706	1	0	0
T215	0	1	0	0
T216	0	1	0	0
T217	1964	0	0	0
T218	29652	0	0	0
T219	25039	0	0	0
T220	446	0	0	0
T221	505	0	0	0
T222	523	0	0	0
T223	489	0	0	0
T224	184808	0	0	0
T225	728	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	34428	0	0
T8	1171	334	0	0
T9	943	44	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	22	0	0
T46	0	78	0	0
T48	0	52	0	0
T49	0	122	0	0
T51	0	70	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	22	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	30509	0	0
T139	713	0	0	0
T170	0	255	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	47	0	0
T8	1171	2	0	0
T9	943	1	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	1	0	0
T139	713	0	0	0
T170	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5871004	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5872906	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	54	0	0
T8	1171	2	0	0
T9	943	1	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T116	0	1	0	0
T139	713	0	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	50	0	0
T8	1171	2	0	0
T9	943	1	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	1	0	0
T139	713	0	0	0
T170	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	47	0	0
T8	1171	2	0	0
T9	943	1	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	1	0	0
T139	713	0	0	0
T170	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	47	0	0
T8	1171	2	0	0
T9	943	1	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	1	0	0
T46	0	2	0	0
T48	0	1	0	0
T49	0	2	0	0
T51	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	1	0	0
T139	713	0	0	0
T170	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	34363	0	0
T8	1171	331	0	0
T9	943	43	0	0
T10	12010	0	0	0
T23	959	0	0	0
T44	0	21	0	0
T46	0	75	0	0
T48	0	50	0	0
T49	0	119	0	0
T51	0	69	0	0
T57	408	0	0	0
T60	4539	0	0	0
T64	0	21	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	30508	0	0
T139	713	0	0	0
T170	0	254	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	27	0	0
T8	1171	1	0	0
T9	943	1	0	0
T10	12010	0	0	0
T23	959	0	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T57	408	0	0	0
T60	4539	0	0	0
T72	428	0	0	0
T83	502	0	0	0
T84	522	0	0	0
T104	0	1	0	0
T139	713	0	0	0
T159	0	2	0	0
T170	0	1	0	0
T182	0	2	0	0
T196	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T44 T46 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T44 T46 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T44 T46 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T44 T46 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T44 T46 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T44 T46 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T44 T46 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T44 T46 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T44 T46 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T159 T226 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T44 T46 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T44 T46 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T44 T46 
186        1/1                    state_d = IdleSt;
           Tests:       T105 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T105 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T44 T46 
191        1/1                      state_d = StableSt;
           Tests:       T1 T44 T46 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T44 T46 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T44 T46 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T44 T46 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T44 T46 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T44 T46 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T44 T46 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T44,T46

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T1,T44,T46

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T44,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T12,T50
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T44,T46

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T44,T46
0	1	Covered	T105
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T44,T46
0	1	Covered	T1,T46,T49
1	0	Covered	T44,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T44,T46
1	-	Covered	T1,T46,T49

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T44,T46
DetectSt	168	Covered	T1,T44,T46
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T44,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T44,T46
DebounceSt->IdleSt	163	Covered	T159,T226
DetectSt->IdleSt	186	Covered	T105
DetectSt->StableSt	191	Covered	T1,T44,T46
IdleSt->DebounceSt	148	Covered	T1,T44,T46
StableSt->IdleSt	206	Covered	T1,T44,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		20	19	95.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T1,T44,T46
0	1	Covered	T1,T44,T46
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T44,T46
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T44,T46
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T44,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T159,T226
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T44,T46
DetectSt	-	-	-	-	1	-	-	Covered	T105
DetectSt	-	-	-	-	0	1	-	Covered	T1,T44,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T44,T46
StableSt	-	-	-	-	-	-	0	Covered	T1,T44,T46
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	72	0	0
CntIncr_A	6668985	81936	0	0
CntNoWrap_A	6668985	6186936	0	0
DetectStDropOut_A	6668985	1	0	0
DetectedOut_A	6668985	59511	0	0
DetectedPulseOut_A	6668985	34	0	0
DisabledIdleSt_A	6668985	5871700	0	0
DisabledNoDetection_A	6668985	5873600	0	0
EnterDebounceSt_A	6668985	37	0	0
EnterDetectSt_A	6668985	35	0	0
EnterStableSt_A	6668985	34	0	0
PulseIsPulse_A	6668985	34	0	0
StayInStableSt	6668985	59460	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	6668985	5256	0	0
gen_low_level_sva.LowLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	15	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	72	0	0
T1	822	4	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T49	0	2	0	0
T51	0	2	0	0
T64	0	2	0	0
T104	0	4	0	0
T159	0	3	0	0
T170	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	81936	0	0
T1	822	166	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	15	0	0
T45	0	89	0	0
T46	0	38	0	0
T49	0	94	0	0
T51	0	99	0	0
T64	0	22	0	0
T104	0	22728	0	0
T159	0	142	0	0
T170	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186936	0	0
T1	822	417	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1	0	0
T105	13512	1	0	0
T112	706	0	0	0
T151	427	0	0	0
T217	1964	0	0	0
T218	29652	0	0	0
T219	25039	0	0	0
T220	446	0	0	0
T221	505	0	0	0
T222	523	0	0	0
T223	489	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	59511	0	0
T1	822	83	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	22	0	0
T45	0	41	0	0
T46	0	157	0	0
T49	0	42	0	0
T51	0	42	0	0
T64	0	23	0	0
T104	0	86	0	0
T159	0	43	0	0
T170	0	39	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	34	0	0
T1	822	2	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T64	0	1	0	0
T104	0	2	0	0
T159	0	1	0	0
T170	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5871700	0	0
T1	822	3	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5873600	0	0
T1	822	3	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	37	0	0
T1	822	2	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T64	0	1	0	0
T104	0	2	0	0
T159	0	2	0	0
T170	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	35	0	0
T1	822	2	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T64	0	1	0	0
T104	0	2	0	0
T159	0	1	0	0
T170	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	34	0	0
T1	822	2	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T64	0	1	0	0
T104	0	2	0	0
T159	0	1	0	0
T170	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	34	0	0
T1	822	2	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T51	0	1	0	0
T64	0	1	0	0
T104	0	2	0	0
T159	0	1	0	0
T170	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	59460	0	0
T1	822	80	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T44	0	21	0	0
T45	0	40	0	0
T46	0	156	0	0
T49	0	41	0	0
T51	0	40	0	0
T64	0	22	0	0
T104	0	83	0	0
T159	0	42	0	0
T170	0	37	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5256	0	0
T1	822	2	0	0
T4	513	2	0	0
T5	442	1	0	0
T6	429	1	0	0
T14	453	1	0	0
T15	489	8	0	0
T16	487	1	0	0
T17	0	12	0	0
T22	1040	0	0	0
T26	527	4	0	0
T36	423	2	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	15	0	0
T1	822	1	0	0
T2	2239	0	0	0
T14	453	0	0	0
T15	489	0	0	0
T16	487	0	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T49	0	1	0	0
T104	0	1	0	0
T159	0	1	0	0
T168	0	1	0	0
T183	0	1	0	0
T209	0	1	0	0
T216	0	1	0	0