Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	95.24		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T32 T33 T34 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T32 T33 T34 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T14 T16 T31 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T14 T16 T31 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T14 T16 T31 
129        1/1              cnt_en = 1'b0;
           Tests:       T14 T16 T31 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T14 T16 T31 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T14 T16 T31 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T14 T16 T31 
139                     
140        1/1              unique case (state_q)
           Tests:       T14 T16 T31 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T14 T16 T31 
148        1/1                    state_d = DebounceSt;
           Tests:       T14 T16 T31 
149        1/1                    cnt_en = 1'b1;
           Tests:       T14 T16 T31 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T14 T16 T31 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T14 T16 T31 
163        1/1                    state_d = IdleSt;
           Tests:       T44 T64 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 
165        1/1                  end else if (cnt_done) begin
           Tests:       T14 T16 T31 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T14 T16 T31 
167        1/1                    if (trigger_active) begin
           Tests:       T14 T16 T31 
168        1/1                      state_d = DetectSt;
           Tests:       T14 T16 T31 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T44 T64 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T14 T16 T31 
182        1/1                  cnt_en = 1'b1;
           Tests:       T14 T16 T31 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T14 T16 T31 
186        1/1                    state_d = IdleSt;
           Tests:       T33 T44 T41 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T33 T44 T41 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T14 T16 T31 
191        1/1                      state_d = StableSt;
           Tests:       T14 T16 T31 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T14 T16 T31 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T14 T16 T31 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T14 T16 T31 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T14 T16 T31 
206        1/1                    state_d = IdleSt;
           Tests:       T32 T34 T44 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T14 T16 T31 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T32,T33,T34
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T16,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T16,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T14,T16,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T44
1	1	Covered	T14,T16,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T31
0	1	Covered	T33,T44,T41
1	0	Covered	T33,T44,T41

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T14,T16,T31
0	1	Covered	T32,T34,T44
1	0	Covered	T41,T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T14,T16,T31
1	-	Covered	T32,T34,T44

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T14,T16,T31
DetectSt	168	Covered	T14,T16,T31
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T14,T16,T31

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T14,T16,T31
DebounceSt->IdleSt	163	Covered	T34,T44,T64
DetectSt->IdleSt	186	Covered	T33,T44,T41
DetectSt->StableSt	191	Covered	T14,T16,T31
IdleSt->DebounceSt	148	Covered	T14,T16,T31
StableSt->IdleSt	206	Covered	T32,T34,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T14,T16,T31
0	1	Covered	T14,T16,T31
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T14,T16,T31
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T14,T16,T31
IdleSt	0	-	-	-	-	-	-	Covered	T32,T33,T34
DebounceSt	-	1	-	-	-	-	-	Covered	T44,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T14,T16,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T44,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T14,T16,T31
DetectSt	-	-	-	-	1	-	-	Covered	T33,T44,T41
DetectSt	-	-	-	-	0	1	-	Covered	T14,T16,T31
DetectSt	-	-	-	-	0	0	-	Covered	T14,T16,T31
StableSt	-	-	-	-	-	-	1	Covered	T32,T34,T44
StableSt	-	-	-	-	-	-	0	Covered	T14,T16,T31
default	-	-	-	-	-	-	-	Not Covered

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	3130	0	0
CntIncr_A	6668985	116304	0	0
CntNoWrap_A	6668985	6183878	0	0
DetectStDropOut_A	6668985	489	0	0
DetectedOut_A	6668985	86403	0	0
DetectedPulseOut_A	6668985	867	0	0
DisabledIdleSt_A	6668985	5697202	0	0
DisabledNoDetection_A	6668985	5698930	0	0
EnterDebounceSt_A	6668985	1605	0	0
EnterDetectSt_A	6668985	1528	0	0
EnterStableSt_A	6668985	867	0	0
PulseIsPulse_A	6668985	867	0	0
StayInStableSt	6668985	85418	0	0
gen_high_event_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	742	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	3130	0	0
T2	2239	0	0	0
T11	0	2	0	0
T14	453	2	0	0
T15	489	0	0	0
T16	487	2	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T31	0	2	0	0
T32	0	22	0	0
T33	0	8	0	0
T34	0	22	0	0
T41	0	54	0	0
T44	0	16	0	0
T89	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	116304	0	0
T2	2239	0	0	0
T11	0	21	0	0
T14	453	21	0	0
T15	489	0	0	0
T16	487	21	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T31	0	21	0	0
T32	0	693	0	0
T33	0	231	0	0
T34	0	1030	0	0
T41	0	1602	0	0
T44	0	576	0	0
T89	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6183878	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	50	0	0
T15	489	88	0	0
T16	487	84	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	489	0	0
T33	9264	2	0	0
T34	4765	0	0	0
T39	0	17	0	0
T41	0	11	0	0
T44	7695	1	0	0
T46	808	0	0	0
T53	8402	0	0	0
T64	0	1	0	0
T68	1591	0	0	0
T90	0	24	0	0
T92	0	22	0	0
T118	0	5	0	0
T121	0	16	0	0
T154	885	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T197	419	0	0	0
T261	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	86403	0	0
T2	2239	0	0	0
T11	0	84	0	0
T14	453	27	0	0
T15	489	0	0	0
T16	487	61	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T31	0	46	0	0
T32	0	2082	0	0
T34	0	21	0	0
T41	0	6	0	0
T44	0	346	0	0
T64	0	501	0	0
T89	0	37	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	867	0	0
T2	2239	0	0	0
T11	0	1	0	0
T14	453	1	0	0
T15	489	0	0	0
T16	487	1	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T31	0	1	0	0
T32	0	11	0	0
T34	0	3	0	0
T41	0	6	0	0
T44	0	5	0	0
T64	0	5	0	0
T89	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5697202	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	4	0	0
T15	489	88	0	0
T16	487	4	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5698930	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	4	0	0
T15	489	89	0	0
T16	487	4	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1605	0	0
T2	2239	0	0	0
T11	0	1	0	0
T14	453	1	0	0
T15	489	0	0	0
T16	487	1	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T31	0	1	0	0
T32	0	11	0	0
T33	0	4	0	0
T34	0	20	0	0
T41	0	27	0	0
T44	0	9	0	0
T89	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1528	0	0
T2	2239	0	0	0
T11	0	1	0	0
T14	453	1	0	0
T15	489	0	0	0
T16	487	1	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T31	0	1	0	0
T32	0	11	0	0
T33	0	4	0	0
T34	0	3	0	0
T41	0	27	0	0
T44	0	7	0	0
T89	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	867	0	0
T2	2239	0	0	0
T11	0	1	0	0
T14	453	1	0	0
T15	489	0	0	0
T16	487	1	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T31	0	1	0	0
T32	0	11	0	0
T34	0	3	0	0
T41	0	6	0	0
T44	0	5	0	0
T64	0	5	0	0
T89	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	867	0	0
T2	2239	0	0	0
T11	0	1	0	0
T14	453	1	0	0
T15	489	0	0	0
T16	487	1	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T31	0	1	0	0
T32	0	11	0	0
T34	0	3	0	0
T41	0	6	0	0
T44	0	5	0	0
T64	0	5	0	0
T89	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	85418	0	0
T2	2239	0	0	0
T11	0	82	0	0
T14	453	25	0	0
T15	489	0	0	0
T16	487	59	0	0
T17	497	0	0	0
T18	441	0	0	0
T19	428	0	0	0
T20	402	0	0	0
T21	422	0	0	0
T27	522	0	0	0
T31	0	44	0	0
T32	0	2068	0	0
T34	0	18	0	0
T44	0	341	0	0
T64	0	496	0	0
T89	0	35	0	0
T91	0	682	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	742	0	0
T24	1142	0	0	0
T32	14266	8	0	0
T34	0	3	0	0
T44	0	5	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	4	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T91	0	14	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0
T165	0	8	0	0
T262	0	9	0	0
T263	0	22	0	0
T264	0	19	0	0
T265	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T14 T16 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T5 T14 T16 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T5 T14 T16 
149        1/1                    cnt_en = 1'b1;
           Tests:       T5 T14 T16 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T5 T14 T16 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T5 T14 T16 
163        1/1                    state_d = IdleSt;
           Tests:       T44 T64 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 
165        1/1                  end else if (cnt_done) begin
           Tests:       T5 T14 T16 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T5 T14 T16 
167        1/1                    if (trigger_active) begin
           Tests:       T5 T14 T16 
168        1/1                      state_d = DetectSt;
           Tests:       T7 T10 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T5 T14 T16 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T7 T10 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T7 T10 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T7 T10 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T44 T64 T108 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 T108 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T7 T10 T11 
191        1/1                      state_d = StableSt;
           Tests:       T7 T10 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T7 T10 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T7 T10 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T7 T10 T11 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T7 T10 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T7 T10 T11 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T7 T10 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T14,T16
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T16
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T14,T16

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T5,T14,T16

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T10,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T5,T14,T16
1	0	Covered	T7,T29,T60
1	1	Covered	T5,T14,T16

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T108,T43,T117
1	0	Covered	T44,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T10,T11
0	1	Covered	T7,T10,T11
1	0	Covered	T44,T64,T266

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T10,T11
1	-	Covered	T7,T10,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T14,T16
DetectSt	168	Covered	T7,T10,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T10,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T10,T11
DebounceSt->IdleSt	163	Covered	T5,T14,T16
DetectSt->IdleSt	186	Covered	T44,T64,T108
DetectSt->StableSt	191	Covered	T7,T10,T11
IdleSt->DebounceSt	148	Covered	T5,T14,T16
StableSt->IdleSt	206	Covered	T7,T10,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T5,T14,T16
0	1	Covered	T5,T14,T16
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T10,T11
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T14,T16
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T44,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T10,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T14,T16
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T14,T16
DetectSt	-	-	-	-	1	-	-	Covered	T44,T64,T108
DetectSt	-	-	-	-	0	1	-	Covered	T7,T10,T11
DetectSt	-	-	-	-	0	0	-	Covered	T7,T10,T11
StableSt	-	-	-	-	-	-	1	Covered	T7,T10,T11
StableSt	-	-	-	-	-	-	0	Covered	T7,T10,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	910	0	0
CntIncr_A	6668985	49465	0	0
CntNoWrap_A	6668985	6186098	0	0
DetectStDropOut_A	6668985	36	0	0
DetectedOut_A	6668985	19235	0	0
DetectedPulseOut_A	6668985	384	0	0
DisabledIdleSt_A	6668985	5829416	0	0
DisabledNoDetection_A	6668985	5830684	0	0
EnterDebounceSt_A	6668985	489	0	0
EnterDetectSt_A	6668985	423	0	0
EnterStableSt_A	6668985	384	0	0
PulseIsPulse_A	6668985	384	0	0
StayInStableSt	6668985	18833	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	363	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	910	0	0
T1	822	0	0	0
T5	442	1	0	0
T6	429	0	0	0
T7	0	4	0	0
T10	0	5	0	0
T11	0	2	0	0
T13	0	2	0	0
T14	453	1	0	0
T15	489	0	0	0
T16	487	1	0	0
T17	497	0	0	0
T19	0	1	0	0
T22	1040	0	0	0
T26	527	0	0	0
T31	0	1	0	0
T36	423	0	0	0
T65	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	49465	0	0
T1	822	0	0	0
T5	442	20	0	0
T6	429	0	0	0
T7	0	50	0	0
T10	0	240	0	0
T11	0	25	0	0
T13	0	25	0	0
T14	453	20	0	0
T15	489	0	0	0
T16	487	20	0	0
T17	497	0	0	0
T19	0	20	0	0
T22	1040	0	0	0
T26	527	0	0	0
T31	0	20	0	0
T36	423	0	0	0
T65	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186098	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	40	0	0
T6	429	28	0	0
T14	453	51	0	0
T15	489	88	0	0
T16	487	85	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	36	0	0
T43	0	9	0	0
T55	3079	0	0	0
T99	1136	0	0	0
T102	8582	0	0	0
T108	6599	5	0	0
T116	625	0	0	0
T117	0	2	0	0
T119	0	5	0	0
T120	0	2	0	0
T123	0	6	0	0
T124	0	3	0	0
T127	0	4	0	0
T134	402	0	0	0
T135	504	0	0	0
T136	426	0	0	0
T137	414	0	0	0
T138	506	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	19235	0	0
T7	3077	6	0	0
T8	1171	0	0	0
T9	943	0	0	0
T10	0	15	0	0
T11	0	3	0	0
T13	0	3	0	0
T23	959	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T32	0	264	0	0
T35	0	102	0	0
T38	0	108	0	0
T44	0	85	0	0
T48	0	7	0	0
T60	4539	0	0	0
T64	0	103	0	0
T72	428	0	0	0
T83	502	0	0	0
T139	713	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	384	0	0
T7	3077	2	0	0
T8	1171	0	0	0
T9	943	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T13	0	1	0	0
T23	959	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T32	0	3	0	0
T35	0	8	0	0
T38	0	1	0	0
T44	0	1	0	0
T48	0	2	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T139	713	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5829416	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	3	0	0
T6	429	28	0	0
T14	453	26	0	0
T15	489	88	0	0
T16	487	26	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5830684	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	3	0	0
T6	429	29	0	0
T14	453	26	0	0
T15	489	89	0	0
T16	487	26	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	489	0	0
T1	822	0	0	0
T5	442	1	0	0
T6	429	0	0	0
T7	0	2	0	0
T10	0	3	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	453	1	0	0
T15	489	0	0	0
T16	487	1	0	0
T17	497	0	0	0
T19	0	1	0	0
T22	1040	0	0	0
T26	527	0	0	0
T31	0	1	0	0
T36	423	0	0	0
T65	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	423	0	0
T7	3077	2	0	0
T8	1171	0	0	0
T9	943	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T13	0	1	0	0
T23	959	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T32	0	3	0	0
T35	0	8	0	0
T38	0	1	0	0
T44	0	2	0	0
T48	0	2	0	0
T60	4539	0	0	0
T64	0	3	0	0
T72	428	0	0	0
T83	502	0	0	0
T139	713	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	384	0	0
T7	3077	2	0	0
T8	1171	0	0	0
T9	943	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T13	0	1	0	0
T23	959	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T32	0	3	0	0
T35	0	8	0	0
T38	0	1	0	0
T44	0	1	0	0
T48	0	2	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T139	713	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	384	0	0
T7	3077	2	0	0
T8	1171	0	0	0
T9	943	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T13	0	1	0	0
T23	959	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T32	0	3	0	0
T35	0	8	0	0
T38	0	1	0	0
T44	0	1	0	0
T48	0	2	0	0
T60	4539	0	0	0
T64	0	1	0	0
T72	428	0	0	0
T83	502	0	0	0
T139	713	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	18833	0	0
T7	3077	4	0	0
T8	1171	0	0	0
T9	943	0	0	0
T10	0	13	0	0
T11	0	2	0	0
T13	0	2	0	0
T23	959	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T32	0	261	0	0
T35	0	94	0	0
T38	0	107	0	0
T44	0	84	0	0
T48	0	5	0	0
T60	4539	0	0	0
T64	0	102	0	0
T72	428	0	0	0
T83	502	0	0	0
T139	713	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	363	0	0
T7	3077	2	0	0
T8	1171	0	0	0
T9	943	0	0	0
T10	0	2	0	0
T11	0	1	0	0
T13	0	1	0	0
T23	959	0	0	0
T29	2392	0	0	0
T31	471	0	0	0
T32	0	3	0	0
T35	0	8	0	0
T38	0	1	0	0
T42	0	2	0	0
T48	0	2	0	0
T60	4539	0	0	0
T72	428	0	0	0
T83	502	0	0	0
T102	0	1	0	0
T139	713	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T32 T33 T34 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T32 T33 T34 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T32 T33 T34 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T32 T33 T34 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T32 T33 T34 
129        1/1              cnt_en = 1'b0;
           Tests:       T32 T33 T34 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T32 T33 T34 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T32 T33 T34 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T32 T33 T34 
139                     
140        1/1              unique case (state_q)
           Tests:       T32 T33 T34 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T32 T33 T34 
148        1/1                    state_d = DebounceSt;
           Tests:       T32 T33 T34 
149        1/1                    cnt_en = 1'b1;
           Tests:       T32 T33 T34 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T34 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T32 T33 T34 
163        1/1                    state_d = IdleSt;
           Tests:       T44 T64 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 
165        1/1                  end else if (cnt_done) begin
           Tests:       T32 T33 T34 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
167        1/1                    if (trigger_active) begin
           Tests:       T32 T33 T34 
168        1/1                      state_d = DetectSt;
           Tests:       T32 T33 T44 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T44 T64 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T32 T33 T44 
182        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T44 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T32 T33 T44 
186        1/1                    state_d = IdleSt;
           Tests:       T32 T44 T41 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T44 T41 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T32 T33 T44 
191        1/1                      state_d = StableSt;
           Tests:       T33 T44 T39 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T33 T44 T39 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T33 T44 T39 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T33 T44 T39 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T33 T44 T39 
206        1/1                    state_d = IdleSt;
           Tests:       T33 T44 T39 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T33 T44 T39 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T32,T33,T34
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T44
1	1	Covered	T32,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T44
0	1	Covered	T32,T44,T41
1	0	Covered	T32,T44,T41

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T44,T39
0	1	Covered	T33,T44,T39
1	0	Covered	T111

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T44,T39
1	-	Covered	T33,T44,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T33,T34
DetectSt	168	Covered	T32,T33,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T33,T44,T39

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T33,T44
DebounceSt->IdleSt	163	Covered	T34,T44,T64
DetectSt->IdleSt	186	Covered	T32,T44,T41
DetectSt->StableSt	191	Covered	T33,T44,T39
IdleSt->DebounceSt	148	Covered	T32,T33,T34
StableSt->IdleSt	206	Covered	T33,T44,T39

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T32,T33,T34
0	1	Covered	T32,T33,T34
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T44
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T32,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T32,T33,T34
DebounceSt	-	1	-	-	-	-	-	Covered	T44,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T33,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T44,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T33,T34
DetectSt	-	-	-	-	1	-	-	Covered	T32,T44,T41
DetectSt	-	-	-	-	0	1	-	Covered	T33,T44,T39
DetectSt	-	-	-	-	0	0	-	Covered	T32,T33,T44
StableSt	-	-	-	-	-	-	1	Covered	T33,T44,T39
StableSt	-	-	-	-	-	-	0	Covered	T33,T44,T39
default	-	-	-	-	-	-	-	Not Covered

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	2924	0	0
CntIncr_A	6668985	98961	0	0
CntNoWrap_A	6668985	6184084	0	0
DetectStDropOut_A	6668985	407	0	0
DetectedOut_A	6668985	70018	0	0
DetectedPulseOut_A	6668985	818	0	0
DisabledIdleSt_A	6668985	5712222	0	0
DisabledNoDetection_A	6668985	5713962	0	0
EnterDebounceSt_A	6668985	1499	0	0
EnterDetectSt_A	6668985	1426	0	0
EnterStableSt_A	6668985	818	0	0
PulseIsPulse_A	6668985	818	0	0
StayInStableSt	6668985	69093	0	0
gen_high_event_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	698	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	2924	0	0
T24	1142	0	0	0
T32	14266	40	0	0
T33	0	48	0	0
T34	0	13	0	0
T39	0	22	0	0
T41	0	6	0	0
T44	0	16	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	16	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	10	0	0
T91	0	46	0	0
T92	0	16	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	98961	0	0
T24	1142	0	0	0
T32	14266	1447	0	0
T33	0	1392	0	0
T34	0	598	0	0
T39	0	418	0	0
T41	0	178	0	0
T44	0	491	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	566	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	287	0	0
T91	0	1058	0	0
T92	0	405	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6184084	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	407	0	0
T24	1142	0	0	0
T32	14266	9	0	0
T41	0	2	0	0
T44	0	1	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	1	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	5	0	0
T92	0	8	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0
T118	0	32	0	0
T265	0	2	0	0
T267	0	2	0	0
T268	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	70018	0	0
T33	9264	1716	0	0
T34	4765	0	0	0
T39	0	1857	0	0
T44	7695	368	0	0
T46	808	0	0	0
T53	8402	0	0	0
T64	0	505	0	0
T68	1591	0	0	0
T91	0	1918	0	0
T154	885	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	156	0	0
T197	419	0	0	0
T263	0	124	0	0
T264	0	222	0	0
T269	0	1669	0	0
T270	0	2432	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	818	0	0
T33	9264	24	0	0
T34	4765	0	0	0
T39	0	11	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T64	0	5	0	0
T68	1591	0	0	0
T91	0	23	0	0
T154	885	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	5	0	0
T197	419	0	0	0
T263	0	13	0	0
T264	0	15	0	0
T269	0	27	0	0
T270	0	29	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5712222	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5713962	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1499	0	0
T24	1142	0	0	0
T32	14266	20	0	0
T33	0	24	0	0
T34	0	13	0	0
T39	0	11	0	0
T41	0	3	0	0
T44	0	9	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	9	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	5	0	0
T91	0	23	0	0
T92	0	8	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1426	0	0
T24	1142	0	0	0
T32	14266	20	0	0
T33	0	24	0	0
T39	0	11	0	0
T41	0	3	0	0
T44	0	7	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	7	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	5	0	0
T91	0	23	0	0
T92	0	8	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0
T262	0	9	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	818	0	0
T33	9264	24	0	0
T34	4765	0	0	0
T39	0	11	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T64	0	5	0	0
T68	1591	0	0	0
T91	0	23	0	0
T154	885	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	5	0	0
T197	419	0	0	0
T263	0	13	0	0
T264	0	15	0	0
T269	0	27	0	0
T270	0	29	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	818	0	0
T33	9264	24	0	0
T34	4765	0	0	0
T39	0	11	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T64	0	5	0	0
T68	1591	0	0	0
T91	0	23	0	0
T154	885	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	5	0	0
T197	419	0	0	0
T263	0	13	0	0
T264	0	15	0	0
T269	0	27	0	0
T270	0	29	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	69093	0	0
T33	9264	1691	0	0
T34	4765	0	0	0
T39	0	1840	0	0
T44	7695	363	0	0
T46	808	0	0	0
T53	8402	0	0	0
T64	0	500	0	0
T68	1591	0	0	0
T91	0	1894	0	0
T154	885	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	151	0	0
T197	419	0	0	0
T263	0	111	0	0
T264	0	207	0	0
T269	0	1642	0	0
T270	0	2403	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	698	0	0
T33	9264	23	0	0
T34	4765	0	0	0
T39	0	5	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T64	0	5	0	0
T68	1591	0	0	0
T91	0	22	0	0
T154	885	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	5	0	0
T197	419	0	0	0
T263	0	13	0	0
T264	0	15	0	0
T269	0	27	0	0
T270	0	29	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T10 T35 T32 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T10 T35 T33 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T10 T35 T33 
149        1/1                    cnt_en = 1'b1;
           Tests:       T10 T35 T33 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T10 T35 T33 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T10 T35 T33 
163        1/1                    state_d = IdleSt;
           Tests:       T44 T64 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 
165        1/1                  end else if (cnt_done) begin
           Tests:       T10 T35 T33 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T35 T33 
167        1/1                    if (trigger_active) begin
           Tests:       T10 T35 T33 
168        1/1                      state_d = DetectSt;
           Tests:       T35 T33 T44 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T10 T35 T38 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T35 T33 T44 
182        1/1                  cnt_en = 1'b1;
           Tests:       T35 T33 T44 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T35 T33 T44 
186        1/1                    state_d = IdleSt;
           Tests:       T44 T64 T108 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 T108 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T35 T33 T44 
191        1/1                      state_d = StableSt;
           Tests:       T35 T33 T44 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T35 T33 T44 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T35 T33 T44 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T35 T33 T44 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T35 T33 T44 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T44 T38 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T35 T33 T44 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T10,T35,T32
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T35,T32
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T35,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T35,T33

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T33,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T35,T33
1	0	Covered	T7,T29,T60
1	1	Covered	T10,T35,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T33,T44
0	1	Covered	T108,T109,T271
1	0	Covered	T44,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T33,T44
0	1	Covered	T35,T38,T39
1	0	Covered	T44

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T33,T44
1	-	Covered	T35,T38,T39

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T35,T33
DetectSt	168	Covered	T35,T33,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T33,T44

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T33,T44
DebounceSt->IdleSt	163	Covered	T10,T35,T44
DetectSt->IdleSt	186	Covered	T44,T64,T108
DetectSt->StableSt	191	Covered	T35,T33,T44
IdleSt->DebounceSt	148	Covered	T10,T35,T33
StableSt->IdleSt	206	Covered	T35,T33,T44

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T35,T33
0	1	Covered	T10,T35,T33
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T33,T44
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T35,T33
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T44,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T33,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T35,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T35,T33
DetectSt	-	-	-	-	1	-	-	Covered	T44,T64,T108
DetectSt	-	-	-	-	0	1	-	Covered	T35,T33,T44
DetectSt	-	-	-	-	0	0	-	Covered	T35,T33,T44
StableSt	-	-	-	-	-	-	1	Covered	T35,T44,T38
StableSt	-	-	-	-	-	-	0	Covered	T35,T33,T44
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	736	0	0
CntIncr_A	6668985	42628	0	0
CntNoWrap_A	6668985	6186272	0	0
DetectStDropOut_A	6668985	40	0	0
DetectedOut_A	6668985	14420	0	0
DetectedPulseOut_A	6668985	301	0	0
DisabledIdleSt_A	6668985	5841982	0	0
DisabledNoDetection_A	6668985	5843297	0	0
EnterDebounceSt_A	6668985	391	0	0
EnterDetectSt_A	6668985	345	0	0
EnterStableSt_A	6668985	301	0	0
PulseIsPulse_A	6668985	301	0	0
StayInStableSt	6668985	14091	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	271	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	736	0	0
T10	12010	1	0	0
T11	510	0	0	0
T30	724	0	0	0
T33	0	2	0	0
T35	0	21	0	0
T38	0	21	0	0
T39	0	12	0	0
T44	0	8	0	0
T61	743	0	0	0
T64	0	8	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T91	0	2	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T108	0	5	0	0
T109	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	42628	0	0
T10	12010	28	0	0
T11	510	0	0	0
T30	724	0	0	0
T33	0	82	0	0
T35	0	1893	0	0
T38	0	2240	0	0
T39	0	336	0	0
T44	0	219	0	0
T61	743	0	0	0
T64	0	335	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T91	0	81	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T108	0	159	0	0
T109	0	146	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186272	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	40	0	0
T55	3079	0	0	0
T99	1136	0	0	0
T102	8582	0	0	0
T108	6599	2	0	0
T109	0	1	0	0
T116	625	0	0	0
T124	0	7	0	0
T134	402	0	0	0
T135	504	0	0	0
T136	426	0	0	0
T137	414	0	0	0
T138	506	0	0	0
T218	0	2	0	0
T271	0	2	0	0
T272	0	1	0	0
T273	0	6	0	0
T274	0	7	0	0
T275	0	5	0	0
T276	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	14420	0	0
T32	14266	0	0	0
T33	0	65	0	0
T35	8365	525	0	0
T38	0	51	0	0
T39	0	329	0	0
T40	0	110	0	0
T43	0	147	0	0
T44	0	84	0	0
T64	0	101	0	0
T66	775	0	0	0
T79	494	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T89	463	0	0	0
T91	0	58	0	0
T117	0	200	0	0
T243	425	0	0	0
T244	436	0	0	0
T245	421	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	301	0	0
T32	14266	0	0	0
T33	0	1	0	0
T35	8365	10	0	0
T38	0	10	0	0
T39	0	6	0	0
T40	0	2	0	0
T43	0	5	0	0
T44	0	1	0	0
T64	0	1	0	0
T66	775	0	0	0
T79	494	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T89	463	0	0	0
T91	0	1	0	0
T117	0	7	0	0
T243	425	0	0	0
T244	436	0	0	0
T245	421	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5841982	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5843297	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	391	0	0
T10	12010	1	0	0
T11	510	0	0	0
T30	724	0	0	0
T33	0	1	0	0
T35	0	11	0	0
T38	0	11	0	0
T39	0	6	0	0
T44	0	5	0	0
T61	743	0	0	0
T64	0	5	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T91	0	1	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T108	0	3	0	0
T109	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	345	0	0
T32	14266	0	0	0
T33	0	1	0	0
T35	8365	10	0	0
T38	0	10	0	0
T39	0	6	0	0
T40	0	2	0	0
T44	0	3	0	0
T64	0	3	0	0
T66	775	0	0	0
T79	494	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T89	463	0	0	0
T91	0	1	0	0
T108	0	2	0	0
T109	0	1	0	0
T243	425	0	0	0
T244	436	0	0	0
T245	421	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	301	0	0
T32	14266	0	0	0
T33	0	1	0	0
T35	8365	10	0	0
T38	0	10	0	0
T39	0	6	0	0
T40	0	2	0	0
T43	0	5	0	0
T44	0	1	0	0
T64	0	1	0	0
T66	775	0	0	0
T79	494	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T89	463	0	0	0
T91	0	1	0	0
T117	0	7	0	0
T243	425	0	0	0
T244	436	0	0	0
T245	421	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	301	0	0
T32	14266	0	0	0
T33	0	1	0	0
T35	8365	10	0	0
T38	0	10	0	0
T39	0	6	0	0
T40	0	2	0	0
T43	0	5	0	0
T44	0	1	0	0
T64	0	1	0	0
T66	775	0	0	0
T79	494	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T89	463	0	0	0
T91	0	1	0	0
T117	0	7	0	0
T243	425	0	0	0
T244	436	0	0	0
T245	421	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	14091	0	0
T32	14266	0	0	0
T33	0	63	0	0
T35	8365	515	0	0
T38	0	41	0	0
T39	0	323	0	0
T40	0	108	0	0
T43	0	142	0	0
T44	0	83	0	0
T64	0	100	0	0
T66	775	0	0	0
T79	494	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T89	463	0	0	0
T91	0	57	0	0
T117	0	193	0	0
T243	425	0	0	0
T244	436	0	0	0
T245	421	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	271	0	0
T32	14266	0	0	0
T35	8365	10	0	0
T38	0	10	0	0
T39	0	6	0	0
T40	0	2	0	0
T43	0	5	0	0
T66	775	0	0	0
T79	494	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T89	463	0	0	0
T91	0	1	0	0
T117	0	7	0	0
T119	0	4	0	0
T243	425	0	0	0
T244	436	0	0	0
T245	421	0	0	0
T277	0	2	0	0
T278	0	3	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T32 T33 T34 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T32 T33 T34 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T32 T33 T34 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T32 T33 T34 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T32 T33 T34 
129        1/1              cnt_en = 1'b0;
           Tests:       T32 T33 T34 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T32 T33 T34 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T32 T33 T34 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T32 T33 T34 
139                     
140        1/1              unique case (state_q)
           Tests:       T32 T33 T34 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T32 T33 T34 
148        1/1                    state_d = DebounceSt;
           Tests:       T32 T33 T34 
149        1/1                    cnt_en = 1'b1;
           Tests:       T32 T33 T34 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T34 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T32 T33 T34 
163        1/1                    state_d = IdleSt;
           Tests:       T44 T64 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 
165        1/1                  end else if (cnt_done) begin
           Tests:       T32 T33 T34 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
167        1/1                    if (trigger_active) begin
           Tests:       T32 T33 T34 
168        1/1                      state_d = DetectSt;
           Tests:       T32 T33 T44 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T44 T64 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T32 T33 T44 
182        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T44 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T32 T33 T44 
186        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T44 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T44 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T32 T33 T44 
191        1/1                      state_d = StableSt;
           Tests:       T44 T41 T64 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T44 T41 T64 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T44 T41 T64 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T44 T41 T64 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T44 T41 T64 
206        1/1                    state_d = IdleSt;
           Tests:       T44 T41 T64 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T44 T41 T64 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T32,T33,T34
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T44
1	1	Covered	T32,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T44
0	1	Covered	T32,T33,T44
1	0	Covered	T32,T33,T44

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T41,T64
0	1	Covered	T44,T41,T64
1	0	Covered	T64

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T41,T64
1	-	Covered	T44,T41,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T33,T34
DetectSt	168	Covered	T32,T33,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T44,T41,T64

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T33,T44
DebounceSt->IdleSt	163	Covered	T34,T44,T64
DetectSt->IdleSt	186	Covered	T32,T33,T44
DetectSt->StableSt	191	Covered	T44,T41,T64
IdleSt->DebounceSt	148	Covered	T32,T33,T34
StableSt->IdleSt	206	Covered	T44,T41,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T32,T33,T34
0	1	Covered	T32,T33,T34
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T44
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T32,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T32,T33,T34
DebounceSt	-	1	-	-	-	-	-	Covered	T44,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T33,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T44,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T33,T34
DetectSt	-	-	-	-	1	-	-	Covered	T32,T33,T44
DetectSt	-	-	-	-	0	1	-	Covered	T44,T41,T64
DetectSt	-	-	-	-	0	0	-	Covered	T32,T33,T44
StableSt	-	-	-	-	-	-	1	Covered	T44,T41,T64
StableSt	-	-	-	-	-	-	0	Covered	T44,T41,T64
default	-	-	-	-	-	-	-	Not Covered

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	3157	0	0
CntIncr_A	6668985	110889	0	0
CntNoWrap_A	6668985	6183851	0	0
DetectStDropOut_A	6668985	374	0	0
DetectedOut_A	6668985	95506	0	0
DetectedPulseOut_A	6668985	1002	0	0
DisabledIdleSt_A	6668985	5692343	0	0
DisabledNoDetection_A	6668985	5694066	0	0
EnterDebounceSt_A	6668985	1617	0	0
EnterDetectSt_A	6668985	1542	0	0
EnterStableSt_A	6668985	1002	0	0
PulseIsPulse_A	6668985	1002	0	0
StayInStableSt	6668985	94383	0	0
gen_high_event_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	879	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	3157	0	0
T24	1142	0	0	0
T32	14266	26	0	0
T33	0	44	0	0
T34	0	12	0	0
T39	0	26	0	0
T41	0	32	0	0
T44	0	16	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	17	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	56	0	0
T91	0	16	0	0
T92	0	14	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	110889	0	0
T24	1142	0	0	0
T32	14266	934	0	0
T33	0	1285	0	0
T34	0	552	0	0
T39	0	730	0	0
T41	0	896	0	0
T44	0	680	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	617	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	1625	0	0
T91	0	376	0	0
T92	0	351	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6183851	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	374	0	0
T24	1142	0	0	0
T32	14266	9	0	0
T33	0	9	0	0
T39	0	7	0	0
T44	0	1	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	1	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	28	0	0
T92	0	7	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0
T118	0	13	0	0
T121	0	29	0	0
T265	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	95506	0	0
T41	0	1399	0	0
T44	7695	447	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	441	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	635	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	133	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	1858	0	0
T263	0	1586	0	0
T264	0	2277	0	0
T267	0	2321	0	0
T269	0	87	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1002	0	0
T41	0	16	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	5	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	8	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	5	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	26	0	0
T263	0	21	0	0
T264	0	25	0	0
T267	0	25	0	0
T269	0	9	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5692343	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5694066	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1617	0	0
T24	1142	0	0	0
T32	14266	13	0	0
T33	0	22	0	0
T34	0	12	0	0
T39	0	13	0	0
T41	0	16	0	0
T44	0	9	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	10	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	28	0	0
T91	0	8	0	0
T92	0	7	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1542	0	0
T24	1142	0	0	0
T32	14266	13	0	0
T33	0	22	0	0
T39	0	13	0	0
T41	0	16	0	0
T44	0	7	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	7	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	28	0	0
T91	0	8	0	0
T92	0	7	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0
T262	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1002	0	0
T41	0	16	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	5	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	8	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	5	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	26	0	0
T263	0	21	0	0
T264	0	25	0	0
T267	0	25	0	0
T269	0	9	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1002	0	0
T41	0	16	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	5	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	8	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	5	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	26	0	0
T263	0	21	0	0
T264	0	25	0	0
T267	0	25	0	0
T269	0	9	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	94383	0	0
T41	0	1382	0	0
T44	7695	442	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	436	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	626	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	128	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	1832	0	0
T263	0	1563	0	0
T264	0	2250	0	0
T267	0	2290	0	0
T269	0	78	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	879	0	0
T41	0	15	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	4	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	7	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	5	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	26	0	0
T263	0	19	0	0
T264	0	23	0	0
T267	0	19	0	0
T269	0	9	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T10 T35 T32 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T10 T44 T38 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T10 T44 T38 
149        1/1                    cnt_en = 1'b1;
           Tests:       T10 T44 T38 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T10 T44 T38 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T10 T44 T38 
163        1/1                    state_d = IdleSt;
           Tests:       T44 T64 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 
165        1/1                  end else if (cnt_done) begin
           Tests:       T10 T44 T38 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T44 T38 
167        1/1                    if (trigger_active) begin
           Tests:       T10 T44 T38 
168        1/1                      state_d = DetectSt;
           Tests:       T44 T38 T41 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T10 T41 T43 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T44 T38 T41 
182        1/1                  cnt_en = 1'b1;
           Tests:       T44 T38 T41 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T44 T38 T41 
186        1/1                    state_d = IdleSt;
           Tests:       T44 T64 T108 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 T108 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T44 T38 T41 
191        1/1                      state_d = StableSt;
           Tests:       T44 T38 T41 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T44 T38 T41 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T44 T38 T41 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T44 T38 T41 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T44 T38 T41 
206        1/1                    state_d = IdleSt;
           Tests:       T44 T38 T41 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T44 T38 T41 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	20	95.24
Logical	21	20	95.24
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T10,T35,T32
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T35,T32
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T44,T38

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T44,T38

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T44,T38,T41

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T35,T44
1	0	Covered	T7,T29,T60
1	1	Covered	T10,T44,T38

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T44,T38,T41
0	1	Covered	T108,T117,T119
1	0	Covered	T44,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T38,T41
0	1	Covered	T38,T41,T64
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T38,T41
1	-	Covered	T44,T38,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T44,T38
DetectSt	168	Covered	T44,T38,T41
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T44,T38,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T44,T38,T41
DebounceSt->IdleSt	163	Covered	T10,T44,T41
DetectSt->IdleSt	186	Covered	T44,T64,T108
DetectSt->StableSt	191	Covered	T44,T38,T41
IdleSt->DebounceSt	148	Covered	T10,T44,T38
StableSt->IdleSt	206	Covered	T44,T38,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T44,T38
0	1	Covered	T10,T44,T38
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T44,T38,T41
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T44,T38
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T44,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T44,T38,T41
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T41,T43
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T44,T38
DetectSt	-	-	-	-	1	-	-	Covered	T44,T64,T108
DetectSt	-	-	-	-	0	1	-	Covered	T44,T38,T41
DetectSt	-	-	-	-	0	0	-	Covered	T44,T38,T41
StableSt	-	-	-	-	-	-	1	Covered	T44,T38,T41
StableSt	-	-	-	-	-	-	0	Covered	T44,T38,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	871	0	0
CntIncr_A	6668985	49221	0	0
CntNoWrap_A	6668985	6186137	0	0
DetectStDropOut_A	6668985	46	0	0
DetectedOut_A	6668985	17460	0	0
DetectedPulseOut_A	6668985	354	0	0
DisabledIdleSt_A	6668985	5825784	0	0
DisabledNoDetection_A	6668985	5827084	0	0
EnterDebounceSt_A	6668985	467	0	0
EnterDetectSt_A	6668985	404	0	0
EnterStableSt_A	6668985	354	0	0
PulseIsPulse_A	6668985	354	0	0
StayInStableSt	6668985	17048	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	294	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	871	0	0
T10	12010	1	0	0
T11	510	0	0	0
T30	724	0	0	0
T38	0	10	0	0
T40	0	6	0	0
T41	0	4	0	0
T42	0	2	0	0
T43	0	11	0	0
T44	0	8	0	0
T61	743	0	0	0
T64	0	8	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T91	0	2	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T108	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	49221	0	0
T10	12010	28	0	0
T11	510	0	0	0
T30	724	0	0	0
T38	0	815	0	0
T40	0	453	0	0
T41	0	150	0	0
T42	0	104	0	0
T43	0	846	0	0
T44	0	298	0	0
T61	743	0	0	0
T64	0	266	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T91	0	55	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T108	0	138	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186137	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	46	0	0
T55	3079	0	0	0
T99	1136	0	0	0
T102	8582	0	0	0
T108	6599	2	0	0
T116	625	0	0	0
T117	0	5	0	0
T119	0	3	0	0
T134	402	0	0	0
T135	504	0	0	0
T136	426	0	0	0
T137	414	0	0	0
T138	506	0	0	0
T272	0	7	0	0
T273	0	1	0	0
T279	0	6	0	0
T280	0	8	0	0
T281	0	4	0	0
T282	0	1	0	0
T283	0	9	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	17460	0	0
T38	0	278	0	0
T40	0	25	0	0
T41	0	37	0	0
T42	0	60	0	0
T43	0	137	0	0
T44	7695	85	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	101	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	83	0	0
T155	424	0	0	0
T156	402	0	0	0
T197	419	0	0	0
T198	524	0	0	0
T271	0	199	0	0
T277	0	18	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	354	0	0
T38	0	5	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	5	0	0
T44	7695	1	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	1	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	1	0	0
T155	424	0	0	0
T156	402	0	0	0
T197	419	0	0	0
T198	524	0	0	0
T271	0	14	0	0
T277	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5825784	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5827084	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	467	0	0
T10	12010	1	0	0
T11	510	0	0	0
T30	724	0	0	0
T38	0	5	0	0
T40	0	3	0	0
T41	0	3	0	0
T42	0	1	0	0
T43	0	6	0	0
T44	0	5	0	0
T61	743	0	0	0
T64	0	5	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T91	0	1	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T108	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	404	0	0
T38	0	5	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	5	0	0
T44	7695	3	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	3	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	1	0	0
T108	0	2	0	0
T117	0	5	0	0
T155	424	0	0	0
T156	402	0	0	0
T197	419	0	0	0
T198	524	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	354	0	0
T38	0	5	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	5	0	0
T44	7695	1	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	1	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	1	0	0
T155	424	0	0	0
T156	402	0	0	0
T197	419	0	0	0
T198	524	0	0	0
T271	0	14	0	0
T277	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	354	0	0
T38	0	5	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	5	0	0
T44	7695	1	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	1	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	1	0	0
T155	424	0	0	0
T156	402	0	0	0
T197	419	0	0	0
T198	524	0	0	0
T271	0	14	0	0
T277	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	17048	0	0
T38	0	273	0	0
T40	0	22	0	0
T41	0	36	0	0
T42	0	59	0	0
T43	0	132	0	0
T44	7695	84	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	100	0	0
T68	1591	0	0	0
T81	499	0	0	0
T91	0	81	0	0
T155	424	0	0	0
T156	402	0	0	0
T197	419	0	0	0
T198	524	0	0	0
T271	0	185	0	0
T277	0	14	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	294	0	0
T38	30851	5	0	0
T40	0	3	0	0
T41	0	1	0	0
T42	0	1	0	0
T43	0	5	0	0
T49	857	0	0	0
T64	0	1	0	0
T69	664	0	0	0
T82	498	0	0	0
T262	0	4	0	0
T271	0	13	0	0
T277	0	4	0	0
T278	0	4	0	0
T284	501	0	0	0
T285	408	0	0	0
T286	428	0	0	0
T287	1927	0	0	0
T288	403	0	0	0
T289	531	0	0	0