Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.05	100.00	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
96.15	100.00	92.31					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T32 T33 T34 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T32 T33 T34 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T32 T33 T34 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T32 T33 T34 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T32 T33 T34 
129        1/1              cnt_en = 1'b0;
           Tests:       T32 T33 T34 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T32 T33 T34 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T32 T33 T34 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T32 T33 T34 
139                     
140        1/1              unique case (state_q)
           Tests:       T32 T33 T34 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T32 T33 T34 
148        1/1                    state_d = DebounceSt;
           Tests:       T32 T33 T34 
149        1/1                    cnt_en = 1'b1;
           Tests:       T32 T33 T34 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T34 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T32 T33 T34 
163        1/1                    state_d = IdleSt;
           Tests:       T44 T64 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 
165        1/1                  end else if (cnt_done) begin
           Tests:       T32 T33 T34 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
167        1/1                    if (trigger_active) begin
           Tests:       T32 T33 T34 
168        1/1                      state_d = DetectSt;
           Tests:       T32 T33 T34 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T44 T64 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T32 T33 T34 
182        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T34 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T32 T33 T34 
186        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T34 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T34 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T32 T33 T34 
191        1/1                      state_d = StableSt;
           Tests:       T44 T39 T64 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T44 T39 T64 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T44 T39 T64 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T44 T39 T64 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T44 T39 T64 
206        1/1                    state_d = IdleSt;
           Tests:       T44 T39 T64 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T44 T39 T64 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T32,T33,T34
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T34

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T44
1	1	Covered	T32,T33,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T34
0	1	Covered	T32,T33,T34
1	0	Covered	T32,T33,T44

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T44,T39,T64
0	1	Covered	T44,T39,T64
1	0	Covered	T290,T291

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T44,T39,T64
1	-	Covered	T44,T39,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T33,T34
DetectSt	168	Covered	T32,T33,T34
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T44,T39,T64

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T33,T34
DebounceSt->IdleSt	163	Covered	T34,T44,T64
DetectSt->IdleSt	186	Covered	T32,T33,T34
DetectSt->StableSt	191	Covered	T44,T39,T64
IdleSt->DebounceSt	148	Covered	T32,T33,T34
StableSt->IdleSt	206	Covered	T44,T39,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T32,T33,T34
0	1	Covered	T32,T33,T34
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T34
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T32,T33,T34
IdleSt	0	-	-	-	-	-	-	Covered	T32,T33,T34
DebounceSt	-	1	-	-	-	-	-	Covered	T44,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T33,T34
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T44,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T33,T34
DetectSt	-	-	-	-	1	-	-	Covered	T32,T33,T34
DetectSt	-	-	-	-	0	1	-	Covered	T44,T39,T64
DetectSt	-	-	-	-	0	0	-	Covered	T32,T33,T34
StableSt	-	-	-	-	-	-	1	Covered	T44,T39,T64
StableSt	-	-	-	-	-	-	0	Covered	T44,T39,T64
default	-	-	-	-	-	-	-	Not Covered

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	3053	0	0
CntIncr_A	6668985	114592	0	0
CntNoWrap_A	6668985	6183955	0	0
DetectStDropOut_A	6668985	477	0	0
DetectedOut_A	6668985	68743	0	0
DetectedPulseOut_A	6668985	765	0	0
DisabledIdleSt_A	6668985	5711975	0	0
DisabledNoDetection_A	6668985	5713715	0	0
EnterDebounceSt_A	6668985	1564	0	0
EnterDetectSt_A	6668985	1492	0	0
EnterStableSt_A	6668985	765	0	0
PulseIsPulse_A	6668985	765	0	0
StayInStableSt	6668985	67873	0	0
gen_high_event_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	656	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	3053	0	0
T24	1142	0	0	0
T32	14266	4	0	0
T33	0	26	0	0
T34	0	23	0	0
T39	0	10	0	0
T41	0	18	0	0
T44	0	16	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	16	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	26	0	0
T91	0	26	0	0
T92	0	16	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	114592	0	0
T24	1142	0	0	0
T32	14266	143	0	0
T33	0	751	0	0
T34	0	1093	0	0
T39	0	250	0	0
T41	0	528	0	0
T44	0	542	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	671	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	749	0	0
T91	0	924	0	0
T92	0	407	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6183955	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	477	0	0
T24	1142	0	0	0
T32	14266	1	0	0
T33	0	8	0	0
T34	0	3	0	0
T41	0	8	0	0
T44	0	1	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	1	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	13	0	0
T91	0	5	0	0
T92	0	8	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0
T118	0	18	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	68743	0	0
T39	0	502	0	0
T44	7695	371	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	431	0	0
T68	1591	0	0	0
T81	499	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	81	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	84	0	0
T263	0	410	0	0
T264	0	2152	0	0
T265	0	1829	0	0
T267	0	204	0	0
T269	0	354	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	765	0	0
T39	0	5	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	5	0	0
T68	1591	0	0	0
T81	499	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	8	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	4	0	0
T263	0	13	0	0
T264	0	25	0	0
T265	0	15	0	0
T267	0	4	0	0
T269	0	23	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5711975	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5713715	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1564	0	0
T24	1142	0	0	0
T32	14266	2	0	0
T33	0	13	0	0
T34	0	21	0	0
T39	0	5	0	0
T41	0	9	0	0
T44	0	9	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	9	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	13	0	0
T91	0	13	0	0
T92	0	8	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	1492	0	0
T24	1142	0	0	0
T32	14266	2	0	0
T33	0	13	0	0
T34	0	3	0	0
T39	0	5	0	0
T41	0	9	0	0
T44	0	7	0	0
T50	710	0	0	0
T58	1031	0	0	0
T64	0	7	0	0
T66	775	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T90	0	13	0	0
T91	0	13	0	0
T92	0	8	0	0
T93	502	0	0	0
T94	1152	0	0	0
T95	425	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	765	0	0
T39	0	5	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	5	0	0
T68	1591	0	0	0
T81	499	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	8	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	4	0	0
T263	0	13	0	0
T264	0	25	0	0
T265	0	15	0	0
T267	0	4	0	0
T269	0	23	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	765	0	0
T39	0	5	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	5	0	0
T68	1591	0	0	0
T81	499	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	8	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	4	0	0
T263	0	13	0	0
T264	0	25	0	0
T265	0	15	0	0
T267	0	4	0	0
T269	0	23	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	67873	0	0
T39	0	496	0	0
T44	7695	366	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	426	0	0
T68	1591	0	0	0
T81	499	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	73	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	80	0	0
T263	0	397	0	0
T264	0	2125	0	0
T265	0	1810	0	0
T267	0	199	0	0
T269	0	331	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	656	0	0
T39	0	4	0	0
T44	7695	5	0	0
T46	808	0	0	0
T53	8402	0	0	0
T54	4402	0	0	0
T64	0	5	0	0
T68	1591	0	0	0
T81	499	0	0	0
T155	424	0	0	0
T156	402	0	0	0
T165	0	8	0	0
T197	419	0	0	0
T198	524	0	0	0
T262	0	4	0	0
T263	0	13	0	0
T264	0	23	0	0
T265	0	11	0	0
T267	0	3	0	0
T269	0	23	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T10 T35 T32 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T10 T35 T44 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T5 T1 T14 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T5 T1 T14 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T10 T35 T44 
149        1/1                    cnt_en = 1'b1;
           Tests:       T10 T35 T44 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T10 T35 T44 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T10 T35 T44 
163        1/1                    state_d = IdleSt;
           Tests:       T44 T64 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T44 T64 
165        1/1                  end else if (cnt_done) begin
           Tests:       T10 T35 T44 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T35 T44 
167        1/1                    if (trigger_active) begin
           Tests:       T10 T35 T44 
168        1/1                      state_d = DetectSt;
           Tests:       T10 T35 T44 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T10 T35 T38 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T10 T35 T44 
182        1/1                  cnt_en = 1'b1;
           Tests:       T10 T35 T44 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T10 T35 T44 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T44 T64 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T44 T64 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T10 T35 T44 
191        1/1                      state_d = StableSt;
           Tests:       T10 T44 T38 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T10 T44 T38 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T10 T44 T38 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T10 T44 T38 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T10 T44 T38 
206        1/1                    state_d = IdleSt;
           Tests:       T10 T44 T38 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T10 T44 T38 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	21	21	100.00
Logical	21	21	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T10,T35,T32
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T10,T35,T32
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T35,T44

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests	Exclude Annotation
0	Excluded	T4,T5,T6	VC_COV_UNR
1	Covered	T10,T35,T44

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T35,T44

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T35,T44
1	0	Covered	T7,T29,T60
1	1	Covered	T10,T35,T44

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T35,T44
0	1	Covered	T35,T44,T108
1	0	Covered	T44,T64

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T44,T38
0	1	Covered	T10,T38,T39
1	0	Covered	T110

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T10,T44,T38
1	-	Covered	T10,T44,T38

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T10,T35,T44
DetectSt	168	Covered	T10,T35,T44
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T44,T38

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T35,T44
DebounceSt->IdleSt	163	Covered	T10,T35,T44
DetectSt->IdleSt	186	Covered	T35,T44,T64
DetectSt->StableSt	191	Covered	T10,T44,T38
IdleSt->DebounceSt	148	Covered	T10,T35,T44
StableSt->IdleSt	206	Covered	T10,T44,T38

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	2	2	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==> (Excluded)  

Branches:

-1-	-2-	Status	Tests	Exclude Annotation
1	-	Covered	T10,T35,T44
0	1	Covered	T10,T35,T44
0	0	Excluded	T4,T5,T6	VC_COV_UNR

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T35,T44
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T10,T35,T44
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T44,T64
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T35,T44
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T35,T38
DebounceSt	-	0	0	-	-	-	-	Covered	T10,T35,T44
DetectSt	-	-	-	-	1	-	-	Covered	T35,T44,T64
DetectSt	-	-	-	-	0	1	-	Covered	T10,T44,T38
DetectSt	-	-	-	-	0	0	-	Covered	T10,T35,T44
StableSt	-	-	-	-	-	-	1	Covered	T10,T44,T38
StableSt	-	-	-	-	-	-	0	Covered	T10,T44,T38
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	6668985	704	0	0
CntIncr_A	6668985	40515	0	0
CntNoWrap_A	6668985	6186304	0	0
DetectStDropOut_A	6668985	48	0	0
DetectedOut_A	6668985	13816	0	0
DetectedPulseOut_A	6668985	277	0	0
DisabledIdleSt_A	6668985	5848090	0	0
DisabledNoDetection_A	6668985	5849413	0	0
EnterDebounceSt_A	6668985	377	0	0
EnterDetectSt_A	6668985	328	0	0
EnterStableSt_A	6668985	277	0	0
PulseIsPulse_A	6668985	277	0	0
StayInStableSt	6668985	13512	0	0
gen_high_level_sva.HighLevelEvent_A	6668985	6188948	0	0
gen_not_sticky_sva.StableStDropOut_A	6668985	245	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	704	0	0
T10	12010	3	0	0
T11	510	0	0	0
T30	724	0	0	0
T35	0	17	0	0
T38	0	21	0	0
T39	0	2	0	0
T40	0	12	0	0
T42	0	9	0	0
T43	0	11	0	0
T44	0	8	0	0
T61	743	0	0	0
T64	0	8	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T108	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	40515	0	0
T10	12010	104	0	0
T11	510	0	0	0
T30	724	0	0	0
T35	0	1957	0	0
T38	0	1440	0	0
T39	0	61	0	0
T40	0	958	0	0
T42	0	702	0	0
T43	0	936	0	0
T44	0	217	0	0
T61	743	0	0	0
T64	0	259	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T108	0	159	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6186304	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	48	0	0
T32	14266	0	0	0
T35	8365	8	0	0
T40	0	6	0	0
T44	0	1	0	0
T66	775	0	0	0
T79	494	0	0	0
T87	527	0	0	0
T88	502	0	0	0
T89	463	0	0	0
T108	0	2	0	0
T119	0	4	0	0
T243	425	0	0	0
T244	436	0	0	0
T245	421	0	0	0
T271	0	4	0	0
T272	0	2	0	0
T278	0	7	0	0
T292	0	5	0	0
T293	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	13816	0	0
T10	12010	37	0	0
T11	510	0	0	0
T30	724	0	0	0
T38	0	851	0	0
T39	0	50	0	0
T42	0	32	0	0
T43	0	47	0	0
T44	0	84	0	0
T61	743	0	0	0
T64	0	101	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T117	0	52	0	0
T120	0	353	0	0
T277	0	294	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	277	0	0
T10	12010	1	0	0
T11	510	0	0	0
T30	724	0	0	0
T38	0	10	0	0
T39	0	1	0	0
T42	0	4	0	0
T43	0	5	0	0
T44	0	1	0	0
T61	743	0	0	0
T64	0	1	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T117	0	4	0	0
T120	0	4	0	0
T277	0	8	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5848090	0	0
T1	822	421	0	0
T4	513	112	0	0
T5	442	41	0	0
T6	429	28	0	0
T14	453	52	0	0
T15	489	88	0	0
T16	487	86	0	0
T22	1040	639	0	0
T26	527	126	0	0
T36	423	22	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	5849413	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	377	0	0
T10	12010	2	0	0
T11	510	0	0	0
T30	724	0	0	0
T35	0	9	0	0
T38	0	11	0	0
T39	0	1	0	0
T40	0	6	0	0
T42	0	5	0	0
T43	0	6	0	0
T44	0	5	0	0
T61	743	0	0	0
T64	0	5	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T108	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	328	0	0
T10	12010	1	0	0
T11	510	0	0	0
T30	724	0	0	0
T35	0	8	0	0
T38	0	10	0	0
T39	0	1	0	0
T40	0	6	0	0
T42	0	4	0	0
T43	0	5	0	0
T44	0	3	0	0
T61	743	0	0	0
T64	0	3	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T108	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	277	0	0
T10	12010	1	0	0
T11	510	0	0	0
T30	724	0	0	0
T38	0	10	0	0
T39	0	1	0	0
T42	0	4	0	0
T43	0	5	0	0
T44	0	1	0	0
T61	743	0	0	0
T64	0	1	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T117	0	4	0	0
T120	0	4	0	0
T277	0	8	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	277	0	0
T10	12010	1	0	0
T11	510	0	0	0
T30	724	0	0	0
T38	0	10	0	0
T39	0	1	0	0
T42	0	4	0	0
T43	0	5	0	0
T44	0	1	0	0
T61	743	0	0	0
T64	0	1	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T117	0	4	0	0
T120	0	4	0	0
T277	0	8	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	13512	0	0
T10	12010	36	0	0
T11	510	0	0	0
T30	724	0	0	0
T38	0	841	0	0
T39	0	49	0	0
T42	0	28	0	0
T43	0	42	0	0
T44	0	83	0	0
T61	743	0	0	0
T64	0	100	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T117	0	48	0	0
T120	0	349	0	0
T277	0	286	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	6188948	0	0
T1	822	422	0	0
T4	513	113	0	0
T5	442	42	0	0
T6	429	29	0	0
T14	453	53	0	0
T15	489	89	0	0
T16	487	87	0	0
T22	1040	640	0	0
T26	527	127	0	0
T36	423	23	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	6668985	245	0	0
T10	12010	1	0	0
T11	510	0	0	0
T30	724	0	0	0
T38	0	10	0	0
T39	0	1	0	0
T42	0	4	0	0
T43	0	5	0	0
T61	743	0	0	0
T78	495	0	0	0
T84	522	0	0	0
T85	523	0	0	0
T96	421	0	0	0
T97	430	0	0	0
T98	772	0	0	0
T117	0	4	0	0
T120	0	4	0	0
T218	0	5	0	0
T264	0	5	0	0
T277	0	8	0	0