| T225 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1334809888 |
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Aug 27 07:32:24 PM UTC 24 |
Aug 27 07:32:37 PM UTC 24 |
3644433121 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.2529490909 |
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Aug 27 07:31:16 PM UTC 24 |
Aug 27 07:32:38 PM UTC 24 |
16571048969 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3555323638 |
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Aug 27 07:32:37 PM UTC 24 |
Aug 27 07:32:41 PM UTC 24 |
2131194217 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.2484903262 |
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Aug 27 07:32:37 PM UTC 24 |
Aug 27 07:32:41 PM UTC 24 |
2033191228 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.1328405629 |
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Aug 27 07:32:38 PM UTC 24 |
Aug 27 07:32:41 PM UTC 24 |
2147372482 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2207228304 |
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Aug 27 07:32:25 PM UTC 24 |
Aug 27 07:32:43 PM UTC 24 |
3237991424 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.1797289554 |
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Aug 27 07:32:38 PM UTC 24 |
Aug 27 07:32:43 PM UTC 24 |
2459434036 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2301301136 |
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Aug 27 07:31:35 PM UTC 24 |
Aug 27 07:32:45 PM UTC 24 |
67980584436 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.3808351261 |
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Aug 27 07:32:39 PM UTC 24 |
Aug 27 07:32:45 PM UTC 24 |
2519391668 ps |
| T445 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2012680114 |
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Aug 27 07:32:41 PM UTC 24 |
Aug 27 07:32:47 PM UTC 24 |
2638341935 ps |
| T322 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.3179697968 |
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Aug 27 07:32:34 PM UTC 24 |
Aug 27 07:32:48 PM UTC 24 |
10904341304 ps |
| T181 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1821588442 |
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Aug 27 07:32:28 PM UTC 24 |
Aug 27 07:32:48 PM UTC 24 |
3701360893 ps |
| T107 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.3740898040 |
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Aug 27 07:32:44 PM UTC 24 |
Aug 27 07:32:49 PM UTC 24 |
4416724256 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1069408419 |
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Aug 27 07:32:29 PM UTC 24 |
Aug 27 07:32:50 PM UTC 24 |
3641803670 ps |
| T447 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.483480772 |
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Aug 27 07:32:43 PM UTC 24 |
Aug 27 07:32:50 PM UTC 24 |
3305621232 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.700605296 |
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Aug 27 07:32:46 PM UTC 24 |
Aug 27 07:32:53 PM UTC 24 |
4424454907 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.3288576662 |
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Aug 27 07:33:15 PM UTC 24 |
Aug 27 07:33:26 PM UTC 24 |
5945250187 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.4229100454 |
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Aug 27 07:32:41 PM UTC 24 |
Aug 27 07:32:53 PM UTC 24 |
3366716577 ps |
| T210 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.1931217630 |
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Aug 27 07:32:13 PM UTC 24 |
Aug 27 07:32:53 PM UTC 24 |
9276781370 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.132120733 |
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Aug 27 07:32:50 PM UTC 24 |
Aug 27 07:32:54 PM UTC 24 |
2037711079 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.3696153936 |
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Aug 27 07:27:19 PM UTC 24 |
Aug 27 07:32:54 PM UTC 24 |
177484762112 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.2897650953 |
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Aug 27 07:32:51 PM UTC 24 |
Aug 27 07:32:55 PM UTC 24 |
2489817789 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.291025783 |
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Aug 27 07:32:50 PM UTC 24 |
Aug 27 07:32:56 PM UTC 24 |
2120451868 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3751868244 |
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Aug 27 07:32:51 PM UTC 24 |
Aug 27 07:32:56 PM UTC 24 |
2233925721 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.278627584 |
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Aug 27 07:32:54 PM UTC 24 |
Aug 27 07:32:58 PM UTC 24 |
2636211985 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.531215778 |
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Aug 27 07:32:49 PM UTC 24 |
Aug 27 07:32:59 PM UTC 24 |
12335774660 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.605699856 |
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Aug 27 07:32:53 PM UTC 24 |
Aug 27 07:32:59 PM UTC 24 |
2528895264 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.20434524 |
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Aug 27 07:32:56 PM UTC 24 |
Aug 27 07:33:00 PM UTC 24 |
6010936776 ps |
| T449 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.428836607 |
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Aug 27 07:33:00 PM UTC 24 |
Aug 27 07:33:03 PM UTC 24 |
2178966903 ps |
| T265 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1057131414 |
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Aug 27 07:30:53 PM UTC 24 |
Aug 27 07:33:04 PM UTC 24 |
88198617913 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1475896520 |
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Aug 27 07:32:55 PM UTC 24 |
Aug 27 07:33:06 PM UTC 24 |
3313174930 ps |
| T324 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.4040245997 |
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Aug 27 07:33:02 PM UTC 24 |
Aug 27 07:33:10 PM UTC 24 |
2475411299 ps |
| T451 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.3471692287 |
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Aug 27 07:33:05 PM UTC 24 |
Aug 27 07:33:10 PM UTC 24 |
2530786222 ps |
| T452 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.2891061911 |
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Aug 27 07:32:59 PM UTC 24 |
Aug 27 07:33:12 PM UTC 24 |
2015002355 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1874180499 |
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Aug 27 07:32:58 PM UTC 24 |
Aug 27 07:33:13 PM UTC 24 |
5171388700 ps |
| T453 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3420851797 |
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Aug 27 07:33:07 PM UTC 24 |
Aug 27 07:33:14 PM UTC 24 |
2619806191 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3427891832 |
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Aug 27 07:33:12 PM UTC 24 |
Aug 27 07:33:16 PM UTC 24 |
3652019432 ps |
| T454 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.959837862 |
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Aug 27 07:33:04 PM UTC 24 |
Aug 27 07:33:16 PM UTC 24 |
2061935470 ps |
| T455 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2278038722 |
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Aug 27 07:33:10 PM UTC 24 |
Aug 27 07:33:22 PM UTC 24 |
3702819514 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3992763663 |
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Aug 27 07:27:34 PM UTC 24 |
Aug 27 07:33:22 PM UTC 24 |
96646786492 ps |
| T456 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.4144305015 |
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Aug 27 07:33:23 PM UTC 24 |
Aug 27 07:33:31 PM UTC 24 |
2012501856 ps |
| T267 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1337660811 |
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Aug 27 07:32:10 PM UTC 24 |
Aug 27 07:33:28 PM UTC 24 |
110058847955 ps |
| T457 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1164072326 |
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Aug 27 07:33:13 PM UTC 24 |
Aug 27 07:33:28 PM UTC 24 |
5779368317 ps |
| T269 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1597439833 |
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Aug 27 07:31:16 PM UTC 24 |
Aug 27 07:33:30 PM UTC 24 |
43392830096 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3385727155 |
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Aug 27 07:33:17 PM UTC 24 |
Aug 27 07:33:31 PM UTC 24 |
9329506758 ps |
| T458 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.319778464 |
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Aug 27 07:33:29 PM UTC 24 |
Aug 27 07:33:32 PM UTC 24 |
2102825792 ps |
| T459 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.1304864806 |
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Aug 27 07:33:29 PM UTC 24 |
Aug 27 07:33:32 PM UTC 24 |
2590264631 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.31473076 |
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Aug 27 07:32:55 PM UTC 24 |
Aug 27 07:33:33 PM UTC 24 |
2484096823956 ps |
| T460 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.1349470698 |
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Aug 27 07:33:27 PM UTC 24 |
Aug 27 07:33:33 PM UTC 24 |
2491642687 ps |
| T461 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.1293634390 |
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Aug 27 07:33:23 PM UTC 24 |
Aug 27 07:33:34 PM UTC 24 |
2109784119 ps |
| T462 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1972165318 |
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Aug 27 07:33:31 PM UTC 24 |
Aug 27 07:33:36 PM UTC 24 |
2625422225 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.876603247 |
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Aug 27 07:32:59 PM UTC 24 |
Aug 27 07:33:38 PM UTC 24 |
16195615551 ps |
| T463 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3376859159 |
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Aug 27 07:33:33 PM UTC 24 |
Aug 27 07:33:40 PM UTC 24 |
5323888044 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1037738439 |
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Aug 27 07:33:34 PM UTC 24 |
Aug 27 07:33:41 PM UTC 24 |
4315220728 ps |
| T297 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2878030751 |
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Aug 27 07:33:35 PM UTC 24 |
Aug 27 07:33:41 PM UTC 24 |
6919150627 ps |
| T464 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.3301109445 |
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Aug 27 07:33:40 PM UTC 24 |
Aug 27 07:33:45 PM UTC 24 |
2129920355 ps |
| T465 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.1147689883 |
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Aug 27 07:33:42 PM UTC 24 |
Aug 27 07:33:45 PM UTC 24 |
2483932928 ps |
| T333 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.1560942489 |
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Aug 27 07:32:07 PM UTC 24 |
Aug 27 07:33:46 PM UTC 24 |
120683807927 ps |
| T207 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2340490329 |
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Aug 27 07:33:37 PM UTC 24 |
Aug 27 07:33:47 PM UTC 24 |
10644099772 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1294714978 |
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Aug 27 07:30:21 PM UTC 24 |
Aug 27 07:33:47 PM UTC 24 |
2116347424224 ps |
| T466 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3495342811 |
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Aug 27 07:33:19 PM UTC 24 |
Aug 27 07:33:47 PM UTC 24 |
11224295138 ps |
| T467 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.738161209 |
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Aug 27 07:33:38 PM UTC 24 |
Aug 27 07:33:47 PM UTC 24 |
2013679112 ps |
| T468 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.3445358444 |
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Aug 27 07:33:46 PM UTC 24 |
Aug 27 07:33:52 PM UTC 24 |
2528930160 ps |
| T469 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.855317885 |
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Aug 27 07:33:33 PM UTC 24 |
Aug 27 07:33:53 PM UTC 24 |
3366570909 ps |
| T470 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2362346555 |
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Aug 27 07:33:46 PM UTC 24 |
Aug 27 07:33:54 PM UTC 24 |
2619890006 ps |
| T471 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.2352545855 |
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Aug 27 07:33:42 PM UTC 24 |
Aug 27 07:33:56 PM UTC 24 |
2173093683 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.131949015 |
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Aug 27 07:33:35 PM UTC 24 |
Aug 27 07:33:58 PM UTC 24 |
42374493905 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1990622849 |
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Aug 27 07:33:49 PM UTC 24 |
Aug 27 07:33:59 PM UTC 24 |
7535938537 ps |
| T472 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.2383857405 |
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Aug 27 07:33:55 PM UTC 24 |
Aug 27 07:33:59 PM UTC 24 |
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| T473 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2270998132 |
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Aug 27 07:32:55 PM UTC 24 |
Aug 27 07:33:59 PM UTC 24 |
91909430734 ps |
| T268 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3723936132 |
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Aug 27 07:31:51 PM UTC 24 |
Aug 27 07:34:00 PM UTC 24 |
31162808659 ps |
| T474 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.22938075 |
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Aug 27 07:33:57 PM UTC 24 |
Aug 27 07:34:00 PM UTC 24 |
2131628379 ps |
| T208 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.2671057 |
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Aug 27 07:33:49 PM UTC 24 |
Aug 27 07:34:02 PM UTC 24 |
3675331342 ps |
| T475 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.2309894643 |
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Aug 27 07:33:47 PM UTC 24 |
Aug 27 07:34:04 PM UTC 24 |
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| T476 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1825424929 |
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Aug 27 07:34:02 PM UTC 24 |
Aug 27 07:34:04 PM UTC 24 |
3870189518 ps |
| T209 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.829906425 |
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Aug 27 07:33:54 PM UTC 24 |
Aug 27 07:34:06 PM UTC 24 |
11460367062 ps |
| T477 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.802940476 |
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Aug 27 07:34:02 PM UTC 24 |
Aug 27 07:34:06 PM UTC 24 |
2627768177 ps |
| T478 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.4234235918 |
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Aug 27 07:34:00 PM UTC 24 |
Aug 27 07:34:07 PM UTC 24 |
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| T479 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3827002139 |
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Aug 27 07:34:02 PM UTC 24 |
Aug 27 07:34:08 PM UTC 24 |
5138787294 ps |
| T480 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.3258967019 |
|
|
Aug 27 07:34:00 PM UTC 24 |
Aug 27 07:34:10 PM UTC 24 |
2465097670 ps |
| T167 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3313779499 |
|
|
Aug 27 07:34:04 PM UTC 24 |
Aug 27 07:34:10 PM UTC 24 |
4127055936 ps |
| T481 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.4250549841 |
|
|
Aug 27 07:34:00 PM UTC 24 |
Aug 27 07:34:11 PM UTC 24 |
2090364826 ps |
| T482 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2910394554 |
|
|
Aug 27 07:33:53 PM UTC 24 |
Aug 27 07:34:11 PM UTC 24 |
13143537135 ps |
| T483 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.4035711906 |
|
|
Aug 27 07:34:10 PM UTC 24 |
Aug 27 07:34:12 PM UTC 24 |
2248657298 ps |
| T484 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.861683213 |
|
|
Aug 27 07:27:52 PM UTC 24 |
Aug 27 07:34:13 PM UTC 24 |
231828987477 ps |
| T485 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.3734408 |
|
|
Aug 27 07:34:08 PM UTC 24 |
Aug 27 07:34:13 PM UTC 24 |
2484858402 ps |
| T486 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.2799344162 |
|
|
Aug 27 07:34:08 PM UTC 24 |
Aug 27 07:34:15 PM UTC 24 |
2119583959 ps |
| T487 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.462117221 |
|
|
Aug 27 07:34:07 PM UTC 24 |
Aug 27 07:34:15 PM UTC 24 |
2011516598 ps |
| T488 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2439317145 |
|
|
Aug 27 07:34:13 PM UTC 24 |
Aug 27 07:34:16 PM UTC 24 |
4401444032 ps |
| T292 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3351469793 |
|
|
Aug 27 07:33:14 PM UTC 24 |
Aug 27 07:34:17 PM UTC 24 |
81475147818 ps |
| T489 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2690442272 |
|
|
Aug 27 07:33:52 PM UTC 24 |
Aug 27 07:34:17 PM UTC 24 |
33617660711 ps |
| T490 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.4253166279 |
|
|
Aug 27 07:34:14 PM UTC 24 |
Aug 27 07:34:19 PM UTC 24 |
2886237610 ps |
| T365 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.230795946 |
|
|
Aug 27 07:32:28 PM UTC 24 |
Aug 27 07:34:20 PM UTC 24 |
72446223959 ps |
| T491 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2424867858 |
|
|
Aug 27 07:34:18 PM UTC 24 |
Aug 27 07:34:21 PM UTC 24 |
2042372038 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.4252853175 |
|
|
Aug 27 07:32:58 PM UTC 24 |
Aug 27 07:34:21 PM UTC 24 |
28830356435 ps |
| T492 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2742084318 |
|
|
Aug 27 07:34:06 PM UTC 24 |
Aug 27 07:34:22 PM UTC 24 |
9757750791 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.580970504 |
|
|
Aug 27 07:32:26 PM UTC 24 |
Aug 27 07:34:23 PM UTC 24 |
38218059387 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.872064471 |
|
|
Aug 27 07:34:13 PM UTC 24 |
Aug 27 07:34:23 PM UTC 24 |
3188702069 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.743581209 |
|
|
Aug 27 07:34:04 PM UTC 24 |
Aug 27 07:34:24 PM UTC 24 |
62355657218 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1105319964 |
|
|
Aug 27 07:34:21 PM UTC 24 |
Aug 27 07:34:25 PM UTC 24 |
2271362617 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.4161833981 |
|
|
Aug 27 07:34:11 PM UTC 24 |
Aug 27 07:34:25 PM UTC 24 |
2511310932 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.2532818912 |
|
|
Aug 27 07:34:18 PM UTC 24 |
Aug 27 07:34:26 PM UTC 24 |
2113359840 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.4288515868 |
|
|
Aug 27 07:34:11 PM UTC 24 |
Aug 27 07:34:26 PM UTC 24 |
2613214673 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.234507772 |
|
|
Aug 27 07:34:19 PM UTC 24 |
Aug 27 07:34:27 PM UTC 24 |
2457447662 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3348815109 |
|
|
Aug 27 07:34:22 PM UTC 24 |
Aug 27 07:34:28 PM UTC 24 |
2622076343 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1514623382 |
|
|
Aug 27 07:34:25 PM UTC 24 |
Aug 27 07:34:30 PM UTC 24 |
4352972842 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.4184126693 |
|
|
Aug 27 07:34:13 PM UTC 24 |
Aug 27 07:34:30 PM UTC 24 |
3312723927 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2864165575 |
|
|
Aug 27 07:34:25 PM UTC 24 |
Aug 27 07:34:31 PM UTC 24 |
3384822702 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2636078952 |
|
|
Aug 27 07:34:26 PM UTC 24 |
Aug 27 07:34:32 PM UTC 24 |
3266665004 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.456504829 |
|
|
Aug 27 07:33:33 PM UTC 24 |
Aug 27 07:34:33 PM UTC 24 |
146476370707 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.2671683972 |
|
|
Aug 27 07:34:28 PM UTC 24 |
Aug 27 07:34:33 PM UTC 24 |
2042611782 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.745899544 |
|
|
Aug 27 07:34:17 PM UTC 24 |
Aug 27 07:34:33 PM UTC 24 |
10561667491 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.2780532829 |
|
|
Aug 27 07:34:22 PM UTC 24 |
Aug 27 07:34:35 PM UTC 24 |
2511372108 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.3668285095 |
|
|
Aug 27 07:34:32 PM UTC 24 |
Aug 27 07:34:35 PM UTC 24 |
2507500273 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.2381528576 |
|
|
Aug 27 07:34:17 PM UTC 24 |
Aug 27 07:34:36 PM UTC 24 |
17286717225 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.3412069961 |
|
|
Aug 27 07:34:29 PM UTC 24 |
Aug 27 07:34:37 PM UTC 24 |
2116687087 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.647906662 |
|
|
Aug 27 07:34:34 PM UTC 24 |
Aug 27 07:34:38 PM UTC 24 |
3681772641 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1839863507 |
|
|
Aug 27 07:34:22 PM UTC 24 |
Aug 27 07:34:38 PM UTC 24 |
3649686525 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.3686903335 |
|
|
Aug 27 07:34:33 PM UTC 24 |
Aug 27 07:34:38 PM UTC 24 |
2528531401 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3520635104 |
|
|
Aug 27 07:32:46 PM UTC 24 |
Aug 27 07:34:39 PM UTC 24 |
230419788187 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3331198559 |
|
|
Aug 27 07:34:27 PM UTC 24 |
Aug 27 07:34:39 PM UTC 24 |
63023497941 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.423882208 |
|
|
Aug 27 07:34:33 PM UTC 24 |
Aug 27 07:34:40 PM UTC 24 |
2621950975 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.397489998 |
|
|
Aug 27 07:34:38 PM UTC 24 |
Aug 27 07:34:41 PM UTC 24 |
2043811443 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.1672253017 |
|
|
Aug 27 07:34:36 PM UTC 24 |
Aug 27 07:34:42 PM UTC 24 |
4972142549 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3385269593 |
|
|
Aug 27 07:34:40 PM UTC 24 |
Aug 27 07:34:43 PM UTC 24 |
2161174153 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.3013746494 |
|
|
Aug 27 07:34:40 PM UTC 24 |
Aug 27 07:34:43 PM UTC 24 |
2540861160 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.1381800301 |
|
|
Aug 27 07:34:32 PM UTC 24 |
Aug 27 07:34:46 PM UTC 24 |
2134057695 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3399963693 |
|
|
Aug 27 07:34:41 PM UTC 24 |
Aug 27 07:34:46 PM UTC 24 |
2630466091 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.1207518537 |
|
|
Aug 27 07:30:23 PM UTC 24 |
Aug 27 07:34:46 PM UTC 24 |
1176703304402 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2795362507 |
|
|
Aug 27 07:34:35 PM UTC 24 |
Aug 27 07:34:47 PM UTC 24 |
8598205526 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2810109185 |
|
|
Aug 27 07:34:40 PM UTC 24 |
Aug 27 07:34:48 PM UTC 24 |
2195209380 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2100848744 |
|
|
Aug 27 07:34:41 PM UTC 24 |
Aug 27 07:34:48 PM UTC 24 |
3631536010 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.743307767 |
|
|
Aug 27 07:34:44 PM UTC 24 |
Aug 27 07:34:49 PM UTC 24 |
8725993594 ps |
| T200 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.647341521 |
|
|
Aug 27 07:34:44 PM UTC 24 |
Aug 27 07:34:49 PM UTC 24 |
2399786844 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.430759665 |
|
|
Aug 27 07:34:42 PM UTC 24 |
Aug 27 07:34:50 PM UTC 24 |
3394054787 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.4231428714 |
|
|
Aug 27 07:34:50 PM UTC 24 |
Aug 27 07:34:52 PM UTC 24 |
2603673849 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.2720907211 |
|
|
Aug 27 07:34:49 PM UTC 24 |
Aug 27 07:34:53 PM UTC 24 |
2499307182 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1650811798 |
|
|
Aug 27 07:34:50 PM UTC 24 |
Aug 27 07:34:54 PM UTC 24 |
2161423017 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2104396864 |
|
|
Aug 27 07:34:51 PM UTC 24 |
Aug 27 07:34:56 PM UTC 24 |
2623806100 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.1968862236 |
|
|
Aug 27 07:34:41 PM UTC 24 |
Aug 27 07:34:56 PM UTC 24 |
2514276267 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.4002966252 |
|
|
Aug 27 07:34:49 PM UTC 24 |
Aug 27 07:34:57 PM UTC 24 |
2109227151 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.3200542392 |
|
|
Aug 27 07:34:07 PM UTC 24 |
Aug 27 07:34:58 PM UTC 24 |
855071361238 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3487128967 |
|
|
Aug 27 07:34:55 PM UTC 24 |
Aug 27 07:34:59 PM UTC 24 |
5313418694 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.4250531740 |
|
|
Aug 27 07:34:48 PM UTC 24 |
Aug 27 07:35:00 PM UTC 24 |
2010867951 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.3834252724 |
|
|
Aug 27 07:34:52 PM UTC 24 |
Aug 27 07:35:04 PM UTC 24 |
3433009959 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.1037109968 |
|
|
Aug 27 07:34:48 PM UTC 24 |
Aug 27 07:35:04 PM UTC 24 |
18323928054 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1038819966 |
|
|
Aug 27 07:34:57 PM UTC 24 |
Aug 27 07:35:05 PM UTC 24 |
2969087804 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.955081689 |
|
|
Aug 27 07:34:38 PM UTC 24 |
Aug 27 07:35:05 PM UTC 24 |
5154473220 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1795150901 |
|
|
Aug 27 07:35:01 PM UTC 24 |
Aug 27 07:35:05 PM UTC 24 |
2131473733 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.1286642594 |
|
|
Aug 27 07:35:00 PM UTC 24 |
Aug 27 07:35:08 PM UTC 24 |
2011653161 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2872913383 |
|
|
Aug 27 07:34:48 PM UTC 24 |
Aug 27 07:35:09 PM UTC 24 |
5044203807 ps |
| T176 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.2243617271 |
|
|
Aug 27 07:35:04 PM UTC 24 |
Aug 27 07:35:09 PM UTC 24 |
2492205884 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.3401014986 |
|
|
Aug 27 07:35:06 PM UTC 24 |
Aug 27 07:35:11 PM UTC 24 |
2528325744 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3752945703 |
|
|
Aug 27 07:34:58 PM UTC 24 |
Aug 27 07:35:12 PM UTC 24 |
16909865805 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.4172560089 |
|
|
Aug 27 07:34:38 PM UTC 24 |
Aug 27 07:35:12 PM UTC 24 |
11917825097 ps |
| T180 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3802521964 |
|
|
Aug 27 07:35:07 PM UTC 24 |
Aug 27 07:35:12 PM UTC 24 |
2633120550 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.64795099 |
|
|
Aug 27 07:33:49 PM UTC 24 |
Aug 27 07:35:12 PM UTC 24 |
45232050765 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.28254381 |
|
|
Aug 27 07:35:06 PM UTC 24 |
Aug 27 07:35:14 PM UTC 24 |
2245138802 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1828457319 |
|
|
Aug 27 07:35:10 PM UTC 24 |
Aug 27 07:35:16 PM UTC 24 |
3856584111 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.4170977079 |
|
|
Aug 27 07:35:15 PM UTC 24 |
Aug 27 07:35:18 PM UTC 24 |
2515683134 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.1115452801 |
|
|
Aug 27 07:30:48 PM UTC 24 |
Aug 27 07:35:18 PM UTC 24 |
159494345442 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.914663765 |
|
|
Aug 27 07:35:14 PM UTC 24 |
Aug 27 07:35:19 PM UTC 24 |
2023579761 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.3216838833 |
|
|
Aug 27 07:35:16 PM UTC 24 |
Aug 27 07:35:21 PM UTC 24 |
2250201642 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.619299585 |
|
|
Aug 27 07:34:35 PM UTC 24 |
Aug 27 07:35:21 PM UTC 24 |
14715557971 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2470589553 |
|
|
Aug 27 07:35:10 PM UTC 24 |
Aug 27 07:35:21 PM UTC 24 |
3595967813 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.2546415877 |
|
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Aug 27 07:35:12 PM UTC 24 |
Aug 27 07:35:21 PM UTC 24 |
3530346652 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1014246774 |
|
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Aug 27 07:35:07 PM UTC 24 |
Aug 27 07:35:22 PM UTC 24 |
3643119657 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.3057548924 |
|
|
Aug 27 07:35:19 PM UTC 24 |
Aug 27 07:35:23 PM UTC 24 |
2523035643 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.2181932477 |
|
|
Aug 27 07:35:15 PM UTC 24 |
Aug 27 07:35:26 PM UTC 24 |
2107677232 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3826033571 |
|
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Aug 27 07:35:21 PM UTC 24 |
Aug 27 07:35:26 PM UTC 24 |
3148342952 ps |
| T195 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3455562917 |
|
|
Aug 27 07:35:23 PM UTC 24 |
Aug 27 07:35:29 PM UTC 24 |
4812917372 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2975033233 |
|
|
Aug 27 07:35:20 PM UTC 24 |
Aug 27 07:35:29 PM UTC 24 |
2612409378 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.384728429 |
|
|
Aug 27 07:35:21 PM UTC 24 |
Aug 27 07:35:31 PM UTC 24 |
9325111992 ps |
| T317 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1123294716 |
|
|
Aug 27 07:35:14 PM UTC 24 |
Aug 27 07:35:32 PM UTC 24 |
8247845124 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.499735449 |
|
|
Aug 27 07:35:28 PM UTC 24 |
Aug 27 07:35:32 PM UTC 24 |
2023533715 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.4107257630 |
|
|
Aug 27 07:34:44 PM UTC 24 |
Aug 27 07:35:32 PM UTC 24 |
63729404782 ps |
| T293 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.1824528626 |
|
|
Aug 27 07:33:33 PM UTC 24 |
Aug 27 07:35:33 PM UTC 24 |
139465845496 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2218288160 |
|
|
Aug 27 07:35:20 PM UTC 24 |
Aug 27 07:35:34 PM UTC 24 |
2587793534 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.485463586 |
|
|
Aug 27 07:35:30 PM UTC 24 |
Aug 27 07:35:36 PM UTC 24 |
2482819859 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.3739091750 |
|
|
Aug 27 07:35:29 PM UTC 24 |
Aug 27 07:35:36 PM UTC 24 |
2119623095 ps |
| T332 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2482273263 |
|
|
Aug 27 07:34:36 PM UTC 24 |
Aug 27 07:35:36 PM UTC 24 |
31099393789 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.137521177 |
|
|
Aug 27 07:34:55 PM UTC 24 |
Aug 27 07:35:37 PM UTC 24 |
52850661265 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1256288845 |
|
|
Aug 27 07:35:24 PM UTC 24 |
Aug 27 07:35:38 PM UTC 24 |
3892931366 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2901575330 |
|
|
Aug 27 07:35:32 PM UTC 24 |
Aug 27 07:35:39 PM UTC 24 |
2520702579 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.1946587218 |
|
|
Aug 27 07:35:14 PM UTC 24 |
Aug 27 07:35:39 PM UTC 24 |
11273702579 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2395865153 |
|
|
Aug 27 07:35:35 PM UTC 24 |
Aug 27 07:35:41 PM UTC 24 |
12046568981 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1488871640 |
|
|
Aug 27 07:35:39 PM UTC 24 |
Aug 27 07:35:41 PM UTC 24 |
2071846994 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1955604372 |
|
|
Aug 27 07:35:33 PM UTC 24 |
Aug 27 07:35:42 PM UTC 24 |
3559805590 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1686825186 |
|
|
Aug 27 07:35:35 PM UTC 24 |
Aug 27 07:35:42 PM UTC 24 |
3844111088 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.3107974201 |
|
|
Aug 27 07:35:30 PM UTC 24 |
Aug 27 07:35:43 PM UTC 24 |
2050099088 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.1827669219 |
|
|
Aug 27 07:35:40 PM UTC 24 |
Aug 27 07:35:44 PM UTC 24 |
2502547625 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.1152494744 |
|
|
Aug 27 07:35:40 PM UTC 24 |
Aug 27 07:35:44 PM UTC 24 |
2130258244 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2374344975 |
|
|
Aug 27 07:35:43 PM UTC 24 |
Aug 27 07:35:45 PM UTC 24 |
2276374858 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.4101781022 |
|
|
Aug 27 07:35:43 PM UTC 24 |
Aug 27 07:35:47 PM UTC 24 |
2529499134 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.2293402892 |
|
|
Aug 27 07:35:37 PM UTC 24 |
Aug 27 07:35:47 PM UTC 24 |
3912647369 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.594851378 |
|
|
Aug 27 07:35:43 PM UTC 24 |
Aug 27 07:35:47 PM UTC 24 |
2483044889 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2623086928 |
|
|
Aug 27 07:35:44 PM UTC 24 |
Aug 27 07:35:48 PM UTC 24 |
9365376929 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.470144547 |
|
|
Aug 27 07:35:33 PM UTC 24 |
Aug 27 07:35:48 PM UTC 24 |
2609691720 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2687130911 |
|
|
Aug 27 07:35:38 PM UTC 24 |
Aug 27 07:35:49 PM UTC 24 |
9419635373 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.687094273 |
|
|
Aug 27 07:35:44 PM UTC 24 |
Aug 27 07:35:50 PM UTC 24 |
3511549239 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.2037198420 |
|
|
Aug 27 07:35:00 PM UTC 24 |
Aug 27 07:35:50 PM UTC 24 |
59023827717 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.862747751 |
|
|
Aug 27 07:35:50 PM UTC 24 |
Aug 27 07:35:54 PM UTC 24 |
2136116346 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.1518869482 |
|
|
Aug 27 07:35:50 PM UTC 24 |
Aug 27 07:35:55 PM UTC 24 |
2139654265 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3776040601 |
|
|
Aug 27 07:33:17 PM UTC 24 |
Aug 27 07:35:55 PM UTC 24 |
46047921648 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.4105218457 |
|
|
Aug 27 07:35:49 PM UTC 24 |
Aug 27 07:35:55 PM UTC 24 |
2023582404 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.2486571914 |
|
|
Aug 27 07:35:52 PM UTC 24 |
Aug 27 07:35:57 PM UTC 24 |
2522570821 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2938363325 |
|
|
Aug 27 07:35:43 PM UTC 24 |
Aug 27 07:35:59 PM UTC 24 |
2613206110 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.759062645 |
|
|
Aug 27 07:35:50 PM UTC 24 |
Aug 27 07:36:00 PM UTC 24 |
2479079900 ps |
| T318 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.166516803 |
|
|
Aug 27 07:35:49 PM UTC 24 |
Aug 27 07:36:00 PM UTC 24 |
13091955352 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.783107633 |
|
|
Aug 27 07:35:56 PM UTC 24 |
Aug 27 07:36:02 PM UTC 24 |
3465255746 ps |
| T211 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.356349592 |
|
|
Aug 27 07:35:47 PM UTC 24 |
Aug 27 07:36:02 PM UTC 24 |
3008396822 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3154921652 |
|
|
Aug 27 07:35:56 PM UTC 24 |
Aug 27 07:36:04 PM UTC 24 |
2731189046 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.3881689023 |
|
|
Aug 27 07:36:04 PM UTC 24 |
Aug 27 07:36:07 PM UTC 24 |
2038963204 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3462628297 |
|
|
Aug 27 07:35:56 PM UTC 24 |
Aug 27 07:36:07 PM UTC 24 |
3170784639 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.4044114787 |
|
|
Aug 27 07:35:55 PM UTC 24 |
Aug 27 07:36:08 PM UTC 24 |
2610853978 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.3963593692 |
|
|
Aug 27 07:36:06 PM UTC 24 |
Aug 27 07:36:13 PM UTC 24 |
2114882148 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3305863253 |
|
|
Aug 27 07:34:53 PM UTC 24 |
Aug 27 07:36:16 PM UTC 24 |
54721076301 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.252330208 |
|
|
Aug 27 07:36:08 PM UTC 24 |
Aug 27 07:36:16 PM UTC 24 |
2154079546 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.1537609477 |
|
|
Aug 27 07:36:08 PM UTC 24 |
Aug 27 07:36:18 PM UTC 24 |
2478531981 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2217544061 |
|
|
Aug 27 07:35:37 PM UTC 24 |
Aug 27 07:36:18 PM UTC 24 |
24590106968 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.3574951491 |
|
|
Aug 27 07:36:01 PM UTC 24 |
Aug 27 07:36:20 PM UTC 24 |
4366102772 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.149787893 |
|
|
Aug 27 07:36:17 PM UTC 24 |
Aug 27 07:36:22 PM UTC 24 |
3409521415 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.127083858 |
|
|
Aug 27 07:36:18 PM UTC 24 |
Aug 27 07:36:22 PM UTC 24 |
6894888016 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3510236129 |
|
|
Aug 27 07:36:15 PM UTC 24 |
Aug 27 07:36:23 PM UTC 24 |
2622975033 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.757060629 |
|
|
Aug 27 07:32:44 PM UTC 24 |
Aug 27 07:36:23 PM UTC 24 |
185592407130 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.4020082557 |
|
|
Aug 27 07:36:09 PM UTC 24 |
Aug 27 07:36:23 PM UTC 24 |
2511010687 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2553608288 |
|
|
Aug 27 07:36:17 PM UTC 24 |
Aug 27 07:36:25 PM UTC 24 |
3876920130 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.1468002098 |
|
|
Aug 27 07:36:25 PM UTC 24 |
Aug 27 07:36:28 PM UTC 24 |
2522068695 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.2803167686 |
|
|
Aug 27 07:36:25 PM UTC 24 |
Aug 27 07:36:29 PM UTC 24 |
2117274194 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3705946331 |
|
|
Aug 27 07:36:01 PM UTC 24 |
Aug 27 07:36:30 PM UTC 24 |
30926274772 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.2429639090 |
|
|
Aug 27 07:35:38 PM UTC 24 |
Aug 27 07:36:32 PM UTC 24 |
16647244088 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.4280935304 |
|
|
Aug 27 07:36:26 PM UTC 24 |
Aug 27 07:36:33 PM UTC 24 |
2039851159 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.987219442 |
|
|
Aug 27 07:36:30 PM UTC 24 |
Aug 27 07:36:35 PM UTC 24 |
2625918251 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.766806988 |
|
|
Aug 27 07:36:25 PM UTC 24 |
Aug 27 07:36:35 PM UTC 24 |
2014062126 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.1121102623 |
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Aug 27 07:36:22 PM UTC 24 |
Aug 27 07:36:37 PM UTC 24 |
2656707137 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3980966830 |
|
|
Aug 27 07:36:33 PM UTC 24 |
Aug 27 07:36:37 PM UTC 24 |
3240568259 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1693905703 |
|
|
Aug 27 07:34:46 PM UTC 24 |
Aug 27 07:36:39 PM UTC 24 |
71175366067 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3572087586 |
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Aug 27 07:36:23 PM UTC 24 |
Aug 27 07:36:39 PM UTC 24 |
13379658711 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.21231151 |
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Aug 27 07:36:28 PM UTC 24 |
Aug 27 07:36:39 PM UTC 24 |
2511694447 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.2508444109 |
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Aug 27 07:36:36 PM UTC 24 |
Aug 27 07:36:41 PM UTC 24 |
3645639906 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.4057244548 |
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Aug 27 07:36:34 PM UTC 24 |
Aug 27 07:36:45 PM UTC 24 |
12677819632 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2046440601 |
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Aug 27 07:36:20 PM UTC 24 |
Aug 27 07:36:47 PM UTC 24 |
76106716446 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.18735670 |
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Aug 27 07:34:14 PM UTC 24 |
Aug 27 07:36:47 PM UTC 24 |
176299962560 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.152105992 |
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Aug 27 07:36:40 PM UTC 24 |
Aug 27 07:36:47 PM UTC 24 |
2455175726 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.2822874195 |
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Aug 27 07:36:40 PM UTC 24 |
Aug 27 07:36:48 PM UTC 24 |
2115159841 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.2700379672 |
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Aug 27 07:36:40 PM UTC 24 |
Aug 27 07:36:49 PM UTC 24 |
2014223748 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2642718179 |
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Aug 27 07:36:37 PM UTC 24 |
Aug 27 07:36:49 PM UTC 24 |
2143161921 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.83989114 |
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Aug 27 07:36:41 PM UTC 24 |
Aug 27 07:36:49 PM UTC 24 |
2036919427 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2150378155 |
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Aug 27 07:36:37 PM UTC 24 |
Aug 27 07:36:50 PM UTC 24 |
24142588981 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2725257039 |
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Aug 27 07:36:31 PM UTC 24 |
Aug 27 07:36:51 PM UTC 24 |
4760462214 ps |