| T582 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.397029482 |
|
|
Aug 27 07:36:48 PM UTC 24 |
Aug 27 07:36:51 PM UTC 24 |
2672105143 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.2651431366 |
|
|
Aug 27 07:36:25 PM UTC 24 |
Aug 27 07:36:53 PM UTC 24 |
15352041829 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3794316989 |
|
|
Aug 27 07:36:50 PM UTC 24 |
Aug 27 07:36:55 PM UTC 24 |
6880115764 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1767501502 |
|
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Aug 27 07:36:48 PM UTC 24 |
Aug 27 07:36:55 PM UTC 24 |
3528770430 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.442082178 |
|
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Aug 27 07:36:53 PM UTC 24 |
Aug 27 07:36:56 PM UTC 24 |
2029063164 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.3711410821 |
|
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Aug 27 07:36:47 PM UTC 24 |
Aug 27 07:36:56 PM UTC 24 |
2510394403 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2619593306 |
|
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Aug 27 07:36:54 PM UTC 24 |
Aug 27 07:36:57 PM UTC 24 |
2180398746 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.551752535 |
|
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Aug 27 07:35:14 PM UTC 24 |
Aug 27 07:36:58 PM UTC 24 |
162409670576 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.2020656280 |
|
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Aug 27 07:36:56 PM UTC 24 |
Aug 27 07:37:00 PM UTC 24 |
2141748335 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3891516984 |
|
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Aug 27 07:34:57 PM UTC 24 |
Aug 27 07:37:01 PM UTC 24 |
32163167548 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.2482248437 |
|
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Aug 27 07:36:56 PM UTC 24 |
Aug 27 07:37:01 PM UTC 24 |
2484786378 ps |
| T346 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.2270107648 |
|
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Aug 27 07:35:10 PM UTC 24 |
Aug 27 07:37:02 PM UTC 24 |
114434502238 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1697707858 |
|
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Aug 27 07:36:58 PM UTC 24 |
Aug 27 07:37:02 PM UTC 24 |
2646987070 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.3594713748 |
|
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Aug 27 07:36:58 PM UTC 24 |
Aug 27 07:37:02 PM UTC 24 |
2542625094 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.2148317190 |
|
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Aug 27 07:36:58 PM UTC 24 |
Aug 27 07:37:03 PM UTC 24 |
4340836124 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.689816283 |
|
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Aug 27 07:37:02 PM UTC 24 |
Aug 27 07:37:05 PM UTC 24 |
6611765688 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.547949211 |
|
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Aug 27 07:36:48 PM UTC 24 |
Aug 27 07:37:06 PM UTC 24 |
3477222429 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2821581959 |
|
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Aug 27 07:36:53 PM UTC 24 |
Aug 27 07:37:06 PM UTC 24 |
17714371141 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.1356459291 |
|
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Aug 27 07:36:50 PM UTC 24 |
Aug 27 07:37:07 PM UTC 24 |
2960654288 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.2236162799 |
|
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Aug 27 07:36:39 PM UTC 24 |
Aug 27 07:37:08 PM UTC 24 |
7433479093 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.2296251794 |
|
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Aug 27 07:37:05 PM UTC 24 |
Aug 27 07:37:10 PM UTC 24 |
2026042304 ps |
| T319 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2685394242 |
|
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Aug 27 07:36:51 PM UTC 24 |
Aug 27 07:37:10 PM UTC 24 |
3231686859 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3149904023 |
|
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Aug 27 07:37:10 PM UTC 24 |
Aug 27 07:37:12 PM UTC 24 |
2759750838 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.2589053658 |
|
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Aug 27 07:37:06 PM UTC 24 |
Aug 27 07:37:12 PM UTC 24 |
2118413086 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1604594249 |
|
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Aug 27 07:37:11 PM UTC 24 |
Aug 27 07:37:15 PM UTC 24 |
3389429153 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.755067410 |
|
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Aug 27 07:37:07 PM UTC 24 |
Aug 27 07:37:15 PM UTC 24 |
2469965141 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.994379532 |
|
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Aug 27 07:37:11 PM UTC 24 |
Aug 27 07:37:17 PM UTC 24 |
3997038603 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3479328356 |
|
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Aug 27 07:36:59 PM UTC 24 |
Aug 27 07:37:18 PM UTC 24 |
3327610390 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.593333476 |
|
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Aug 27 07:37:02 PM UTC 24 |
Aug 27 07:37:19 PM UTC 24 |
3522992300 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2894896287 |
|
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Aug 27 07:37:07 PM UTC 24 |
Aug 27 07:37:20 PM UTC 24 |
2237295182 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3010676160 |
|
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Aug 27 07:37:13 PM UTC 24 |
Aug 27 07:37:21 PM UTC 24 |
5985285930 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.58160897 |
|
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Aug 27 07:37:08 PM UTC 24 |
Aug 27 07:37:22 PM UTC 24 |
2511694280 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3847413081 |
|
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Aug 27 07:37:03 PM UTC 24 |
Aug 27 07:37:24 PM UTC 24 |
7773283033 ps |
| T390 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3259945942 |
|
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Aug 27 07:31:10 PM UTC 24 |
Aug 27 07:37:26 PM UTC 24 |
2356172511682 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.501254129 |
|
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Aug 27 07:37:22 PM UTC 24 |
Aug 27 07:37:26 PM UTC 24 |
2126956659 ps |
| T334 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1253983582 |
|
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Aug 27 07:35:49 PM UTC 24 |
Aug 27 07:37:26 PM UTC 24 |
122869240892 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.3461325503 |
|
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Aug 27 07:37:24 PM UTC 24 |
Aug 27 07:37:28 PM UTC 24 |
2747976683 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.285238127 |
|
|
Aug 27 07:37:16 PM UTC 24 |
Aug 27 07:37:28 PM UTC 24 |
3254478417 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.237687744 |
|
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Aug 27 07:36:04 PM UTC 24 |
Aug 27 07:37:28 PM UTC 24 |
92238357486 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.4100025725 |
|
|
Aug 27 07:33:49 PM UTC 24 |
Aug 27 07:37:29 PM UTC 24 |
88619277005 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.1592823518 |
|
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Aug 27 07:37:22 PM UTC 24 |
Aug 27 07:37:32 PM UTC 24 |
2482868050 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3053617590 |
|
|
Aug 27 07:37:26 PM UTC 24 |
Aug 27 07:37:34 PM UTC 24 |
2611864111 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.1695089307 |
|
|
Aug 27 07:37:21 PM UTC 24 |
Aug 27 07:37:34 PM UTC 24 |
2012300804 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.923569041 |
|
|
Aug 27 07:37:18 PM UTC 24 |
Aug 27 07:37:34 PM UTC 24 |
5450895602 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.172466307 |
|
|
Aug 27 07:37:23 PM UTC 24 |
Aug 27 07:37:34 PM UTC 24 |
2042657731 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3845160113 |
|
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Aug 27 07:37:27 PM UTC 24 |
Aug 27 07:37:36 PM UTC 24 |
3046231243 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1048129604 |
|
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Aug 27 07:37:27 PM UTC 24 |
Aug 27 07:37:39 PM UTC 24 |
3548581449 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.2997908520 |
|
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Aug 27 07:37:35 PM UTC 24 |
Aug 27 07:37:39 PM UTC 24 |
2127613063 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.3004168458 |
|
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Aug 27 07:37:35 PM UTC 24 |
Aug 27 07:37:39 PM UTC 24 |
2135862496 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.3224110306 |
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Aug 27 07:37:30 PM UTC 24 |
Aug 27 07:37:40 PM UTC 24 |
3279619685 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2773066664 |
|
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Aug 27 07:37:35 PM UTC 24 |
Aug 27 07:37:41 PM UTC 24 |
2483404882 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.351417120 |
|
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Aug 27 07:37:39 PM UTC 24 |
Aug 27 07:37:42 PM UTC 24 |
2674947527 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.802815216 |
|
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Aug 27 07:37:36 PM UTC 24 |
Aug 27 07:37:42 PM UTC 24 |
2520908444 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.398341086 |
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Aug 27 07:37:35 PM UTC 24 |
Aug 27 07:37:42 PM UTC 24 |
2013531320 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.906007133 |
|
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Aug 27 07:37:03 PM UTC 24 |
Aug 27 07:37:45 PM UTC 24 |
25582028817 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.238162214 |
|
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Aug 27 07:37:17 PM UTC 24 |
Aug 27 07:37:46 PM UTC 24 |
39706893041 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3731948296 |
|
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Aug 27 07:37:40 PM UTC 24 |
Aug 27 07:37:46 PM UTC 24 |
4218355483 ps |
| T303 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2970466458 |
|
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Aug 27 07:37:31 PM UTC 24 |
Aug 27 07:37:49 PM UTC 24 |
6056966619 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1324348881 |
|
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Aug 27 07:38:00 PM UTC 24 |
Aug 27 07:38:03 PM UTC 24 |
2648171635 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.2987233019 |
|
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Aug 27 07:37:47 PM UTC 24 |
Aug 27 07:37:50 PM UTC 24 |
2534231868 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.160508356 |
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Aug 27 07:34:28 PM UTC 24 |
Aug 27 07:37:50 PM UTC 24 |
219764569894 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.2399143180 |
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Aug 27 07:29:54 PM UTC 24 |
Aug 27 07:37:51 PM UTC 24 |
157163812064 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.212477462 |
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Aug 27 07:37:45 PM UTC 24 |
Aug 27 07:37:51 PM UTC 24 |
2019963476 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.4098013064 |
|
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Aug 27 07:37:40 PM UTC 24 |
Aug 27 07:37:53 PM UTC 24 |
7842764819 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.408977227 |
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Aug 27 07:37:49 PM UTC 24 |
Aug 27 07:37:53 PM UTC 24 |
2075850436 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.572586875 |
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Aug 27 07:37:19 PM UTC 24 |
Aug 27 07:37:54 PM UTC 24 |
13231312748 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3632698564 |
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Aug 27 07:37:51 PM UTC 24 |
Aug 27 07:37:54 PM UTC 24 |
2632155397 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.3044803384 |
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Aug 27 07:37:33 PM UTC 24 |
Aug 27 07:37:54 PM UTC 24 |
7384173694 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.2628539430 |
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Aug 27 07:37:43 PM UTC 24 |
Aug 27 07:37:55 PM UTC 24 |
2595024523 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.575603854 |
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Aug 27 07:35:58 PM UTC 24 |
Aug 27 07:37:57 PM UTC 24 |
191217285242 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.2690346428 |
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Aug 27 07:37:47 PM UTC 24 |
Aug 27 07:37:57 PM UTC 24 |
2111046767 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.4116844882 |
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Aug 27 07:37:54 PM UTC 24 |
Aug 27 07:37:58 PM UTC 24 |
3405164343 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.18664747 |
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Aug 27 07:37:51 PM UTC 24 |
Aug 27 07:37:59 PM UTC 24 |
2510911727 ps |
| T335 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.2161457406 |
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Aug 27 07:35:46 PM UTC 24 |
Aug 27 07:37:59 PM UTC 24 |
81604575947 ps |
| T640 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3931496684 |
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Aug 27 07:37:43 PM UTC 24 |
Aug 27 07:37:59 PM UTC 24 |
28981458578 ps |
| T641 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.852071093 |
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Aug 27 07:37:56 PM UTC 24 |
Aug 27 07:37:59 PM UTC 24 |
2032214684 ps |
| T642 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3712300336 |
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Aug 27 07:37:40 PM UTC 24 |
Aug 27 07:38:00 PM UTC 24 |
3644028618 ps |
| T643 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2397411366 |
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Aug 27 07:37:56 PM UTC 24 |
Aug 27 07:38:01 PM UTC 24 |
2131051990 ps |
| T644 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.530682946 |
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Aug 27 07:37:58 PM UTC 24 |
Aug 27 07:38:02 PM UTC 24 |
2177938857 ps |
| T645 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3139317553 |
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Aug 27 07:37:51 PM UTC 24 |
Aug 27 07:38:05 PM UTC 24 |
3518852621 ps |
| T646 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2257618647 |
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Aug 27 07:38:00 PM UTC 24 |
Aug 27 07:38:05 PM UTC 24 |
3401554860 ps |
| T647 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.521970508 |
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Aug 27 07:37:52 PM UTC 24 |
Aug 27 07:38:05 PM UTC 24 |
3592089080 ps |
| T648 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3758815128 |
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Aug 27 07:37:52 PM UTC 24 |
Aug 27 07:38:05 PM UTC 24 |
5828454135 ps |
| T649 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.588454886 |
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Aug 27 07:37:44 PM UTC 24 |
Aug 27 07:38:05 PM UTC 24 |
6967988123 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1695397969 |
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Aug 27 07:38:02 PM UTC 24 |
Aug 27 07:38:05 PM UTC 24 |
4056318308 ps |
| T650 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.944812988 |
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Aug 27 07:37:57 PM UTC 24 |
Aug 27 07:38:05 PM UTC 24 |
2475226969 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.2616294874 |
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Aug 27 07:34:03 PM UTC 24 |
Aug 27 07:38:06 PM UTC 24 |
88938986627 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1935624727 |
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Aug 27 07:37:56 PM UTC 24 |
Aug 27 07:38:07 PM UTC 24 |
10895186355 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.1623029007 |
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Aug 27 07:38:37 PM UTC 24 |
Aug 27 07:38:44 PM UTC 24 |
2449968183 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.489546111 |
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Aug 27 07:37:58 PM UTC 24 |
Aug 27 07:38:10 PM UTC 24 |
2510822626 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2552133963 |
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Aug 27 07:38:01 PM UTC 24 |
Aug 27 07:38:10 PM UTC 24 |
3334661055 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.690460821 |
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Aug 27 07:38:07 PM UTC 24 |
Aug 27 07:38:11 PM UTC 24 |
2048603783 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.2389378871 |
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Aug 27 07:38:07 PM UTC 24 |
Aug 27 07:38:12 PM UTC 24 |
2522354360 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2585963831 |
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Aug 27 07:38:02 PM UTC 24 |
Aug 27 07:38:12 PM UTC 24 |
6093102781 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1561733130 |
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Aug 27 07:38:07 PM UTC 24 |
Aug 27 07:38:12 PM UTC 24 |
3407798677 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.448547331 |
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Aug 27 07:38:06 PM UTC 24 |
Aug 27 07:38:13 PM UTC 24 |
2023152562 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.3420432329 |
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Aug 27 07:37:03 PM UTC 24 |
Aug 27 07:38:14 PM UTC 24 |
187312079100 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.163621046 |
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Aug 27 07:38:06 PM UTC 24 |
Aug 27 07:38:14 PM UTC 24 |
2121077245 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1478202438 |
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Aug 27 07:38:13 PM UTC 24 |
Aug 27 07:38:16 PM UTC 24 |
2095857963 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.1802425986 |
|
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Aug 27 07:38:12 PM UTC 24 |
Aug 27 07:38:16 PM UTC 24 |
3460990398 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3224597719 |
|
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Aug 27 07:38:07 PM UTC 24 |
Aug 27 07:38:17 PM UTC 24 |
2607307895 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.90522541 |
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Aug 27 07:38:08 PM UTC 24 |
Aug 27 07:38:17 PM UTC 24 |
7832441307 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.3338069064 |
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Aug 27 07:38:14 PM UTC 24 |
Aug 27 07:38:17 PM UTC 24 |
2133481856 ps |
| T305 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2254266204 |
|
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Aug 27 07:38:03 PM UTC 24 |
Aug 27 07:38:18 PM UTC 24 |
23883697352 ps |
| T368 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3403738852 |
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Aug 27 07:35:23 PM UTC 24 |
Aug 27 07:38:18 PM UTC 24 |
54139660833 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.901177026 |
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Aug 27 07:37:41 PM UTC 24 |
Aug 27 07:38:18 PM UTC 24 |
128691084648 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.389694126 |
|
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Aug 27 07:38:15 PM UTC 24 |
Aug 27 07:38:18 PM UTC 24 |
2153167923 ps |
| T388 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.4015674979 |
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Aug 27 07:37:56 PM UTC 24 |
Aug 27 07:38:19 PM UTC 24 |
15407440128 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.1599493792 |
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Aug 27 07:36:36 PM UTC 24 |
Aug 27 07:38:19 PM UTC 24 |
152010586358 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.267196730 |
|
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Aug 27 07:38:17 PM UTC 24 |
Aug 27 07:38:19 PM UTC 24 |
2710010850 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.1971603040 |
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Aug 27 07:35:27 PM UTC 24 |
Aug 27 07:38:20 PM UTC 24 |
130866297883 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.3821767098 |
|
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Aug 27 07:38:06 PM UTC 24 |
Aug 27 07:38:21 PM UTC 24 |
2446446615 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.1583834568 |
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Aug 27 07:37:52 PM UTC 24 |
Aug 27 07:38:21 PM UTC 24 |
94223746884 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.3476580519 |
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Aug 27 07:38:15 PM UTC 24 |
Aug 27 07:38:24 PM UTC 24 |
2513080403 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.684103020 |
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Aug 27 07:38:20 PM UTC 24 |
Aug 27 07:38:26 PM UTC 24 |
3649583986 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.322395002 |
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Aug 27 07:38:18 PM UTC 24 |
Aug 27 07:38:26 PM UTC 24 |
6252909620 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.1752403409 |
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Aug 27 07:38:22 PM UTC 24 |
Aug 27 07:38:26 PM UTC 24 |
2219796344 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1323492606 |
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Aug 27 07:38:22 PM UTC 24 |
Aug 27 07:38:26 PM UTC 24 |
2637232672 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.1386395751 |
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Aug 27 07:38:15 PM UTC 24 |
Aug 27 07:38:26 PM UTC 24 |
2452398546 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2991967423 |
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Aug 27 07:38:21 PM UTC 24 |
Aug 27 07:38:27 PM UTC 24 |
2014388403 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.2845907985 |
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Aug 27 07:38:13 PM UTC 24 |
Aug 27 07:38:28 PM UTC 24 |
16135734146 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.2649143147 |
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Aug 27 07:38:21 PM UTC 24 |
Aug 27 07:38:28 PM UTC 24 |
2113704322 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.3399498652 |
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Aug 27 07:37:29 PM UTC 24 |
Aug 27 07:38:28 PM UTC 24 |
82556689761 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.3978379545 |
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Aug 27 07:38:22 PM UTC 24 |
Aug 27 07:38:29 PM UTC 24 |
2519109023 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1024311665 |
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Aug 27 07:38:18 PM UTC 24 |
Aug 27 07:38:29 PM UTC 24 |
3744839752 ps |
| T361 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.514370859 |
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Aug 27 07:36:23 PM UTC 24 |
Aug 27 07:38:29 PM UTC 24 |
83769469133 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1287883628 |
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Aug 27 07:38:17 PM UTC 24 |
Aug 27 07:38:30 PM UTC 24 |
3571520310 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2042624692 |
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Aug 27 07:38:26 PM UTC 24 |
Aug 27 07:38:30 PM UTC 24 |
2690237134 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1271936451 |
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Aug 27 07:38:27 PM UTC 24 |
Aug 27 07:38:31 PM UTC 24 |
6198040120 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1576473471 |
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Aug 27 07:38:13 PM UTC 24 |
Aug 27 07:38:32 PM UTC 24 |
4790139260 ps |
| T389 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2484510647 |
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Aug 27 07:38:12 PM UTC 24 |
Aug 27 07:38:32 PM UTC 24 |
55671204034 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1249392401 |
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Aug 27 07:38:21 PM UTC 24 |
Aug 27 07:38:32 PM UTC 24 |
2463377015 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.254432288 |
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Aug 27 07:38:30 PM UTC 24 |
Aug 27 07:38:33 PM UTC 24 |
2148661709 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1336881748 |
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Aug 27 07:38:27 PM UTC 24 |
Aug 27 07:38:34 PM UTC 24 |
3497379500 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2861251943 |
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Aug 27 07:38:31 PM UTC 24 |
Aug 27 07:38:34 PM UTC 24 |
3429087641 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.620023151 |
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Aug 27 07:38:31 PM UTC 24 |
Aug 27 07:38:35 PM UTC 24 |
2570617727 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.2692732466 |
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Aug 27 07:38:04 PM UTC 24 |
Aug 27 07:38:35 PM UTC 24 |
10959536148 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.2724485599 |
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Aug 27 07:38:31 PM UTC 24 |
Aug 27 07:38:35 PM UTC 24 |
2211972405 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3232000312 |
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Aug 27 07:38:30 PM UTC 24 |
Aug 27 07:38:37 PM UTC 24 |
2015054190 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.824480978 |
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Aug 27 07:38:33 PM UTC 24 |
Aug 27 07:38:37 PM UTC 24 |
4532505346 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.341293763 |
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Aug 27 07:38:30 PM UTC 24 |
Aug 27 07:38:38 PM UTC 24 |
2468411122 ps |
| T275 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.4094685674 |
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Aug 27 07:38:10 PM UTC 24 |
Aug 27 07:38:38 PM UTC 24 |
95576423204 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.1844330199 |
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Aug 27 07:38:33 PM UTC 24 |
Aug 27 07:38:39 PM UTC 24 |
3242970005 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.2806411399 |
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Aug 27 07:38:36 PM UTC 24 |
Aug 27 07:38:41 PM UTC 24 |
2132348299 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.3295072039 |
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Aug 27 07:38:28 PM UTC 24 |
Aug 27 07:38:41 PM UTC 24 |
2638399708 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2546161639 |
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Aug 27 07:38:20 PM UTC 24 |
Aug 27 07:38:41 PM UTC 24 |
5676609621 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.1813410258 |
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Aug 27 07:38:20 PM UTC 24 |
Aug 27 07:38:43 PM UTC 24 |
10864865786 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.1227559542 |
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Aug 27 07:38:36 PM UTC 24 |
Aug 27 07:38:43 PM UTC 24 |
2020089229 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2442132963 |
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Aug 27 07:38:40 PM UTC 24 |
Aug 27 07:38:44 PM UTC 24 |
3470924298 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.4137245208 |
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Aug 27 07:38:31 PM UTC 24 |
Aug 27 07:38:44 PM UTC 24 |
2609720404 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1297833902 |
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Aug 27 07:38:35 PM UTC 24 |
Aug 27 07:38:44 PM UTC 24 |
6943535852 ps |
| T276 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1283944707 |
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Aug 27 07:40:19 PM UTC 24 |
Aug 27 07:41:07 PM UTC 24 |
33604079581 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1087812206 |
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Aug 27 07:39:09 PM UTC 24 |
Aug 27 07:41:13 PM UTC 24 |
26581523425 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2482926208 |
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Aug 27 07:38:29 PM UTC 24 |
Aug 27 07:38:45 PM UTC 24 |
36920532135 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.4093371616 |
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Aug 27 07:38:40 PM UTC 24 |
Aug 27 07:38:46 PM UTC 24 |
3275369864 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1125291744 |
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Aug 27 07:38:35 PM UTC 24 |
Aug 27 07:38:46 PM UTC 24 |
11099807571 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1341020105 |
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Aug 27 07:38:33 PM UTC 24 |
Aug 27 07:38:46 PM UTC 24 |
3762819785 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2442247654 |
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Aug 27 07:38:42 PM UTC 24 |
Aug 27 07:38:48 PM UTC 24 |
2982874976 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.1796771430 |
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Aug 27 07:38:38 PM UTC 24 |
Aug 27 07:38:48 PM UTC 24 |
2513109038 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.3155200895 |
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Aug 27 07:38:38 PM UTC 24 |
Aug 27 07:38:49 PM UTC 24 |
2249869528 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1678087576 |
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Aug 27 07:38:39 PM UTC 24 |
Aug 27 07:38:50 PM UTC 24 |
2612095515 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.4083250219 |
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Aug 27 07:38:46 PM UTC 24 |
Aug 27 07:38:50 PM UTC 24 |
2069369143 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.4283137499 |
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Aug 27 07:38:46 PM UTC 24 |
Aug 27 07:38:50 PM UTC 24 |
2492451383 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.383960675 |
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Aug 27 07:38:48 PM UTC 24 |
Aug 27 07:38:51 PM UTC 24 |
2655156292 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.3652766353 |
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Aug 27 07:38:46 PM UTC 24 |
Aug 27 07:38:52 PM UTC 24 |
2118846115 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2100278978 |
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Aug 27 07:38:48 PM UTC 24 |
Aug 27 07:38:52 PM UTC 24 |
4031097326 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2289890287 |
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Aug 27 07:38:44 PM UTC 24 |
Aug 27 07:38:53 PM UTC 24 |
10162610033 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.1371882358 |
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Aug 27 07:38:46 PM UTC 24 |
Aug 27 07:38:53 PM UTC 24 |
2521622247 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.3775739174 |
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Aug 27 07:38:46 PM UTC 24 |
Aug 27 07:38:53 PM UTC 24 |
2012578556 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.2250342827 |
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Aug 27 07:38:49 PM UTC 24 |
Aug 27 07:38:55 PM UTC 24 |
4455812862 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.3762128720 |
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Aug 27 07:38:51 PM UTC 24 |
Aug 27 07:38:55 PM UTC 24 |
2035059601 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.1982164316 |
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Aug 27 07:32:56 PM UTC 24 |
Aug 27 07:38:56 PM UTC 24 |
112321052264 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.3896822312 |
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Aug 27 07:38:44 PM UTC 24 |
Aug 27 07:38:57 PM UTC 24 |
3289887554 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3825985299 |
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Aug 27 07:38:48 PM UTC 24 |
Aug 27 07:38:57 PM UTC 24 |
6898453751 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.3291731740 |
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Aug 27 07:35:23 PM UTC 24 |
Aug 27 07:38:59 PM UTC 24 |
81945422533 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.4007699227 |
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Aug 27 07:38:48 PM UTC 24 |
Aug 27 07:39:00 PM UTC 24 |
3696344334 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.2380961755 |
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|
Aug 27 07:38:29 PM UTC 24 |
Aug 27 07:39:03 PM UTC 24 |
210490710061 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2514219095 |
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|
Aug 27 07:38:51 PM UTC 24 |
Aug 27 07:39:03 PM UTC 24 |
2558548052 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.1742543609 |
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|
Aug 27 07:38:51 PM UTC 24 |
Aug 27 07:39:05 PM UTC 24 |
8668087641 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.3772286068 |
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Aug 27 07:38:18 PM UTC 24 |
Aug 27 07:39:07 PM UTC 24 |
129419754466 ps |
| T345 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.367362186 |
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|
Aug 27 07:37:13 PM UTC 24 |
Aug 27 07:39:18 PM UTC 24 |
154395845552 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.4205451424 |
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Aug 27 07:38:28 PM UTC 24 |
Aug 27 07:39:18 PM UTC 24 |
32580840711 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2125367386 |
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|
Aug 27 07:38:57 PM UTC 24 |
Aug 27 07:39:22 PM UTC 24 |
22601527561 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.267655469 |
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|
Aug 27 07:38:54 PM UTC 24 |
Aug 27 07:39:23 PM UTC 24 |
28101583645 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.306057931 |
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|
Aug 27 07:32:26 PM UTC 24 |
Aug 27 07:39:24 PM UTC 24 |
4120846041428 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.743776752 |
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|
Aug 27 07:30:21 PM UTC 24 |
Aug 27 07:39:25 PM UTC 24 |
162846565383 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1669625097 |
|
|
Aug 27 07:39:01 PM UTC 24 |
Aug 27 07:39:25 PM UTC 24 |
73707618190 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.428897324 |
|
|
Aug 27 07:36:50 PM UTC 24 |
Aug 27 07:39:26 PM UTC 24 |
69107768247 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1310888657 |
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Aug 27 07:40:03 PM UTC 24 |
Aug 27 07:41:19 PM UTC 24 |
22828406659 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1316739417 |
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Aug 27 07:39:04 PM UTC 24 |
Aug 27 07:39:28 PM UTC 24 |
29865498169 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2088895085 |
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|
Aug 27 07:38:54 PM UTC 24 |
Aug 27 07:39:31 PM UTC 24 |
34448042043 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2848427552 |
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|
Aug 27 07:38:56 PM UTC 24 |
Aug 27 07:39:39 PM UTC 24 |
71280882552 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.2619292955 |
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|
Aug 27 07:38:02 PM UTC 24 |
Aug 27 07:39:44 PM UTC 24 |
137075208607 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.2394594575 |
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|
Aug 27 07:38:42 PM UTC 24 |
Aug 27 07:39:45 PM UTC 24 |
51748895533 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3502780861 |
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|
Aug 27 07:38:53 PM UTC 24 |
Aug 27 07:39:47 PM UTC 24 |
59656898749 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.1905209529 |
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|
Aug 27 07:38:49 PM UTC 24 |
Aug 27 07:40:00 PM UTC 24 |
91544256507 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1174763790 |
|
|
Aug 27 07:39:28 PM UTC 24 |
Aug 27 07:40:01 PM UTC 24 |
22339778554 ps |
| T110 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1707746294 |
|
|
Aug 27 07:39:26 PM UTC 24 |
Aug 27 07:40:03 PM UTC 24 |
56494975816 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2594705433 |
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|
Aug 27 07:34:26 PM UTC 24 |
Aug 27 07:40:04 PM UTC 24 |
114483130528 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.536268023 |
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|
Aug 27 07:39:04 PM UTC 24 |
Aug 27 07:40:06 PM UTC 24 |
81900430784 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2053260664 |
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|
Aug 27 07:39:40 PM UTC 24 |
Aug 27 07:40:10 PM UTC 24 |
19582678468 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.4293478196 |
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|
Aug 27 07:40:00 PM UTC 24 |
Aug 27 07:40:10 PM UTC 24 |
24130734382 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2796013795 |
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|
Aug 27 07:38:33 PM UTC 24 |
Aug 27 07:40:20 PM UTC 24 |
123536009571 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2155562235 |
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|
Aug 27 07:38:57 PM UTC 24 |
Aug 27 07:40:22 PM UTC 24 |
91057592697 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.2567136665 |
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|
Aug 27 07:34:36 PM UTC 24 |
Aug 27 07:40:28 PM UTC 24 |
104160872661 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3649219817 |
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|
Aug 27 07:38:58 PM UTC 24 |
Aug 27 07:40:33 PM UTC 24 |
27833477721 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.929858422 |
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|
Aug 27 07:39:28 PM UTC 24 |
Aug 27 07:40:38 PM UTC 24 |
173662013197 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1581474113 |
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Aug 27 07:40:04 PM UTC 24 |
Aug 27 07:40:40 PM UTC 24 |
102859945463 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1729446754 |
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Aug 27 07:38:54 PM UTC 24 |
Aug 27 07:40:49 PM UTC 24 |
43769695243 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3215968380 |
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Aug 27 07:38:58 PM UTC 24 |
Aug 27 07:40:51 PM UTC 24 |
27084065025 ps |
| T369 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3020168454 |
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|
Aug 27 07:38:44 PM UTC 24 |
Aug 27 07:40:55 PM UTC 24 |
53870268895 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.1793205644 |
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Aug 27 07:34:25 PM UTC 24 |
Aug 27 07:40:55 PM UTC 24 |
150592823336 ps |
| T366 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2545658715 |
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Aug 27 07:37:30 PM UTC 24 |
Aug 27 07:40:59 PM UTC 24 |
56959839761 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3712809448 |
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Aug 27 07:39:19 PM UTC 24 |
Aug 27 07:41:02 PM UTC 24 |
119259540477 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.4119237423 |
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Aug 27 07:40:12 PM UTC 24 |
Aug 27 07:41:06 PM UTC 24 |
78850827924 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2637888971 |
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Aug 27 07:40:29 PM UTC 24 |
Aug 27 07:41:07 PM UTC 24 |
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| T741 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3840907040 |
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Aug 27 07:40:06 PM UTC 24 |
Aug 27 07:41:07 PM UTC 24 |
50214733795 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1941457835 |
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Aug 27 07:27:52 PM UTC 24 |
Aug 27 07:41:08 PM UTC 24 |
948238604581 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3196977011 |
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Aug 27 07:39:26 PM UTC 24 |
Aug 27 07:41:19 PM UTC 24 |
57212887422 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.522564732 |
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Aug 27 07:36:50 PM UTC 24 |
Aug 27 07:41:21 PM UTC 24 |
156060432181 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1530524006 |
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Aug 27 07:38:53 PM UTC 24 |
Aug 27 07:41:24 PM UTC 24 |
54610073579 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.2940952518 |
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Aug 27 07:31:15 PM UTC 24 |
Aug 27 07:41:25 PM UTC 24 |
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| T111 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1084811556 |
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Aug 27 07:39:46 PM UTC 24 |
Aug 27 07:41:35 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3837893458 |
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Aug 27 07:39:00 PM UTC 24 |
Aug 27 07:41:38 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2618024809 |
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Aug 27 07:39:22 PM UTC 24 |
Aug 27 07:41:40 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3941590316 |
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Aug 27 07:39:19 PM UTC 24 |
Aug 27 07:41:40 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3024346513 |
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Aug 27 07:39:25 PM UTC 24 |
Aug 27 07:41:42 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2198227234 |
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Aug 27 07:39:26 PM UTC 24 |
Aug 27 07:41:52 PM UTC 24 |
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Aug 27 07:34:17 PM UTC 24 |
Aug 27 07:41:58 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.748564021 |
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Aug 27 07:40:39 PM UTC 24 |
Aug 27 07:42:03 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3820407198 |
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Aug 27 07:40:23 PM UTC 24 |
Aug 27 07:42:09 PM UTC 24 |
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Aug 27 07:35:49 PM UTC 24 |
Aug 27 07:42:12 PM UTC 24 |
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Aug 27 07:37:54 PM UTC 24 |
Aug 27 07:42:15 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1922298656 |
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Aug 27 07:40:50 PM UTC 24 |
Aug 27 07:42:24 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.440721851 |
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Aug 27 07:38:27 PM UTC 24 |
Aug 27 07:42:27 PM UTC 24 |
97506950070 ps |
| T360 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1369069369 |
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Aug 27 07:39:06 PM UTC 24 |
Aug 27 07:42:31 PM UTC 24 |
65254794132 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.890702946 |
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Aug 27 07:38:44 PM UTC 24 |
Aug 27 07:42:36 PM UTC 24 |
141420061035 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4049268526 |
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Aug 27 07:38:20 PM UTC 24 |
Aug 27 07:42:55 PM UTC 24 |
99863017021 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3480594000 |
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Aug 27 07:38:03 PM UTC 24 |
Aug 27 07:43:03 PM UTC 24 |
113160602608 ps |
| T362 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1990220914 |
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Aug 27 07:40:56 PM UTC 24 |
Aug 27 07:43:08 PM UTC 24 |
67136615411 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1775636672 |
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Aug 27 07:40:21 PM UTC 24 |
Aug 27 07:43:12 PM UTC 24 |
75085780645 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3321038477 |
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Aug 27 07:40:34 PM UTC 24 |
Aug 27 07:43:44 PM UTC 24 |
65948785076 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.210689257 |
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Aug 27 07:38:53 PM UTC 24 |
Aug 27 07:43:46 PM UTC 24 |
86669203364 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.566793525 |
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Aug 27 07:38:51 PM UTC 24 |
Aug 27 07:43:56 PM UTC 24 |
83902594691 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2796315857 |
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Aug 27 07:40:42 PM UTC 24 |
Aug 27 07:43:56 PM UTC 24 |
61157665972 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.3533856907 |
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Aug 27 07:35:35 PM UTC 24 |
Aug 27 07:44:09 PM UTC 24 |
161271013306 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2942695386 |
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Aug 27 07:39:48 PM UTC 24 |
Aug 27 07:45:39 PM UTC 24 |
126741746929 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.773792811 |
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Aug 27 07:39:46 PM UTC 24 |
Aug 27 07:46:43 PM UTC 24 |
105434886241 ps |
| T363 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1868555622 |
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Aug 27 07:39:29 PM UTC 24 |
Aug 27 07:46:58 PM UTC 24 |
157638398285 ps |
| T341 |
/workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.1001847610 |
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Aug 27 07:38:33 PM UTC 24 |
Aug 27 07:47:31 PM UTC 24 |
173279053346 ps |