| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
| 96.39 | 98.86 | 94.55 | 100.00 | 98.08 | 98.26 | 98.94 | 86.07 |
| T364 | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.614625467 | Aug 27 07:40:32 PM UTC 24 | Aug 27 07:47:57 PM UTC 24 | 129518455042 ps | ||
| T348 | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2956858547 | Aug 27 07:39:31 PM UTC 24 | Aug 27 07:49:11 PM UTC 24 | 221062499346 ps | ||
| T753 | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.4190211855 | Aug 27 07:37:02 PM UTC 24 | Aug 27 07:49:35 PM UTC 24 | 219382071304 ps |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1573588595 |
| Short name | T1 |
| Test name | |
| Test status | |
| Simulation time | 4114982576 ps |
| CPU time | 6.91 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:26:35 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1573588595 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.1573588595 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.2329241724 |
| Short name | T44 |
| Test name | |
| Test status | |
| Simulation time | 38475968648 ps |
| CPU time | 128.94 seconds |
| Started | Aug 27 07:26:31 PM UTC 24 |
| Finished | Aug 27 07:28:42 PM UTC 24 |
| Peak memory | 210400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329241724 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.2329241724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.360720529 |
| Short name | T10 |
| Test name | |
| Test status | |
| Simulation time | 60050228847 ps |
| CPU time | 41.19 seconds |
| Started | Aug 27 07:26:45 PM UTC 24 |
| Finished | Aug 27 07:27:27 PM UTC 24 |
| Peak memory | 210496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=360720529 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.360720529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.3543217029 |
| Short name | T15 |
| Test name | |
| Test status | |
| Simulation time | 2448210485 ps |
| CPU time | 9.09 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:26:37 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3543217029 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.3543217029 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.4033241548 |
| Short name | T105 |
| Test name | |
| Test status | |
| Simulation time | 67562427179 ps |
| CPU time | 29.4 seconds |
| Started | Aug 27 07:31:52 PM UTC 24 |
| Finished | Aug 27 07:32:23 PM UTC 24 |
| Peak memory | 220792 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4033241548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.4033241548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.3906687440 |
| Short name | T83 |
| Test name | |
| Test status | |
| Simulation time | 2517114635 ps |
| CPU time | 11.52 seconds |
| Started | Aug 27 07:27:11 PM UTC 24 |
| Finished | Aug 27 07:27:24 PM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3906687440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.3906687440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4073114781 |
| Short name | T48 |
| Test name | |
| Test status | |
| Simulation time | 41374016058 ps |
| CPU time | 14.75 seconds |
| Started | Aug 27 07:29:07 PM UTC 24 |
| Finished | Aug 27 07:29:23 PM UTC 24 |
| Peak memory | 226908 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=4073114781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.4073114781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.177265013 |
| Short name | T277 |
| Test name | |
| Test status | |
| Simulation time | 128948435696 ps |
| CPU time | 95.6 seconds |
| Started | Aug 27 07:29:04 PM UTC 24 |
| Finished | Aug 27 07:30:42 PM UTC 24 |
| Peak memory | 210440 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=177265013 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.177265013 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.663417187 |
| Short name | T60 |
| Test name | |
| Test status | |
| Simulation time | 22697619419 ps |
| CPU time | 25.19 seconds |
| Started | Aug 27 07:26:49 PM UTC 24 |
| Finished | Aug 27 07:27:16 PM UTC 24 |
| Peak memory | 210628 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=663417187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.663417187 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.2620380608 |
| Short name | T73 |
| Test name | |
| Test status | |
| Simulation time | 6944058510 ps |
| CPU time | 7.04 seconds |
| Started | Aug 27 07:28:24 PM UTC 24 |
| Finished | Aug 27 07:28:32 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2620380608 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.2620380608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.3647297443 |
| Short name | T38 |
| Test name | |
| Test status | |
| Simulation time | 154260648283 ps |
| CPU time | 94.06 seconds |
| Started | Aug 27 07:27:15 PM UTC 24 |
| Finished | Aug 27 07:28:51 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3647297443 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.3647297443 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3907389888 |
| Short name | T102 |
| Test name | |
| Test status | |
| Simulation time | 42912390315 ps |
| CPU time | 26.96 seconds |
| Started | Aug 27 07:29:38 PM UTC 24 |
| Finished | Aug 27 07:30:06 PM UTC 24 |
| Peak memory | 220476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3907389888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.3907389888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.1337660811 |
| Short name | T267 |
| Test name | |
| Test status | |
| Simulation time | 110058847955 ps |
| CPU time | 75.37 seconds |
| Started | Aug 27 07:32:10 PM UTC 24 |
| Finished | Aug 27 07:33:28 PM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337660811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_with_pre_cond.1337660811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.3827410155 |
| Short name | T52 |
| Test name | |
| Test status | |
| Simulation time | 42017867628 ps |
| CPU time | 65.47 seconds |
| Started | Aug 27 07:26:32 PM UTC 24 |
| Finished | Aug 27 07:27:39 PM UTC 24 |
| Peak memory | 240212 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827410155 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.3827410155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.1207518537 |
| Short name | T186 |
| Test name | |
| Test status | |
| Simulation time | 1176703304402 ps |
| CPU time | 259.5 seconds |
| Started | Aug 27 07:30:23 PM UTC 24 |
| Finished | Aug 27 07:34:46 PM UTC 24 |
| Peak memory | 209920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1207518537 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.1207518537 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1695397969 |
| Short name | T215 |
| Test name | |
| Test status | |
| Simulation time | 4056318308 ps |
| CPU time | 2.68 seconds |
| Started | Aug 27 07:38:02 PM UTC 24 |
| Finished | Aug 27 07:38:05 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695397969 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.1695397969 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.728918113 |
| Short name | T278 |
| Test name | |
| Test status | |
| Simulation time | 76633332867 ps |
| CPU time | 26.52 seconds |
| Started | Aug 27 07:31:33 PM UTC 24 |
| Finished | Aug 27 07:32:00 PM UTC 24 |
| Peak memory | 210228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=728918113 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.728918113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.3572087586 |
| Short name | T227 |
| Test name | |
| Test status | |
| Simulation time | 13379658711 ps |
| CPU time | 15.17 seconds |
| Started | Aug 27 07:36:23 PM UTC 24 |
| Finished | Aug 27 07:36:39 PM UTC 24 |
| Peak memory | 220024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3572087586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.3572087586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.2301301136 |
| Short name | T264 |
| Test name | |
| Test status | |
| Simulation time | 67980584436 ps |
| CPU time | 68.35 seconds |
| Started | Aug 27 07:31:35 PM UTC 24 |
| Finished | Aug 27 07:32:45 PM UTC 24 |
| Peak memory | 210564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2301301136 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_with_pre_cond.2301301136 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.4015501801 |
| Short name | T108 |
| Test name | |
| Test status | |
| Simulation time | 32998301508 ps |
| CPU time | 110.11 seconds |
| Started | Aug 27 07:28:01 PM UTC 24 |
| Finished | Aug 27 07:29:53 PM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015501801 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.4015501801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.2244350886 |
| Short name | T55 |
| Test name | |
| Test status | |
| Simulation time | 15397572330 ps |
| CPU time | 50.11 seconds |
| Started | Aug 27 07:29:09 PM UTC 24 |
| Finished | Aug 27 07:30:01 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2244350886 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.2244350886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all_with_rand_reset.1935624727 |
| Short name | T187 |
| Test name | |
| Test status | |
| Simulation time | 10895186355 ps |
| CPU time | 10.08 seconds |
| Started | Aug 27 07:37:56 PM UTC 24 |
| Finished | Aug 27 07:38:07 PM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1935624727 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 42.sysrst_ctrl_stress_all_with_rand_reset.1935624727 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.448057452 |
| Short name | T39 |
| Test name | |
| Test status | |
| Simulation time | 96007921090 ps |
| CPU time | 36.48 seconds |
| Started | Aug 27 07:28:50 PM UTC 24 |
| Finished | Aug 27 07:29:28 PM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448057452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_with_pre_cond.448057452 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.2090485431 |
| Short name | T29 |
| Test name | |
| Test status | |
| Simulation time | 11962246317 ps |
| CPU time | 39.18 seconds |
| Started | Aug 27 07:26:32 PM UTC 24 |
| Finished | Aug 27 07:27:13 PM UTC 24 |
| Peak memory | 210012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090485431 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.2090485431 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2636078952 |
| Short name | T168 |
| Test name | |
| Test status | |
| Simulation time | 3266665004 ps |
| CPU time | 4.41 seconds |
| Started | Aug 27 07:34:26 PM UTC 24 |
| Finished | Aug 27 07:34:32 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2636078952 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.2636078952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.1672253017 |
| Short name | T185 |
| Test name | |
| Test status | |
| Simulation time | 4972142549 ps |
| CPU time | 5.07 seconds |
| Started | Aug 27 07:34:36 PM UTC 24 |
| Finished | Aug 27 07:34:42 PM UTC 24 |
| Peak memory | 209828 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672253017 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.1672253017 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.31473076 |
| Short name | T115 |
| Test name | |
| Test status | |
| Simulation time | 2484096823956 ps |
| CPU time | 35.81 seconds |
| Started | Aug 27 07:32:55 PM UTC 24 |
| Finished | Aug 27 07:33:33 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31473076 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.31473076 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1068503493 |
| Short name | T159 |
| Test name | |
| Test status | |
| Simulation time | 5033178768 ps |
| CPU time | 15 seconds |
| Started | Aug 27 07:31:34 PM UTC 24 |
| Finished | Aug 27 07:31:50 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1068503493 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.1068503493 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1038819966 |
| Short name | T169 |
| Test name | |
| Test status | |
| Simulation time | 2969087804 ps |
| CPU time | 6.85 seconds |
| Started | Aug 27 07:34:57 PM UTC 24 |
| Finished | Aug 27 07:35:05 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1038819966 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.1038819966 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.551752535 |
| Short name | T344 |
| Test name | |
| Test status | |
| Simulation time | 162409670576 ps |
| CPU time | 102.25 seconds |
| Started | Aug 27 07:35:14 PM UTC 24 |
| Finished | Aug 27 07:36:58 PM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=551752535 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect_with_pre_cond.551752535 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.2686736319 |
| Short name | T4 |
| Test name | |
| Test status | |
| Simulation time | 2565258845 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:26:30 PM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686736319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.2686736319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3313779499 |
| Short name | T167 |
| Test name | |
| Test status | |
| Simulation time | 4127055936 ps |
| CPU time | 5.07 seconds |
| Started | Aug 27 07:34:04 PM UTC 24 |
| Finished | Aug 27 07:34:10 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3313779499 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.3313779499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1821588442 |
| Short name | T181 |
| Test name | |
| Test status | |
| Simulation time | 3701360893 ps |
| CPU time | 19.33 seconds |
| Started | Aug 27 07:32:28 PM UTC 24 |
| Finished | Aug 27 07:32:48 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1821588442 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.1821588442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3455562917 |
| Short name | T195 |
| Test name | |
| Test status | |
| Simulation time | 4812917372 ps |
| CPU time | 4.78 seconds |
| Started | Aug 27 07:35:23 PM UTC 24 |
| Finished | Aug 27 07:35:29 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3455562917 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.3455562917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.2429639090 |
| Short name | T212 |
| Test name | |
| Test status | |
| Simulation time | 16647244088 ps |
| CPU time | 53.27 seconds |
| Started | Aug 27 07:35:38 PM UTC 24 |
| Finished | Aug 27 07:36:32 PM UTC 24 |
| Peak memory | 210004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2429639090 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.2429639090 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1057131414 |
| Short name | T265 |
| Test name | |
| Test status | |
| Simulation time | 88198617913 ps |
| CPU time | 128.65 seconds |
| Started | Aug 27 07:30:53 PM UTC 24 |
| Finished | Aug 27 07:33:04 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1057131414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_with_pre_cond.1057131414 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.757060629 |
| Short name | T279 |
| Test name | |
| Test status | |
| Simulation time | 185592407130 ps |
| CPU time | 215.76 seconds |
| Started | Aug 27 07:32:44 PM UTC 24 |
| Finished | Aug 27 07:36:23 PM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=757060629 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.757060629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.1707746294 |
| Short name | T110 |
| Test name | |
| Test status | |
| Simulation time | 56494975816 ps |
| CPU time | 35.66 seconds |
| Started | Aug 27 07:39:26 PM UTC 24 |
| Finished | Aug 27 07:40:03 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707746294 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_with_pre_cond.1707746294 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.929858422 |
| Short name | T343 |
| Test name | |
| Test status | |
| Simulation time | 173662013197 ps |
| CPU time | 69.22 seconds |
| Started | Aug 27 07:39:28 PM UTC 24 |
| Finished | Aug 27 07:40:38 PM UTC 24 |
| Peak memory | 210192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929858422 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_with_pre_cond.929858422 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.4138135591 |
| Short name | T20 |
| Test name | |
| Test status | |
| Simulation time | 2012031326 ps |
| CPU time | 12.08 seconds |
| Started | Aug 27 07:26:35 PM UTC 24 |
| Finished | Aug 27 07:26:48 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138135591 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.4138135591 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.745899544 |
| Short name | T253 |
| Test name | |
| Test status | |
| Simulation time | 10561667491 ps |
| CPU time | 15.46 seconds |
| Started | Aug 27 07:34:17 PM UTC 24 |
| Finished | Aug 27 07:34:33 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=745899544 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.745899544 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.2578961128 |
| Short name | T86 |
| Test name | |
| Test status | |
| Simulation time | 2514097540 ps |
| CPU time | 6.62 seconds |
| Started | Aug 27 07:27:28 PM UTC 24 |
| Finished | Aug 27 07:27:36 PM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2578961128 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.2578961128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.3420432329 |
| Short name | T274 |
| Test name | |
| Test status | |
| Simulation time | 187312079100 ps |
| CPU time | 68.7 seconds |
| Started | Aug 27 07:37:03 PM UTC 24 |
| Finished | Aug 27 07:38:14 PM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420432329 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.3420432329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.217917288 |
| Short name | T350 |
| Test name | |
| Test status | |
| Simulation time | 104045120043 ps |
| CPU time | 258.18 seconds |
| Started | Aug 27 07:37:54 PM UTC 24 |
| Finished | Aug 27 07:42:15 PM UTC 24 |
| Peak memory | 210648 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=217917288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_with_pre_cond.217917288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.3403738852 |
| Short name | T368 |
| Test name | |
| Test status | |
| Simulation time | 54139660833 ps |
| CPU time | 172.39 seconds |
| Started | Aug 27 07:35:23 PM UTC 24 |
| Finished | Aug 27 07:38:18 PM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403738852 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_with_pre_cond.3403738852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.1824528626 |
| Short name | T293 |
| Test name | |
| Test status | |
| Simulation time | 139465845496 ps |
| CPU time | 117.93 seconds |
| Started | Aug 27 07:33:33 PM UTC 24 |
| Finished | Aug 27 07:35:33 PM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1824528626 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.1824528626 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.3291731740 |
| Short name | T717 |
| Test name | |
| Test status | |
| Simulation time | 81945422533 ps |
| CPU time | 213.14 seconds |
| Started | Aug 27 07:35:23 PM UTC 24 |
| Finished | Aug 27 07:38:59 PM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3291731740 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.3291731740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.2942695386 |
| Short name | T347 |
| Test name | |
| Test status | |
| Simulation time | 126741746929 ps |
| CPU time | 346.98 seconds |
| Started | Aug 27 07:39:48 PM UTC 24 |
| Finished | Aug 27 07:45:39 PM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2942695386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_with_pre_cond.2942695386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.3847413081 |
| Short name | T37 |
| Test name | |
| Test status | |
| Simulation time | 7773283033 ps |
| CPU time | 19.7 seconds |
| Started | Aug 27 07:37:03 PM UTC 24 |
| Finished | Aug 27 07:37:24 PM UTC 24 |
| Peak memory | 220780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3847413081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.3847413081 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.3187189104 |
| Short name | T263 |
| Test name | |
| Test status | |
| Simulation time | 67186701938 ps |
| CPU time | 116.1 seconds |
| Started | Aug 27 07:29:36 PM UTC 24 |
| Finished | Aug 27 07:31:34 PM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187189104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_with_pre_cond.3187189104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.2198227234 |
| Short name | T290 |
| Test name | |
| Test status | |
| Simulation time | 181604120625 ps |
| CPU time | 143.94 seconds |
| Started | Aug 27 07:39:26 PM UTC 24 |
| Finished | Aug 27 07:41:52 PM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2198227234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_with_pre_cond.2198227234 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1253983582 |
| Short name | T334 |
| Test name | |
| Test status | |
| Simulation time | 122869240892 ps |
| CPU time | 95.6 seconds |
| Started | Aug 27 07:35:49 PM UTC 24 |
| Finished | Aug 27 07:37:26 PM UTC 24 |
| Peak memory | 210480 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1253983582 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.1253983582 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.2619292955 |
| Short name | T382 |
| Test name | |
| Test status | |
| Simulation time | 137075208607 ps |
| CPU time | 100.97 seconds |
| Started | Aug 27 07:38:02 PM UTC 24 |
| Finished | Aug 27 07:39:44 PM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619292955 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.2619292955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.440721851 |
| Short name | T338 |
| Test name | |
| Test status | |
| Simulation time | 97506950070 ps |
| CPU time | 236.24 seconds |
| Started | Aug 27 07:38:27 PM UTC 24 |
| Finished | Aug 27 07:42:27 PM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=440721851 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.440721851 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.3502780861 |
| Short name | T372 |
| Test name | |
| Test status | |
| Simulation time | 59656898749 ps |
| CPU time | 52.65 seconds |
| Started | Aug 27 07:38:53 PM UTC 24 |
| Finished | Aug 27 07:39:47 PM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3502780861 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_with_pre_cond.3502780861 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/52.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.3024346513 |
| Short name | T351 |
| Test name | |
| Test status | |
| Simulation time | 147868160025 ps |
| CPU time | 135.67 seconds |
| Started | Aug 27 07:39:25 PM UTC 24 |
| Finished | Aug 27 07:41:42 PM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3024346513 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_with_pre_cond.3024346513 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.773792811 |
| Short name | T349 |
| Test name | |
| Test status | |
| Simulation time | 105434886241 ps |
| CPU time | 411.33 seconds |
| Started | Aug 27 07:39:46 PM UTC 24 |
| Finished | Aug 27 07:46:43 PM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=773792811 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_with_pre_cond.773792811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/80.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.1294714978 |
| Short name | T391 |
| Test name | |
| Test status | |
| Simulation time | 2116347424224 ps |
| CPU time | 203.23 seconds |
| Started | Aug 27 07:30:21 PM UTC 24 |
| Finished | Aug 27 07:33:47 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1294714978 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.1294714978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.2253858101 |
| Short name | T59 |
| Test name | |
| Test status | |
| Simulation time | 4731133023 ps |
| CPU time | 25.83 seconds |
| Started | Aug 27 07:29:52 PM UTC 24 |
| Finished | Aug 27 07:30:19 PM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2253858101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.2253858101 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.703758383 |
| Short name | T64 |
| Test name | |
| Test status | |
| Simulation time | 42590674532 ps |
| CPU time | 158.88 seconds |
| Started | Aug 27 07:26:49 PM UTC 24 |
| Finished | Aug 27 07:29:31 PM UTC 24 |
| Peak memory | 210396 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=703758383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.703758383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_feature_disable/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.2810653623 |
| Short name | T410 |
| Test name | |
| Test status | |
| Simulation time | 3663615207 ps |
| CPU time | 2.96 seconds |
| Started | Aug 27 07:29:48 PM UTC 24 |
| Finished | Aug 27 07:29:51 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810653623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.2810653623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.2399143180 |
| Short name | T126 |
| Test name | |
| Test status | |
| Simulation time | 157163812064 ps |
| CPU time | 471.14 seconds |
| Started | Aug 27 07:29:54 PM UTC 24 |
| Finished | Aug 27 07:37:51 PM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2399143180 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.2399143180 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.3259945942 |
| Short name | T390 |
| Test name | |
| Test status | |
| Simulation time | 2356172511682 ps |
| CPU time | 370.77 seconds |
| Started | Aug 27 07:31:10 PM UTC 24 |
| Finished | Aug 27 07:37:26 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3259945942 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.3259945942 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.230795946 |
| Short name | T365 |
| Test name | |
| Test status | |
| Simulation time | 72446223959 ps |
| CPU time | 109.93 seconds |
| Started | Aug 27 07:32:28 PM UTC 24 |
| Finished | Aug 27 07:34:20 PM UTC 24 |
| Peak memory | 210328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=230795946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_with_pre_cond.230795946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.1037109968 |
| Short name | T387 |
| Test name | |
| Test status | |
| Simulation time | 18323928054 ps |
| CPU time | 14.97 seconds |
| Started | Aug 27 07:34:48 PM UTC 24 |
| Finished | Aug 27 07:35:04 PM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037109968 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.1037109968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.514370859 |
| Short name | T361 |
| Test name | |
| Test status | |
| Simulation time | 83769469133 ps |
| CPU time | 124.27 seconds |
| Started | Aug 27 07:36:23 PM UTC 24 |
| Finished | Aug 27 07:38:29 PM UTC 24 |
| Peak memory | 209784 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514370859 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_with_pre_cond.514370859 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2848427552 |
| Short name | T339 |
| Test name | |
| Test status | |
| Simulation time | 71280882552 ps |
| CPU time | 42.18 seconds |
| Started | Aug 27 07:38:56 PM UTC 24 |
| Finished | Aug 27 07:39:39 PM UTC 24 |
| Peak memory | 210516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2848427552 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_with_pre_cond.2848427552 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.3215968380 |
| Short name | T383 |
| Test name | |
| Test status | |
| Simulation time | 27084065025 ps |
| CPU time | 110.76 seconds |
| Started | Aug 27 07:38:58 PM UTC 24 |
| Finished | Aug 27 07:40:51 PM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215968380 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_with_pre_cond.3215968380 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/60.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.2618024809 |
| Short name | T386 |
| Test name | |
| Test status | |
| Simulation time | 55198647822 ps |
| CPU time | 135.34 seconds |
| Started | Aug 27 07:39:22 PM UTC 24 |
| Finished | Aug 27 07:41:40 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2618024809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_with_pre_cond.2618024809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1868555622 |
| Short name | T363 |
| Test name | |
| Test status | |
| Simulation time | 157638398285 ps |
| CPU time | 443.92 seconds |
| Started | Aug 27 07:39:29 PM UTC 24 |
| Finished | Aug 27 07:46:58 PM UTC 24 |
| Peak memory | 210516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1868555622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_with_pre_cond.1868555622 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.2956858547 |
| Short name | T348 |
| Test name | |
| Test status | |
| Simulation time | 221062499346 ps |
| CPU time | 574.23 seconds |
| Started | Aug 27 07:39:31 PM UTC 24 |
| Finished | Aug 27 07:49:11 PM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2956858547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_with_pre_cond.2956858547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/77.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.3820407198 |
| Short name | T371 |
| Test name | |
| Test status | |
| Simulation time | 72918136918 ps |
| CPU time | 103.2 seconds |
| Started | Aug 27 07:40:23 PM UTC 24 |
| Finished | Aug 27 07:42:09 PM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3820407198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_with_pre_cond.3820407198 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.1389055063 |
| Short name | T35 |
| Test name | |
| Test status | |
| Simulation time | 41827429168 ps |
| CPU time | 78.07 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:27:47 PM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1389055063 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.1389055063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.1627085163 |
| Short name | T58 |
| Test name | |
| Test status | |
| Simulation time | 5157840522 ps |
| CPU time | 10.82 seconds |
| Started | Aug 27 07:27:58 PM UTC 24 |
| Finished | Aug 27 07:28:10 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1627085163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.1627085163 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.1084811556 |
| Short name | T111 |
| Test name | |
| Test status | |
| Simulation time | 116158307426 ps |
| CPU time | 106.99 seconds |
| Started | Aug 27 07:39:46 PM UTC 24 |
| Finished | Aug 27 07:41:35 PM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1084811556 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_with_pre_cond.1084811556 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.172762674 |
| Short name | T219 |
| Test name | |
| Test status | |
| Simulation time | 125196744461 ps |
| CPU time | 355.65 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:32:27 PM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172762674 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.172762674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.4282528805 |
| Short name | T5 |
| Test name | |
| Test status | |
| Simulation time | 2212869746 ps |
| CPU time | 3.43 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:26:31 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4282528805 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.4282528805 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.130395502 |
| Short name | T14 |
| Test name | |
| Test status | |
| Simulation time | 2265870862 ps |
| CPU time | 8.05 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:26:36 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=130395502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.130395502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.259309780 |
| Short name | T33 |
| Test name | |
| Test status | |
| Simulation time | 46322958734 ps |
| CPU time | 128.67 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:28:38 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259309780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_with_pre_cond.259309780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.339594980 |
| Short name | T22 |
| Test name | |
| Test status | |
| Simulation time | 5198253991 ps |
| CPU time | 5.35 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:26:33 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=339594980 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.339594980 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.1814557768 |
| Short name | T26 |
| Test name | |
| Test status | |
| Simulation time | 2639588231 ps |
| CPU time | 3.83 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:26:32 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814557768 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.1814557768 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.1170798536 |
| Short name | T6 |
| Test name | |
| Test status | |
| Simulation time | 2147935353 ps |
| CPU time | 3.56 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:26:31 PM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1170798536 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.1170798536 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.2145308248 |
| Short name | T36 |
| Test name | |
| Test status | |
| Simulation time | 2118111256 ps |
| CPU time | 6.5 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:26:34 PM UTC 24 |
| Peak memory | 209892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145308248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.2145308248 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.50169120 |
| Short name | T2 |
| Test name | |
| Test status | |
| Simulation time | 11196477946 ps |
| CPU time | 15.16 seconds |
| Started | Aug 27 07:26:27 PM UTC 24 |
| Finished | Aug 27 07:26:43 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=50169120 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.50169120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.2483679153 |
| Short name | T56 |
| Test name | |
| Test status | |
| Simulation time | 2025806550 ps |
| CPU time | 2.98 seconds |
| Started | Aug 27 07:26:56 PM UTC 24 |
| Finished | Aug 27 07:27:00 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2483679153 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.2483679153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3319238276 |
| Short name | T28 |
| Test name | |
| Test status | |
| Simulation time | 4166176835 ps |
| CPU time | 20.89 seconds |
| Started | Aug 27 07:26:44 PM UTC 24 |
| Finished | Aug 27 07:27:06 PM UTC 24 |
| Peak memory | 210012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3319238276 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.3319238276 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.175012881 |
| Short name | T19 |
| Test name | |
| Test status | |
| Simulation time | 2145976278 ps |
| CPU time | 6.81 seconds |
| Started | Aug 27 07:26:36 PM UTC 24 |
| Finished | Aug 27 07:26:44 PM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175012881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.175012881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3110245597 |
| Short name | T16 |
| Test name | |
| Test status | |
| Simulation time | 2439592863 ps |
| CPU time | 1.57 seconds |
| Started | Aug 27 07:26:37 PM UTC 24 |
| Finished | Aug 27 07:26:40 PM UTC 24 |
| Peak memory | 208176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3110245597 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3110245597 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.4087873075 |
| Short name | T32 |
| Test name | |
| Test status | |
| Simulation time | 71328392533 ps |
| CPU time | 65.55 seconds |
| Started | Aug 27 07:26:49 PM UTC 24 |
| Finished | Aug 27 07:27:56 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4087873075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_with_pre_cond.4087873075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.256883950 |
| Short name | T63 |
| Test name | |
| Test status | |
| Simulation time | 3259944579 ps |
| CPU time | 7.59 seconds |
| Started | Aug 27 07:26:43 PM UTC 24 |
| Finished | Aug 27 07:26:51 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=256883950 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.256883950 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.1457614792 |
| Short name | T8 |
| Test name | |
| Test status | |
| Simulation time | 5857685732 ps |
| CPU time | 26.59 seconds |
| Started | Aug 27 07:26:46 PM UTC 24 |
| Finished | Aug 27 07:27:14 PM UTC 24 |
| Peak memory | 209864 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1457614792 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.1457614792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.3101785645 |
| Short name | T27 |
| Test name | |
| Test status | |
| Simulation time | 2615518782 ps |
| CPU time | 6.73 seconds |
| Started | Aug 27 07:26:40 PM UTC 24 |
| Finished | Aug 27 07:26:48 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3101785645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.3101785645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.3366759370 |
| Short name | T17 |
| Test name | |
| Test status | |
| Simulation time | 2489459102 ps |
| CPU time | 4.91 seconds |
| Started | Aug 27 07:26:36 PM UTC 24 |
| Finished | Aug 27 07:26:42 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3366759370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.3366759370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.3334102903 |
| Short name | T18 |
| Test name | |
| Test status | |
| Simulation time | 2206148642 ps |
| CPU time | 3.77 seconds |
| Started | Aug 27 07:26:38 PM UTC 24 |
| Finished | Aug 27 07:26:43 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3334102903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.3334102903 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.4064534608 |
| Short name | T62 |
| Test name | |
| Test status | |
| Simulation time | 2513360428 ps |
| CPU time | 13.03 seconds |
| Started | Aug 27 07:26:40 PM UTC 24 |
| Finished | Aug 27 07:26:54 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4064534608 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.4064534608 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.3459668257 |
| Short name | T53 |
| Test name | |
| Test status | |
| Simulation time | 42014981111 ps |
| CPU time | 109.07 seconds |
| Started | Aug 27 07:26:52 PM UTC 24 |
| Finished | Aug 27 07:28:43 PM UTC 24 |
| Peak memory | 238300 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3459668257 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.3459668257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.623682161 |
| Short name | T21 |
| Test name | |
| Test status | |
| Simulation time | 2111699096 ps |
| CPU time | 12.2 seconds |
| Started | Aug 27 07:26:35 PM UTC 24 |
| Finished | Aug 27 07:26:48 PM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=623682161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.623682161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.739350492 |
| Short name | T7 |
| Test name | |
| Test status | |
| Simulation time | 15386157992 ps |
| CPU time | 19.92 seconds |
| Started | Aug 27 07:26:51 PM UTC 24 |
| Finished | Aug 27 07:27:13 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=739350492 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.739350492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.3519061275 |
| Short name | T3 |
| Test name | |
| Test status | |
| Simulation time | 5178215196 ps |
| CPU time | 14.56 seconds |
| Started | Aug 27 07:26:44 PM UTC 24 |
| Finished | Aug 27 07:26:59 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3519061275 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.3519061275 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.3417658296 |
| Short name | T285 |
| Test name | |
| Test status | |
| Simulation time | 2040732132 ps |
| CPU time | 3.03 seconds |
| Started | Aug 27 07:29:55 PM UTC 24 |
| Finished | Aug 27 07:29:59 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3417658296 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.3417658296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.1701087295 |
| Short name | T120 |
| Test name | |
| Test status | |
| Simulation time | 95577621043 ps |
| CPU time | 144.46 seconds |
| Started | Aug 27 07:29:52 PM UTC 24 |
| Finished | Aug 27 07:32:18 PM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1701087295 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.1701087295 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect_with_pre_cond.1655299231 |
| Short name | T262 |
| Test name | |
| Test status | |
| Simulation time | 32815136064 ps |
| CPU time | 80.94 seconds |
| Started | Aug 27 07:29:52 PM UTC 24 |
| Finished | Aug 27 07:31:15 PM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1655299231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect_with_pre_cond.1655299231 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.1137661787 |
| Short name | T116 |
| Test name | |
| Test status | |
| Simulation time | 3130569807 ps |
| CPU time | 12.6 seconds |
| Started | Aug 27 07:29:52 PM UTC 24 |
| Finished | Aug 27 07:30:06 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1137661787 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.1137661787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.1711651733 |
| Short name | T409 |
| Test name | |
| Test status | |
| Simulation time | 2657039532 ps |
| CPU time | 2.53 seconds |
| Started | Aug 27 07:29:47 PM UTC 24 |
| Finished | Aug 27 07:29:51 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1711651733 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.1711651733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_in_out_inverted.282366955 |
| Short name | T407 |
| Test name | |
| Test status | |
| Simulation time | 2472570847 ps |
| CPU time | 4.28 seconds |
| Started | Aug 27 07:29:41 PM UTC 24 |
| Finished | Aug 27 07:29:46 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=282366955 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_in_out_inverted.282366955 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_access_test.1744179728 |
| Short name | T133 |
| Test name | |
| Test status | |
| Simulation time | 2254239292 ps |
| CPU time | 12.13 seconds |
| Started | Aug 27 07:29:42 PM UTC 24 |
| Finished | Aug 27 07:29:55 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1744179728 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_access_test.1744179728 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.578514660 |
| Short name | T395 |
| Test name | |
| Test status | |
| Simulation time | 2525294213 ps |
| CPU time | 3.77 seconds |
| Started | Aug 27 07:29:42 PM UTC 24 |
| Finished | Aug 27 07:29:47 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=578514660 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.578514660 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_smoke.4223700802 |
| Short name | T408 |
| Test name | |
| Test status | |
| Simulation time | 2108646089 ps |
| CPU time | 6.18 seconds |
| Started | Aug 27 07:29:41 PM UTC 24 |
| Finished | Aug 27 07:29:48 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223700802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_smoke.4223700802 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.1847732788 |
| Short name | T99 |
| Test name | |
| Test status | |
| Simulation time | 5679435950 ps |
| CPU time | 4.35 seconds |
| Started | Aug 27 07:29:49 PM UTC 24 |
| Finished | Aug 27 07:29:54 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1847732788 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.1847732788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.1602844797 |
| Short name | T204 |
| Test name | |
| Test status | |
| Simulation time | 2024852566 ps |
| CPU time | 3.88 seconds |
| Started | Aug 27 07:30:09 PM UTC 24 |
| Finished | Aug 27 07:30:15 PM UTC 24 |
| Peak memory | 209992 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1602844797 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.1602844797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.1929660359 |
| Short name | T203 |
| Test name | |
| Test status | |
| Simulation time | 3166201525 ps |
| CPU time | 2.54 seconds |
| Started | Aug 27 07:30:06 PM UTC 24 |
| Finished | Aug 27 07:30:09 PM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1929660359 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.1929660359 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.2642953829 |
| Short name | T119 |
| Test name | |
| Test status | |
| Simulation time | 24225093448 ps |
| CPU time | 83.31 seconds |
| Started | Aug 27 07:30:07 PM UTC 24 |
| Finished | Aug 27 07:31:32 PM UTC 24 |
| Peak memory | 210224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2642953829 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.2642953829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.611137034 |
| Short name | T118 |
| Test name | |
| Test status | |
| Simulation time | 27827534843 ps |
| CPU time | 76.09 seconds |
| Started | Aug 27 07:30:07 PM UTC 24 |
| Finished | Aug 27 07:31:25 PM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=611137034 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_with_pre_cond.611137034 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.2282692879 |
| Short name | T202 |
| Test name | |
| Test status | |
| Simulation time | 3174232166 ps |
| CPU time | 4.28 seconds |
| Started | Aug 27 07:30:02 PM UTC 24 |
| Finished | Aug 27 07:30:07 PM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2282692879 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.2282692879 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.364343968 |
| Short name | T104 |
| Test name | |
| Test status | |
| Simulation time | 339862720285 ps |
| CPU time | 92.16 seconds |
| Started | Aug 27 07:30:07 PM UTC 24 |
| Finished | Aug 27 07:31:41 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=364343968 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.364343968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.589403070 |
| Short name | T201 |
| Test name | |
| Test status | |
| Simulation time | 2635035089 ps |
| CPU time | 4.46 seconds |
| Started | Aug 27 07:30:01 PM UTC 24 |
| Finished | Aug 27 07:30:06 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=589403070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.589403070 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.2757335889 |
| Short name | T135 |
| Test name | |
| Test status | |
| Simulation time | 2526229928 ps |
| CPU time | 1.88 seconds |
| Started | Aug 27 07:29:56 PM UTC 24 |
| Finished | Aug 27 07:29:59 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757335889 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.2757335889 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.1255608389 |
| Short name | T137 |
| Test name | |
| Test status | |
| Simulation time | 2071173073 ps |
| CPU time | 3.59 seconds |
| Started | Aug 27 07:30:00 PM UTC 24 |
| Finished | Aug 27 07:30:05 PM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1255608389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1255608389 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2313244547 |
| Short name | T138 |
| Test name | |
| Test status | |
| Simulation time | 2532926327 ps |
| CPU time | 4.17 seconds |
| Started | Aug 27 07:30:01 PM UTC 24 |
| Finished | Aug 27 07:30:06 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2313244547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2313244547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.3937290636 |
| Short name | T136 |
| Test name | |
| Test status | |
| Simulation time | 2132267925 ps |
| CPU time | 3.89 seconds |
| Started | Aug 27 07:29:55 PM UTC 24 |
| Finished | Aug 27 07:30:00 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937290636 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.3937290636 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.3186338124 |
| Short name | T100 |
| Test name | |
| Test status | |
| Simulation time | 6767649604 ps |
| CPU time | 8.59 seconds |
| Started | Aug 27 07:30:09 PM UTC 24 |
| Finished | Aug 27 07:30:20 PM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3186338124 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.3186338124 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.2718069976 |
| Short name | T311 |
| Test name | |
| Test status | |
| Simulation time | 5781879430 ps |
| CPU time | 29.1 seconds |
| Started | Aug 27 07:30:08 PM UTC 24 |
| Finished | Aug 27 07:30:39 PM UTC 24 |
| Peak memory | 220536 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2718069976 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.2718069976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.1462813150 |
| Short name | T101 |
| Test name | |
| Test status | |
| Simulation time | 8507969522 ps |
| CPU time | 14.53 seconds |
| Started | Aug 27 07:30:07 PM UTC 24 |
| Finished | Aug 27 07:30:23 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1462813150 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.1462813150 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.808899332 |
| Short name | T419 |
| Test name | |
| Test status | |
| Simulation time | 2014434999 ps |
| CPU time | 10.45 seconds |
| Started | Aug 27 07:30:40 PM UTC 24 |
| Finished | Aug 27 07:30:51 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=808899332 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.808899332 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.2245234908 |
| Short name | T312 |
| Test name | |
| Test status | |
| Simulation time | 3642966429 ps |
| CPU time | 17.45 seconds |
| Started | Aug 27 07:30:20 PM UTC 24 |
| Finished | Aug 27 07:30:39 PM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2245234908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.2245234908 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.743776752 |
| Short name | T724 |
| Test name | |
| Test status | |
| Simulation time | 162846565383 ps |
| CPU time | 537.06 seconds |
| Started | Aug 27 07:30:21 PM UTC 24 |
| Finished | Aug 27 07:39:25 PM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743776752 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.743776752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect_with_pre_cond.2784914526 |
| Short name | T165 |
| Test name | |
| Test status | |
| Simulation time | 24081329104 ps |
| CPU time | 89.38 seconds |
| Started | Aug 27 07:30:24 PM UTC 24 |
| Finished | Aug 27 07:31:55 PM UTC 24 |
| Peak memory | 210556 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2784914526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect_with_pre_cond.2784914526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.2554945725 |
| Short name | T415 |
| Test name | |
| Test status | |
| Simulation time | 4023839952 ps |
| CPU time | 19.6 seconds |
| Started | Aug 27 07:30:20 PM UTC 24 |
| Finished | Aug 27 07:30:41 PM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2554945725 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.2554945725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.3520420809 |
| Short name | T413 |
| Test name | |
| Test status | |
| Simulation time | 2613402612 ps |
| CPU time | 8.2 seconds |
| Started | Aug 27 07:30:20 PM UTC 24 |
| Finished | Aug 27 07:30:29 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520420809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.3520420809 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.2133599476 |
| Short name | T206 |
| Test name | |
| Test status | |
| Simulation time | 2531223459 ps |
| CPU time | 2.12 seconds |
| Started | Aug 27 07:30:16 PM UTC 24 |
| Finished | Aug 27 07:30:19 PM UTC 24 |
| Peak memory | 209832 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2133599476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.2133599476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.3332125092 |
| Short name | T411 |
| Test name | |
| Test status | |
| Simulation time | 2051399461 ps |
| CPU time | 3.47 seconds |
| Started | Aug 27 07:30:16 PM UTC 24 |
| Finished | Aug 27 07:30:20 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3332125092 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.3332125092 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3710117397 |
| Short name | T412 |
| Test name | |
| Test status | |
| Simulation time | 2573329155 ps |
| CPU time | 2.05 seconds |
| Started | Aug 27 07:30:20 PM UTC 24 |
| Finished | Aug 27 07:30:23 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3710117397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.3710117397 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.4200501952 |
| Short name | T205 |
| Test name | |
| Test status | |
| Simulation time | 2139540905 ps |
| CPU time | 3.49 seconds |
| Started | Aug 27 07:30:10 PM UTC 24 |
| Finished | Aug 27 07:30:15 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4200501952 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.4200501952 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.1647160042 |
| Short name | T414 |
| Test name | |
| Test status | |
| Simulation time | 12146944222 ps |
| CPU time | 7.17 seconds |
| Started | Aug 27 07:30:32 PM UTC 24 |
| Finished | Aug 27 07:30:40 PM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1647160042 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.1647160042 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.74082974 |
| Short name | T418 |
| Test name | |
| Test status | |
| Simulation time | 18372108189 ps |
| CPU time | 15.22 seconds |
| Started | Aug 27 07:30:31 PM UTC 24 |
| Finished | Aug 27 07:30:47 PM UTC 24 |
| Peak memory | 226620 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=74082974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 - cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev /null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.74082974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1045606891 |
| Short name | T424 |
| Test name | |
| Test status | |
| Simulation time | 2014267052 ps |
| CPU time | 9.35 seconds |
| Started | Aug 27 07:30:58 PM UTC 24 |
| Finished | Aug 27 07:31:09 PM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1045606891 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.1045606891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.2544067427 |
| Short name | T141 |
| Test name | |
| Test status | |
| Simulation time | 3112758819 ps |
| CPU time | 7.09 seconds |
| Started | Aug 27 07:30:47 PM UTC 24 |
| Finished | Aug 27 07:30:55 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544067427 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.2544067427 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.1115452801 |
| Short name | T380 |
| Test name | |
| Test status | |
| Simulation time | 159494345442 ps |
| CPU time | 266.59 seconds |
| Started | Aug 27 07:30:48 PM UTC 24 |
| Finished | Aug 27 07:35:18 PM UTC 24 |
| Peak memory | 210420 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1115452801 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.1115452801 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.3940700498 |
| Short name | T421 |
| Test name | |
| Test status | |
| Simulation time | 3632778157 ps |
| CPU time | 6.03 seconds |
| Started | Aug 27 07:30:46 PM UTC 24 |
| Finished | Aug 27 07:30:53 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3940700498 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.3940700498 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.2840950329 |
| Short name | T51 |
| Test name | |
| Test status | |
| Simulation time | 5294588003 ps |
| CPU time | 20.04 seconds |
| Started | Aug 27 07:30:52 PM UTC 24 |
| Finished | Aug 27 07:31:13 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2840950329 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.2840950329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.175583082 |
| Short name | T420 |
| Test name | |
| Test status | |
| Simulation time | 2611528169 ps |
| CPU time | 8.34 seconds |
| Started | Aug 27 07:30:42 PM UTC 24 |
| Finished | Aug 27 07:30:52 PM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175583082 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.175583082 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.3947827127 |
| Short name | T422 |
| Test name | |
| Test status | |
| Simulation time | 2455625371 ps |
| CPU time | 14.8 seconds |
| Started | Aug 27 07:30:41 PM UTC 24 |
| Finished | Aug 27 07:30:57 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947827127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.3947827127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.2139951893 |
| Short name | T417 |
| Test name | |
| Test status | |
| Simulation time | 2240283495 ps |
| CPU time | 3.95 seconds |
| Started | Aug 27 07:30:41 PM UTC 24 |
| Finished | Aug 27 07:30:46 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139951893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.2139951893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.1062199868 |
| Short name | T326 |
| Test name | |
| Test status | |
| Simulation time | 2530328182 ps |
| CPU time | 3.63 seconds |
| Started | Aug 27 07:30:42 PM UTC 24 |
| Finished | Aug 27 07:30:47 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1062199868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.1062199868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.475415052 |
| Short name | T416 |
| Test name | |
| Test status | |
| Simulation time | 2130438148 ps |
| CPU time | 3.54 seconds |
| Started | Aug 27 07:30:40 PM UTC 24 |
| Finished | Aug 27 07:30:45 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=475415052 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.475415052 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.2087144806 |
| Short name | T171 |
| Test name | |
| Test status | |
| Simulation time | 16813055426 ps |
| CPU time | 13.2 seconds |
| Started | Aug 27 07:30:55 PM UTC 24 |
| Finished | Aug 27 07:31:10 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2087144806 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.2087144806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.1125437074 |
| Short name | T313 |
| Test name | |
| Test status | |
| Simulation time | 4639855778 ps |
| CPU time | 26.43 seconds |
| Started | Aug 27 07:30:53 PM UTC 24 |
| Finished | Aug 27 07:31:21 PM UTC 24 |
| Peak memory | 220464 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1125437074 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.1125437074 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.3074734621 |
| Short name | T224 |
| Test name | |
| Test status | |
| Simulation time | 924041601571 ps |
| CPU time | 106.72 seconds |
| Started | Aug 27 07:30:48 PM UTC 24 |
| Finished | Aug 27 07:32:37 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3074734621 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.3074734621 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.666959976 |
| Short name | T429 |
| Test name | |
| Test status | |
| Simulation time | 2025331256 ps |
| CPU time | 3.74 seconds |
| Started | Aug 27 07:31:17 PM UTC 24 |
| Finished | Aug 27 07:31:22 PM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=666959976 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.666959976 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.2164941496 |
| Short name | T428 |
| Test name | |
| Test status | |
| Simulation time | 3521966449 ps |
| CPU time | 4.66 seconds |
| Started | Aug 27 07:31:10 PM UTC 24 |
| Finished | Aug 27 07:31:16 PM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2164941496 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.2164941496 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.3998576910 |
| Short name | T272 |
| Test name | |
| Test status | |
| Simulation time | 70850926762 ps |
| CPU time | 25.05 seconds |
| Started | Aug 27 07:31:15 PM UTC 24 |
| Finished | Aug 27 07:31:41 PM UTC 24 |
| Peak memory | 210364 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3998576910 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.3998576910 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.1597439833 |
| Short name | T269 |
| Test name | |
| Test status | |
| Simulation time | 43392830096 ps |
| CPU time | 132.17 seconds |
| Started | Aug 27 07:31:16 PM UTC 24 |
| Finished | Aug 27 07:33:30 PM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597439833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_with_pre_cond.1597439833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.3632300410 |
| Short name | T427 |
| Test name | |
| Test status | |
| Simulation time | 4709964728 ps |
| CPU time | 5.01 seconds |
| Started | Aug 27 07:31:09 PM UTC 24 |
| Finished | Aug 27 07:31:15 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632300410 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.3632300410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.2940952518 |
| Short name | T744 |
| Test name | |
| Test status | |
| Simulation time | 370492023866 ps |
| CPU time | 603.84 seconds |
| Started | Aug 27 07:31:15 PM UTC 24 |
| Finished | Aug 27 07:41:25 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2940952518 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.2940952518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.4034380570 |
| Short name | T426 |
| Test name | |
| Test status | |
| Simulation time | 2626596712 ps |
| CPU time | 4.25 seconds |
| Started | Aug 27 07:31:08 PM UTC 24 |
| Finished | Aug 27 07:31:13 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4034380570 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.4034380570 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.2544086242 |
| Short name | T323 |
| Test name | |
| Test status | |
| Simulation time | 2449546716 ps |
| CPU time | 10.67 seconds |
| Started | Aug 27 07:31:03 PM UTC 24 |
| Finished | Aug 27 07:31:15 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2544086242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.2544086242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.3777586046 |
| Short name | T425 |
| Test name | |
| Test status | |
| Simulation time | 2075501588 ps |
| CPU time | 4.09 seconds |
| Started | Aug 27 07:31:04 PM UTC 24 |
| Finished | Aug 27 07:31:09 PM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3777586046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.3777586046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.733724203 |
| Short name | T327 |
| Test name | |
| Test status | |
| Simulation time | 2510058167 ps |
| CPU time | 10.99 seconds |
| Started | Aug 27 07:31:05 PM UTC 24 |
| Finished | Aug 27 07:31:17 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=733724203 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.733724203 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.345941997 |
| Short name | T423 |
| Test name | |
| Test status | |
| Simulation time | 2112607066 ps |
| CPU time | 6.69 seconds |
| Started | Aug 27 07:31:00 PM UTC 24 |
| Finished | Aug 27 07:31:07 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=345941997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.345941997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.2529490909 |
| Short name | T140 |
| Test name | |
| Test status | |
| Simulation time | 16571048969 ps |
| CPU time | 80.53 seconds |
| Started | Aug 27 07:31:16 PM UTC 24 |
| Finished | Aug 27 07:32:38 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529490909 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.2529490909 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.381233655 |
| Short name | T433 |
| Test name | |
| Test status | |
| Simulation time | 3280257774 ps |
| CPU time | 15.15 seconds |
| Started | Aug 27 07:31:16 PM UTC 24 |
| Finished | Aug 27 07:31:32 PM UTC 24 |
| Peak memory | 209996 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=381233655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.381233655 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.2753408852 |
| Short name | T231 |
| Test name | |
| Test status | |
| Simulation time | 2035269747 ps |
| CPU time | 3.06 seconds |
| Started | Aug 27 07:31:39 PM UTC 24 |
| Finished | Aug 27 07:31:44 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2753408852 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.2753408852 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.1090986974 |
| Short name | T437 |
| Test name | |
| Test status | |
| Simulation time | 3921997526 ps |
| CPU time | 10.17 seconds |
| Started | Aug 27 07:31:27 PM UTC 24 |
| Finished | Aug 27 07:31:39 PM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1090986974 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.1090986974 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3768452494 |
| Short name | T434 |
| Test name | |
| Test status | |
| Simulation time | 4075618225 ps |
| CPU time | 4.21 seconds |
| Started | Aug 27 07:31:27 PM UTC 24 |
| Finished | Aug 27 07:31:33 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768452494 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.3768452494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.2289974161 |
| Short name | T435 |
| Test name | |
| Test status | |
| Simulation time | 2611847375 ps |
| CPU time | 9.49 seconds |
| Started | Aug 27 07:31:26 PM UTC 24 |
| Finished | Aug 27 07:31:37 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2289974161 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.2289974161 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.3659453849 |
| Short name | T431 |
| Test name | |
| Test status | |
| Simulation time | 2485633117 ps |
| CPU time | 3.07 seconds |
| Started | Aug 27 07:31:22 PM UTC 24 |
| Finished | Aug 27 07:31:26 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3659453849 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.3659453849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.3377674844 |
| Short name | T432 |
| Test name | |
| Test status | |
| Simulation time | 2050174905 ps |
| CPU time | 3.28 seconds |
| Started | Aug 27 07:31:22 PM UTC 24 |
| Finished | Aug 27 07:31:27 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377674844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.3377674844 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.2149775798 |
| Short name | T436 |
| Test name | |
| Test status | |
| Simulation time | 2510946851 ps |
| CPU time | 13.77 seconds |
| Started | Aug 27 07:31:23 PM UTC 24 |
| Finished | Aug 27 07:31:38 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2149775798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.2149775798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.3468242104 |
| Short name | T430 |
| Test name | |
| Test status | |
| Simulation time | 2123932022 ps |
| CPU time | 3.82 seconds |
| Started | Aug 27 07:31:18 PM UTC 24 |
| Finished | Aug 27 07:31:23 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3468242104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3468242104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3342301785 |
| Short name | T106 |
| Test name | |
| Test status | |
| Simulation time | 17918576165 ps |
| CPU time | 5.05 seconds |
| Started | Aug 27 07:31:38 PM UTC 24 |
| Finished | Aug 27 07:31:45 PM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3342301785 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.3342301785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.3299016780 |
| Short name | T296 |
| Test name | |
| Test status | |
| Simulation time | 6110343441 ps |
| CPU time | 27.72 seconds |
| Started | Aug 27 07:31:37 PM UTC 24 |
| Finished | Aug 27 07:32:07 PM UTC 24 |
| Peak memory | 226656 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3299016780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.3299016780 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.2838898792 |
| Short name | T329 |
| Test name | |
| Test status | |
| Simulation time | 3959604323 ps |
| CPU time | 2.59 seconds |
| Started | Aug 27 07:31:33 PM UTC 24 |
| Finished | Aug 27 07:31:36 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2838898792 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.2838898792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2661785336 |
| Short name | T166 |
| Test name | |
| Test status | |
| Simulation time | 2030864327 ps |
| CPU time | 3.38 seconds |
| Started | Aug 27 07:31:52 PM UTC 24 |
| Finished | Aug 27 07:31:57 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2661785336 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.2661785336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1597447891 |
| Short name | T163 |
| Test name | |
| Test status | |
| Simulation time | 3736253016 ps |
| CPU time | 6.08 seconds |
| Started | Aug 27 07:31:45 PM UTC 24 |
| Finished | Aug 27 07:31:52 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1597447891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.1597447891 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1329282002 |
| Short name | T218 |
| Test name | |
| Test status | |
| Simulation time | 148261282597 ps |
| CPU time | 37.25 seconds |
| Started | Aug 27 07:31:47 PM UTC 24 |
| Finished | Aug 27 07:32:26 PM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1329282002 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.1329282002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.3723936132 |
| Short name | T268 |
| Test name | |
| Test status | |
| Simulation time | 31162808659 ps |
| CPU time | 126.17 seconds |
| Started | Aug 27 07:31:51 PM UTC 24 |
| Finished | Aug 27 07:34:00 PM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723936132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_with_pre_cond.3723936132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.2916235440 |
| Short name | T306 |
| Test name | |
| Test status | |
| Simulation time | 3868009846 ps |
| CPU time | 20.81 seconds |
| Started | Aug 27 07:31:45 PM UTC 24 |
| Finished | Aug 27 07:32:07 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916235440 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.2916235440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.4160340003 |
| Short name | T196 |
| Test name | |
| Test status | |
| Simulation time | 3378423574 ps |
| CPU time | 8.42 seconds |
| Started | Aug 27 07:31:51 PM UTC 24 |
| Finished | Aug 27 07:32:01 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4160340003 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.4160340003 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.336816825 |
| Short name | T160 |
| Test name | |
| Test status | |
| Simulation time | 2630287466 ps |
| CPU time | 4.61 seconds |
| Started | Aug 27 07:31:45 PM UTC 24 |
| Finished | Aug 27 07:31:50 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336816825 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.336816825 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.2054458232 |
| Short name | T229 |
| Test name | |
| Test status | |
| Simulation time | 2522403768 ps |
| CPU time | 1.73 seconds |
| Started | Aug 27 07:31:40 PM UTC 24 |
| Finished | Aug 27 07:31:44 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2054458232 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.2054458232 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.1777199139 |
| Short name | T162 |
| Test name | |
| Test status | |
| Simulation time | 2074113843 ps |
| CPU time | 8.99 seconds |
| Started | Aug 27 07:31:42 PM UTC 24 |
| Finished | Aug 27 07:31:52 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1777199139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.1777199139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.610518515 |
| Short name | T161 |
| Test name | |
| Test status | |
| Simulation time | 2510630762 ps |
| CPU time | 7.6 seconds |
| Started | Aug 27 07:31:43 PM UTC 24 |
| Finished | Aug 27 07:31:52 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=610518515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.610518515 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.3491240678 |
| Short name | T230 |
| Test name | |
| Test status | |
| Simulation time | 2151284266 ps |
| CPU time | 2.97 seconds |
| Started | Aug 27 07:31:39 PM UTC 24 |
| Finished | Aug 27 07:31:44 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3491240678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.3491240678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.1853865308 |
| Short name | T217 |
| Test name | |
| Test status | |
| Simulation time | 9822916283 ps |
| CPU time | 31.55 seconds |
| Started | Aug 27 07:31:52 PM UTC 24 |
| Finished | Aug 27 07:32:25 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1853865308 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.1853865308 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.1623206132 |
| Short name | T164 |
| Test name | |
| Test status | |
| Simulation time | 2872497199 ps |
| CPU time | 5.18 seconds |
| Started | Aug 27 07:31:46 PM UTC 24 |
| Finished | Aug 27 07:31:52 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623206132 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.1623206132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.775382487 |
| Short name | T148 |
| Test name | |
| Test status | |
| Simulation time | 2015677317 ps |
| CPU time | 3.02 seconds |
| Started | Aug 27 07:32:17 PM UTC 24 |
| Finished | Aug 27 07:32:21 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=775382487 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.775382487 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.419767418 |
| Short name | T150 |
| Test name | |
| Test status | |
| Simulation time | 3549431911 ps |
| CPU time | 18.56 seconds |
| Started | Aug 27 07:32:02 PM UTC 24 |
| Finished | Aug 27 07:32:22 PM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=419767418 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.419767418 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.1560942489 |
| Short name | T333 |
| Test name | |
| Test status | |
| Simulation time | 120683807927 ps |
| CPU time | 96.76 seconds |
| Started | Aug 27 07:32:07 PM UTC 24 |
| Finished | Aug 27 07:33:46 PM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1560942489 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.1560942489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.2873824108 |
| Short name | T145 |
| Test name | |
| Test status | |
| Simulation time | 4666440326 ps |
| CPU time | 7.74 seconds |
| Started | Aug 27 07:32:02 PM UTC 24 |
| Finished | Aug 27 07:32:11 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2873824108 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.2873824108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.2836497954 |
| Short name | T112 |
| Test name | |
| Test status | |
| Simulation time | 3535055648 ps |
| CPU time | 15.74 seconds |
| Started | Aug 27 07:32:07 PM UTC 24 |
| Finished | Aug 27 07:32:24 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2836497954 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.2836497954 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.3887794306 |
| Short name | T147 |
| Test name | |
| Test status | |
| Simulation time | 2608506268 ps |
| CPU time | 13.01 seconds |
| Started | Aug 27 07:32:02 PM UTC 24 |
| Finished | Aug 27 07:32:16 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3887794306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.3887794306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.1923487272 |
| Short name | T146 |
| Test name | |
| Test status | |
| Simulation time | 2452279289 ps |
| CPU time | 14.14 seconds |
| Started | Aug 27 07:31:56 PM UTC 24 |
| Finished | Aug 27 07:32:11 PM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1923487272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.1923487272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.2824626904 |
| Short name | T438 |
| Test name | |
| Test status | |
| Simulation time | 2262215992 ps |
| CPU time | 2.32 seconds |
| Started | Aug 27 07:31:58 PM UTC 24 |
| Finished | Aug 27 07:32:01 PM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2824626904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.2824626904 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.1659742357 |
| Short name | T328 |
| Test name | |
| Test status | |
| Simulation time | 2569280871 ps |
| CPU time | 2.64 seconds |
| Started | Aug 27 07:32:01 PM UTC 24 |
| Finished | Aug 27 07:32:04 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1659742357 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.1659742357 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.3443528440 |
| Short name | T439 |
| Test name | |
| Test status | |
| Simulation time | 2118331725 ps |
| CPU time | 6.39 seconds |
| Started | Aug 27 07:31:54 PM UTC 24 |
| Finished | Aug 27 07:32:01 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3443528440 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.3443528440 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.1931217630 |
| Short name | T210 |
| Test name | |
| Test status | |
| Simulation time | 9276781370 ps |
| CPU time | 39.34 seconds |
| Started | Aug 27 07:32:13 PM UTC 24 |
| Finished | Aug 27 07:32:53 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1931217630 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.1931217630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.1089863561 |
| Short name | T149 |
| Test name | |
| Test status | |
| Simulation time | 2675523223 ps |
| CPU time | 8.41 seconds |
| Started | Aug 27 07:32:11 PM UTC 24 |
| Finished | Aug 27 07:32:21 PM UTC 24 |
| Peak memory | 210400 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1089863561 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.1089863561 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.2680489738 |
| Short name | T103 |
| Test name | |
| Test status | |
| Simulation time | 9182086911 ps |
| CPU time | 3.35 seconds |
| Started | Aug 27 07:32:05 PM UTC 24 |
| Finished | Aug 27 07:32:10 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680489738 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.2680489738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.2484903262 |
| Short name | T441 |
| Test name | |
| Test status | |
| Simulation time | 2033191228 ps |
| CPU time | 3.36 seconds |
| Started | Aug 27 07:32:37 PM UTC 24 |
| Finished | Aug 27 07:32:41 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484903262 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.2484903262 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.2207228304 |
| Short name | T314 |
| Test name | |
| Test status | |
| Simulation time | 3237991424 ps |
| CPU time | 16.2 seconds |
| Started | Aug 27 07:32:25 PM UTC 24 |
| Finished | Aug 27 07:32:43 PM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2207228304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.2207228304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.580970504 |
| Short name | T379 |
| Test name | |
| Test status | |
| Simulation time | 38218059387 ps |
| CPU time | 114.78 seconds |
| Started | Aug 27 07:32:26 PM UTC 24 |
| Finished | Aug 27 07:34:23 PM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=580970504 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.580970504 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.1334809888 |
| Short name | T225 |
| Test name | |
| Test status | |
| Simulation time | 3644433121 ps |
| CPU time | 11.39 seconds |
| Started | Aug 27 07:32:24 PM UTC 24 |
| Finished | Aug 27 07:32:37 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334809888 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.1334809888 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.587513461 |
| Short name | T222 |
| Test name | |
| Test status | |
| Simulation time | 2617521214 ps |
| CPU time | 8.42 seconds |
| Started | Aug 27 07:32:24 PM UTC 24 |
| Finished | Aug 27 07:32:34 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=587513461 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.587513461 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.1671773744 |
| Short name | T223 |
| Test name | |
| Test status | |
| Simulation time | 2445522936 ps |
| CPU time | 12.23 seconds |
| Started | Aug 27 07:32:22 PM UTC 24 |
| Finished | Aug 27 07:32:35 PM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671773744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.1671773744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1827665993 |
| Short name | T220 |
| Test name | |
| Test status | |
| Simulation time | 2230239929 ps |
| CPU time | 4.28 seconds |
| Started | Aug 27 07:32:22 PM UTC 24 |
| Finished | Aug 27 07:32:27 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827665993 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.1827665993 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.1095165729 |
| Short name | T221 |
| Test name | |
| Test status | |
| Simulation time | 2525695750 ps |
| CPU time | 4.22 seconds |
| Started | Aug 27 07:32:23 PM UTC 24 |
| Finished | Aug 27 07:32:28 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1095165729 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.1095165729 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.3690153994 |
| Short name | T151 |
| Test name | |
| Test status | |
| Simulation time | 2138339982 ps |
| CPU time | 2.46 seconds |
| Started | Aug 27 07:32:20 PM UTC 24 |
| Finished | Aug 27 07:32:23 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3690153994 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.3690153994 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.3179697968 |
| Short name | T322 |
| Test name | |
| Test status | |
| Simulation time | 10904341304 ps |
| CPU time | 12.79 seconds |
| Started | Aug 27 07:32:34 PM UTC 24 |
| Finished | Aug 27 07:32:48 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3179697968 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.3179697968 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1069408419 |
| Short name | T446 |
| Test name | |
| Test status | |
| Simulation time | 3641803670 ps |
| CPU time | 19.63 seconds |
| Started | Aug 27 07:32:29 PM UTC 24 |
| Finished | Aug 27 07:32:50 PM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1069408419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.1069408419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ultra_low_pwr.306057931 |
| Short name | T723 |
| Test name | |
| Test status | |
| Simulation time | 4120846041428 ps |
| CPU time | 413.07 seconds |
| Started | Aug 27 07:32:26 PM UTC 24 |
| Finished | Aug 27 07:39:24 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=306057931 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ultra_low_pwr.306057931 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.132120733 |
| Short name | T233 |
| Test name | |
| Test status | |
| Simulation time | 2037711079 ps |
| CPU time | 2.82 seconds |
| Started | Aug 27 07:32:50 PM UTC 24 |
| Finished | Aug 27 07:32:54 PM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=132120733 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.132120733 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.483480772 |
| Short name | T447 |
| Test name | |
| Test status | |
| Simulation time | 3305621232 ps |
| CPU time | 6.16 seconds |
| Started | Aug 27 07:32:43 PM UTC 24 |
| Finished | Aug 27 07:32:50 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=483480772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.483480772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.3520635104 |
| Short name | T355 |
| Test name | |
| Test status | |
| Simulation time | 230419788187 ps |
| CPU time | 110.79 seconds |
| Started | Aug 27 07:32:46 PM UTC 24 |
| Finished | Aug 27 07:34:39 PM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3520635104 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_with_pre_cond.3520635104 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.4229100454 |
| Short name | T448 |
| Test name | |
| Test status | |
| Simulation time | 3366716577 ps |
| CPU time | 10.37 seconds |
| Started | Aug 27 07:32:41 PM UTC 24 |
| Finished | Aug 27 07:32:53 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4229100454 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.4229100454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.700605296 |
| Short name | T182 |
| Test name | |
| Test status | |
| Simulation time | 4424454907 ps |
| CPU time | 5.49 seconds |
| Started | Aug 27 07:32:46 PM UTC 24 |
| Finished | Aug 27 07:32:53 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=700605296 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.700605296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.2012680114 |
| Short name | T445 |
| Test name | |
| Test status | |
| Simulation time | 2638341935 ps |
| CPU time | 4.61 seconds |
| Started | Aug 27 07:32:41 PM UTC 24 |
| Finished | Aug 27 07:32:47 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012680114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.2012680114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.1797289554 |
| Short name | T443 |
| Test name | |
| Test status | |
| Simulation time | 2459434036 ps |
| CPU time | 4.07 seconds |
| Started | Aug 27 07:32:38 PM UTC 24 |
| Finished | Aug 27 07:32:43 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1797289554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.1797289554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.1328405629 |
| Short name | T442 |
| Test name | |
| Test status | |
| Simulation time | 2147372482 ps |
| CPU time | 2.39 seconds |
| Started | Aug 27 07:32:38 PM UTC 24 |
| Finished | Aug 27 07:32:41 PM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1328405629 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.1328405629 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.3808351261 |
| Short name | T444 |
| Test name | |
| Test status | |
| Simulation time | 2519391668 ps |
| CPU time | 5.17 seconds |
| Started | Aug 27 07:32:39 PM UTC 24 |
| Finished | Aug 27 07:32:45 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3808351261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.3808351261 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3555323638 |
| Short name | T440 |
| Test name | |
| Test status | |
| Simulation time | 2131194217 ps |
| CPU time | 3.25 seconds |
| Started | Aug 27 07:32:37 PM UTC 24 |
| Finished | Aug 27 07:32:41 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3555323638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.3555323638 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.531215778 |
| Short name | T239 |
| Test name | |
| Test status | |
| Simulation time | 12335774660 ps |
| CPU time | 8.95 seconds |
| Started | Aug 27 07:32:49 PM UTC 24 |
| Finished | Aug 27 07:32:59 PM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=531215778 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.531215778 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.3740898040 |
| Short name | T107 |
| Test name | |
| Test status | |
| Simulation time | 4416724256 ps |
| CPU time | 4.38 seconds |
| Started | Aug 27 07:32:44 PM UTC 24 |
| Finished | Aug 27 07:32:49 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3740898040 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.3740898040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.1752334106 |
| Short name | T57 |
| Test name | |
| Test status | |
| Simulation time | 2041193416 ps |
| CPU time | 3.28 seconds |
| Started | Aug 27 07:27:23 PM UTC 24 |
| Finished | Aug 27 07:27:27 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752334106 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.1752334106 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.3211569757 |
| Short name | T30 |
| Test name | |
| Test status | |
| Simulation time | 3621698465 ps |
| CPU time | 19.99 seconds |
| Started | Aug 27 07:27:14 PM UTC 24 |
| Finished | Aug 27 07:27:35 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3211569757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.3211569757 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.137990139 |
| Short name | T65 |
| Test name | |
| Test status | |
| Simulation time | 2226368017 ps |
| CPU time | 4.08 seconds |
| Started | Aug 27 07:27:07 PM UTC 24 |
| Finished | Aug 27 07:27:12 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137990139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.137990139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2256743430 |
| Short name | T31 |
| Test name | |
| Test status | |
| Simulation time | 2356860921 ps |
| CPU time | 3.61 seconds |
| Started | Aug 27 07:27:08 PM UTC 24 |
| Finished | Aug 27 07:27:13 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2256743430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2256743430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.553284393 |
| Short name | T34 |
| Test name | |
| Test status | |
| Simulation time | 23829252656 ps |
| CPU time | 82.59 seconds |
| Started | Aug 27 07:27:17 PM UTC 24 |
| Finished | Aug 27 07:28:41 PM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=553284393 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_with_pre_cond.553284393 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.143725289 |
| Short name | T139 |
| Test name | |
| Test status | |
| Simulation time | 3566538212 ps |
| CPU time | 3.19 seconds |
| Started | Aug 27 07:27:14 PM UTC 24 |
| Finished | Aug 27 07:27:18 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=143725289 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.143725289 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.2821969588 |
| Short name | T9 |
| Test name | |
| Test status | |
| Simulation time | 4718334893 ps |
| CPU time | 4.06 seconds |
| Started | Aug 27 07:27:16 PM UTC 24 |
| Finished | Aug 27 07:27:21 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821969588 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.2821969588 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.1267984884 |
| Short name | T84 |
| Test name | |
| Test status | |
| Simulation time | 2611513147 ps |
| CPU time | 13.85 seconds |
| Started | Aug 27 07:27:12 PM UTC 24 |
| Finished | Aug 27 07:27:27 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1267984884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.1267984884 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.514451707 |
| Short name | T25 |
| Test name | |
| Test status | |
| Simulation time | 2453337500 ps |
| CPU time | 7.05 seconds |
| Started | Aug 27 07:27:01 PM UTC 24 |
| Finished | Aug 27 07:27:09 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=514451707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.514451707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.3963333741 |
| Short name | T72 |
| Test name | |
| Test status | |
| Simulation time | 2141700058 ps |
| CPU time | 3.9 seconds |
| Started | Aug 27 07:27:10 PM UTC 24 |
| Finished | Aug 27 07:27:15 PM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963333741 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.3963333741 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.3187674988 |
| Short name | T54 |
| Test name | |
| Test status | |
| Simulation time | 22012034752 ps |
| CPU time | 87.12 seconds |
| Started | Aug 27 07:27:19 PM UTC 24 |
| Finished | Aug 27 07:28:49 PM UTC 24 |
| Peak memory | 238228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187674988 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.3187674988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3231857489 |
| Short name | T71 |
| Test name | |
| Test status | |
| Simulation time | 2114531256 ps |
| CPU time | 6.48 seconds |
| Started | Aug 27 07:27:00 PM UTC 24 |
| Finished | Aug 27 07:27:07 PM UTC 24 |
| Peak memory | 209820 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3231857489 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.3231857489 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.3696153936 |
| Short name | T234 |
| Test name | |
| Test status | |
| Simulation time | 177484762112 ps |
| CPU time | 330.1 seconds |
| Started | Aug 27 07:27:19 PM UTC 24 |
| Finished | Aug 27 07:32:54 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696153936 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.3696153936 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1221409194 |
| Short name | T61 |
| Test name | |
| Test status | |
| Simulation time | 3717787311 ps |
| CPU time | 6.58 seconds |
| Started | Aug 27 07:27:19 PM UTC 24 |
| Finished | Aug 27 07:27:28 PM UTC 24 |
| Peak memory | 210044 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1221409194 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.1221409194 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.3775293917 |
| Short name | T23 |
| Test name | |
| Test status | |
| Simulation time | 4799582382 ps |
| CPU time | 3.43 seconds |
| Started | Aug 27 07:27:14 PM UTC 24 |
| Finished | Aug 27 07:27:18 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775293917 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.3775293917 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.2891061911 |
| Short name | T452 |
| Test name | |
| Test status | |
| Simulation time | 2015002355 ps |
| CPU time | 10.93 seconds |
| Started | Aug 27 07:32:59 PM UTC 24 |
| Finished | Aug 27 07:33:12 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2891061911 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.2891061911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2270998132 |
| Short name | T473 |
| Test name | |
| Test status | |
| Simulation time | 91909430734 ps |
| CPU time | 62.33 seconds |
| Started | Aug 27 07:32:55 PM UTC 24 |
| Finished | Aug 27 07:33:59 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270998132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.2270998132 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.1982164316 |
| Short name | T376 |
| Test name | |
| Test status | |
| Simulation time | 112321052264 ps |
| CPU time | 355.41 seconds |
| Started | Aug 27 07:32:56 PM UTC 24 |
| Finished | Aug 27 07:38:56 PM UTC 24 |
| Peak memory | 210564 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1982164316 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.1982164316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.4252853175 |
| Short name | T121 |
| Test name | |
| Test status | |
| Simulation time | 28830356435 ps |
| CPU time | 81.58 seconds |
| Started | Aug 27 07:32:58 PM UTC 24 |
| Finished | Aug 27 07:34:21 PM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252853175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_with_pre_cond.4252853175 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.1475896520 |
| Short name | T450 |
| Test name | |
| Test status | |
| Simulation time | 3313174930 ps |
| CPU time | 9.63 seconds |
| Started | Aug 27 07:32:55 PM UTC 24 |
| Finished | Aug 27 07:33:06 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1475896520 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.1475896520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.20434524 |
| Short name | T216 |
| Test name | |
| Test status | |
| Simulation time | 6010936776 ps |
| CPU time | 2.75 seconds |
| Started | Aug 27 07:32:56 PM UTC 24 |
| Finished | Aug 27 07:33:00 PM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20434524 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra tch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.20434524 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.278627584 |
| Short name | T238 |
| Test name | |
| Test status | |
| Simulation time | 2636211985 ps |
| CPU time | 3.63 seconds |
| Started | Aug 27 07:32:54 PM UTC 24 |
| Finished | Aug 27 07:32:58 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=278627584 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.278627584 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.2897650953 |
| Short name | T235 |
| Test name | |
| Test status | |
| Simulation time | 2489817789 ps |
| CPU time | 2.5 seconds |
| Started | Aug 27 07:32:51 PM UTC 24 |
| Finished | Aug 27 07:32:55 PM UTC 24 |
| Peak memory | 210100 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2897650953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.2897650953 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3751868244 |
| Short name | T237 |
| Test name | |
| Test status | |
| Simulation time | 2233925721 ps |
| CPU time | 4.19 seconds |
| Started | Aug 27 07:32:51 PM UTC 24 |
| Finished | Aug 27 07:32:56 PM UTC 24 |
| Peak memory | 209780 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751868244 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.3751868244 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.605699856 |
| Short name | T240 |
| Test name | |
| Test status | |
| Simulation time | 2528895264 ps |
| CPU time | 4.11 seconds |
| Started | Aug 27 07:32:53 PM UTC 24 |
| Finished | Aug 27 07:32:59 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=605699856 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.605699856 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.291025783 |
| Short name | T236 |
| Test name | |
| Test status | |
| Simulation time | 2120451868 ps |
| CPU time | 4.86 seconds |
| Started | Aug 27 07:32:50 PM UTC 24 |
| Finished | Aug 27 07:32:56 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=291025783 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.291025783 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.876603247 |
| Short name | T113 |
| Test name | |
| Test status | |
| Simulation time | 16195615551 ps |
| CPU time | 36.63 seconds |
| Started | Aug 27 07:32:59 PM UTC 24 |
| Finished | Aug 27 07:33:38 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=876603247 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.876603247 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1874180499 |
| Short name | T304 |
| Test name | |
| Test status | |
| Simulation time | 5171388700 ps |
| CPU time | 14.4 seconds |
| Started | Aug 27 07:32:58 PM UTC 24 |
| Finished | Aug 27 07:33:13 PM UTC 24 |
| Peak memory | 220476 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1874180499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.1874180499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.4144305015 |
| Short name | T456 |
| Test name | |
| Test status | |
| Simulation time | 2012501856 ps |
| CPU time | 7.15 seconds |
| Started | Aug 27 07:33:23 PM UTC 24 |
| Finished | Aug 27 07:33:31 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4144305015 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.4144305015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3427891832 |
| Short name | T315 |
| Test name | |
| Test status | |
| Simulation time | 3652019432 ps |
| CPU time | 2.86 seconds |
| Started | Aug 27 07:33:12 PM UTC 24 |
| Finished | Aug 27 07:33:16 PM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3427891832 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.3427891832 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.3351469793 |
| Short name | T292 |
| Test name | |
| Test status | |
| Simulation time | 81475147818 ps |
| CPU time | 60.83 seconds |
| Started | Aug 27 07:33:14 PM UTC 24 |
| Finished | Aug 27 07:34:17 PM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3351469793 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.3351469793 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.3776040601 |
| Short name | T352 |
| Test name | |
| Test status | |
| Simulation time | 46047921648 ps |
| CPU time | 155.72 seconds |
| Started | Aug 27 07:33:17 PM UTC 24 |
| Finished | Aug 27 07:35:55 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3776040601 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_with_pre_cond.3776040601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2278038722 |
| Short name | T455 |
| Test name | |
| Test status | |
| Simulation time | 3702819514 ps |
| CPU time | 10.22 seconds |
| Started | Aug 27 07:33:10 PM UTC 24 |
| Finished | Aug 27 07:33:22 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278038722 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.2278038722 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.3288576662 |
| Short name | T183 |
| Test name | |
| Test status | |
| Simulation time | 5945250187 ps |
| CPU time | 9.53 seconds |
| Started | Aug 27 07:33:15 PM UTC 24 |
| Finished | Aug 27 07:33:26 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3288576662 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.3288576662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3420851797 |
| Short name | T453 |
| Test name | |
| Test status | |
| Simulation time | 2619806191 ps |
| CPU time | 5.45 seconds |
| Started | Aug 27 07:33:07 PM UTC 24 |
| Finished | Aug 27 07:33:14 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420851797 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.3420851797 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.4040245997 |
| Short name | T324 |
| Test name | |
| Test status | |
| Simulation time | 2475411299 ps |
| CPU time | 6.95 seconds |
| Started | Aug 27 07:33:02 PM UTC 24 |
| Finished | Aug 27 07:33:10 PM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4040245997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.4040245997 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.959837862 |
| Short name | T454 |
| Test name | |
| Test status | |
| Simulation time | 2061935470 ps |
| CPU time | 10.72 seconds |
| Started | Aug 27 07:33:04 PM UTC 24 |
| Finished | Aug 27 07:33:16 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959837862 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.959837862 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.3471692287 |
| Short name | T451 |
| Test name | |
| Test status | |
| Simulation time | 2530786222 ps |
| CPU time | 4.22 seconds |
| Started | Aug 27 07:33:05 PM UTC 24 |
| Finished | Aug 27 07:33:10 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3471692287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.3471692287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.428836607 |
| Short name | T449 |
| Test name | |
| Test status | |
| Simulation time | 2178966903 ps |
| CPU time | 1.73 seconds |
| Started | Aug 27 07:33:00 PM UTC 24 |
| Finished | Aug 27 07:33:03 PM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428836607 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.428836607 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3495342811 |
| Short name | T466 |
| Test name | |
| Test status | |
| Simulation time | 11224295138 ps |
| CPU time | 26.92 seconds |
| Started | Aug 27 07:33:19 PM UTC 24 |
| Finished | Aug 27 07:33:47 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495342811 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.3495342811 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3385727155 |
| Short name | T316 |
| Test name | |
| Test status | |
| Simulation time | 9329506758 ps |
| CPU time | 13.13 seconds |
| Started | Aug 27 07:33:17 PM UTC 24 |
| Finished | Aug 27 07:33:31 PM UTC 24 |
| Peak memory | 220408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3385727155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.3385727155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1164072326 |
| Short name | T457 |
| Test name | |
| Test status | |
| Simulation time | 5779368317 ps |
| CPU time | 14.02 seconds |
| Started | Aug 27 07:33:13 PM UTC 24 |
| Finished | Aug 27 07:33:28 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164072326 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.1164072326 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.738161209 |
| Short name | T467 |
| Test name | |
| Test status | |
| Simulation time | 2013679112 ps |
| CPU time | 8.3 seconds |
| Started | Aug 27 07:33:38 PM UTC 24 |
| Finished | Aug 27 07:33:47 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=738161209 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.738161209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.855317885 |
| Short name | T469 |
| Test name | |
| Test status | |
| Simulation time | 3366570909 ps |
| CPU time | 18.82 seconds |
| Started | Aug 27 07:33:33 PM UTC 24 |
| Finished | Aug 27 07:33:53 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=855317885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.855317885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.131949015 |
| Short name | T270 |
| Test name | |
| Test status | |
| Simulation time | 42374493905 ps |
| CPU time | 22.52 seconds |
| Started | Aug 27 07:33:35 PM UTC 24 |
| Finished | Aug 27 07:33:58 PM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=131949015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_with_pre_cond.131949015 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3376859159 |
| Short name | T463 |
| Test name | |
| Test status | |
| Simulation time | 5323888044 ps |
| CPU time | 5.71 seconds |
| Started | Aug 27 07:33:33 PM UTC 24 |
| Finished | Aug 27 07:33:40 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3376859159 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.3376859159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1037738439 |
| Short name | T184 |
| Test name | |
| Test status | |
| Simulation time | 4315220728 ps |
| CPU time | 5.23 seconds |
| Started | Aug 27 07:33:34 PM UTC 24 |
| Finished | Aug 27 07:33:41 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037738439 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.1037738439 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1972165318 |
| Short name | T462 |
| Test name | |
| Test status | |
| Simulation time | 2625422225 ps |
| CPU time | 3.82 seconds |
| Started | Aug 27 07:33:31 PM UTC 24 |
| Finished | Aug 27 07:33:36 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1972165318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.1972165318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.1349470698 |
| Short name | T460 |
| Test name | |
| Test status | |
| Simulation time | 2491642687 ps |
| CPU time | 4.23 seconds |
| Started | Aug 27 07:33:27 PM UTC 24 |
| Finished | Aug 27 07:33:33 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1349470698 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.1349470698 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.319778464 |
| Short name | T458 |
| Test name | |
| Test status | |
| Simulation time | 2102825792 ps |
| CPU time | 1.95 seconds |
| Started | Aug 27 07:33:29 PM UTC 24 |
| Finished | Aug 27 07:33:32 PM UTC 24 |
| Peak memory | 208240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=319778464 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.319778464 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.1304864806 |
| Short name | T459 |
| Test name | |
| Test status | |
| Simulation time | 2590264631 ps |
| CPU time | 1.86 seconds |
| Started | Aug 27 07:33:29 PM UTC 24 |
| Finished | Aug 27 07:33:32 PM UTC 24 |
| Peak memory | 208192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1304864806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.1304864806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.1293634390 |
| Short name | T461 |
| Test name | |
| Test status | |
| Simulation time | 2109784119 ps |
| CPU time | 9.38 seconds |
| Started | Aug 27 07:33:23 PM UTC 24 |
| Finished | Aug 27 07:33:34 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1293634390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.1293634390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.2340490329 |
| Short name | T207 |
| Test name | |
| Test status | |
| Simulation time | 10644099772 ps |
| CPU time | 9.16 seconds |
| Started | Aug 27 07:33:37 PM UTC 24 |
| Finished | Aug 27 07:33:47 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2340490329 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.2340490329 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2878030751 |
| Short name | T297 |
| Test name | |
| Test status | |
| Simulation time | 6919150627 ps |
| CPU time | 5.37 seconds |
| Started | Aug 27 07:33:35 PM UTC 24 |
| Finished | Aug 27 07:33:41 PM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2878030751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.2878030751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.456504829 |
| Short name | T251 |
| Test name | |
| Test status | |
| Simulation time | 146476370707 ps |
| CPU time | 58.57 seconds |
| Started | Aug 27 07:33:33 PM UTC 24 |
| Finished | Aug 27 07:34:33 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=456504829 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ultra_low_pwr.456504829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.2383857405 |
| Short name | T472 |
| Test name | |
| Test status | |
| Simulation time | 2030205566 ps |
| CPU time | 3.24 seconds |
| Started | Aug 27 07:33:55 PM UTC 24 |
| Finished | Aug 27 07:33:59 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383857405 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.2383857405 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.64795099 |
| Short name | T511 |
| Test name | |
| Test status | |
| Simulation time | 45232050765 ps |
| CPU time | 81.63 seconds |
| Started | Aug 27 07:33:49 PM UTC 24 |
| Finished | Aug 27 07:35:12 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=64795099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_0 8_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.64795099 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.4100025725 |
| Short name | T610 |
| Test name | |
| Test status | |
| Simulation time | 88619277005 ps |
| CPU time | 217.36 seconds |
| Started | Aug 27 07:33:49 PM UTC 24 |
| Finished | Aug 27 07:37:29 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4100025725 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.4100025725 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect_with_pre_cond.2690442272 |
| Short name | T489 |
| Test name | |
| Test status | |
| Simulation time | 33617660711 ps |
| CPU time | 23.18 seconds |
| Started | Aug 27 07:33:52 PM UTC 24 |
| Finished | Aug 27 07:34:17 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690442272 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect_with_pre_cond.2690442272 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.2309894643 |
| Short name | T475 |
| Test name | |
| Test status | |
| Simulation time | 3014795038 ps |
| CPU time | 15.32 seconds |
| Started | Aug 27 07:33:47 PM UTC 24 |
| Finished | Aug 27 07:34:04 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309894643 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.2309894643 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.2671057 |
| Short name | T208 |
| Test name | |
| Test status | |
| Simulation time | 3675331342 ps |
| CPU time | 11.35 seconds |
| Started | Aug 27 07:33:49 PM UTC 24 |
| Finished | Aug 27 07:34:02 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671057 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scrat ch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.2671057 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2362346555 |
| Short name | T470 |
| Test name | |
| Test status | |
| Simulation time | 2619890006 ps |
| CPU time | 6.61 seconds |
| Started | Aug 27 07:33:46 PM UTC 24 |
| Finished | Aug 27 07:33:54 PM UTC 24 |
| Peak memory | 210084 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362346555 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.2362346555 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.1147689883 |
| Short name | T465 |
| Test name | |
| Test status | |
| Simulation time | 2483932928 ps |
| CPU time | 2.24 seconds |
| Started | Aug 27 07:33:42 PM UTC 24 |
| Finished | Aug 27 07:33:45 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1147689883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.1147689883 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.2352545855 |
| Short name | T471 |
| Test name | |
| Test status | |
| Simulation time | 2173093683 ps |
| CPU time | 13.02 seconds |
| Started | Aug 27 07:33:42 PM UTC 24 |
| Finished | Aug 27 07:33:56 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352545855 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.2352545855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.3445358444 |
| Short name | T468 |
| Test name | |
| Test status | |
| Simulation time | 2528930160 ps |
| CPU time | 4.69 seconds |
| Started | Aug 27 07:33:46 PM UTC 24 |
| Finished | Aug 27 07:33:52 PM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3445358444 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.3445358444 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.3301109445 |
| Short name | T464 |
| Test name | |
| Test status | |
| Simulation time | 2129920355 ps |
| CPU time | 3.59 seconds |
| Started | Aug 27 07:33:40 PM UTC 24 |
| Finished | Aug 27 07:33:45 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301109445 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.3301109445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.829906425 |
| Short name | T209 |
| Test name | |
| Test status | |
| Simulation time | 11460367062 ps |
| CPU time | 10.78 seconds |
| Started | Aug 27 07:33:54 PM UTC 24 |
| Finished | Aug 27 07:34:06 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829906425 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.829906425 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.2910394554 |
| Short name | T482 |
| Test name | |
| Test status | |
| Simulation time | 13143537135 ps |
| CPU time | 17.69 seconds |
| Started | Aug 27 07:33:53 PM UTC 24 |
| Finished | Aug 27 07:34:11 PM UTC 24 |
| Peak memory | 222528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2910394554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.2910394554 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.1990622849 |
| Short name | T330 |
| Test name | |
| Test status | |
| Simulation time | 7535938537 ps |
| CPU time | 9.04 seconds |
| Started | Aug 27 07:33:49 PM UTC 24 |
| Finished | Aug 27 07:33:59 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990622849 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.1990622849 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.462117221 |
| Short name | T487 |
| Test name | |
| Test status | |
| Simulation time | 2011516598 ps |
| CPU time | 7.17 seconds |
| Started | Aug 27 07:34:07 PM UTC 24 |
| Finished | Aug 27 07:34:15 PM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=462117221 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.462117221 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3827002139 |
| Short name | T479 |
| Test name | |
| Test status | |
| Simulation time | 5138787294 ps |
| CPU time | 5.04 seconds |
| Started | Aug 27 07:34:02 PM UTC 24 |
| Finished | Aug 27 07:34:08 PM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3827002139 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.3827002139 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.2616294874 |
| Short name | T280 |
| Test name | |
| Test status | |
| Simulation time | 88938986627 ps |
| CPU time | 240.23 seconds |
| Started | Aug 27 07:34:03 PM UTC 24 |
| Finished | Aug 27 07:38:06 PM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2616294874 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.2616294874 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.743581209 |
| Short name | T261 |
| Test name | |
| Test status | |
| Simulation time | 62355657218 ps |
| CPU time | 18.39 seconds |
| Started | Aug 27 07:34:04 PM UTC 24 |
| Finished | Aug 27 07:34:24 PM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743581209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_with_pre_cond.743581209 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1825424929 |
| Short name | T476 |
| Test name | |
| Test status | |
| Simulation time | 3870189518 ps |
| CPU time | 1.54 seconds |
| Started | Aug 27 07:34:02 PM UTC 24 |
| Finished | Aug 27 07:34:04 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1825424929 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.1825424929 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.802940476 |
| Short name | T477 |
| Test name | |
| Test status | |
| Simulation time | 2627768177 ps |
| CPU time | 3.26 seconds |
| Started | Aug 27 07:34:02 PM UTC 24 |
| Finished | Aug 27 07:34:06 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802940476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.802940476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.3258967019 |
| Short name | T480 |
| Test name | |
| Test status | |
| Simulation time | 2465097670 ps |
| CPU time | 8.8 seconds |
| Started | Aug 27 07:34:00 PM UTC 24 |
| Finished | Aug 27 07:34:10 PM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3258967019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.3258967019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.4250549841 |
| Short name | T481 |
| Test name | |
| Test status | |
| Simulation time | 2090364826 ps |
| CPU time | 10.43 seconds |
| Started | Aug 27 07:34:00 PM UTC 24 |
| Finished | Aug 27 07:34:11 PM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250549841 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.4250549841 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.4234235918 |
| Short name | T478 |
| Test name | |
| Test status | |
| Simulation time | 2519408663 ps |
| CPU time | 6.59 seconds |
| Started | Aug 27 07:34:00 PM UTC 24 |
| Finished | Aug 27 07:34:07 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4234235918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.4234235918 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.22938075 |
| Short name | T474 |
| Test name | |
| Test status | |
| Simulation time | 2131628379 ps |
| CPU time | 1.78 seconds |
| Started | Aug 27 07:33:57 PM UTC 24 |
| Finished | Aug 27 07:34:00 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=22938075 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ct rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.22938075 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.3200542392 |
| Short name | T331 |
| Test name | |
| Test status | |
| Simulation time | 855071361238 ps |
| CPU time | 49.96 seconds |
| Started | Aug 27 07:34:07 PM UTC 24 |
| Finished | Aug 27 07:34:58 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3200542392 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.3200542392 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2742084318 |
| Short name | T492 |
| Test name | |
| Test status | |
| Simulation time | 9757750791 ps |
| CPU time | 14.89 seconds |
| Started | Aug 27 07:34:06 PM UTC 24 |
| Finished | Aug 27 07:34:22 PM UTC 24 |
| Peak memory | 220504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2742084318 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.2742084318 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2424867858 |
| Short name | T491 |
| Test name | |
| Test status | |
| Simulation time | 2042372038 ps |
| CPU time | 1.61 seconds |
| Started | Aug 27 07:34:18 PM UTC 24 |
| Finished | Aug 27 07:34:21 PM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2424867858 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.2424867858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.4184126693 |
| Short name | T501 |
| Test name | |
| Test status | |
| Simulation time | 3312723927 ps |
| CPU time | 16.51 seconds |
| Started | Aug 27 07:34:13 PM UTC 24 |
| Finished | Aug 27 07:34:30 PM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4184126693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.4184126693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.18735670 |
| Short name | T374 |
| Test name | |
| Test status | |
| Simulation time | 176299962560 ps |
| CPU time | 150.71 seconds |
| Started | Aug 27 07:34:14 PM UTC 24 |
| Finished | Aug 27 07:36:47 PM UTC 24 |
| Peak memory | 210004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18735670 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.18735670 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect_with_pre_cond.42015858 |
| Short name | T370 |
| Test name | |
| Test status | |
| Simulation time | 154472985383 ps |
| CPU time | 455.66 seconds |
| Started | Aug 27 07:34:17 PM UTC 24 |
| Finished | Aug 27 07:41:58 PM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=42015858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression _2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect_with_pre_cond.42015858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.872064471 |
| Short name | T493 |
| Test name | |
| Test status | |
| Simulation time | 3188702069 ps |
| CPU time | 9.76 seconds |
| Started | Aug 27 07:34:13 PM UTC 24 |
| Finished | Aug 27 07:34:23 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=872064471 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.872064471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.4253166279 |
| Short name | T490 |
| Test name | |
| Test status | |
| Simulation time | 2886237610 ps |
| CPU time | 3.84 seconds |
| Started | Aug 27 07:34:14 PM UTC 24 |
| Finished | Aug 27 07:34:19 PM UTC 24 |
| Peak memory | 209716 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4253166279 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.4253166279 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.4288515868 |
| Short name | T497 |
| Test name | |
| Test status | |
| Simulation time | 2613214673 ps |
| CPU time | 13.63 seconds |
| Started | Aug 27 07:34:11 PM UTC 24 |
| Finished | Aug 27 07:34:26 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4288515868 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.4288515868 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.3734408 |
| Short name | T485 |
| Test name | |
| Test status | |
| Simulation time | 2484858402 ps |
| CPU time | 3.63 seconds |
| Started | Aug 27 07:34:08 PM UTC 24 |
| Finished | Aug 27 07:34:13 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3734408 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_ TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.3734408 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.4035711906 |
| Short name | T483 |
| Test name | |
| Test status | |
| Simulation time | 2248657298 ps |
| CPU time | 1.43 seconds |
| Started | Aug 27 07:34:10 PM UTC 24 |
| Finished | Aug 27 07:34:12 PM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4035711906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.4035711906 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.4161833981 |
| Short name | T495 |
| Test name | |
| Test status | |
| Simulation time | 2511310932 ps |
| CPU time | 12.98 seconds |
| Started | Aug 27 07:34:11 PM UTC 24 |
| Finished | Aug 27 07:34:25 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4161833981 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.4161833981 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.2799344162 |
| Short name | T486 |
| Test name | |
| Test status | |
| Simulation time | 2119583959 ps |
| CPU time | 5.69 seconds |
| Started | Aug 27 07:34:08 PM UTC 24 |
| Finished | Aug 27 07:34:15 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799344162 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.2799344162 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.2381528576 |
| Short name | T246 |
| Test name | |
| Test status | |
| Simulation time | 17286717225 ps |
| CPU time | 18.09 seconds |
| Started | Aug 27 07:34:17 PM UTC 24 |
| Finished | Aug 27 07:34:36 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2381528576 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.2381528576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.2439317145 |
| Short name | T488 |
| Test name | |
| Test status | |
| Simulation time | 4401444032 ps |
| CPU time | 1.83 seconds |
| Started | Aug 27 07:34:13 PM UTC 24 |
| Finished | Aug 27 07:34:16 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2439317145 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.2439317145 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.2671683972 |
| Short name | T252 |
| Test name | |
| Test status | |
| Simulation time | 2042611782 ps |
| CPU time | 3.65 seconds |
| Started | Aug 27 07:34:28 PM UTC 24 |
| Finished | Aug 27 07:34:33 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2671683972 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.2671683972 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.2864165575 |
| Short name | T122 |
| Test name | |
| Test status | |
| Simulation time | 3384822702 ps |
| CPU time | 4.99 seconds |
| Started | Aug 27 07:34:25 PM UTC 24 |
| Finished | Aug 27 07:34:31 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2864165575 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.2864165575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.1793205644 |
| Short name | T738 |
| Test name | |
| Test status | |
| Simulation time | 150592823336 ps |
| CPU time | 384.95 seconds |
| Started | Aug 27 07:34:25 PM UTC 24 |
| Finished | Aug 27 07:40:55 PM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1793205644 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.1793205644 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.2594705433 |
| Short name | T340 |
| Test name | |
| Test status | |
| Simulation time | 114483130528 ps |
| CPU time | 333.02 seconds |
| Started | Aug 27 07:34:26 PM UTC 24 |
| Finished | Aug 27 07:40:04 PM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2594705433 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect_with_pre_cond.2594705433 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.1839863507 |
| Short name | T258 |
| Test name | |
| Test status | |
| Simulation time | 3649686525 ps |
| CPU time | 14.66 seconds |
| Started | Aug 27 07:34:22 PM UTC 24 |
| Finished | Aug 27 07:34:38 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1839863507 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.1839863507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3348815109 |
| Short name | T499 |
| Test name | |
| Test status | |
| Simulation time | 2622076343 ps |
| CPU time | 4.3 seconds |
| Started | Aug 27 07:34:22 PM UTC 24 |
| Finished | Aug 27 07:34:28 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348815109 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.3348815109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.234507772 |
| Short name | T498 |
| Test name | |
| Test status | |
| Simulation time | 2457447662 ps |
| CPU time | 6.24 seconds |
| Started | Aug 27 07:34:19 PM UTC 24 |
| Finished | Aug 27 07:34:27 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=234507772 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.234507772 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1105319964 |
| Short name | T494 |
| Test name | |
| Test status | |
| Simulation time | 2271362617 ps |
| CPU time | 3.01 seconds |
| Started | Aug 27 07:34:21 PM UTC 24 |
| Finished | Aug 27 07:34:25 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105319964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.1105319964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.2780532829 |
| Short name | T254 |
| Test name | |
| Test status | |
| Simulation time | 2511372108 ps |
| CPU time | 11.57 seconds |
| Started | Aug 27 07:34:22 PM UTC 24 |
| Finished | Aug 27 07:34:35 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2780532829 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.2780532829 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.2532818912 |
| Short name | T496 |
| Test name | |
| Test status | |
| Simulation time | 2113359840 ps |
| CPU time | 6.29 seconds |
| Started | Aug 27 07:34:18 PM UTC 24 |
| Finished | Aug 27 07:34:26 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2532818912 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.2532818912 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.160508356 |
| Short name | T628 |
| Test name | |
| Test status | |
| Simulation time | 219764569894 ps |
| CPU time | 199.54 seconds |
| Started | Aug 27 07:34:28 PM UTC 24 |
| Finished | Aug 27 07:37:50 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160508356 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.160508356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.3331198559 |
| Short name | T302 |
| Test name | |
| Test status | |
| Simulation time | 63023497941 ps |
| CPU time | 11.15 seconds |
| Started | Aug 27 07:34:27 PM UTC 24 |
| Finished | Aug 27 07:34:39 PM UTC 24 |
| Peak memory | 220600 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3331198559 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.3331198559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.1514623382 |
| Short name | T500 |
| Test name | |
| Test status | |
| Simulation time | 4352972842 ps |
| CPU time | 3.51 seconds |
| Started | Aug 27 07:34:25 PM UTC 24 |
| Finished | Aug 27 07:34:30 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1514623382 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.1514623382 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.397489998 |
| Short name | T504 |
| Test name | |
| Test status | |
| Simulation time | 2043811443 ps |
| CPU time | 2.31 seconds |
| Started | Aug 27 07:34:38 PM UTC 24 |
| Finished | Aug 27 07:34:41 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397489998 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.397489998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.619299585 |
| Short name | T517 |
| Test name | |
| Test status | |
| Simulation time | 14715557971 ps |
| CPU time | 44.75 seconds |
| Started | Aug 27 07:34:35 PM UTC 24 |
| Finished | Aug 27 07:35:21 PM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=619299585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.619299585 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.2567136665 |
| Short name | T734 |
| Test name | |
| Test status | |
| Simulation time | 104160872661 ps |
| CPU time | 347.04 seconds |
| Started | Aug 27 07:34:36 PM UTC 24 |
| Finished | Aug 27 07:40:28 PM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567136665 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.2567136665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2482273263 |
| Short name | T332 |
| Test name | |
| Test status | |
| Simulation time | 31099393789 ps |
| CPU time | 58.27 seconds |
| Started | Aug 27 07:34:36 PM UTC 24 |
| Finished | Aug 27 07:35:36 PM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482273263 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_with_pre_cond.2482273263 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.647906662 |
| Short name | T257 |
| Test name | |
| Test status | |
| Simulation time | 3681772641 ps |
| CPU time | 2.1 seconds |
| Started | Aug 27 07:34:34 PM UTC 24 |
| Finished | Aug 27 07:34:38 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647906662 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.647906662 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.423882208 |
| Short name | T503 |
| Test name | |
| Test status | |
| Simulation time | 2621950975 ps |
| CPU time | 6.21 seconds |
| Started | Aug 27 07:34:33 PM UTC 24 |
| Finished | Aug 27 07:34:40 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=423882208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.423882208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.3668285095 |
| Short name | T255 |
| Test name | |
| Test status | |
| Simulation time | 2507500273 ps |
| CPU time | 2.72 seconds |
| Started | Aug 27 07:34:32 PM UTC 24 |
| Finished | Aug 27 07:34:35 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3668285095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.3668285095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.1381800301 |
| Short name | T190 |
| Test name | |
| Test status | |
| Simulation time | 2134057695 ps |
| CPU time | 12.77 seconds |
| Started | Aug 27 07:34:32 PM UTC 24 |
| Finished | Aug 27 07:34:46 PM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381800301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.1381800301 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.3686903335 |
| Short name | T502 |
| Test name | |
| Test status | |
| Simulation time | 2528531401 ps |
| CPU time | 4.23 seconds |
| Started | Aug 27 07:34:33 PM UTC 24 |
| Finished | Aug 27 07:34:38 PM UTC 24 |
| Peak memory | 209956 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3686903335 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.3686903335 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.3412069961 |
| Short name | T256 |
| Test name | |
| Test status | |
| Simulation time | 2116687087 ps |
| CPU time | 6.63 seconds |
| Started | Aug 27 07:34:29 PM UTC 24 |
| Finished | Aug 27 07:34:37 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3412069961 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.3412069961 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.4172560089 |
| Short name | T179 |
| Test name | |
| Test status | |
| Simulation time | 11917825097 ps |
| CPU time | 32.6 seconds |
| Started | Aug 27 07:34:38 PM UTC 24 |
| Finished | Aug 27 07:35:12 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4172560089 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.4172560089 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.955081689 |
| Short name | T172 |
| Test name | |
| Test status | |
| Simulation time | 5154473220 ps |
| CPU time | 25.9 seconds |
| Started | Aug 27 07:34:38 PM UTC 24 |
| Finished | Aug 27 07:35:05 PM UTC 24 |
| Peak memory | 220408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=955081689 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.955081689 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2795362507 |
| Short name | T142 |
| Test name | |
| Test status | |
| Simulation time | 8598205526 ps |
| CPU time | 11.05 seconds |
| Started | Aug 27 07:34:35 PM UTC 24 |
| Finished | Aug 27 07:34:47 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2795362507 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.2795362507 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.4250531740 |
| Short name | T509 |
| Test name | |
| Test status | |
| Simulation time | 2010867951 ps |
| CPU time | 11.03 seconds |
| Started | Aug 27 07:34:48 PM UTC 24 |
| Finished | Aug 27 07:35:00 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4250531740 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.4250531740 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.430759665 |
| Short name | T247 |
| Test name | |
| Test status | |
| Simulation time | 3394054787 ps |
| CPU time | 5.75 seconds |
| Started | Aug 27 07:34:42 PM UTC 24 |
| Finished | Aug 27 07:34:50 PM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=430759665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.430759665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.4107257630 |
| Short name | T123 |
| Test name | |
| Test status | |
| Simulation time | 63729404782 ps |
| CPU time | 47.06 seconds |
| Started | Aug 27 07:34:44 PM UTC 24 |
| Finished | Aug 27 07:35:32 PM UTC 24 |
| Peak memory | 210488 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107257630 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.4107257630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.1693905703 |
| Short name | T353 |
| Test name | |
| Test status | |
| Simulation time | 71175366067 ps |
| CPU time | 110.69 seconds |
| Started | Aug 27 07:34:46 PM UTC 24 |
| Finished | Aug 27 07:36:39 PM UTC 24 |
| Peak memory | 210312 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1693905703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_with_pre_cond.1693905703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.2100848744 |
| Short name | T193 |
| Test name | |
| Test status | |
| Simulation time | 3631536010 ps |
| CPU time | 5.59 seconds |
| Started | Aug 27 07:34:41 PM UTC 24 |
| Finished | Aug 27 07:34:48 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100848744 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.2100848744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.647341521 |
| Short name | T200 |
| Test name | |
| Test status | |
| Simulation time | 2399786844 ps |
| CPU time | 3.94 seconds |
| Started | Aug 27 07:34:44 PM UTC 24 |
| Finished | Aug 27 07:34:49 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=647341521 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.647341521 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.3399963693 |
| Short name | T191 |
| Test name | |
| Test status | |
| Simulation time | 2630466091 ps |
| CPU time | 3.99 seconds |
| Started | Aug 27 07:34:41 PM UTC 24 |
| Finished | Aug 27 07:34:46 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399963693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.3399963693 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.3013746494 |
| Short name | T189 |
| Test name | |
| Test status | |
| Simulation time | 2540861160 ps |
| CPU time | 2.6 seconds |
| Started | Aug 27 07:34:40 PM UTC 24 |
| Finished | Aug 27 07:34:43 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3013746494 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.3013746494 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.2810109185 |
| Short name | T192 |
| Test name | |
| Test status | |
| Simulation time | 2195209380 ps |
| CPU time | 6.76 seconds |
| Started | Aug 27 07:34:40 PM UTC 24 |
| Finished | Aug 27 07:34:48 PM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2810109185 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.2810109185 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.1968862236 |
| Short name | T506 |
| Test name | |
| Test status | |
| Simulation time | 2514276267 ps |
| CPU time | 13.36 seconds |
| Started | Aug 27 07:34:41 PM UTC 24 |
| Finished | Aug 27 07:34:56 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1968862236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1968862236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3385269593 |
| Short name | T188 |
| Test name | |
| Test status | |
| Simulation time | 2161174153 ps |
| CPU time | 2.27 seconds |
| Started | Aug 27 07:34:40 PM UTC 24 |
| Finished | Aug 27 07:34:43 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3385269593 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.3385269593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2872913383 |
| Short name | T175 |
| Test name | |
| Test status | |
| Simulation time | 5044203807 ps |
| CPU time | 19.7 seconds |
| Started | Aug 27 07:34:48 PM UTC 24 |
| Finished | Aug 27 07:35:09 PM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2872913383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.2872913383 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.743307767 |
| Short name | T194 |
| Test name | |
| Test status | |
| Simulation time | 8725993594 ps |
| CPU time | 3.47 seconds |
| Started | Aug 27 07:34:44 PM UTC 24 |
| Finished | Aug 27 07:34:49 PM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=743307767 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.743307767 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.1286642594 |
| Short name | T174 |
| Test name | |
| Test status | |
| Simulation time | 2011653161 ps |
| CPU time | 7.32 seconds |
| Started | Aug 27 07:35:00 PM UTC 24 |
| Finished | Aug 27 07:35:08 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286642594 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.1286642594 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.3305863253 |
| Short name | T556 |
| Test name | |
| Test status | |
| Simulation time | 54721076301 ps |
| CPU time | 80.51 seconds |
| Started | Aug 27 07:34:53 PM UTC 24 |
| Finished | Aug 27 07:36:16 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3305863253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.3305863253 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.137521177 |
| Short name | T124 |
| Test name | |
| Test status | |
| Simulation time | 52850661265 ps |
| CPU time | 40.52 seconds |
| Started | Aug 27 07:34:55 PM UTC 24 |
| Finished | Aug 27 07:35:37 PM UTC 24 |
| Peak memory | 210484 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137521177 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.137521177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.3891516984 |
| Short name | T590 |
| Test name | |
| Test status | |
| Simulation time | 32163167548 ps |
| CPU time | 121.52 seconds |
| Started | Aug 27 07:34:57 PM UTC 24 |
| Finished | Aug 27 07:37:01 PM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3891516984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_with_pre_cond.3891516984 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.3834252724 |
| Short name | T510 |
| Test name | |
| Test status | |
| Simulation time | 3433009959 ps |
| CPU time | 10.51 seconds |
| Started | Aug 27 07:34:52 PM UTC 24 |
| Finished | Aug 27 07:35:04 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834252724 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.3834252724 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2104396864 |
| Short name | T505 |
| Test name | |
| Test status | |
| Simulation time | 2623806100 ps |
| CPU time | 3.75 seconds |
| Started | Aug 27 07:34:51 PM UTC 24 |
| Finished | Aug 27 07:34:56 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104396864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.2104396864 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.2720907211 |
| Short name | T249 |
| Test name | |
| Test status | |
| Simulation time | 2499307182 ps |
| CPU time | 2.49 seconds |
| Started | Aug 27 07:34:49 PM UTC 24 |
| Finished | Aug 27 07:34:53 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2720907211 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2720907211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.1650811798 |
| Short name | T250 |
| Test name | |
| Test status | |
| Simulation time | 2161423017 ps |
| CPU time | 3.47 seconds |
| Started | Aug 27 07:34:50 PM UTC 24 |
| Finished | Aug 27 07:34:54 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1650811798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.1650811798 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.4231428714 |
| Short name | T248 |
| Test name | |
| Test status | |
| Simulation time | 2603673849 ps |
| CPU time | 1.58 seconds |
| Started | Aug 27 07:34:50 PM UTC 24 |
| Finished | Aug 27 07:34:52 PM UTC 24 |
| Peak memory | 208192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4231428714 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.4231428714 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.4002966252 |
| Short name | T507 |
| Test name | |
| Test status | |
| Simulation time | 2109227151 ps |
| CPU time | 6.71 seconds |
| Started | Aug 27 07:34:49 PM UTC 24 |
| Finished | Aug 27 07:34:57 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002966252 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.4002966252 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.2037198420 |
| Short name | T392 |
| Test name | |
| Test status | |
| Simulation time | 59023827717 ps |
| CPU time | 49.21 seconds |
| Started | Aug 27 07:35:00 PM UTC 24 |
| Finished | Aug 27 07:35:50 PM UTC 24 |
| Peak memory | 210004 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2037198420 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.2037198420 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.3752945703 |
| Short name | T178 |
| Test name | |
| Test status | |
| Simulation time | 16909865805 ps |
| CPU time | 12.15 seconds |
| Started | Aug 27 07:34:58 PM UTC 24 |
| Finished | Aug 27 07:35:12 PM UTC 24 |
| Peak memory | 220856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3752945703 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.3752945703 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.3487128967 |
| Short name | T508 |
| Test name | |
| Test status | |
| Simulation time | 5313418694 ps |
| CPU time | 3.3 seconds |
| Started | Aug 27 07:34:55 PM UTC 24 |
| Finished | Aug 27 07:34:59 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3487128967 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ultra_low_pwr.3487128967 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.1275519113 |
| Short name | T242 |
| Test name | |
| Test status | |
| Simulation time | 2043306466 ps |
| CPU time | 3.03 seconds |
| Started | Aug 27 07:27:41 PM UTC 24 |
| Finished | Aug 27 07:27:45 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1275519113 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.1275519113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.1395055881 |
| Short name | T66 |
| Test name | |
| Test status | |
| Simulation time | 3880860280 ps |
| CPU time | 22.45 seconds |
| Started | Aug 27 07:27:33 PM UTC 24 |
| Finished | Aug 27 07:27:57 PM UTC 24 |
| Peak memory | 209920 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1395055881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.1395055881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.3992763663 |
| Short name | T375 |
| Test name | |
| Test status | |
| Simulation time | 96646786492 ps |
| CPU time | 344.21 seconds |
| Started | Aug 27 07:27:34 PM UTC 24 |
| Finished | Aug 27 07:33:22 PM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3992763663 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.3992763663 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.3677046419 |
| Short name | T13 |
| Test name | |
| Test status | |
| Simulation time | 2423942258 ps |
| CPU time | 14.37 seconds |
| Started | Aug 27 07:27:28 PM UTC 24 |
| Finished | Aug 27 07:27:44 PM UTC 24 |
| Peak memory | 209528 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3677046419 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.3677046419 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1002749144 |
| Short name | T11 |
| Test name | |
| Test status | |
| Simulation time | 2550700537 ps |
| CPU time | 3.5 seconds |
| Started | Aug 27 07:27:28 PM UTC 24 |
| Finished | Aug 27 07:27:33 PM UTC 24 |
| Peak memory | 209752 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1002749144 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1002749144 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.2125079158 |
| Short name | T98 |
| Test name | |
| Test status | |
| Simulation time | 3861861458 ps |
| CPU time | 3.09 seconds |
| Started | Aug 27 07:27:31 PM UTC 24 |
| Finished | Aug 27 07:27:35 PM UTC 24 |
| Peak memory | 210012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125079158 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.2125079158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.1737271623 |
| Short name | T12 |
| Test name | |
| Test status | |
| Simulation time | 2479584308 ps |
| CPU time | 5.87 seconds |
| Started | Aug 27 07:27:36 PM UTC 24 |
| Finished | Aug 27 07:27:43 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1737271623 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.1737271623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.3645933678 |
| Short name | T85 |
| Test name | |
| Test status | |
| Simulation time | 2620497416 ps |
| CPU time | 6.47 seconds |
| Started | Aug 27 07:27:29 PM UTC 24 |
| Finished | Aug 27 07:27:36 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3645933678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.3645933678 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.2002521648 |
| Short name | T78 |
| Test name | |
| Test status | |
| Simulation time | 2478917037 ps |
| CPU time | 3.53 seconds |
| Started | Aug 27 07:27:25 PM UTC 24 |
| Finished | Aug 27 07:27:29 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2002521648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.2002521648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.3299046477 |
| Short name | T97 |
| Test name | |
| Test status | |
| Simulation time | 2152534965 ps |
| CPU time | 2.2 seconds |
| Started | Aug 27 07:27:28 PM UTC 24 |
| Finished | Aug 27 07:27:32 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3299046477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.3299046477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.3442277056 |
| Short name | T295 |
| Test name | |
| Test status | |
| Simulation time | 22014517408 ps |
| CPU time | 91.74 seconds |
| Started | Aug 27 07:27:38 PM UTC 24 |
| Finished | Aug 27 07:29:12 PM UTC 24 |
| Peak memory | 240284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3442277056 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.3442277056 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.2375865236 |
| Short name | T96 |
| Test name | |
| Test status | |
| Simulation time | 2107388630 ps |
| CPU time | 7.76 seconds |
| Started | Aug 27 07:27:23 PM UTC 24 |
| Finished | Aug 27 07:27:32 PM UTC 24 |
| Peak memory | 209892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2375865236 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.2375865236 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.2625142027 |
| Short name | T42 |
| Test name | |
| Test status | |
| Simulation time | 79879379861 ps |
| CPU time | 120.64 seconds |
| Started | Aug 27 07:27:37 PM UTC 24 |
| Finished | Aug 27 07:29:40 PM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625142027 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.2625142027 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.3124714505 |
| Short name | T94 |
| Test name | |
| Test status | |
| Simulation time | 5759219902 ps |
| CPU time | 31.48 seconds |
| Started | Aug 27 07:27:37 PM UTC 24 |
| Finished | Aug 27 07:28:10 PM UTC 24 |
| Peak memory | 222700 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3124714505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.3124714505 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.1240151023 |
| Short name | T75 |
| Test name | |
| Test status | |
| Simulation time | 3984903075 ps |
| CPU time | 12.54 seconds |
| Started | Aug 27 07:27:33 PM UTC 24 |
| Finished | Aug 27 07:27:47 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1240151023 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.1240151023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.914663765 |
| Short name | T515 |
| Test name | |
| Test status | |
| Simulation time | 2023579761 ps |
| CPU time | 4.41 seconds |
| Started | Aug 27 07:35:14 PM UTC 24 |
| Finished | Aug 27 07:35:19 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914663765 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.914663765 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.1828457319 |
| Short name | T513 |
| Test name | |
| Test status | |
| Simulation time | 3856584111 ps |
| CPU time | 5.23 seconds |
| Started | Aug 27 07:35:10 PM UTC 24 |
| Finished | Aug 27 07:35:16 PM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1828457319 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.1828457319 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.2270107648 |
| Short name | T346 |
| Test name | |
| Test status | |
| Simulation time | 114434502238 ps |
| CPU time | 110.24 seconds |
| Started | Aug 27 07:35:10 PM UTC 24 |
| Finished | Aug 27 07:37:02 PM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270107648 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.2270107648 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.1014246774 |
| Short name | T519 |
| Test name | |
| Test status | |
| Simulation time | 3643119657 ps |
| CPU time | 13.68 seconds |
| Started | Aug 27 07:35:07 PM UTC 24 |
| Finished | Aug 27 07:35:22 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1014246774 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.1014246774 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.2546415877 |
| Short name | T213 |
| Test name | |
| Test status | |
| Simulation time | 3530346652 ps |
| CPU time | 8.4 seconds |
| Started | Aug 27 07:35:12 PM UTC 24 |
| Finished | Aug 27 07:35:21 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2546415877 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.2546415877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.3802521964 |
| Short name | T180 |
| Test name | |
| Test status | |
| Simulation time | 2633120550 ps |
| CPU time | 4.15 seconds |
| Started | Aug 27 07:35:07 PM UTC 24 |
| Finished | Aug 27 07:35:12 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3802521964 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.3802521964 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.2243617271 |
| Short name | T176 |
| Test name | |
| Test status | |
| Simulation time | 2492205884 ps |
| CPU time | 3.65 seconds |
| Started | Aug 27 07:35:04 PM UTC 24 |
| Finished | Aug 27 07:35:09 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2243617271 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.2243617271 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.28254381 |
| Short name | T512 |
| Test name | |
| Test status | |
| Simulation time | 2245138802 ps |
| CPU time | 7.27 seconds |
| Started | Aug 27 07:35:06 PM UTC 24 |
| Finished | Aug 27 07:35:14 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=28254381 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysr st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.28254381 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.3401014986 |
| Short name | T177 |
| Test name | |
| Test status | |
| Simulation time | 2528325744 ps |
| CPU time | 4.46 seconds |
| Started | Aug 27 07:35:06 PM UTC 24 |
| Finished | Aug 27 07:35:11 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3401014986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.3401014986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1795150901 |
| Short name | T173 |
| Test name | |
| Test status | |
| Simulation time | 2131473733 ps |
| CPU time | 3.47 seconds |
| Started | Aug 27 07:35:01 PM UTC 24 |
| Finished | Aug 27 07:35:05 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1795150901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1795150901 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.1946587218 |
| Short name | T530 |
| Test name | |
| Test status | |
| Simulation time | 11273702579 ps |
| CPU time | 24.52 seconds |
| Started | Aug 27 07:35:14 PM UTC 24 |
| Finished | Aug 27 07:35:39 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1946587218 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.1946587218 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.1123294716 |
| Short name | T317 |
| Test name | |
| Test status | |
| Simulation time | 8247845124 ps |
| CPU time | 17.01 seconds |
| Started | Aug 27 07:35:14 PM UTC 24 |
| Finished | Aug 27 07:35:32 PM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1123294716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.1123294716 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2470589553 |
| Short name | T518 |
| Test name | |
| Test status | |
| Simulation time | 3595967813 ps |
| CPU time | 10.48 seconds |
| Started | Aug 27 07:35:10 PM UTC 24 |
| Finished | Aug 27 07:35:21 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2470589553 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.2470589553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.499735449 |
| Short name | T524 |
| Test name | |
| Test status | |
| Simulation time | 2023533715 ps |
| CPU time | 3.38 seconds |
| Started | Aug 27 07:35:28 PM UTC 24 |
| Finished | Aug 27 07:35:32 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=499735449 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.499735449 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3826033571 |
| Short name | T522 |
| Test name | |
| Test status | |
| Simulation time | 3148342952 ps |
| CPU time | 3.99 seconds |
| Started | Aug 27 07:35:21 PM UTC 24 |
| Finished | Aug 27 07:35:26 PM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826033571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3826033571 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.2218288160 |
| Short name | T525 |
| Test name | |
| Test status | |
| Simulation time | 2587793534 ps |
| CPU time | 12.71 seconds |
| Started | Aug 27 07:35:20 PM UTC 24 |
| Finished | Aug 27 07:35:34 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2218288160 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.2218288160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.2975033233 |
| Short name | T523 |
| Test name | |
| Test status | |
| Simulation time | 2612409378 ps |
| CPU time | 8.32 seconds |
| Started | Aug 27 07:35:20 PM UTC 24 |
| Finished | Aug 27 07:35:29 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975033233 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.2975033233 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.4170977079 |
| Short name | T514 |
| Test name | |
| Test status | |
| Simulation time | 2515683134 ps |
| CPU time | 1.67 seconds |
| Started | Aug 27 07:35:15 PM UTC 24 |
| Finished | Aug 27 07:35:18 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4170977079 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.4170977079 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.3216838833 |
| Short name | T516 |
| Test name | |
| Test status | |
| Simulation time | 2250201642 ps |
| CPU time | 3.22 seconds |
| Started | Aug 27 07:35:16 PM UTC 24 |
| Finished | Aug 27 07:35:21 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3216838833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.3216838833 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.3057548924 |
| Short name | T520 |
| Test name | |
| Test status | |
| Simulation time | 2523035643 ps |
| CPU time | 3.8 seconds |
| Started | Aug 27 07:35:19 PM UTC 24 |
| Finished | Aug 27 07:35:23 PM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057548924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.3057548924 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.2181932477 |
| Short name | T521 |
| Test name | |
| Test status | |
| Simulation time | 2107677232 ps |
| CPU time | 9.68 seconds |
| Started | Aug 27 07:35:15 PM UTC 24 |
| Finished | Aug 27 07:35:26 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2181932477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.2181932477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.1971603040 |
| Short name | T336 |
| Test name | |
| Test status | |
| Simulation time | 130866297883 ps |
| CPU time | 171.13 seconds |
| Started | Aug 27 07:35:27 PM UTC 24 |
| Finished | Aug 27 07:38:20 PM UTC 24 |
| Peak memory | 210168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1971603040 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.1971603040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.1256288845 |
| Short name | T528 |
| Test name | |
| Test status | |
| Simulation time | 3892931366 ps |
| CPU time | 12.56 seconds |
| Started | Aug 27 07:35:24 PM UTC 24 |
| Finished | Aug 27 07:35:38 PM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1256288845 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.1256288845 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.384728429 |
| Short name | T143 |
| Test name | |
| Test status | |
| Simulation time | 9325111992 ps |
| CPU time | 8.45 seconds |
| Started | Aug 27 07:35:21 PM UTC 24 |
| Finished | Aug 27 07:35:31 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=384728429 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.384728429 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1488871640 |
| Short name | T532 |
| Test name | |
| Test status | |
| Simulation time | 2071846994 ps |
| CPU time | 1.71 seconds |
| Started | Aug 27 07:35:39 PM UTC 24 |
| Finished | Aug 27 07:35:41 PM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1488871640 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.1488871640 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.1686825186 |
| Short name | T125 |
| Test name | |
| Test status | |
| Simulation time | 3844111088 ps |
| CPU time | 6.12 seconds |
| Started | Aug 27 07:35:35 PM UTC 24 |
| Finished | Aug 27 07:35:42 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1686825186 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.1686825186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.3533856907 |
| Short name | T752 |
| Test name | |
| Test status | |
| Simulation time | 161271013306 ps |
| CPU time | 508.35 seconds |
| Started | Aug 27 07:35:35 PM UTC 24 |
| Finished | Aug 27 07:44:09 PM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3533856907 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.3533856907 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2217544061 |
| Short name | T559 |
| Test name | |
| Test status | |
| Simulation time | 24590106968 ps |
| CPU time | 39.51 seconds |
| Started | Aug 27 07:35:37 PM UTC 24 |
| Finished | Aug 27 07:36:18 PM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2217544061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_with_pre_cond.2217544061 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1955604372 |
| Short name | T533 |
| Test name | |
| Test status | |
| Simulation time | 3559805590 ps |
| CPU time | 7.61 seconds |
| Started | Aug 27 07:35:33 PM UTC 24 |
| Finished | Aug 27 07:35:42 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1955604372 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.1955604372 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.2293402892 |
| Short name | T214 |
| Test name | |
| Test status | |
| Simulation time | 3912647369 ps |
| CPU time | 8.65 seconds |
| Started | Aug 27 07:35:37 PM UTC 24 |
| Finished | Aug 27 07:35:47 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2293402892 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.2293402892 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.470144547 |
| Short name | T541 |
| Test name | |
| Test status | |
| Simulation time | 2609691720 ps |
| CPU time | 13.91 seconds |
| Started | Aug 27 07:35:33 PM UTC 24 |
| Finished | Aug 27 07:35:48 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=470144547 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.470144547 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.485463586 |
| Short name | T526 |
| Test name | |
| Test status | |
| Simulation time | 2482819859 ps |
| CPU time | 4.21 seconds |
| Started | Aug 27 07:35:30 PM UTC 24 |
| Finished | Aug 27 07:35:36 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=485463586 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.485463586 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.3107974201 |
| Short name | T534 |
| Test name | |
| Test status | |
| Simulation time | 2050099088 ps |
| CPU time | 11.05 seconds |
| Started | Aug 27 07:35:30 PM UTC 24 |
| Finished | Aug 27 07:35:43 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3107974201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.3107974201 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2901575330 |
| Short name | T529 |
| Test name | |
| Test status | |
| Simulation time | 2520702579 ps |
| CPU time | 6.1 seconds |
| Started | Aug 27 07:35:32 PM UTC 24 |
| Finished | Aug 27 07:35:39 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2901575330 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.2901575330 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.3739091750 |
| Short name | T527 |
| Test name | |
| Test status | |
| Simulation time | 2119623095 ps |
| CPU time | 5.73 seconds |
| Started | Aug 27 07:35:29 PM UTC 24 |
| Finished | Aug 27 07:35:36 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3739091750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.3739091750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.2687130911 |
| Short name | T542 |
| Test name | |
| Test status | |
| Simulation time | 9419635373 ps |
| CPU time | 10.37 seconds |
| Started | Aug 27 07:35:38 PM UTC 24 |
| Finished | Aug 27 07:35:49 PM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2687130911 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.2687130911 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.2395865153 |
| Short name | T531 |
| Test name | |
| Test status | |
| Simulation time | 12046568981 ps |
| CPU time | 5.56 seconds |
| Started | Aug 27 07:35:35 PM UTC 24 |
| Finished | Aug 27 07:35:41 PM UTC 24 |
| Peak memory | 209496 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2395865153 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.2395865153 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.4105218457 |
| Short name | T546 |
| Test name | |
| Test status | |
| Simulation time | 2023582404 ps |
| CPU time | 5.16 seconds |
| Started | Aug 27 07:35:49 PM UTC 24 |
| Finished | Aug 27 07:35:55 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105218457 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.4105218457 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.687094273 |
| Short name | T543 |
| Test name | |
| Test status | |
| Simulation time | 3511549239 ps |
| CPU time | 4.18 seconds |
| Started | Aug 27 07:35:44 PM UTC 24 |
| Finished | Aug 27 07:35:50 PM UTC 24 |
| Peak memory | 209936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687094273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.687094273 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.2161457406 |
| Short name | T335 |
| Test name | |
| Test status | |
| Simulation time | 81604575947 ps |
| CPU time | 131.01 seconds |
| Started | Aug 27 07:35:46 PM UTC 24 |
| Finished | Aug 27 07:37:59 PM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2161457406 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.2161457406 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.4118328471 |
| Short name | T367 |
| Test name | |
| Test status | |
| Simulation time | 129556366880 ps |
| CPU time | 378.6 seconds |
| Started | Aug 27 07:35:49 PM UTC 24 |
| Finished | Aug 27 07:42:12 PM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118328471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_with_pre_cond.4118328471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.594851378 |
| Short name | T539 |
| Test name | |
| Test status | |
| Simulation time | 2483044889 ps |
| CPU time | 3.12 seconds |
| Started | Aug 27 07:35:43 PM UTC 24 |
| Finished | Aug 27 07:35:47 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=594851378 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.594851378 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.356349592 |
| Short name | T211 |
| Test name | |
| Test status | |
| Simulation time | 3008396822 ps |
| CPU time | 13.57 seconds |
| Started | Aug 27 07:35:47 PM UTC 24 |
| Finished | Aug 27 07:36:02 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=356349592 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.356349592 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.2938363325 |
| Short name | T548 |
| Test name | |
| Test status | |
| Simulation time | 2613206110 ps |
| CPU time | 15.24 seconds |
| Started | Aug 27 07:35:43 PM UTC 24 |
| Finished | Aug 27 07:35:59 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2938363325 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.2938363325 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.1827669219 |
| Short name | T535 |
| Test name | |
| Test status | |
| Simulation time | 2502547625 ps |
| CPU time | 2.33 seconds |
| Started | Aug 27 07:35:40 PM UTC 24 |
| Finished | Aug 27 07:35:44 PM UTC 24 |
| Peak memory | 209896 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827669219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.1827669219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2374344975 |
| Short name | T537 |
| Test name | |
| Test status | |
| Simulation time | 2276374858 ps |
| CPU time | 1.48 seconds |
| Started | Aug 27 07:35:43 PM UTC 24 |
| Finished | Aug 27 07:35:45 PM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2374344975 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.2374344975 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.4101781022 |
| Short name | T538 |
| Test name | |
| Test status | |
| Simulation time | 2529499134 ps |
| CPU time | 2.71 seconds |
| Started | Aug 27 07:35:43 PM UTC 24 |
| Finished | Aug 27 07:35:47 PM UTC 24 |
| Peak memory | 210280 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4101781022 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.4101781022 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.1152494744 |
| Short name | T536 |
| Test name | |
| Test status | |
| Simulation time | 2130258244 ps |
| CPU time | 2.93 seconds |
| Started | Aug 27 07:35:40 PM UTC 24 |
| Finished | Aug 27 07:35:44 PM UTC 24 |
| Peak memory | 209840 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1152494744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1152494744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.166516803 |
| Short name | T318 |
| Test name | |
| Test status | |
| Simulation time | 13091955352 ps |
| CPU time | 9.94 seconds |
| Started | Aug 27 07:35:49 PM UTC 24 |
| Finished | Aug 27 07:36:00 PM UTC 24 |
| Peak memory | 220544 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=166516803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.166516803 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.2623086928 |
| Short name | T540 |
| Test name | |
| Test status | |
| Simulation time | 9365376929 ps |
| CPU time | 2.32 seconds |
| Started | Aug 27 07:35:44 PM UTC 24 |
| Finished | Aug 27 07:35:48 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623086928 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.2623086928 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.3881689023 |
| Short name | T552 |
| Test name | |
| Test status | |
| Simulation time | 2038963204 ps |
| CPU time | 2.12 seconds |
| Started | Aug 27 07:36:04 PM UTC 24 |
| Finished | Aug 27 07:36:07 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881689023 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.3881689023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.3462628297 |
| Short name | T553 |
| Test name | |
| Test status | |
| Simulation time | 3170784639 ps |
| CPU time | 9.73 seconds |
| Started | Aug 27 07:35:56 PM UTC 24 |
| Finished | Aug 27 07:36:07 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3462628297 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.3462628297 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.575603854 |
| Short name | T636 |
| Test name | |
| Test status | |
| Simulation time | 191217285242 ps |
| CPU time | 116.96 seconds |
| Started | Aug 27 07:35:58 PM UTC 24 |
| Finished | Aug 27 07:37:57 PM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=575603854 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.575603854 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3705946331 |
| Short name | T385 |
| Test name | |
| Test status | |
| Simulation time | 30926274772 ps |
| CPU time | 27.38 seconds |
| Started | Aug 27 07:36:01 PM UTC 24 |
| Finished | Aug 27 07:36:30 PM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3705946331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_with_pre_cond.3705946331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.783107633 |
| Short name | T550 |
| Test name | |
| Test status | |
| Simulation time | 3465255746 ps |
| CPU time | 4.56 seconds |
| Started | Aug 27 07:35:56 PM UTC 24 |
| Finished | Aug 27 07:36:02 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=783107633 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.783107633 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.3574951491 |
| Short name | T560 |
| Test name | |
| Test status | |
| Simulation time | 4366102772 ps |
| CPU time | 17.94 seconds |
| Started | Aug 27 07:36:01 PM UTC 24 |
| Finished | Aug 27 07:36:20 PM UTC 24 |
| Peak memory | 210220 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3574951491 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.3574951491 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.4044114787 |
| Short name | T554 |
| Test name | |
| Test status | |
| Simulation time | 2610853978 ps |
| CPU time | 12.1 seconds |
| Started | Aug 27 07:35:55 PM UTC 24 |
| Finished | Aug 27 07:36:08 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4044114787 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.4044114787 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.759062645 |
| Short name | T549 |
| Test name | |
| Test status | |
| Simulation time | 2479079900 ps |
| CPU time | 8.27 seconds |
| Started | Aug 27 07:35:50 PM UTC 24 |
| Finished | Aug 27 07:36:00 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=759062645 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.759062645 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.1518869482 |
| Short name | T545 |
| Test name | |
| Test status | |
| Simulation time | 2139654265 ps |
| CPU time | 3.57 seconds |
| Started | Aug 27 07:35:50 PM UTC 24 |
| Finished | Aug 27 07:35:55 PM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518869482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.1518869482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.2486571914 |
| Short name | T547 |
| Test name | |
| Test status | |
| Simulation time | 2522570821 ps |
| CPU time | 4.24 seconds |
| Started | Aug 27 07:35:52 PM UTC 24 |
| Finished | Aug 27 07:35:57 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2486571914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.2486571914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.862747751 |
| Short name | T544 |
| Test name | |
| Test status | |
| Simulation time | 2136116346 ps |
| CPU time | 2.95 seconds |
| Started | Aug 27 07:35:50 PM UTC 24 |
| Finished | Aug 27 07:35:54 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=862747751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.862747751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.237687744 |
| Short name | T273 |
| Test name | |
| Test status | |
| Simulation time | 92238357486 ps |
| CPU time | 82.32 seconds |
| Started | Aug 27 07:36:04 PM UTC 24 |
| Finished | Aug 27 07:37:28 PM UTC 24 |
| Peak memory | 210508 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=237687744 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.237687744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.3154921652 |
| Short name | T551 |
| Test name | |
| Test status | |
| Simulation time | 2731189046 ps |
| CPU time | 6.87 seconds |
| Started | Aug 27 07:35:56 PM UTC 24 |
| Finished | Aug 27 07:36:04 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154921652 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.3154921652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.766806988 |
| Short name | T570 |
| Test name | |
| Test status | |
| Simulation time | 2014062126 ps |
| CPU time | 9.22 seconds |
| Started | Aug 27 07:36:25 PM UTC 24 |
| Finished | Aug 27 07:36:35 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766806988 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.766806988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.149787893 |
| Short name | T561 |
| Test name | |
| Test status | |
| Simulation time | 3409521415 ps |
| CPU time | 3.65 seconds |
| Started | Aug 27 07:36:17 PM UTC 24 |
| Finished | Aug 27 07:36:22 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=149787893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.149787893 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2046440601 |
| Short name | T574 |
| Test name | |
| Test status | |
| Simulation time | 76106716446 ps |
| CPU time | 26.37 seconds |
| Started | Aug 27 07:36:20 PM UTC 24 |
| Finished | Aug 27 07:36:47 PM UTC 24 |
| Peak memory | 210160 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2046440601 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.2046440601 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2553608288 |
| Short name | T565 |
| Test name | |
| Test status | |
| Simulation time | 3876920130 ps |
| CPU time | 6.95 seconds |
| Started | Aug 27 07:36:17 PM UTC 24 |
| Finished | Aug 27 07:36:25 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2553608288 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.2553608288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.1121102623 |
| Short name | T571 |
| Test name | |
| Test status | |
| Simulation time | 2656707137 ps |
| CPU time | 13.94 seconds |
| Started | Aug 27 07:36:22 PM UTC 24 |
| Finished | Aug 27 07:36:37 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1121102623 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.1121102623 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3510236129 |
| Short name | T563 |
| Test name | |
| Test status | |
| Simulation time | 2622975033 ps |
| CPU time | 6.77 seconds |
| Started | Aug 27 07:36:15 PM UTC 24 |
| Finished | Aug 27 07:36:23 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3510236129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.3510236129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.1537609477 |
| Short name | T558 |
| Test name | |
| Test status | |
| Simulation time | 2478531981 ps |
| CPU time | 8.38 seconds |
| Started | Aug 27 07:36:08 PM UTC 24 |
| Finished | Aug 27 07:36:18 PM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1537609477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.1537609477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.252330208 |
| Short name | T557 |
| Test name | |
| Test status | |
| Simulation time | 2154079546 ps |
| CPU time | 6.8 seconds |
| Started | Aug 27 07:36:08 PM UTC 24 |
| Finished | Aug 27 07:36:16 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=252330208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.252330208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.4020082557 |
| Short name | T564 |
| Test name | |
| Test status | |
| Simulation time | 2511010687 ps |
| CPU time | 12.34 seconds |
| Started | Aug 27 07:36:09 PM UTC 24 |
| Finished | Aug 27 07:36:23 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4020082557 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.4020082557 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.3963593692 |
| Short name | T555 |
| Test name | |
| Test status | |
| Simulation time | 2114882148 ps |
| CPU time | 6.56 seconds |
| Started | Aug 27 07:36:06 PM UTC 24 |
| Finished | Aug 27 07:36:13 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3963593692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.3963593692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.2651431366 |
| Short name | T583 |
| Test name | |
| Test status | |
| Simulation time | 15352041829 ps |
| CPU time | 27.04 seconds |
| Started | Aug 27 07:36:25 PM UTC 24 |
| Finished | Aug 27 07:36:53 PM UTC 24 |
| Peak memory | 209936 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651431366 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.2651431366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.127083858 |
| Short name | T562 |
| Test name | |
| Test status | |
| Simulation time | 6894888016 ps |
| CPU time | 2.96 seconds |
| Started | Aug 27 07:36:18 PM UTC 24 |
| Finished | Aug 27 07:36:22 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=127083858 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.127083858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.2700379672 |
| Short name | T577 |
| Test name | |
| Test status | |
| Simulation time | 2014223748 ps |
| CPU time | 7.41 seconds |
| Started | Aug 27 07:36:40 PM UTC 24 |
| Finished | Aug 27 07:36:49 PM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2700379672 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.2700379672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3980966830 |
| Short name | T572 |
| Test name | |
| Test status | |
| Simulation time | 3240568259 ps |
| CPU time | 3.02 seconds |
| Started | Aug 27 07:36:33 PM UTC 24 |
| Finished | Aug 27 07:36:37 PM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3980966830 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.3980966830 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.1599493792 |
| Short name | T666 |
| Test name | |
| Test status | |
| Simulation time | 152010586358 ps |
| CPU time | 101.39 seconds |
| Started | Aug 27 07:36:36 PM UTC 24 |
| Finished | Aug 27 07:38:19 PM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1599493792 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.1599493792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2150378155 |
| Short name | T580 |
| Test name | |
| Test status | |
| Simulation time | 24142588981 ps |
| CPU time | 11.21 seconds |
| Started | Aug 27 07:36:37 PM UTC 24 |
| Finished | Aug 27 07:36:50 PM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2150378155 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_with_pre_cond.2150378155 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2725257039 |
| Short name | T581 |
| Test name | |
| Test status | |
| Simulation time | 4760462214 ps |
| CPU time | 18.72 seconds |
| Started | Aug 27 07:36:31 PM UTC 24 |
| Finished | Aug 27 07:36:51 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2725257039 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.2725257039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.2508444109 |
| Short name | T241 |
| Test name | |
| Test status | |
| Simulation time | 3645639906 ps |
| CPU time | 3.98 seconds |
| Started | Aug 27 07:36:36 PM UTC 24 |
| Finished | Aug 27 07:36:41 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2508444109 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.2508444109 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.987219442 |
| Short name | T569 |
| Test name | |
| Test status | |
| Simulation time | 2625918251 ps |
| CPU time | 4.23 seconds |
| Started | Aug 27 07:36:30 PM UTC 24 |
| Finished | Aug 27 07:36:35 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987219442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.987219442 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.1468002098 |
| Short name | T566 |
| Test name | |
| Test status | |
| Simulation time | 2522068695 ps |
| CPU time | 2 seconds |
| Started | Aug 27 07:36:25 PM UTC 24 |
| Finished | Aug 27 07:36:28 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468002098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.1468002098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.4280935304 |
| Short name | T568 |
| Test name | |
| Test status | |
| Simulation time | 2039851159 ps |
| CPU time | 6.12 seconds |
| Started | Aug 27 07:36:26 PM UTC 24 |
| Finished | Aug 27 07:36:33 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280935304 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.4280935304 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.21231151 |
| Short name | T573 |
| Test name | |
| Test status | |
| Simulation time | 2511694447 ps |
| CPU time | 9.92 seconds |
| Started | Aug 27 07:36:28 PM UTC 24 |
| Finished | Aug 27 07:36:39 PM UTC 24 |
| Peak memory | 210020 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=21231151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.21231151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.2803167686 |
| Short name | T567 |
| Test name | |
| Test status | |
| Simulation time | 2117274194 ps |
| CPU time | 3.13 seconds |
| Started | Aug 27 07:36:25 PM UTC 24 |
| Finished | Aug 27 07:36:29 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2803167686 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.2803167686 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all.2236162799 |
| Short name | T259 |
| Test name | |
| Test status | |
| Simulation time | 7433479093 ps |
| CPU time | 28.25 seconds |
| Started | Aug 27 07:36:39 PM UTC 24 |
| Finished | Aug 27 07:37:08 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2236162799 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_stress_all.2236162799 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.2642718179 |
| Short name | T578 |
| Test name | |
| Test status | |
| Simulation time | 2143161921 ps |
| CPU time | 10.16 seconds |
| Started | Aug 27 07:36:37 PM UTC 24 |
| Finished | Aug 27 07:36:49 PM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2642718179 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.2642718179 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.4057244548 |
| Short name | T114 |
| Test name | |
| Test status | |
| Simulation time | 12677819632 ps |
| CPU time | 9.7 seconds |
| Started | Aug 27 07:36:34 PM UTC 24 |
| Finished | Aug 27 07:36:45 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4057244548 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.4057244548 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.442082178 |
| Short name | T586 |
| Test name | |
| Test status | |
| Simulation time | 2029063164 ps |
| CPU time | 2.38 seconds |
| Started | Aug 27 07:36:53 PM UTC 24 |
| Finished | Aug 27 07:36:56 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=442082178 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.442082178 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.1767501502 |
| Short name | T585 |
| Test name | |
| Test status | |
| Simulation time | 3528770430 ps |
| CPU time | 6.15 seconds |
| Started | Aug 27 07:36:48 PM UTC 24 |
| Finished | Aug 27 07:36:55 PM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1767501502 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.1767501502 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.522564732 |
| Short name | T283 |
| Test name | |
| Test status | |
| Simulation time | 156060432181 ps |
| CPU time | 267.98 seconds |
| Started | Aug 27 07:36:50 PM UTC 24 |
| Finished | Aug 27 07:41:21 PM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522564732 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.522564732 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.428897324 |
| Short name | T725 |
| Test name | |
| Test status | |
| Simulation time | 69107768247 ps |
| CPU time | 153.39 seconds |
| Started | Aug 27 07:36:50 PM UTC 24 |
| Finished | Aug 27 07:39:26 PM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=428897324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_with_pre_cond.428897324 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.547949211 |
| Short name | T596 |
| Test name | |
| Test status | |
| Simulation time | 3477222429 ps |
| CPU time | 16.46 seconds |
| Started | Aug 27 07:36:48 PM UTC 24 |
| Finished | Aug 27 07:37:06 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=547949211 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.547949211 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.1356459291 |
| Short name | T598 |
| Test name | |
| Test status | |
| Simulation time | 2960654288 ps |
| CPU time | 15.59 seconds |
| Started | Aug 27 07:36:50 PM UTC 24 |
| Finished | Aug 27 07:37:07 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1356459291 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.1356459291 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.397029482 |
| Short name | T582 |
| Test name | |
| Test status | |
| Simulation time | 2672105143 ps |
| CPU time | 2.16 seconds |
| Started | Aug 27 07:36:48 PM UTC 24 |
| Finished | Aug 27 07:36:51 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397029482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.397029482 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.152105992 |
| Short name | T575 |
| Test name | |
| Test status | |
| Simulation time | 2455175726 ps |
| CPU time | 6.25 seconds |
| Started | Aug 27 07:36:40 PM UTC 24 |
| Finished | Aug 27 07:36:47 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=152105992 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.152105992 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.83989114 |
| Short name | T579 |
| Test name | |
| Test status | |
| Simulation time | 2036919427 ps |
| CPU time | 6.54 seconds |
| Started | Aug 27 07:36:41 PM UTC 24 |
| Finished | Aug 27 07:36:49 PM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=83989114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysr st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.83989114 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.3711410821 |
| Short name | T587 |
| Test name | |
| Test status | |
| Simulation time | 2510394403 ps |
| CPU time | 8.41 seconds |
| Started | Aug 27 07:36:47 PM UTC 24 |
| Finished | Aug 27 07:36:56 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3711410821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.3711410821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.2822874195 |
| Short name | T576 |
| Test name | |
| Test status | |
| Simulation time | 2115159841 ps |
| CPU time | 6.69 seconds |
| Started | Aug 27 07:36:40 PM UTC 24 |
| Finished | Aug 27 07:36:48 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2822874195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.2822874195 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2821581959 |
| Short name | T597 |
| Test name | |
| Test status | |
| Simulation time | 17714371141 ps |
| CPU time | 12.55 seconds |
| Started | Aug 27 07:36:53 PM UTC 24 |
| Finished | Aug 27 07:37:06 PM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2821581959 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.2821581959 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.2685394242 |
| Short name | T319 |
| Test name | |
| Test status | |
| Simulation time | 3231686859 ps |
| CPU time | 17.66 seconds |
| Started | Aug 27 07:36:51 PM UTC 24 |
| Finished | Aug 27 07:37:10 PM UTC 24 |
| Peak memory | 210336 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2685394242 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.2685394242 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3794316989 |
| Short name | T584 |
| Test name | |
| Test status | |
| Simulation time | 6880115764 ps |
| CPU time | 4.3 seconds |
| Started | Aug 27 07:36:50 PM UTC 24 |
| Finished | Aug 27 07:36:55 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3794316989 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.3794316989 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.2296251794 |
| Short name | T599 |
| Test name | |
| Test status | |
| Simulation time | 2026042304 ps |
| CPU time | 4.17 seconds |
| Started | Aug 27 07:37:05 PM UTC 24 |
| Finished | Aug 27 07:37:10 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296251794 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.2296251794 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3479328356 |
| Short name | T605 |
| Test name | |
| Test status | |
| Simulation time | 3327610390 ps |
| CPU time | 17.73 seconds |
| Started | Aug 27 07:36:59 PM UTC 24 |
| Finished | Aug 27 07:37:18 PM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3479328356 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.3479328356 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.4190211855 |
| Short name | T753 |
| Test name | |
| Test status | |
| Simulation time | 219382071304 ps |
| CPU time | 745.49 seconds |
| Started | Aug 27 07:37:02 PM UTC 24 |
| Finished | Aug 27 07:49:35 PM UTC 24 |
| Peak memory | 210176 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4190211855 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.4190211855 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.906007133 |
| Short name | T624 |
| Test name | |
| Test status | |
| Simulation time | 25582028817 ps |
| CPU time | 39.94 seconds |
| Started | Aug 27 07:37:03 PM UTC 24 |
| Finished | Aug 27 07:37:45 PM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=906007133 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_with_pre_cond.906007133 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.2148317190 |
| Short name | T594 |
| Test name | |
| Test status | |
| Simulation time | 4340836124 ps |
| CPU time | 4.13 seconds |
| Started | Aug 27 07:36:58 PM UTC 24 |
| Finished | Aug 27 07:37:03 PM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2148317190 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.2148317190 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.593333476 |
| Short name | T260 |
| Test name | |
| Test status | |
| Simulation time | 3522992300 ps |
| CPU time | 16.38 seconds |
| Started | Aug 27 07:37:02 PM UTC 24 |
| Finished | Aug 27 07:37:19 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=593333476 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.593333476 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.1697707858 |
| Short name | T592 |
| Test name | |
| Test status | |
| Simulation time | 2646987070 ps |
| CPU time | 3.14 seconds |
| Started | Aug 27 07:36:58 PM UTC 24 |
| Finished | Aug 27 07:37:02 PM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697707858 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.1697707858 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.2482248437 |
| Short name | T591 |
| Test name | |
| Test status | |
| Simulation time | 2484786378 ps |
| CPU time | 3.68 seconds |
| Started | Aug 27 07:36:56 PM UTC 24 |
| Finished | Aug 27 07:37:01 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2482248437 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.2482248437 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.2020656280 |
| Short name | T589 |
| Test name | |
| Test status | |
| Simulation time | 2141748335 ps |
| CPU time | 2.95 seconds |
| Started | Aug 27 07:36:56 PM UTC 24 |
| Finished | Aug 27 07:37:00 PM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2020656280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.2020656280 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.3594713748 |
| Short name | T593 |
| Test name | |
| Test status | |
| Simulation time | 2542625094 ps |
| CPU time | 3.53 seconds |
| Started | Aug 27 07:36:58 PM UTC 24 |
| Finished | Aug 27 07:37:02 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3594713748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.3594713748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2619593306 |
| Short name | T588 |
| Test name | |
| Test status | |
| Simulation time | 2180398746 ps |
| CPU time | 1.91 seconds |
| Started | Aug 27 07:36:54 PM UTC 24 |
| Finished | Aug 27 07:36:57 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2619593306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.2619593306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.689816283 |
| Short name | T595 |
| Test name | |
| Test status | |
| Simulation time | 6611765688 ps |
| CPU time | 1.93 seconds |
| Started | Aug 27 07:37:02 PM UTC 24 |
| Finished | Aug 27 07:37:05 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=689816283 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.689816283 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.1695089307 |
| Short name | T613 |
| Test name | |
| Test status | |
| Simulation time | 2012300804 ps |
| CPU time | 11.92 seconds |
| Started | Aug 27 07:37:21 PM UTC 24 |
| Finished | Aug 27 07:37:34 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1695089307 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.1695089307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1604594249 |
| Short name | T602 |
| Test name | |
| Test status | |
| Simulation time | 3389429153 ps |
| CPU time | 2.57 seconds |
| Started | Aug 27 07:37:11 PM UTC 24 |
| Finished | Aug 27 07:37:15 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1604594249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1604594249 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.367362186 |
| Short name | T345 |
| Test name | |
| Test status | |
| Simulation time | 154395845552 ps |
| CPU time | 122.51 seconds |
| Started | Aug 27 07:37:13 PM UTC 24 |
| Finished | Aug 27 07:39:18 PM UTC 24 |
| Peak memory | 210428 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=367362186 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.367362186 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.238162214 |
| Short name | T342 |
| Test name | |
| Test status | |
| Simulation time | 39706893041 ps |
| CPU time | 27.41 seconds |
| Started | Aug 27 07:37:17 PM UTC 24 |
| Finished | Aug 27 07:37:46 PM UTC 24 |
| Peak memory | 210516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=238162214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_with_pre_cond.238162214 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.994379532 |
| Short name | T604 |
| Test name | |
| Test status | |
| Simulation time | 3997038603 ps |
| CPU time | 4.56 seconds |
| Started | Aug 27 07:37:11 PM UTC 24 |
| Finished | Aug 27 07:37:17 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=994379532 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.994379532 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.285238127 |
| Short name | T226 |
| Test name | |
| Test status | |
| Simulation time | 3254478417 ps |
| CPU time | 10.87 seconds |
| Started | Aug 27 07:37:16 PM UTC 24 |
| Finished | Aug 27 07:37:28 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=285238127 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.285238127 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.3149904023 |
| Short name | T600 |
| Test name | |
| Test status | |
| Simulation time | 2759750838 ps |
| CPU time | 1.62 seconds |
| Started | Aug 27 07:37:10 PM UTC 24 |
| Finished | Aug 27 07:37:12 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3149904023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.3149904023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.755067410 |
| Short name | T603 |
| Test name | |
| Test status | |
| Simulation time | 2469965141 ps |
| CPU time | 7.1 seconds |
| Started | Aug 27 07:37:07 PM UTC 24 |
| Finished | Aug 27 07:37:15 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=755067410 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.755067410 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.2894896287 |
| Short name | T606 |
| Test name | |
| Test status | |
| Simulation time | 2237295182 ps |
| CPU time | 12.07 seconds |
| Started | Aug 27 07:37:07 PM UTC 24 |
| Finished | Aug 27 07:37:20 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2894896287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.2894896287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.58160897 |
| Short name | T607 |
| Test name | |
| Test status | |
| Simulation time | 2511694280 ps |
| CPU time | 12.37 seconds |
| Started | Aug 27 07:37:08 PM UTC 24 |
| Finished | Aug 27 07:37:22 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=58160897 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.58160897 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.2589053658 |
| Short name | T601 |
| Test name | |
| Test status | |
| Simulation time | 2118413086 ps |
| CPU time | 5.68 seconds |
| Started | Aug 27 07:37:06 PM UTC 24 |
| Finished | Aug 27 07:37:12 PM UTC 24 |
| Peak memory | 209812 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589053658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.2589053658 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.572586875 |
| Short name | T632 |
| Test name | |
| Test status | |
| Simulation time | 13231312748 ps |
| CPU time | 32.65 seconds |
| Started | Aug 27 07:37:19 PM UTC 24 |
| Finished | Aug 27 07:37:54 PM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=572586875 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.572586875 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.923569041 |
| Short name | T320 |
| Test name | |
| Test status | |
| Simulation time | 5450895602 ps |
| CPU time | 14.49 seconds |
| Started | Aug 27 07:37:18 PM UTC 24 |
| Finished | Aug 27 07:37:34 PM UTC 24 |
| Peak memory | 210012 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=923569041 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.923569041 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.3010676160 |
| Short name | T144 |
| Test name | |
| Test status | |
| Simulation time | 5985285930 ps |
| CPU time | 6.4 seconds |
| Started | Aug 27 07:37:13 PM UTC 24 |
| Finished | Aug 27 07:37:21 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3010676160 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.3010676160 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.3206314445 |
| Short name | T307 |
| Test name | |
| Test status | |
| Simulation time | 2012333630 ps |
| CPU time | 12.56 seconds |
| Started | Aug 27 07:28:07 PM UTC 24 |
| Finished | Aug 27 07:28:21 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3206314445 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.3206314445 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.861683213 |
| Short name | T484 |
| Test name | |
| Test status | |
| Simulation time | 231828987477 ps |
| CPU time | 376.32 seconds |
| Started | Aug 27 07:27:52 PM UTC 24 |
| Finished | Aug 27 07:34:13 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=861683213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.861683213 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2332998614 |
| Short name | T40 |
| Test name | |
| Test status | |
| Simulation time | 74825896560 ps |
| CPU time | 129.87 seconds |
| Started | Aug 27 07:27:57 PM UTC 24 |
| Finished | Aug 27 07:30:09 PM UTC 24 |
| Peak memory | 210108 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2332998614 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.2332998614 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2408558370 |
| Short name | T244 |
| Test name | |
| Test status | |
| Simulation time | 2183069787 ps |
| CPU time | 4.47 seconds |
| Started | Aug 27 07:27:46 PM UTC 24 |
| Finished | Aug 27 07:27:51 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2408558370 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2408558370 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2276730785 |
| Short name | T89 |
| Test name | |
| Test status | |
| Simulation time | 2315739403 ps |
| CPU time | 2.37 seconds |
| Started | Aug 27 07:27:48 PM UTC 24 |
| Finished | Aug 27 07:27:51 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2276730785 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r egression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2276730785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.4107301977 |
| Short name | T91 |
| Test name | |
| Test status | |
| Simulation time | 59994317780 ps |
| CPU time | 107.02 seconds |
| Started | Aug 27 07:27:58 PM UTC 24 |
| Finished | Aug 27 07:29:47 PM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4107301977 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_with_pre_cond.4107301977 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.1941457835 |
| Short name | T742 |
| Test name | |
| Test status | |
| Simulation time | 948238604581 ps |
| CPU time | 786.79 seconds |
| Started | Aug 27 07:27:52 PM UTC 24 |
| Finished | Aug 27 07:41:08 PM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1941457835 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.1941457835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.444424593 |
| Short name | T50 |
| Test name | |
| Test status | |
| Simulation time | 3556084276 ps |
| CPU time | 12.36 seconds |
| Started | Aug 27 07:27:57 PM UTC 24 |
| Finished | Aug 27 07:28:10 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=444424593 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.444424593 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.4255973207 |
| Short name | T87 |
| Test name | |
| Test status | |
| Simulation time | 2640536279 ps |
| CPU time | 3.36 seconds |
| Started | Aug 27 07:27:52 PM UTC 24 |
| Finished | Aug 27 07:27:57 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4255973207 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.4255973207 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.3004748441 |
| Short name | T79 |
| Test name | |
| Test status | |
| Simulation time | 2472413780 ps |
| CPU time | 4.63 seconds |
| Started | Aug 27 07:27:45 PM UTC 24 |
| Finished | Aug 27 07:27:50 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004748441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.3004748441 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.636991126 |
| Short name | T243 |
| Test name | |
| Test status | |
| Simulation time | 2124908685 ps |
| CPU time | 2 seconds |
| Started | Aug 27 07:27:48 PM UTC 24 |
| Finished | Aug 27 07:27:51 PM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636991126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.636991126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.2981360152 |
| Short name | T93 |
| Test name | |
| Test status | |
| Simulation time | 2510748570 ps |
| CPU time | 14.58 seconds |
| Started | Aug 27 07:27:51 PM UTC 24 |
| Finished | Aug 27 07:28:07 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981360152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.2981360152 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.3723428001 |
| Short name | T294 |
| Test name | |
| Test status | |
| Simulation time | 22013502643 ps |
| CPU time | 59.56 seconds |
| Started | Aug 27 07:28:07 PM UTC 24 |
| Finished | Aug 27 07:29:08 PM UTC 24 |
| Peak memory | 240284 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3723428001 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.3723428001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.901431806 |
| Short name | T245 |
| Test name | |
| Test status | |
| Simulation time | 2112294504 ps |
| CPU time | 8.22 seconds |
| Started | Aug 27 07:27:44 PM UTC 24 |
| Finished | Aug 27 07:27:53 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901431806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.901431806 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.86032430 |
| Short name | T24 |
| Test name | |
| Test status | |
| Simulation time | 5712930396 ps |
| CPU time | 13.04 seconds |
| Started | Aug 27 07:27:53 PM UTC 24 |
| Finished | Aug 27 07:28:08 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=86032430 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.86032430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.398341086 |
| Short name | T623 |
| Test name | |
| Test status | |
| Simulation time | 2013531320 ps |
| CPU time | 6.14 seconds |
| Started | Aug 27 07:37:35 PM UTC 24 |
| Finished | Aug 27 07:37:42 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=398341086 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.398341086 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.3845160113 |
| Short name | T615 |
| Test name | |
| Test status | |
| Simulation time | 3046231243 ps |
| CPU time | 7.57 seconds |
| Started | Aug 27 07:37:27 PM UTC 24 |
| Finished | Aug 27 07:37:36 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3845160113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.3845160113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.3399498652 |
| Short name | T378 |
| Test name | |
| Test status | |
| Simulation time | 82556689761 ps |
| CPU time | 58.13 seconds |
| Started | Aug 27 07:37:29 PM UTC 24 |
| Finished | Aug 27 07:38:28 PM UTC 24 |
| Peak memory | 210104 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399498652 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.3399498652 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.2545658715 |
| Short name | T366 |
| Test name | |
| Test status | |
| Simulation time | 56959839761 ps |
| CPU time | 205.76 seconds |
| Started | Aug 27 07:37:30 PM UTC 24 |
| Finished | Aug 27 07:40:59 PM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2545658715 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_with_pre_cond.2545658715 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1048129604 |
| Short name | T616 |
| Test name | |
| Test status | |
| Simulation time | 3548581449 ps |
| CPU time | 10.38 seconds |
| Started | Aug 27 07:37:27 PM UTC 24 |
| Finished | Aug 27 07:37:39 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1048129604 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.1048129604 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.3224110306 |
| Short name | T619 |
| Test name | |
| Test status | |
| Simulation time | 3279619685 ps |
| CPU time | 8.83 seconds |
| Started | Aug 27 07:37:30 PM UTC 24 |
| Finished | Aug 27 07:37:40 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224110306 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.3224110306 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3053617590 |
| Short name | T612 |
| Test name | |
| Test status | |
| Simulation time | 2611864111 ps |
| CPU time | 6.78 seconds |
| Started | Aug 27 07:37:26 PM UTC 24 |
| Finished | Aug 27 07:37:34 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3053617590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3053617590 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.1592823518 |
| Short name | T611 |
| Test name | |
| Test status | |
| Simulation time | 2482868050 ps |
| CPU time | 8.94 seconds |
| Started | Aug 27 07:37:22 PM UTC 24 |
| Finished | Aug 27 07:37:32 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1592823518 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.1592823518 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.172466307 |
| Short name | T614 |
| Test name | |
| Test status | |
| Simulation time | 2042657731 ps |
| CPU time | 9.78 seconds |
| Started | Aug 27 07:37:23 PM UTC 24 |
| Finished | Aug 27 07:37:34 PM UTC 24 |
| Peak memory | 209804 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=172466307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.172466307 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.3461325503 |
| Short name | T609 |
| Test name | |
| Test status | |
| Simulation time | 2747976683 ps |
| CPU time | 1.69 seconds |
| Started | Aug 27 07:37:24 PM UTC 24 |
| Finished | Aug 27 07:37:28 PM UTC 24 |
| Peak memory | 208192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461325503 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.3461325503 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.501254129 |
| Short name | T608 |
| Test name | |
| Test status | |
| Simulation time | 2126956659 ps |
| CPU time | 2.85 seconds |
| Started | Aug 27 07:37:22 PM UTC 24 |
| Finished | Aug 27 07:37:26 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=501254129 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.501254129 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.3044803384 |
| Short name | T634 |
| Test name | |
| Test status | |
| Simulation time | 7384173694 ps |
| CPU time | 19.2 seconds |
| Started | Aug 27 07:37:33 PM UTC 24 |
| Finished | Aug 27 07:37:54 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3044803384 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.3044803384 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.2970466458 |
| Short name | T303 |
| Test name | |
| Test status | |
| Simulation time | 6056966619 ps |
| CPU time | 16.15 seconds |
| Started | Aug 27 07:37:31 PM UTC 24 |
| Finished | Aug 27 07:37:49 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2970466458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.2970466458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.212477462 |
| Short name | T629 |
| Test name | |
| Test status | |
| Simulation time | 2019963476 ps |
| CPU time | 4.12 seconds |
| Started | Aug 27 07:37:45 PM UTC 24 |
| Finished | Aug 27 07:37:51 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=212477462 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.212477462 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.3712300336 |
| Short name | T642 |
| Test name | |
| Test status | |
| Simulation time | 3644028618 ps |
| CPU time | 18.7 seconds |
| Started | Aug 27 07:37:40 PM UTC 24 |
| Finished | Aug 27 07:38:00 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712300336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.3712300336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.901177026 |
| Short name | T337 |
| Test name | |
| Test status | |
| Simulation time | 128691084648 ps |
| CPU time | 35.26 seconds |
| Started | Aug 27 07:37:41 PM UTC 24 |
| Finished | Aug 27 07:38:18 PM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=901177026 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.901177026 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.3931496684 |
| Short name | T640 |
| Test name | |
| Test status | |
| Simulation time | 28981458578 ps |
| CPU time | 15.24 seconds |
| Started | Aug 27 07:37:43 PM UTC 24 |
| Finished | Aug 27 07:37:59 PM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3931496684 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_with_pre_cond.3931496684 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.3731948296 |
| Short name | T625 |
| Test name | |
| Test status | |
| Simulation time | 4218355483 ps |
| CPU time | 4.93 seconds |
| Started | Aug 27 07:37:40 PM UTC 24 |
| Finished | Aug 27 07:37:46 PM UTC 24 |
| Peak memory | 208708 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731948296 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.3731948296 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.2628539430 |
| Short name | T635 |
| Test name | |
| Test status | |
| Simulation time | 2595024523 ps |
| CPU time | 11.42 seconds |
| Started | Aug 27 07:37:43 PM UTC 24 |
| Finished | Aug 27 07:37:55 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2628539430 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.2628539430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.351417120 |
| Short name | T621 |
| Test name | |
| Test status | |
| Simulation time | 2674947527 ps |
| CPU time | 1.86 seconds |
| Started | Aug 27 07:37:39 PM UTC 24 |
| Finished | Aug 27 07:37:42 PM UTC 24 |
| Peak memory | 208192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=351417120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.351417120 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.2773066664 |
| Short name | T620 |
| Test name | |
| Test status | |
| Simulation time | 2483404882 ps |
| CPU time | 4.83 seconds |
| Started | Aug 27 07:37:35 PM UTC 24 |
| Finished | Aug 27 07:37:41 PM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2773066664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.2773066664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.2997908520 |
| Short name | T617 |
| Test name | |
| Test status | |
| Simulation time | 2127613063 ps |
| CPU time | 3.01 seconds |
| Started | Aug 27 07:37:35 PM UTC 24 |
| Finished | Aug 27 07:37:39 PM UTC 24 |
| Peak memory | 209328 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2997908520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.2997908520 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.802815216 |
| Short name | T622 |
| Test name | |
| Test status | |
| Simulation time | 2520908444 ps |
| CPU time | 4.22 seconds |
| Started | Aug 27 07:37:36 PM UTC 24 |
| Finished | Aug 27 07:37:42 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=802815216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.802815216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.3004168458 |
| Short name | T618 |
| Test name | |
| Test status | |
| Simulation time | 2135862496 ps |
| CPU time | 3.11 seconds |
| Started | Aug 27 07:37:35 PM UTC 24 |
| Finished | Aug 27 07:37:39 PM UTC 24 |
| Peak memory | 209224 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3004168458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.3004168458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.588454886 |
| Short name | T649 |
| Test name | |
| Test status | |
| Simulation time | 6967988123 ps |
| CPU time | 19.66 seconds |
| Started | Aug 27 07:37:44 PM UTC 24 |
| Finished | Aug 27 07:38:05 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=588454886 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.588454886 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.4098013064 |
| Short name | T630 |
| Test name | |
| Test status | |
| Simulation time | 7842764819 ps |
| CPU time | 11.21 seconds |
| Started | Aug 27 07:37:40 PM UTC 24 |
| Finished | Aug 27 07:37:53 PM UTC 24 |
| Peak memory | 208768 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4098013064 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.4098013064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.852071093 |
| Short name | T641 |
| Test name | |
| Test status | |
| Simulation time | 2032214684 ps |
| CPU time | 2.82 seconds |
| Started | Aug 27 07:37:56 PM UTC 24 |
| Finished | Aug 27 07:37:59 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=852071093 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.852071093 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.521970508 |
| Short name | T647 |
| Test name | |
| Test status | |
| Simulation time | 3592089080 ps |
| CPU time | 11.35 seconds |
| Started | Aug 27 07:37:52 PM UTC 24 |
| Finished | Aug 27 07:38:05 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=521970508 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.521970508 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.1583834568 |
| Short name | T281 |
| Test name | |
| Test status | |
| Simulation time | 94223746884 ps |
| CPU time | 27.47 seconds |
| Started | Aug 27 07:37:52 PM UTC 24 |
| Finished | Aug 27 07:38:21 PM UTC 24 |
| Peak memory | 210168 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583834568 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.1583834568 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3139317553 |
| Short name | T645 |
| Test name | |
| Test status | |
| Simulation time | 3518852621 ps |
| CPU time | 12.8 seconds |
| Started | Aug 27 07:37:51 PM UTC 24 |
| Finished | Aug 27 07:38:05 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3139317553 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.3139317553 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.4116844882 |
| Short name | T638 |
| Test name | |
| Test status | |
| Simulation time | 3405164343 ps |
| CPU time | 3.62 seconds |
| Started | Aug 27 07:37:54 PM UTC 24 |
| Finished | Aug 27 07:37:58 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4116844882 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.4116844882 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.3632698564 |
| Short name | T633 |
| Test name | |
| Test status | |
| Simulation time | 2632155397 ps |
| CPU time | 2.08 seconds |
| Started | Aug 27 07:37:51 PM UTC 24 |
| Finished | Aug 27 07:37:54 PM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632698564 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.3632698564 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.2987233019 |
| Short name | T627 |
| Test name | |
| Test status | |
| Simulation time | 2534231868 ps |
| CPU time | 1.87 seconds |
| Started | Aug 27 07:37:47 PM UTC 24 |
| Finished | Aug 27 07:37:50 PM UTC 24 |
| Peak memory | 208184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987233019 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.2987233019 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.408977227 |
| Short name | T631 |
| Test name | |
| Test status | |
| Simulation time | 2075850436 ps |
| CPU time | 2.92 seconds |
| Started | Aug 27 07:37:49 PM UTC 24 |
| Finished | Aug 27 07:37:53 PM UTC 24 |
| Peak memory | 209808 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=408977227 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.408977227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.18664747 |
| Short name | T639 |
| Test name | |
| Test status | |
| Simulation time | 2510911727 ps |
| CPU time | 7.31 seconds |
| Started | Aug 27 07:37:51 PM UTC 24 |
| Finished | Aug 27 07:37:59 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=18664747 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.18664747 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.2690346428 |
| Short name | T637 |
| Test name | |
| Test status | |
| Simulation time | 2111046767 ps |
| CPU time | 9.3 seconds |
| Started | Aug 27 07:37:47 PM UTC 24 |
| Finished | Aug 27 07:37:57 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2690346428 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.2690346428 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.4015674979 |
| Short name | T388 |
| Test name | |
| Test status | |
| Simulation time | 15407440128 ps |
| CPU time | 21.84 seconds |
| Started | Aug 27 07:37:56 PM UTC 24 |
| Finished | Aug 27 07:38:19 PM UTC 24 |
| Peak memory | 209932 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4015674979 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.4015674979 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3758815128 |
| Short name | T648 |
| Test name | |
| Test status | |
| Simulation time | 5828454135 ps |
| CPU time | 11.41 seconds |
| Started | Aug 27 07:37:52 PM UTC 24 |
| Finished | Aug 27 07:38:05 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3758815128 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.3758815128 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.448547331 |
| Short name | T658 |
| Test name | |
| Test status | |
| Simulation time | 2023152562 ps |
| CPU time | 6.06 seconds |
| Started | Aug 27 07:38:06 PM UTC 24 |
| Finished | Aug 27 07:38:13 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=448547331 -assert nopostproc +UVM_TESTNAME =sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg ression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.448547331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.2552133963 |
| Short name | T653 |
| Test name | |
| Test status | |
| Simulation time | 3334661055 ps |
| CPU time | 7.94 seconds |
| Started | Aug 27 07:38:01 PM UTC 24 |
| Finished | Aug 27 07:38:10 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2552133963 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.2552133963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect_with_pre_cond.3480594000 |
| Short name | T748 |
| Test name | |
| Test status | |
| Simulation time | 113160602608 ps |
| CPU time | 295.99 seconds |
| Started | Aug 27 07:38:03 PM UTC 24 |
| Finished | Aug 27 07:43:03 PM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3480594000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect_with_pre_cond.3480594000 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.2257618647 |
| Short name | T646 |
| Test name | |
| Test status | |
| Simulation time | 3401554860 ps |
| CPU time | 4.05 seconds |
| Started | Aug 27 07:38:00 PM UTC 24 |
| Finished | Aug 27 07:38:05 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2257618647 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.2257618647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.1324348881 |
| Short name | T626 |
| Test name | |
| Test status | |
| Simulation time | 2648171635 ps |
| CPU time | 2.47 seconds |
| Started | Aug 27 07:38:00 PM UTC 24 |
| Finished | Aug 27 07:38:03 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324348881 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.1324348881 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.944812988 |
| Short name | T650 |
| Test name | |
| Test status | |
| Simulation time | 2475226969 ps |
| CPU time | 7.36 seconds |
| Started | Aug 27 07:37:57 PM UTC 24 |
| Finished | Aug 27 07:38:05 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944812988 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.944812988 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.530682946 |
| Short name | T644 |
| Test name | |
| Test status | |
| Simulation time | 2177938857 ps |
| CPU time | 3.15 seconds |
| Started | Aug 27 07:37:58 PM UTC 24 |
| Finished | Aug 27 07:38:02 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=530682946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.530682946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.489546111 |
| Short name | T652 |
| Test name | |
| Test status | |
| Simulation time | 2510822626 ps |
| CPU time | 10.34 seconds |
| Started | Aug 27 07:37:58 PM UTC 24 |
| Finished | Aug 27 07:38:10 PM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=489546111 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.489546111 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.2397411366 |
| Short name | T643 |
| Test name | |
| Test status | |
| Simulation time | 2131051990 ps |
| CPU time | 4.58 seconds |
| Started | Aug 27 07:37:56 PM UTC 24 |
| Finished | Aug 27 07:38:01 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2397411366 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.2397411366 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.2692732466 |
| Short name | T685 |
| Test name | |
| Test status | |
| Simulation time | 10959536148 ps |
| CPU time | 29.74 seconds |
| Started | Aug 27 07:38:04 PM UTC 24 |
| Finished | Aug 27 07:38:35 PM UTC 24 |
| Peak memory | 210196 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2692732466 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.2692732466 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.2254266204 |
| Short name | T305 |
| Test name | |
| Test status | |
| Simulation time | 23883697352 ps |
| CPU time | 13.46 seconds |
| Started | Aug 27 07:38:03 PM UTC 24 |
| Finished | Aug 27 07:38:18 PM UTC 24 |
| Peak memory | 220408 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2254266204 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.2254266204 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.2585963831 |
| Short name | T656 |
| Test name | |
| Test status | |
| Simulation time | 6093102781 ps |
| CPU time | 9.05 seconds |
| Started | Aug 27 07:38:02 PM UTC 24 |
| Finished | Aug 27 07:38:12 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2585963831 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.2585963831 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1478202438 |
| Short name | T660 |
| Test name | |
| Test status | |
| Simulation time | 2095857963 ps |
| CPU time | 1.26 seconds |
| Started | Aug 27 07:38:13 PM UTC 24 |
| Finished | Aug 27 07:38:16 PM UTC 24 |
| Peak memory | 208244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478202438 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.1478202438 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.4094685674 |
| Short name | T275 |
| Test name | |
| Test status | |
| Simulation time | 95576423204 ps |
| CPU time | 26.5 seconds |
| Started | Aug 27 07:38:10 PM UTC 24 |
| Finished | Aug 27 07:38:38 PM UTC 24 |
| Peak memory | 210164 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4094685674 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.4094685674 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.2484510647 |
| Short name | T389 |
| Test name | |
| Test status | |
| Simulation time | 55671204034 ps |
| CPU time | 18.85 seconds |
| Started | Aug 27 07:38:12 PM UTC 24 |
| Finished | Aug 27 07:38:32 PM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2484510647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_with_pre_cond.2484510647 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.1561733130 |
| Short name | T657 |
| Test name | |
| Test status | |
| Simulation time | 3407798677 ps |
| CPU time | 4.71 seconds |
| Started | Aug 27 07:38:07 PM UTC 24 |
| Finished | Aug 27 07:38:12 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1561733130 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.1561733130 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.1802425986 |
| Short name | T661 |
| Test name | |
| Test status | |
| Simulation time | 3460990398 ps |
| CPU time | 3.34 seconds |
| Started | Aug 27 07:38:12 PM UTC 24 |
| Finished | Aug 27 07:38:16 PM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802425986 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.1802425986 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3224597719 |
| Short name | T662 |
| Test name | |
| Test status | |
| Simulation time | 2607307895 ps |
| CPU time | 8.93 seconds |
| Started | Aug 27 07:38:07 PM UTC 24 |
| Finished | Aug 27 07:38:17 PM UTC 24 |
| Peak memory | 209916 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3224597719 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.3224597719 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.3821767098 |
| Short name | T668 |
| Test name | |
| Test status | |
| Simulation time | 2446446615 ps |
| CPU time | 13.18 seconds |
| Started | Aug 27 07:38:06 PM UTC 24 |
| Finished | Aug 27 07:38:21 PM UTC 24 |
| Peak memory | 210144 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3821767098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.3821767098 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.690460821 |
| Short name | T654 |
| Test name | |
| Test status | |
| Simulation time | 2048603783 ps |
| CPU time | 3.1 seconds |
| Started | Aug 27 07:38:07 PM UTC 24 |
| Finished | Aug 27 07:38:11 PM UTC 24 |
| Peak memory | 209692 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=690460821 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.690460821 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.2389378871 |
| Short name | T655 |
| Test name | |
| Test status | |
| Simulation time | 2522354360 ps |
| CPU time | 3.96 seconds |
| Started | Aug 27 07:38:07 PM UTC 24 |
| Finished | Aug 27 07:38:12 PM UTC 24 |
| Peak memory | 210216 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2389378871 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.2389378871 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.163621046 |
| Short name | T659 |
| Test name | |
| Test status | |
| Simulation time | 2121077245 ps |
| CPU time | 6.52 seconds |
| Started | Aug 27 07:38:06 PM UTC 24 |
| Finished | Aug 27 07:38:14 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=163621046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.163621046 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.2845907985 |
| Short name | T152 |
| Test name | |
| Test status | |
| Simulation time | 16135734146 ps |
| CPU time | 13.2 seconds |
| Started | Aug 27 07:38:13 PM UTC 24 |
| Finished | Aug 27 07:38:28 PM UTC 24 |
| Peak memory | 210068 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2845907985 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.2845907985 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1576473471 |
| Short name | T298 |
| Test name | |
| Test status | |
| Simulation time | 4790139260 ps |
| CPU time | 16.98 seconds |
| Started | Aug 27 07:38:13 PM UTC 24 |
| Finished | Aug 27 07:38:32 PM UTC 24 |
| Peak memory | 227072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1576473471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.1576473471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.90522541 |
| Short name | T663 |
| Test name | |
| Test status | |
| Simulation time | 7832441307 ps |
| CPU time | 7.66 seconds |
| Started | Aug 27 07:38:08 PM UTC 24 |
| Finished | Aug 27 07:38:17 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=90522541 -assert nopostproc +UVM_TES TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.90522541 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2991967423 |
| Short name | T674 |
| Test name | |
| Test status | |
| Simulation time | 2014388403 ps |
| CPU time | 5.56 seconds |
| Started | Aug 27 07:38:21 PM UTC 24 |
| Finished | Aug 27 07:38:27 PM UTC 24 |
| Peak memory | 209748 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2991967423 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.2991967423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.1024311665 |
| Short name | T677 |
| Test name | |
| Test status | |
| Simulation time | 3744839752 ps |
| CPU time | 10.3 seconds |
| Started | Aug 27 07:38:18 PM UTC 24 |
| Finished | Aug 27 07:38:29 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1024311665 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.1024311665 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.3772286068 |
| Short name | T282 |
| Test name | |
| Test status | |
| Simulation time | 129419754466 ps |
| CPU time | 47.63 seconds |
| Started | Aug 27 07:38:18 PM UTC 24 |
| Finished | Aug 27 07:39:07 PM UTC 24 |
| Peak memory | 210500 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3772286068 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.3772286068 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4049268526 |
| Short name | T747 |
| Test name | |
| Test status | |
| Simulation time | 99863017021 ps |
| CPU time | 271.37 seconds |
| Started | Aug 27 07:38:20 PM UTC 24 |
| Finished | Aug 27 07:42:55 PM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4049268526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_with_pre_cond.4049268526 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.1287883628 |
| Short name | T678 |
| Test name | |
| Test status | |
| Simulation time | 3571520310 ps |
| CPU time | 12.44 seconds |
| Started | Aug 27 07:38:17 PM UTC 24 |
| Finished | Aug 27 07:38:30 PM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1287883628 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.1287883628 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.684103020 |
| Short name | T232 |
| Test name | |
| Test status | |
| Simulation time | 3649583986 ps |
| CPU time | 4.37 seconds |
| Started | Aug 27 07:38:20 PM UTC 24 |
| Finished | Aug 27 07:38:26 PM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=684103020 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.684103020 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.267196730 |
| Short name | T667 |
| Test name | |
| Test status | |
| Simulation time | 2710010850 ps |
| CPU time | 1.86 seconds |
| Started | Aug 27 07:38:17 PM UTC 24 |
| Finished | Aug 27 07:38:19 PM UTC 24 |
| Peak memory | 208192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267196730 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.267196730 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.1386395751 |
| Short name | T673 |
| Test name | |
| Test status | |
| Simulation time | 2452398546 ps |
| CPU time | 9.98 seconds |
| Started | Aug 27 07:38:15 PM UTC 24 |
| Finished | Aug 27 07:38:26 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1386395751 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.1386395751 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.389694126 |
| Short name | T665 |
| Test name | |
| Test status | |
| Simulation time | 2153167923 ps |
| CPU time | 2.04 seconds |
| Started | Aug 27 07:38:15 PM UTC 24 |
| Finished | Aug 27 07:38:18 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=389694126 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.389694126 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.3476580519 |
| Short name | T669 |
| Test name | |
| Test status | |
| Simulation time | 2513080403 ps |
| CPU time | 8 seconds |
| Started | Aug 27 07:38:15 PM UTC 24 |
| Finished | Aug 27 07:38:24 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3476580519 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.3476580519 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.3338069064 |
| Short name | T664 |
| Test name | |
| Test status | |
| Simulation time | 2133481856 ps |
| CPU time | 2.4 seconds |
| Started | Aug 27 07:38:14 PM UTC 24 |
| Finished | Aug 27 07:38:17 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3338069064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.3338069064 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.1813410258 |
| Short name | T692 |
| Test name | |
| Test status | |
| Simulation time | 10864865786 ps |
| CPU time | 21.1 seconds |
| Started | Aug 27 07:38:20 PM UTC 24 |
| Finished | Aug 27 07:38:43 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813410258 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.1813410258 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.2546161639 |
| Short name | T299 |
| Test name | |
| Test status | |
| Simulation time | 5676609621 ps |
| CPU time | 19.91 seconds |
| Started | Aug 27 07:38:20 PM UTC 24 |
| Finished | Aug 27 07:38:41 PM UTC 24 |
| Peak memory | 220540 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2546161639 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.2546161639 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.322395002 |
| Short name | T670 |
| Test name | |
| Test status | |
| Simulation time | 6252909620 ps |
| CPU time | 6.89 seconds |
| Started | Aug 27 07:38:18 PM UTC 24 |
| Finished | Aug 27 07:38:26 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=322395002 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.322395002 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.3232000312 |
| Short name | T687 |
| Test name | |
| Test status | |
| Simulation time | 2015054190 ps |
| CPU time | 6.22 seconds |
| Started | Aug 27 07:38:30 PM UTC 24 |
| Finished | Aug 27 07:38:37 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232000312 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.3232000312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.1336881748 |
| Short name | T682 |
| Test name | |
| Test status | |
| Simulation time | 3497379500 ps |
| CPU time | 5.42 seconds |
| Started | Aug 27 07:38:27 PM UTC 24 |
| Finished | Aug 27 07:38:34 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1336881748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.1336881748 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.4205451424 |
| Short name | T720 |
| Test name | |
| Test status | |
| Simulation time | 32580840711 ps |
| CPU time | 49.46 seconds |
| Started | Aug 27 07:38:28 PM UTC 24 |
| Finished | Aug 27 07:39:18 PM UTC 24 |
| Peak memory | 210644 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4205451424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_with_pre_cond.4205451424 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.2042624692 |
| Short name | T679 |
| Test name | |
| Test status | |
| Simulation time | 2690237134 ps |
| CPU time | 3.7 seconds |
| Started | Aug 27 07:38:26 PM UTC 24 |
| Finished | Aug 27 07:38:30 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042624692 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.2042624692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.3295072039 |
| Short name | T691 |
| Test name | |
| Test status | |
| Simulation time | 2638399708 ps |
| CPU time | 12.66 seconds |
| Started | Aug 27 07:38:28 PM UTC 24 |
| Finished | Aug 27 07:38:41 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3295072039 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.3295072039 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.1323492606 |
| Short name | T672 |
| Test name | |
| Test status | |
| Simulation time | 2637232672 ps |
| CPU time | 2.91 seconds |
| Started | Aug 27 07:38:22 PM UTC 24 |
| Finished | Aug 27 07:38:26 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1323492606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.1323492606 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1249392401 |
| Short name | T680 |
| Test name | |
| Test status | |
| Simulation time | 2463377015 ps |
| CPU time | 10.67 seconds |
| Started | Aug 27 07:38:21 PM UTC 24 |
| Finished | Aug 27 07:38:32 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1249392401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.1249392401 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.1752403409 |
| Short name | T671 |
| Test name | |
| Test status | |
| Simulation time | 2219796344 ps |
| CPU time | 2.94 seconds |
| Started | Aug 27 07:38:22 PM UTC 24 |
| Finished | Aug 27 07:38:26 PM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752403409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.1752403409 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.3978379545 |
| Short name | T676 |
| Test name | |
| Test status | |
| Simulation time | 2519109023 ps |
| CPU time | 5.59 seconds |
| Started | Aug 27 07:38:22 PM UTC 24 |
| Finished | Aug 27 07:38:29 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3978379545 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.3978379545 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.2649143147 |
| Short name | T675 |
| Test name | |
| Test status | |
| Simulation time | 2113704322 ps |
| CPU time | 6.25 seconds |
| Started | Aug 27 07:38:21 PM UTC 24 |
| Finished | Aug 27 07:38:28 PM UTC 24 |
| Peak memory | 209764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2649143147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.2649143147 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.2380961755 |
| Short name | T381 |
| Test name | |
| Test status | |
| Simulation time | 210490710061 ps |
| CPU time | 31.9 seconds |
| Started | Aug 27 07:38:29 PM UTC 24 |
| Finished | Aug 27 07:39:03 PM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2380961755 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.2380961755 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.2482926208 |
| Short name | T698 |
| Test name | |
| Test status | |
| Simulation time | 36920532135 ps |
| CPU time | 14.93 seconds |
| Started | Aug 27 07:38:29 PM UTC 24 |
| Finished | Aug 27 07:38:45 PM UTC 24 |
| Peak memory | 222660 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2482926208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.2482926208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1271936451 |
| Short name | T153 |
| Test name | |
| Test status | |
| Simulation time | 6198040120 ps |
| CPU time | 2.81 seconds |
| Started | Aug 27 07:38:27 PM UTC 24 |
| Finished | Aug 27 07:38:31 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271936451 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.1271936451 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.1227559542 |
| Short name | T693 |
| Test name | |
| Test status | |
| Simulation time | 2020089229 ps |
| CPU time | 5.49 seconds |
| Started | Aug 27 07:38:36 PM UTC 24 |
| Finished | Aug 27 07:38:43 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227559542 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.1227559542 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1341020105 |
| Short name | T701 |
| Test name | |
| Test status | |
| Simulation time | 3762819785 ps |
| CPU time | 11.63 seconds |
| Started | Aug 27 07:38:33 PM UTC 24 |
| Finished | Aug 27 07:38:46 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1341020105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.1341020105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.1001847610 |
| Short name | T341 |
| Test name | |
| Test status | |
| Simulation time | 173279053346 ps |
| CPU time | 531.77 seconds |
| Started | Aug 27 07:38:33 PM UTC 24 |
| Finished | Aug 27 07:47:31 PM UTC 24 |
| Peak memory | 210228 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1001847610 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.1001847610 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2796013795 |
| Short name | T356 |
| Test name | |
| Test status | |
| Simulation time | 123536009571 ps |
| CPU time | 104.47 seconds |
| Started | Aug 27 07:38:33 PM UTC 24 |
| Finished | Aug 27 07:40:20 PM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796013795 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_with_pre_cond.2796013795 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.2861251943 |
| Short name | T683 |
| Test name | |
| Test status | |
| Simulation time | 3429087641 ps |
| CPU time | 1.62 seconds |
| Started | Aug 27 07:38:31 PM UTC 24 |
| Finished | Aug 27 07:38:34 PM UTC 24 |
| Peak memory | 208180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2861251943 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.2861251943 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.1844330199 |
| Short name | T689 |
| Test name | |
| Test status | |
| Simulation time | 3242970005 ps |
| CPU time | 4.08 seconds |
| Started | Aug 27 07:38:33 PM UTC 24 |
| Finished | Aug 27 07:38:39 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1844330199 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.1844330199 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.4137245208 |
| Short name | T695 |
| Test name | |
| Test status | |
| Simulation time | 2609720404 ps |
| CPU time | 11.39 seconds |
| Started | Aug 27 07:38:31 PM UTC 24 |
| Finished | Aug 27 07:38:44 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4137245208 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.4137245208 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.341293763 |
| Short name | T688 |
| Test name | |
| Test status | |
| Simulation time | 2468411122 ps |
| CPU time | 7.1 seconds |
| Started | Aug 27 07:38:30 PM UTC 24 |
| Finished | Aug 27 07:38:38 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=341293763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2 6/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.341293763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.2724485599 |
| Short name | T686 |
| Test name | |
| Test status | |
| Simulation time | 2211972405 ps |
| CPU time | 3.13 seconds |
| Started | Aug 27 07:38:31 PM UTC 24 |
| Finished | Aug 27 07:38:35 PM UTC 24 |
| Peak memory | 210072 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2724485599 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.2724485599 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.620023151 |
| Short name | T684 |
| Test name | |
| Test status | |
| Simulation time | 2570617727 ps |
| CPU time | 2.25 seconds |
| Started | Aug 27 07:38:31 PM UTC 24 |
| Finished | Aug 27 07:38:35 PM UTC 24 |
| Peak memory | 209764 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=620023151 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/s ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.620023151 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.254432288 |
| Short name | T681 |
| Test name | |
| Test status | |
| Simulation time | 2148661709 ps |
| CPU time | 2.09 seconds |
| Started | Aug 27 07:38:30 PM UTC 24 |
| Finished | Aug 27 07:38:33 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=254432288 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.254432288 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.1297833902 |
| Short name | T696 |
| Test name | |
| Test status | |
| Simulation time | 6943535852 ps |
| CPU time | 8.17 seconds |
| Started | Aug 27 07:38:35 PM UTC 24 |
| Finished | Aug 27 07:38:44 PM UTC 24 |
| Peak memory | 210088 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1297833902 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.1297833902 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.1125291744 |
| Short name | T700 |
| Test name | |
| Test status | |
| Simulation time | 11099807571 ps |
| CPU time | 10.05 seconds |
| Started | Aug 27 07:38:35 PM UTC 24 |
| Finished | Aug 27 07:38:46 PM UTC 24 |
| Peak memory | 220672 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=1125291744 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.1125291744 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.824480978 |
| Short name | T157 |
| Test name | |
| Test status | |
| Simulation time | 4532505346 ps |
| CPU time | 3.12 seconds |
| Started | Aug 27 07:38:33 PM UTC 24 |
| Finished | Aug 27 07:38:37 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=824480978 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.824480978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.3775739174 |
| Short name | T713 |
| Test name | |
| Test status | |
| Simulation time | 2012578556 ps |
| CPU time | 6.1 seconds |
| Started | Aug 27 07:38:46 PM UTC 24 |
| Finished | Aug 27 07:38:53 PM UTC 24 |
| Peak memory | 210136 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3775739174 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.3775739174 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.4093371616 |
| Short name | T699 |
| Test name | |
| Test status | |
| Simulation time | 3275369864 ps |
| CPU time | 5.01 seconds |
| Started | Aug 27 07:38:40 PM UTC 24 |
| Finished | Aug 27 07:38:46 PM UTC 24 |
| Peak memory | 210016 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093371616 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.4093371616 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.2394594575 |
| Short name | T729 |
| Test name | |
| Test status | |
| Simulation time | 51748895533 ps |
| CPU time | 61.21 seconds |
| Started | Aug 27 07:38:42 PM UTC 24 |
| Finished | Aug 27 07:39:45 PM UTC 24 |
| Peak memory | 210172 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2394594575 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.2394594575 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect_with_pre_cond.3020168454 |
| Short name | T369 |
| Test name | |
| Test status | |
| Simulation time | 53870268895 ps |
| CPU time | 129.23 seconds |
| Started | Aug 27 07:38:44 PM UTC 24 |
| Finished | Aug 27 07:40:55 PM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3020168454 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect_with_pre_cond.3020168454 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.2442132963 |
| Short name | T694 |
| Test name | |
| Test status | |
| Simulation time | 3470924298 ps |
| CPU time | 3.04 seconds |
| Started | Aug 27 07:38:40 PM UTC 24 |
| Finished | Aug 27 07:38:44 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442132963 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.2442132963 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.3896822312 |
| Short name | T715 |
| Test name | |
| Test status | |
| Simulation time | 3289887554 ps |
| CPU time | 11.76 seconds |
| Started | Aug 27 07:38:44 PM UTC 24 |
| Finished | Aug 27 07:38:57 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3896822312 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.3896822312 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.1678087576 |
| Short name | T705 |
| Test name | |
| Test status | |
| Simulation time | 2612095515 ps |
| CPU time | 9.25 seconds |
| Started | Aug 27 07:38:39 PM UTC 24 |
| Finished | Aug 27 07:38:50 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1678087576 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.1678087576 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.1623029007 |
| Short name | T651 |
| Test name | |
| Test status | |
| Simulation time | 2449968183 ps |
| CPU time | 6.82 seconds |
| Started | Aug 27 07:38:37 PM UTC 24 |
| Finished | Aug 27 07:38:44 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1623029007 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.1623029007 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.3155200895 |
| Short name | T704 |
| Test name | |
| Test status | |
| Simulation time | 2249869528 ps |
| CPU time | 10.4 seconds |
| Started | Aug 27 07:38:38 PM UTC 24 |
| Finished | Aug 27 07:38:49 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3155200895 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.3155200895 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.1796771430 |
| Short name | T703 |
| Test name | |
| Test status | |
| Simulation time | 2513109038 ps |
| CPU time | 9.44 seconds |
| Started | Aug 27 07:38:38 PM UTC 24 |
| Finished | Aug 27 07:38:48 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1796771430 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.1796771430 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.2806411399 |
| Short name | T690 |
| Test name | |
| Test status | |
| Simulation time | 2132348299 ps |
| CPU time | 3.62 seconds |
| Started | Aug 27 07:38:36 PM UTC 24 |
| Finished | Aug 27 07:38:41 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2806411399 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.2806411399 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.890702946 |
| Short name | T746 |
| Test name | |
| Test status | |
| Simulation time | 141420061035 ps |
| CPU time | 229.42 seconds |
| Started | Aug 27 07:38:44 PM UTC 24 |
| Finished | Aug 27 07:42:36 PM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=890702946 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.890702946 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2289890287 |
| Short name | T711 |
| Test name | |
| Test status | |
| Simulation time | 10162610033 ps |
| CPU time | 7.84 seconds |
| Started | Aug 27 07:38:44 PM UTC 24 |
| Finished | Aug 27 07:38:53 PM UTC 24 |
| Peak memory | 226320 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2289890287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.2289890287 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.2442247654 |
| Short name | T702 |
| Test name | |
| Test status | |
| Simulation time | 2982874976 ps |
| CPU time | 5.34 seconds |
| Started | Aug 27 07:38:42 PM UTC 24 |
| Finished | Aug 27 07:38:48 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2442247654 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.2442247654 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.3762128720 |
| Short name | T714 |
| Test name | |
| Test status | |
| Simulation time | 2035059601 ps |
| CPU time | 2.92 seconds |
| Started | Aug 27 07:38:51 PM UTC 24 |
| Finished | Aug 27 07:38:55 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3762128720 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.3762128720 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2100278978 |
| Short name | T710 |
| Test name | |
| Test status | |
| Simulation time | 4031097326 ps |
| CPU time | 3.33 seconds |
| Started | Aug 27 07:38:48 PM UTC 24 |
| Finished | Aug 27 07:38:52 PM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2100278978 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.2100278978 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.1905209529 |
| Short name | T127 |
| Test name | |
| Test status | |
| Simulation time | 91544256507 ps |
| CPU time | 68.68 seconds |
| Started | Aug 27 07:38:49 PM UTC 24 |
| Finished | Aug 27 07:40:00 PM UTC 24 |
| Peak memory | 210432 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1905209529 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.1905209529 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.566793525 |
| Short name | T750 |
| Test name | |
| Test status | |
| Simulation time | 83902594691 ps |
| CPU time | 300.41 seconds |
| Started | Aug 27 07:38:51 PM UTC 24 |
| Finished | Aug 27 07:43:56 PM UTC 24 |
| Peak memory | 210316 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=566793525 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_with_pre_cond.566793525 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.4007699227 |
| Short name | T718 |
| Test name | |
| Test status | |
| Simulation time | 3696344334 ps |
| CPU time | 10.72 seconds |
| Started | Aug 27 07:38:48 PM UTC 24 |
| Finished | Aug 27 07:39:00 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4007699227 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.4007699227 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.2250342827 |
| Short name | T228 |
| Test name | |
| Test status | |
| Simulation time | 4455812862 ps |
| CPU time | 3.94 seconds |
| Started | Aug 27 07:38:49 PM UTC 24 |
| Finished | Aug 27 07:38:55 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250342827 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.2250342827 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.383960675 |
| Short name | T708 |
| Test name | |
| Test status | |
| Simulation time | 2655156292 ps |
| CPU time | 1.99 seconds |
| Started | Aug 27 07:38:48 PM UTC 24 |
| Finished | Aug 27 07:38:51 PM UTC 24 |
| Peak memory | 208192 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=383960675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.383960675 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.4283137499 |
| Short name | T707 |
| Test name | |
| Test status | |
| Simulation time | 2492451383 ps |
| CPU time | 2.6 seconds |
| Started | Aug 27 07:38:46 PM UTC 24 |
| Finished | Aug 27 07:38:50 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4283137499 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.4283137499 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.4083250219 |
| Short name | T706 |
| Test name | |
| Test status | |
| Simulation time | 2069369143 ps |
| CPU time | 2.45 seconds |
| Started | Aug 27 07:38:46 PM UTC 24 |
| Finished | Aug 27 07:38:50 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4083250219 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.4083250219 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.1371882358 |
| Short name | T712 |
| Test name | |
| Test status | |
| Simulation time | 2521622247 ps |
| CPU time | 5.4 seconds |
| Started | Aug 27 07:38:46 PM UTC 24 |
| Finished | Aug 27 07:38:53 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1371882358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.1371882358 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.3652766353 |
| Short name | T709 |
| Test name | |
| Test status | |
| Simulation time | 2118846115 ps |
| CPU time | 4.39 seconds |
| Started | Aug 27 07:38:46 PM UTC 24 |
| Finished | Aug 27 07:38:52 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652766353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.3652766353 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.1742543609 |
| Short name | T719 |
| Test name | |
| Test status | |
| Simulation time | 8668087641 ps |
| CPU time | 12.74 seconds |
| Started | Aug 27 07:38:51 PM UTC 24 |
| Finished | Aug 27 07:39:05 PM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1742543609 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.1742543609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.2514219095 |
| Short name | T300 |
| Test name | |
| Test status | |
| Simulation time | 2558548052 ps |
| CPU time | 11.12 seconds |
| Started | Aug 27 07:38:51 PM UTC 24 |
| Finished | Aug 27 07:39:03 PM UTC 24 |
| Peak memory | 210080 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=2514219095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.2514219095 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.3825985299 |
| Short name | T716 |
| Test name | |
| Test status | |
| Simulation time | 6898453751 ps |
| CPU time | 7.72 seconds |
| Started | Aug 27 07:38:48 PM UTC 24 |
| Finished | Aug 27 07:38:57 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3825985299 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.3825985299 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.20047779 |
| Short name | T156 |
| Test name | |
| Test status | |
| Simulation time | 2014669106 ps |
| CPU time | 6.22 seconds |
| Started | Aug 27 07:28:41 PM UTC 24 |
| Finished | Aug 27 07:28:48 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=20047779 -assert nopostproc +UVM_TESTNAME= sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr ession_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.20047779 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.320863336 |
| Short name | T67 |
| Test name | |
| Test status | |
| Simulation time | 3684881742 ps |
| CPU time | 4.46 seconds |
| Started | Aug 27 07:28:22 PM UTC 24 |
| Finished | Aug 27 07:28:27 PM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=320863336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_ 08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.320863336 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.1380053217 |
| Short name | T271 |
| Test name | |
| Test status | |
| Simulation time | 185461755855 ps |
| CPU time | 155.08 seconds |
| Started | Aug 27 07:28:25 PM UTC 24 |
| Finished | Aug 27 07:31:03 PM UTC 24 |
| Peak memory | 210308 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1380053217 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.1380053217 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1528840723 |
| Short name | T41 |
| Test name | |
| Test status | |
| Simulation time | 44766618102 ps |
| CPU time | 39.73 seconds |
| Started | Aug 27 07:28:28 PM UTC 24 |
| Finished | Aug 27 07:29:10 PM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528840723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_with_pre_cond.1528840723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.2600509925 |
| Short name | T154 |
| Test name | |
| Test status | |
| Simulation time | 4427634105 ps |
| CPU time | 21.98 seconds |
| Started | Aug 27 07:28:17 PM UTC 24 |
| Finished | Aug 27 07:28:40 PM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2600509925 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.2600509925 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.175400241 |
| Short name | T46 |
| Test name | |
| Test status | |
| Simulation time | 4040859448 ps |
| CPU time | 16.08 seconds |
| Started | Aug 27 07:28:27 PM UTC 24 |
| Finished | Aug 27 07:28:45 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=175400241 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.175400241 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.2104682390 |
| Short name | T308 |
| Test name | |
| Test status | |
| Simulation time | 2616147343 ps |
| CPU time | 7.99 seconds |
| Started | Aug 27 07:28:14 PM UTC 24 |
| Finished | Aug 27 07:28:23 PM UTC 24 |
| Peak memory | 210208 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2104682390 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.2104682390 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3573320062 |
| Short name | T80 |
| Test name | |
| Test status | |
| Simulation time | 2480756439 ps |
| CPU time | 4.34 seconds |
| Started | Aug 27 07:28:11 PM UTC 24 |
| Finished | Aug 27 07:28:16 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573320062 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.3573320062 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.3187525331 |
| Short name | T309 |
| Test name | |
| Test status | |
| Simulation time | 2080919857 ps |
| CPU time | 12.04 seconds |
| Started | Aug 27 07:28:11 PM UTC 24 |
| Finished | Aug 27 07:28:24 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3187525331 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.3187525331 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.2491565105 |
| Short name | T88 |
| Test name | |
| Test status | |
| Simulation time | 2511481094 ps |
| CPU time | 14.03 seconds |
| Started | Aug 27 07:28:11 PM UTC 24 |
| Finished | Aug 27 07:28:26 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491565105 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.2491565105 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.1245033001 |
| Short name | T95 |
| Test name | |
| Test status | |
| Simulation time | 2129618809 ps |
| CPU time | 3.75 seconds |
| Started | Aug 27 07:28:09 PM UTC 24 |
| Finished | Aug 27 07:28:13 PM UTC 24 |
| Peak memory | 209892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1245033001 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1245033001 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.106092067 |
| Short name | T68 |
| Test name | |
| Test status | |
| Simulation time | 7958399429 ps |
| CPU time | 2.77 seconds |
| Started | Aug 27 07:28:39 PM UTC 24 |
| Finished | Aug 27 07:28:42 PM UTC 24 |
| Peak memory | 210264 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=106092067 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.106092067 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.3160141738 |
| Short name | T287 |
| Test name | |
| Test status | |
| Simulation time | 9638976388 ps |
| CPU time | 24.66 seconds |
| Started | Aug 27 07:28:33 PM UTC 24 |
| Finished | Aug 27 07:28:59 PM UTC 24 |
| Peak memory | 220736 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=3160141738 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d ev/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.3160141738 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.1530524006 |
| Short name | T743 |
| Test name | |
| Test status | |
| Simulation time | 54610073579 ps |
| CPU time | 148.81 seconds |
| Started | Aug 27 07:38:53 PM UTC 24 |
| Finished | Aug 27 07:41:24 PM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1530524006 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_with_pre_cond.1530524006 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.210689257 |
| Short name | T384 |
| Test name | |
| Test status | |
| Simulation time | 86669203364 ps |
| CPU time | 288.94 seconds |
| Started | Aug 27 07:38:53 PM UTC 24 |
| Finished | Aug 27 07:43:46 PM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210689257 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_with_pre_cond.210689257 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2088895085 |
| Short name | T728 |
| Test name | |
| Test status | |
| Simulation time | 34448042043 ps |
| CPU time | 34.86 seconds |
| Started | Aug 27 07:38:54 PM UTC 24 |
| Finished | Aug 27 07:39:31 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088895085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_with_pre_cond.2088895085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1729446754 |
| Short name | T737 |
| Test name | |
| Test status | |
| Simulation time | 43769695243 ps |
| CPU time | 112.31 seconds |
| Started | Aug 27 07:38:54 PM UTC 24 |
| Finished | Aug 27 07:40:49 PM UTC 24 |
| Peak memory | 210248 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729446754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_with_pre_cond.1729446754 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.267655469 |
| Short name | T722 |
| Test name | |
| Test status | |
| Simulation time | 28101583645 ps |
| CPU time | 27.76 seconds |
| Started | Aug 27 07:38:54 PM UTC 24 |
| Finished | Aug 27 07:39:23 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=267655469 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_with_pre_cond.267655469 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2125367386 |
| Short name | T721 |
| Test name | |
| Test status | |
| Simulation time | 22601527561 ps |
| CPU time | 23.67 seconds |
| Started | Aug 27 07:38:57 PM UTC 24 |
| Finished | Aug 27 07:39:22 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2125367386 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_with_pre_cond.2125367386 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2155562235 |
| Short name | T354 |
| Test name | |
| Test status | |
| Simulation time | 91057592697 ps |
| CPU time | 83.54 seconds |
| Started | Aug 27 07:38:57 PM UTC 24 |
| Finished | Aug 27 07:40:22 PM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2155562235 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_with_pre_cond.2155562235 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.3649219817 |
| Short name | T735 |
| Test name | |
| Test status | |
| Simulation time | 27833477721 ps |
| CPU time | 92.95 seconds |
| Started | Aug 27 07:38:58 PM UTC 24 |
| Finished | Aug 27 07:40:33 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3649219817 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_with_pre_cond.3649219817 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/59.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.3089456031 |
| Short name | T288 |
| Test name | |
| Test status | |
| Simulation time | 2017850097 ps |
| CPU time | 6.48 seconds |
| Started | Aug 27 07:28:52 PM UTC 24 |
| Finished | Aug 27 07:29:00 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3089456031 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.3089456031 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3106873609 |
| Short name | T69 |
| Test name | |
| Test status | |
| Simulation time | 3324514436 ps |
| CPU time | 5.09 seconds |
| Started | Aug 27 07:28:47 PM UTC 24 |
| Finished | Aug 27 07:28:54 PM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3106873609 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.3106873609 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.1119819632 |
| Short name | T117 |
| Test name | |
| Test status | |
| Simulation time | 102871527500 ps |
| CPU time | 98.79 seconds |
| Started | Aug 27 07:28:50 PM UTC 24 |
| Finished | Aug 27 07:30:31 PM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1119819632 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.1119819632 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.1778755559 |
| Short name | T199 |
| Test name | |
| Test status | |
| Simulation time | 3969280234 ps |
| CPU time | 3.9 seconds |
| Started | Aug 27 07:28:45 PM UTC 24 |
| Finished | Aug 27 07:28:50 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1778755559 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.1778755559 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.1326569998 |
| Short name | T49 |
| Test name | |
| Test status | |
| Simulation time | 4284126115 ps |
| CPU time | 11.77 seconds |
| Started | Aug 27 07:28:50 PM UTC 24 |
| Finished | Aug 27 07:29:03 PM UTC 24 |
| Peak memory | 209868 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1326569998 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.1326569998 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.3396744239 |
| Short name | T198 |
| Test name | |
| Test status | |
| Simulation time | 2618717561 ps |
| CPU time | 3.18 seconds |
| Started | Aug 27 07:28:44 PM UTC 24 |
| Finished | Aug 27 07:28:49 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3396744239 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.3396744239 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.3678306752 |
| Short name | T81 |
| Test name | |
| Test status | |
| Simulation time | 2496219121 ps |
| CPU time | 4.48 seconds |
| Started | Aug 27 07:28:43 PM UTC 24 |
| Finished | Aug 27 07:28:49 PM UTC 24 |
| Peak memory | 210272 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3678306752 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.3678306752 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.4033521692 |
| Short name | T197 |
| Test name | |
| Test status | |
| Simulation time | 2098968476 ps |
| CPU time | 4.08 seconds |
| Started | Aug 27 07:28:43 PM UTC 24 |
| Finished | Aug 27 07:28:48 PM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4033521692 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.4033521692 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.2987215750 |
| Short name | T284 |
| Test name | |
| Test status | |
| Simulation time | 2511545218 ps |
| CPU time | 10.18 seconds |
| Started | Aug 27 07:28:44 PM UTC 24 |
| Finished | Aug 27 07:28:56 PM UTC 24 |
| Peak memory | 209960 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2987215750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.2987215750 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.3551251490 |
| Short name | T155 |
| Test name | |
| Test status | |
| Simulation time | 2124202632 ps |
| CPU time | 4.11 seconds |
| Started | Aug 27 07:28:42 PM UTC 24 |
| Finished | Aug 27 07:28:47 PM UTC 24 |
| Peak memory | 209892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3551251490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3551251490 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.3068140290 |
| Short name | T76 |
| Test name | |
| Test status | |
| Simulation time | 7667860892 ps |
| CPU time | 13.96 seconds |
| Started | Aug 27 07:28:49 PM UTC 24 |
| Finished | Aug 27 07:29:04 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3068140290 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.3068140290 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.3837893458 |
| Short name | T358 |
| Test name | |
| Test status | |
| Simulation time | 175183461986 ps |
| CPU time | 155.86 seconds |
| Started | Aug 27 07:39:00 PM UTC 24 |
| Finished | Aug 27 07:41:38 PM UTC 24 |
| Peak memory | 210568 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3837893458 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 61.sysrst_ctrl_combo_detect_with_pre_cond.3837893458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/61.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.1669625097 |
| Short name | T357 |
| Test name | |
| Test status | |
| Simulation time | 73707618190 ps |
| CPU time | 22.98 seconds |
| Started | Aug 27 07:39:01 PM UTC 24 |
| Finished | Aug 27 07:39:25 PM UTC 24 |
| Peak memory | 210268 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1669625097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_with_pre_cond.1669625097 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.1316739417 |
| Short name | T727 |
| Test name | |
| Test status | |
| Simulation time | 29865498169 ps |
| CPU time | 22.27 seconds |
| Started | Aug 27 07:39:04 PM UTC 24 |
| Finished | Aug 27 07:39:28 PM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1316739417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_with_pre_cond.1316739417 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.536268023 |
| Short name | T731 |
| Test name | |
| Test status | |
| Simulation time | 81900430784 ps |
| CPU time | 59.56 seconds |
| Started | Aug 27 07:39:04 PM UTC 24 |
| Finished | Aug 27 07:40:06 PM UTC 24 |
| Peak memory | 210584 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=536268023 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_with_pre_cond.536268023 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.1369069369 |
| Short name | T360 |
| Test name | |
| Test status | |
| Simulation time | 65254794132 ps |
| CPU time | 200.81 seconds |
| Started | Aug 27 07:39:06 PM UTC 24 |
| Finished | Aug 27 07:42:31 PM UTC 24 |
| Peak memory | 210376 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1369069369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_with_pre_cond.1369069369 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.1087812206 |
| Short name | T697 |
| Test name | |
| Test status | |
| Simulation time | 26581523425 ps |
| CPU time | 121.93 seconds |
| Started | Aug 27 07:39:09 PM UTC 24 |
| Finished | Aug 27 07:41:13 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1087812206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_with_pre_cond.1087812206 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3941590316 |
| Short name | T373 |
| Test name | |
| Test status | |
| Simulation time | 114710607621 ps |
| CPU time | 138.74 seconds |
| Started | Aug 27 07:39:19 PM UTC 24 |
| Finished | Aug 27 07:41:40 PM UTC 24 |
| Peak memory | 210576 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3941590316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_with_pre_cond.3941590316 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.3712809448 |
| Short name | T739 |
| Test name | |
| Test status | |
| Simulation time | 119259540477 ps |
| CPU time | 101.25 seconds |
| Started | Aug 27 07:39:19 PM UTC 24 |
| Finished | Aug 27 07:41:02 PM UTC 24 |
| Peak memory | 210632 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3712809448 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_with_pre_cond.3712809448 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/68.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.2070453517 |
| Short name | T400 |
| Test name | |
| Test status | |
| Simulation time | 2012559175 ps |
| CPU time | 10.78 seconds |
| Started | Aug 27 07:29:10 PM UTC 24 |
| Finished | Aug 27 07:29:22 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2070453517 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.2070453517 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.4290441085 |
| Short name | T70 |
| Test name | |
| Test status | |
| Simulation time | 4074968597 ps |
| CPU time | 14.4 seconds |
| Started | Aug 27 07:29:03 PM UTC 24 |
| Finished | Aug 27 07:29:18 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4290441085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.4290441085 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.292009781 |
| Short name | T90 |
| Test name | |
| Test status | |
| Simulation time | 27603876180 ps |
| CPU time | 32.52 seconds |
| Started | Aug 27 07:29:05 PM UTC 24 |
| Finished | Aug 27 07:29:39 PM UTC 24 |
| Peak memory | 210260 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=292009781 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_with_pre_cond.292009781 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2660887630 |
| Short name | T398 |
| Test name | |
| Test status | |
| Simulation time | 3066198195 ps |
| CPU time | 18.08 seconds |
| Started | Aug 27 07:29:01 PM UTC 24 |
| Finished | Aug 27 07:29:20 PM UTC 24 |
| Peak memory | 210204 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2660887630 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.2660887630 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.186366063 |
| Short name | T47 |
| Test name | |
| Test status | |
| Simulation time | 4435615857 ps |
| CPU time | 11.07 seconds |
| Started | Aug 27 07:29:05 PM UTC 24 |
| Finished | Aug 27 07:29:17 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=186366063 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr atch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.186366063 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3495352835 |
| Short name | T289 |
| Test name | |
| Test status | |
| Simulation time | 2653438788 ps |
| CPU time | 2.31 seconds |
| Started | Aug 27 07:29:01 PM UTC 24 |
| Finished | Aug 27 07:29:04 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3495352835 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.3495352835 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.3399274723 |
| Short name | T82 |
| Test name | |
| Test status | |
| Simulation time | 2490418888 ps |
| CPU time | 4.25 seconds |
| Started | Aug 27 07:28:56 PM UTC 24 |
| Finished | Aug 27 07:29:02 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3399274723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.3399274723 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.240312159 |
| Short name | T301 |
| Test name | |
| Test status | |
| Simulation time | 2121535885 ps |
| CPU time | 5.71 seconds |
| Started | Aug 27 07:28:59 PM UTC 24 |
| Finished | Aug 27 07:29:06 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=240312159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sys rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.240312159 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.3996326534 |
| Short name | T325 |
| Test name | |
| Test status | |
| Simulation time | 2513284599 ps |
| CPU time | 11.83 seconds |
| Started | Aug 27 07:28:59 PM UTC 24 |
| Finished | Aug 27 07:29:12 PM UTC 24 |
| Peak memory | 210152 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3996326534 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.3996326534 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.1128692094 |
| Short name | T286 |
| Test name | |
| Test status | |
| Simulation time | 2141337520 ps |
| CPU time | 2.66 seconds |
| Started | Aug 27 07:28:55 PM UTC 24 |
| Finished | Aug 27 07:28:59 PM UTC 24 |
| Peak memory | 209892 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1128692094 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.1128692094 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.3112700310 |
| Short name | T77 |
| Test name | |
| Test status | |
| Simulation time | 4993532148 ps |
| CPU time | 7.45 seconds |
| Started | Aug 27 07:29:04 PM UTC 24 |
| Finished | Aug 27 07:29:12 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3112700310 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.3112700310 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3196977011 |
| Short name | T359 |
| Test name | |
| Test status | |
| Simulation time | 57212887422 ps |
| CPU time | 111.39 seconds |
| Started | Aug 27 07:39:26 PM UTC 24 |
| Finished | Aug 27 07:41:19 PM UTC 24 |
| Peak memory | 209888 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196977011 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_with_pre_cond.3196977011 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/72.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.1174763790 |
| Short name | T730 |
| Test name | |
| Test status | |
| Simulation time | 22339778554 ps |
| CPU time | 32.28 seconds |
| Started | Aug 27 07:39:28 PM UTC 24 |
| Finished | Aug 27 07:40:01 PM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1174763790 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_with_pre_cond.1174763790 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.2053260664 |
| Short name | T732 |
| Test name | |
| Test status | |
| Simulation time | 19582678468 ps |
| CPU time | 28.12 seconds |
| Started | Aug 27 07:39:40 PM UTC 24 |
| Finished | Aug 27 07:40:10 PM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2053260664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_with_pre_cond.2053260664 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.3736105240 |
| Short name | T404 |
| Test name | |
| Test status | |
| Simulation time | 2013541829 ps |
| CPU time | 12.15 seconds |
| Started | Aug 27 07:29:27 PM UTC 24 |
| Finished | Aug 27 07:29:40 PM UTC 24 |
| Peak memory | 209880 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3736105240 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.3736105240 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.1142840746 |
| Short name | T130 |
| Test name | |
| Test status | |
| Simulation time | 3544776893 ps |
| CPU time | 6.77 seconds |
| Started | Aug 27 07:29:19 PM UTC 24 |
| Finished | Aug 27 07:29:27 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1142840746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.1142840746 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.1589954367 |
| Short name | T109 |
| Test name | |
| Test status | |
| Simulation time | 63370493703 ps |
| CPU time | 46.88 seconds |
| Started | Aug 27 07:29:20 PM UTC 24 |
| Finished | Aug 27 07:30:08 PM UTC 24 |
| Peak memory | 210504 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1589954367 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.1589954367 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.1465250177 |
| Short name | T92 |
| Test name | |
| Test status | |
| Simulation time | 25830065403 ps |
| CPU time | 98.7 seconds |
| Started | Aug 27 07:29:23 PM UTC 24 |
| Finished | Aug 27 07:31:04 PM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1465250177 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_with_pre_cond.1465250177 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.2975878274 |
| Short name | T128 |
| Test name | |
| Test status | |
| Simulation time | 5202863314 ps |
| CPU time | 3.95 seconds |
| Started | Aug 27 07:29:19 PM UTC 24 |
| Finished | Aug 27 07:29:24 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2975878274 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.2975878274 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.3814838991 |
| Short name | T45 |
| Test name | |
| Test status | |
| Simulation time | 4655688350 ps |
| CPU time | 7.2 seconds |
| Started | Aug 27 07:29:22 PM UTC 24 |
| Finished | Aug 27 07:29:31 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3814838991 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.3814838991 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1428468315 |
| Short name | T131 |
| Test name | |
| Test status | |
| Simulation time | 2611812746 ps |
| CPU time | 8.68 seconds |
| Started | Aug 27 07:29:18 PM UTC 24 |
| Finished | Aug 27 07:29:28 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1428468315 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.1428468315 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.2799134373 |
| Short name | T397 |
| Test name | |
| Test status | |
| Simulation time | 2469499695 ps |
| CPU time | 4 seconds |
| Started | Aug 27 07:29:13 PM UTC 24 |
| Finished | Aug 27 07:29:18 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2799134373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.2799134373 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.63738492 |
| Short name | T399 |
| Test name | |
| Test status | |
| Simulation time | 2052578753 ps |
| CPU time | 6.92 seconds |
| Started | Aug 27 07:29:14 PM UTC 24 |
| Finished | Aug 27 07:29:21 PM UTC 24 |
| Peak memory | 210140 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=63738492 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM _TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysr st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.63738492 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.1317421885 |
| Short name | T129 |
| Test name | |
| Test status | |
| Simulation time | 2512303612 ps |
| CPU time | 9.83 seconds |
| Started | Aug 27 07:29:15 PM UTC 24 |
| Finished | Aug 27 07:29:26 PM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1317421885 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.1317421885 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.636799766 |
| Short name | T396 |
| Test name | |
| Test status | |
| Simulation time | 2135316507 ps |
| CPU time | 3.71 seconds |
| Started | Aug 27 07:29:13 PM UTC 24 |
| Finished | Aug 27 07:29:18 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636799766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_c trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.636799766 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.2142621792 |
| Short name | T393 |
| Test name | |
| Test status | |
| Simulation time | 9479598233 ps |
| CPU time | 14.13 seconds |
| Started | Aug 27 07:29:25 PM UTC 24 |
| Finished | Aug 27 07:29:40 PM UTC 24 |
| Peak memory | 209872 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2142621792 -assert nopostproc +UVM_TEST NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc h/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.2142621792 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.209576927 |
| Short name | T310 |
| Test name | |
| Test status | |
| Simulation time | 5005699561 ps |
| CPU time | 25.09 seconds |
| Started | Aug 27 07:29:25 PM UTC 24 |
| Finished | Aug 27 07:29:51 PM UTC 24 |
| Peak memory | 210340 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d v/tools/sim.tcl +ntb_random_seed=209576927 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de v/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.209576927 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.3270933458 |
| Short name | T74 |
| Test name | |
| Test status | |
| Simulation time | 9662522407 ps |
| CPU time | 5.63 seconds |
| Started | Aug 27 07:29:19 PM UTC 24 |
| Finished | Aug 27 07:29:26 PM UTC 24 |
| Peak memory | 209948 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3270933458 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.3270933458 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.4293478196 |
| Short name | T733 |
| Test name | |
| Test status | |
| Simulation time | 24130734382 ps |
| CPU time | 8.86 seconds |
| Started | Aug 27 07:40:00 PM UTC 24 |
| Finished | Aug 27 07:40:10 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4293478196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_with_pre_cond.4293478196 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/82.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.1310888657 |
| Short name | T726 |
| Test name | |
| Test status | |
| Simulation time | 22828406659 ps |
| CPU time | 75.19 seconds |
| Started | Aug 27 07:40:03 PM UTC 24 |
| Finished | Aug 27 07:41:19 PM UTC 24 |
| Peak memory | 210512 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1310888657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_with_pre_cond.1310888657 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.1581474113 |
| Short name | T736 |
| Test name | |
| Test status | |
| Simulation time | 102859945463 ps |
| CPU time | 35.22 seconds |
| Started | Aug 27 07:40:04 PM UTC 24 |
| Finished | Aug 27 07:40:40 PM UTC 24 |
| Peak memory | 210236 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1581474113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_with_pre_cond.1581474113 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3840907040 |
| Short name | T741 |
| Test name | |
| Test status | |
| Simulation time | 50214733795 ps |
| CPU time | 58.91 seconds |
| Started | Aug 27 07:40:06 PM UTC 24 |
| Finished | Aug 27 07:41:07 PM UTC 24 |
| Peak memory | 210180 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3840907040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_with_pre_cond.3840907040 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.4119237423 |
| Short name | T377 |
| Test name | |
| Test status | |
| Simulation time | 78850827924 ps |
| CPU time | 52.83 seconds |
| Started | Aug 27 07:40:12 PM UTC 24 |
| Finished | Aug 27 07:41:06 PM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4119237423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_with_pre_cond.4119237423 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/88.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.1283944707 |
| Short name | T276 |
| Test name | |
| Test status | |
| Simulation time | 33604079581 ps |
| CPU time | 45.79 seconds |
| Started | Aug 27 07:40:19 PM UTC 24 |
| Finished | Aug 27 07:41:07 PM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1283944707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_with_pre_cond.1283944707 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_alert_test.3046243788 |
| Short name | T134 |
| Test name | |
| Test status | |
| Simulation time | 2012878304 ps |
| CPU time | 12.21 seconds |
| Started | Aug 27 07:29:41 PM UTC 24 |
| Finished | Aug 27 07:29:54 PM UTC 24 |
| Peak memory | 209856 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046243788 -assert nopostproc +UVM_TESTNAM E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re gression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_alert_test.3046243788 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_alert_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2114946216 |
| Short name | T406 |
| Test name | |
| Test status | |
| Simulation time | 3213727072 ps |
| CPU time | 9.25 seconds |
| Started | Aug 27 07:29:31 PM UTC 24 |
| Finished | Aug 27 07:29:42 PM UTC 24 |
| Peak memory | 209940 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2114946216 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024 _08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.2114946216 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_auto_blk_key_output/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.3280246785 |
| Short name | T43 |
| Test name | |
| Test status | |
| Simulation time | 96758465175 ps |
| CPU time | 43.74 seconds |
| Started | Aug 27 07:29:35 PM UTC 24 |
| Finished | Aug 27 07:30:20 PM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3280246785 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.3280246785 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.596419158 |
| Short name | T321 |
| Test name | |
| Test status | |
| Simulation time | 2895057707 ps |
| CPU time | 2.12 seconds |
| Started | Aug 27 07:29:31 PM UTC 24 |
| Finished | Aug 27 07:29:34 PM UTC 24 |
| Peak memory | 210200 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=596419158 -assert nopostproc +UVM_TE STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s cratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.596419158 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ec_pwr_on_rst/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.3724771708 |
| Short name | T170 |
| Test name | |
| Test status | |
| Simulation time | 4232823438 ps |
| CPU time | 15.24 seconds |
| Started | Aug 27 07:29:35 PM UTC 24 |
| Finished | Aug 27 07:29:51 PM UTC 24 |
| Peak memory | 209944 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3724771708 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc ratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.3724771708 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1491642471 |
| Short name | T402 |
| Test name | |
| Test status | |
| Simulation time | 2671074934 ps |
| CPU time | 2.51 seconds |
| Started | Aug 27 07:29:30 PM UTC 24 |
| Finished | Aug 27 07:29:34 PM UTC 24 |
| Peak memory | 209876 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1491642471 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26 /sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.1491642471 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_flash_wr_prot_out/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.4080450368 |
| Short name | T401 |
| Test name | |
| Test status | |
| Simulation time | 2461525510 ps |
| CPU time | 4.28 seconds |
| Started | Aug 27 07:29:28 PM UTC 24 |
| Finished | Aug 27 07:29:33 PM UTC 24 |
| Peak memory | 209952 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4080450368 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_ 26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.4080450368 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_in_out_inverted/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.1575978763 |
| Short name | T405 |
| Test name | |
| Test status | |
| Simulation time | 2068899619 ps |
| CPU time | 11.49 seconds |
| Started | Aug 27 07:29:29 PM UTC 24 |
| Finished | Aug 27 07:29:42 PM UTC 24 |
| Peak memory | 209884 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1575978763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sy srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.1575978763 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_access_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.1384876877 |
| Short name | T394 |
| Test name | |
| Test status | |
| Simulation time | 2522436356 ps |
| CPU time | 4.04 seconds |
| Started | Aug 27 07:29:29 PM UTC 24 |
| Finished | Aug 27 07:29:34 PM UTC 24 |
| Peak memory | 210024 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1384876877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/ sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.1384876877 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_override_test/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.2709857456 |
| Short name | T132 |
| Test name | |
| Test status | |
| Simulation time | 2143662143 ps |
| CPU time | 1.32 seconds |
| Started | Aug 27 07:29:27 PM UTC 24 |
| Finished | Aug 27 07:29:29 PM UTC 24 |
| Peak memory | 208188 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2709857456 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.2709857456 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_smoke/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all.503356112 |
| Short name | T158 |
| Test name | |
| Test status | |
| Simulation time | 83804018270 ps |
| CPU time | 123.81 seconds |
| Started | Aug 27 07:29:40 PM UTC 24 |
| Finished | Aug 27 07:31:46 PM UTC 24 |
| Peak memory | 210008 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO _RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=503356112 -assert nopostproc +UVM_TESTN AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch /os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_stress_all.503356112 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.1553539108 |
| Short name | T403 |
| Test name | |
| Test status | |
| Simulation time | 5602564126 ps |
| CPU time | 1.61 seconds |
| Started | Aug 27 07:29:34 PM UTC 24 |
| Finished | Aug 27 07:29:37 PM UTC 24 |
| Peak memory | 208148 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM _NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1553539108 -assert nopostproc +UVM_T ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/ scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.1553539108 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.1775636672 |
| Short name | T749 |
| Test name | |
| Test status | |
| Simulation time | 75085780645 ps |
| CPU time | 167.92 seconds |
| Started | Aug 27 07:40:21 PM UTC 24 |
| Finished | Aug 27 07:43:12 PM UTC 24 |
| Peak memory | 210244 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1775636672 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_with_pre_cond.1775636672 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/90.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.2637888971 |
| Short name | T740 |
| Test name | |
| Test status | |
| Simulation time | 25586726945 ps |
| CPU time | 36.43 seconds |
| Started | Aug 27 07:40:29 PM UTC 24 |
| Finished | Aug 27 07:41:07 PM UTC 24 |
| Peak memory | 210252 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2637888971 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_with_pre_cond.2637888971 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/93.sysrst_ctrl_combo_detect_with_pre_cond.614625467 |
| Short name | T364 |
| Test name | |
| Test status | |
| Simulation time | 129518455042 ps |
| CPU time | 439.36 seconds |
| Started | Aug 27 07:40:32 PM UTC 24 |
| Finished | Aug 27 07:47:57 PM UTC 24 |
| Peak memory | 210516 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=614625467 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 93.sysrst_ctrl_combo_detect_with_pre_cond.614625467 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/93.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.3321038477 |
| Short name | T266 |
| Test name | |
| Test status | |
| Simulation time | 65948785076 ps |
| CPU time | 186.55 seconds |
| Started | Aug 27 07:40:34 PM UTC 24 |
| Finished | Aug 27 07:43:44 PM UTC 24 |
| Peak memory | 210324 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3321038477 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_with_pre_cond.3321038477 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/94.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.748564021 |
| Short name | T745 |
| Test name | |
| Test status | |
| Simulation time | 94530186011 ps |
| CPU time | 81.34 seconds |
| Started | Aug 27 07:40:39 PM UTC 24 |
| Finished | Aug 27 07:42:03 PM UTC 24 |
| Peak memory | 210184 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748564021 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio n_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_with_pre_cond.748564021 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2796315857 |
| Short name | T751 |
| Test name | |
| Test status | |
| Simulation time | 61157665972 ps |
| CPU time | 191.85 seconds |
| Started | Aug 27 07:40:42 PM UTC 24 |
| Finished | Aug 27 07:43:56 PM UTC 24 |
| Peak memory | 210256 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2796315857 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_with_pre_cond.2796315857 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.1922298656 |
| Short name | T291 |
| Test name | |
| Test status | |
| Simulation time | 98988070994 ps |
| CPU time | 91.87 seconds |
| Started | Aug 27 07:40:50 PM UTC 24 |
| Finished | Aug 27 07:42:24 PM UTC 24 |
| Peak memory | 210580 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1922298656 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_with_pre_cond.1922298656 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest |
| Test location | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.1990220914 |
| Short name | T362 |
| Test name | |
| Test status | |
| Simulation time | 67136615411 ps |
| CPU time | 129.27 seconds |
| Started | Aug 27 07:40:56 PM UTC 24 |
| Finished | Aug 27 07:43:08 PM UTC 24 |
| Peak memory | 210240 kb |
| Host | riverbear.c.edafarm-workstations-prod.internal |
| User | miguelosorio |
| Command | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_ LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1990220914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi on_2024_08_26/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_with_pre_cond.1990220914 |
| Directory | /workspaces/repo/scratch/os_regression_2024_08_26/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest |
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