Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	100.00	90.91		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	100.00	90.91		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.87	91.30	90.91		83.33	90.48	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.87	91.30	90.91		83.33	90.48	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T5 T6 T19 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T16 T32 T64 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T16 T31 T32 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T16 T31 T32 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T16 T32 T64 
149        1/1                    cnt_en = 1'b1;
           Tests:       T16 T32 T64 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T16 T32 T64 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T16 T32 T64 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T16 T32 T64 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T32 T64 
167        1/1                    if (trigger_active) begin
           Tests:       T16 T32 T64 
168        1/1                      state_d = DetectSt;
           Tests:       T16 T32 T64 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T64 T67 T169 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T16 T32 T64 
182        1/1                  cnt_en = 1'b1;
           Tests:       T16 T32 T64 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T16 T32 T64 
186        1/1                    state_d = IdleSt;
           Tests:       T136 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T136 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T16 T32 T64 
191        1/1                      state_d = StableSt;
           Tests:       T16 T32 T64 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T16 T32 T64 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T16 T32 T64 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T16 T32 T64 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T16 T32 T64 
206        1/1                    state_d = IdleSt;
           Tests:       T16 T32 T64 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T16 T32 T64 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T16,T32,T64

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T16,T32,T64

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T16,T32,T64

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T16,T32,T64
1	0	Covered	T5,T6,T19
1	1	Covered	T16,T32,T64

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T16,T32,T64
0	1	Covered	T136
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T16,T32,T64
0	1	Covered	T16,T32,T64
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T16,T32,T64
1	-	Covered	T16,T32,T64

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T16,T32,T64
DetectSt	168	Covered	T16,T32,T64
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T16,T32,T64

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T16,T32,T64
DebounceSt->IdleSt	163	Covered	T64,T67,T35
DetectSt->IdleSt	186	Covered	T136
DetectSt->StableSt	191	Covered	T16,T32,T64
IdleSt->DebounceSt	148	Covered	T16,T32,T64
StableSt->IdleSt	206	Covered	T16,T32,T64

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T16,T32,T64
0	1	Covered	T16,T32,T64
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T16,T32,T64
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T16,T32,T64
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T16,T32,T64
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T67,T169
DebounceSt	-	0	0	-	-	-	-	Covered	T16,T32,T64
DetectSt	-	-	-	-	1	-	-	Covered	T136
DetectSt	-	-	-	-	0	1	-	Covered	T16,T32,T64
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T16,T32,T64
StableSt	-	-	-	-	-	-	0	Covered	T16,T32,T64
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	164	0	0
CntIncr_A	7444491	98986	0	0
CntNoWrap_A	7444491	6988020	0	0
DetectStDropOut_A	7444491	1	0	0
DetectedOut_A	7444491	504	0	0
DetectedPulseOut_A	7444491	75	0	0
DisabledIdleSt_A	7444491	6885375	0	0
DisabledNoDetection_A	7444491	6887240	0	0
EnterDebounceSt_A	7444491	91	0	0
EnterDetectSt_A	7444491	76	0	0
EnterStableSt_A	7444491	75	0	0
PulseIsPulse_A	7444491	75	0	0
StayInStableSt	7444491	429	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7444491	5272	0	0
gen_low_level_sva.LowLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	75	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	164	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T16	726	4	0	0
T17	404	0	0	0
T18	507	0	0	0
T27	496	0	0	0
T30	524	0	0	0
T32	0	4	0	0
T35	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	3	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T68	0	2	0	0
T69	0	4	0	0
T124	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	98986	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T16	726	141	0	0
T17	404	0	0	0
T18	507	0	0	0
T27	496	0	0	0
T30	524	0	0	0
T32	0	165	0	0
T35	0	21	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	90	0	0
T65	0	30	0	0
T66	0	52	0	0
T67	0	99	0	0
T68	0	98	0	0
T69	0	198	0	0
T124	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988020	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	1	0	0
T122	1245	0	0	0
T136	593	1	0	0
T137	14603	0	0	0
T152	664	0	0	0
T153	449	0	0	0
T154	13804	0	0	0
T155	2674	0	0	0
T156	734	0	0	0
T157	524	0	0	0
T158	334625	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	504	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T16	726	16	0	0
T17	404	0	0	0
T18	507	0	0	0
T27	496	0	0	0
T30	524	0	0	0
T32	0	18	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	5	0	0
T65	0	10	0	0
T66	0	9	0	0
T68	0	11	0	0
T69	0	10	0	0
T124	0	13	0	0
T160	0	3	0	0
T161	0	8	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	75	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T16	726	2	0	0
T17	404	0	0	0
T18	507	0	0	0
T27	496	0	0	0
T30	524	0	0	0
T32	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0
T124	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6885375	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6887240	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	91	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T16	726	2	0	0
T17	404	0	0	0
T18	507	0	0	0
T27	496	0	0	0
T30	524	0	0	0
T32	0	2	0	0
T35	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	2	0	0
T65	0	1	0	0
T66	0	1	0	0
T67	0	2	0	0
T68	0	1	0	0
T69	0	2	0	0
T124	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	76	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T16	726	2	0	0
T17	404	0	0	0
T18	507	0	0	0
T27	496	0	0	0
T30	524	0	0	0
T32	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0
T124	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	75	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T16	726	2	0	0
T17	404	0	0	0
T18	507	0	0	0
T27	496	0	0	0
T30	524	0	0	0
T32	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0
T124	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	75	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T16	726	2	0	0
T17	404	0	0	0
T18	507	0	0	0
T27	496	0	0	0
T30	524	0	0	0
T32	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0
T124	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	429	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T16	726	14	0	0
T17	404	0	0	0
T18	507	0	0	0
T27	496	0	0	0
T30	524	0	0	0
T32	0	16	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	4	0	0
T65	0	9	0	0
T66	0	8	0	0
T68	0	10	0	0
T69	0	8	0	0
T124	0	12	0	0
T160	0	2	0	0
T161	0	7	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	5272	0	0
T1	865	2	0	0
T2	506	0	0	0
T5	429	2	0	0
T6	430	4	0	0
T7	0	1	0	0
T8	0	6	0	0
T14	426	1	0	0
T15	462	0	0	0
T16	726	3	0	0
T18	0	6	0	0
T19	505	5	0	0
T20	418	1	0	0
T21	406	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	75	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T16	726	2	0	0
T17	404	0	0	0
T18	507	0	0	0
T27	496	0	0	0
T30	524	0	0	0
T32	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	1	0	0
T65	0	1	0	0
T66	0	1	0	0
T68	0	1	0	0
T69	0	2	0	0
T124	0	1	0	0
T160	0	1	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T5 T6 T19 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T9 T10 T64 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T8 T9 T10 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T8 T9 T10 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T9 T10 T64 
149        1/1                    cnt_en = 1'b1;
           Tests:       T9 T10 T64 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T9 T10 T64 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T9 T10 T64 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T9 T10 T64 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T9 T10 T64 
167        1/1                    if (trigger_active) begin
           Tests:       T9 T10 T64 
168        1/1                      state_d = DetectSt;
           Tests:       T9 T10 T75 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T64 T108 T109 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T9 T10 T75 
182        1/1                  cnt_en = 1'b1;
           Tests:       T9 T10 T75 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T9 T10 T75 
186        1/1                    state_d = IdleSt;
           Tests:       T10 T109 T123 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T109 T123 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T9 T75 T70 
191        1/1                      state_d = StableSt;
           Tests:       T9 T75 T70 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T9 T75 T70 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T9 T75 T70 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T9 T75 T70 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T9 T75 T70 
206        1/1                    state_d = IdleSt;
           Tests:       T9 T75 T70 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T9 T75 T70 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T10,T64

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T10,T64

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T10,T75

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T5,T6,T19
1	1	Covered	T9,T10,T64

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T75,T70
0	1	Covered	T10,T109,T123
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T75,T70
0	1	Unreachable
1	0	Covered	T9,T75,T70

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T9,T10,T64
DetectSt	168	Covered	T9,T10,T75
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T9,T75,T70

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T9,T10,T75
DebounceSt->IdleSt	163	Covered	T64,T35,T53
DetectSt->IdleSt	186	Covered	T10,T109,T123
DetectSt->StableSt	191	Covered	T9,T75,T70
IdleSt->DebounceSt	148	Covered	T9,T10,T64
StableSt->IdleSt	206	Covered	T9,T75,T70

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T9,T10,T64
0	1	Covered	T9,T10,T64
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T9,T10,T75
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T9,T10,T64
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T9,T10,T75
DebounceSt	-	0	1	0	-	-	-	Covered	T64,T108,T109
DebounceSt	-	0	0	-	-	-	-	Covered	T9,T10,T64
DetectSt	-	-	-	-	1	-	-	Covered	T10,T109,T123
DetectSt	-	-	-	-	0	1	-	Covered	T9,T75,T70
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T9,T75,T70
StableSt	-	-	-	-	-	-	0	Covered	T9,T75,T70
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	100	0	0
CntIncr_A	7444491	206436	0	0
CntNoWrap_A	7444491	6988084	0	0
DetectStDropOut_A	7444491	12	0	0
DetectedOut_A	7444491	393122	0	0
DetectedPulseOut_A	7444491	24	0	0
DisabledIdleSt_A	7444491	5658788	0	0
DisabledNoDetection_A	7444491	5660687	0	0
EnterDebounceSt_A	7444491	64	0	0
EnterDetectSt_A	7444491	36	0	0
EnterStableSt_A	7444491	24	0	0
PulseIsPulse_A	7444491	24	0	0
StayInStableSt	7444491	393098	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7444491	5272	0	0
gen_low_level_sva.LowLevelEvent_A	7444491	6990083	0	0
gen_sticky_sva.StableStDropOut_A	7444491	581382	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	100	0	0
T9	571	2	0	0
T10	1319	2	0	0
T11	630	0	0	0
T12	480	0	0	0
T29	492	0	0	0
T35	0	2	0	0
T53	0	2	0	0
T64	0	3	0	0
T70	0	2	0	0
T75	0	2	0	0
T76	0	4	0	0
T77	0	2	0	0
T95	408	0	0	0
T96	522	0	0	0
T108	0	1	0	0
T166	404	0	0	0
T167	422	0	0	0
T170	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	206436	0	0
T9	571	69	0	0
T10	1319	57	0	0
T11	630	0	0	0
T12	480	0	0	0
T29	492	0	0	0
T35	0	76	0	0
T53	0	30	0	0
T64	0	147	0	0
T70	0	40	0	0
T75	0	68	0	0
T76	0	28	0	0
T77	0	36	0	0
T95	408	0	0	0
T96	522	0	0	0
T108	0	51	0	0
T166	404	0	0	0
T167	422	0	0	0
T170	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988084	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	12	0	0
T10	1319	1	0	0
T11	630	0	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T87	487	0	0	0
T96	522	0	0	0
T109	0	2	0	0
T123	0	1	0	0
T163	0	1	0	0
T164	0	4	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0
T171	0	1	0	0
T172	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	393122	0	0
T9	571	1	0	0
T10	1319	0	0	0
T11	630	0	0	0
T12	480	0	0	0
T29	492	0	0	0
T70	0	20	0	0
T75	0	365	0	0
T76	0	45	0	0
T77	0	106	0	0
T95	408	0	0	0
T96	522	0	0	0
T110	0	254	0	0
T121	0	104	0	0
T163	0	41	0	0
T164	0	44	0	0
T165	0	406	0	0
T166	404	0	0	0
T167	422	0	0	0
T170	402	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	24	0	0
T9	571	1	0	0
T10	1319	0	0	0
T11	630	0	0	0
T12	480	0	0	0
T29	492	0	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T95	408	0	0	0
T96	522	0	0	0
T110	0	1	0	0
T121	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	2	0	0
T166	404	0	0	0
T167	422	0	0	0
T170	402	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	5658788	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	5660687	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	64	0	0
T9	571	1	0	0
T10	1319	1	0	0
T11	630	0	0	0
T12	480	0	0	0
T29	492	0	0	0
T35	0	2	0	0
T53	0	2	0	0
T64	0	3	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T95	408	0	0	0
T96	522	0	0	0
T108	0	1	0	0
T166	404	0	0	0
T167	422	0	0	0
T170	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	36	0	0
T9	571	1	0	0
T10	1319	1	0	0
T11	630	0	0	0
T12	480	0	0	0
T29	492	0	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T95	408	0	0	0
T96	522	0	0	0
T109	0	2	0	0
T110	0	1	0	0
T123	0	1	0	0
T163	0	2	0	0
T166	404	0	0	0
T167	422	0	0	0
T170	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	24	0	0
T9	571	1	0	0
T10	1319	0	0	0
T11	630	0	0	0
T12	480	0	0	0
T29	492	0	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T95	408	0	0	0
T96	522	0	0	0
T110	0	1	0	0
T121	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	2	0	0
T166	404	0	0	0
T167	422	0	0	0
T170	402	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	24	0	0
T9	571	1	0	0
T10	1319	0	0	0
T11	630	0	0	0
T12	480	0	0	0
T29	492	0	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T95	408	0	0	0
T96	522	0	0	0
T110	0	1	0	0
T121	0	1	0	0
T163	0	1	0	0
T164	0	1	0	0
T165	0	2	0	0
T166	404	0	0	0
T167	422	0	0	0
T170	402	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	393098	0	0
T70	0	19	0	0
T75	1663	364	0	0
T76	0	43	0	0
T77	0	105	0	0
T91	498	0	0	0
T110	0	253	0	0
T121	0	103	0	0
T163	0	40	0	0
T164	0	43	0	0
T165	0	404	0	0
T173	0	286	0	0
T174	8451	0	0	0
T175	804	0	0	0
T176	438	0	0	0
T177	524	0	0	0
T178	427	0	0	0
T179	505	0	0	0
T180	423	0	0	0
T181	502	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	5272	0	0
T1	865	2	0	0
T2	506	0	0	0
T5	429	2	0	0
T6	430	4	0	0
T7	0	1	0	0
T8	0	6	0	0
T14	426	1	0	0
T15	462	0	0	0
T16	726	3	0	0
T18	0	6	0	0
T19	505	5	0	0
T20	418	1	0	0
T21	406	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	581382	0	0
T9	571	55	0	0
T10	1319	0	0	0
T11	630	0	0	0
T12	480	0	0	0
T29	492	0	0	0
T70	0	80	0	0
T75	0	171	0	0
T76	0	254	0	0
T77	0	136	0	0
T95	408	0	0	0
T96	522	0	0	0
T110	0	199	0	0
T121	0	86	0	0
T163	0	104	0	0
T164	0	123	0	0
T165	0	140	0	0
T166	404	0	0	0
T167	422	0	0	0
T170	402	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T6 T19 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T5 T6 T19 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T9 T10 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T8 T9 T10 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T8 T9 T10 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T6 T19 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T6 T19 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T6 T19 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T6 T19 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T6 T19 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T6 T19 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T6 T19 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T6 T19 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T9 T10 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T9 T10 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T10 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T9 T10 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T9 T10 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T9 T10 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T9 T10 
168        1/1                      state_d = DetectSt;
           Tests:       T8 T9 T10 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T109 T110 T182 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T8 T9 T10 
182        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T10 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T8 T9 T10 
186        1/1                    state_d = IdleSt;
           Tests:       T121 T122 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T121 T122 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T8 T9 T10 
191        1/1                      state_d = StableSt;
           Tests:       T8 T9 T10 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T8 T9 T10 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T8 T9 T10 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T8 T9 T10 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T8 T9 T10 
206        1/1                    state_d = IdleSt;
           Tests:       T8 T9 T10 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T8 T9 T10 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T19

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T19
1	1	Covered	T5,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T5,T6,T19
1	1	Covered	T8,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T10
0	1	Covered	T121,T122
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T10
0	1	Unreachable
1	0	Covered	T8,T9,T10

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T10
DetectSt	168	Covered	T8,T9,T10
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T8,T9,T10

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T8,T9,T10
DebounceSt->IdleSt	163	Covered	T35,T53,T109
DetectSt->IdleSt	186	Covered	T121,T122
DetectSt->StableSt	191	Covered	T8,T9,T10
IdleSt->DebounceSt	148	Covered	T8,T9,T10
StableSt->IdleSt	206	Covered	T8,T9,T10

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T9,T10
0	1	Covered	T8,T9,T10
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T8,T9,T10
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T19
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T8,T9,T10
DebounceSt	-	0	1	0	-	-	-	Covered	T109,T110,T182
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T121,T122
DetectSt	-	-	-	-	0	1	-	Covered	T8,T9,T10
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T8,T9,T10
StableSt	-	-	-	-	-	-	0	Covered	T8,T9,T10
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	104	0	0
CntIncr_A	7444491	3624	0	0
CntNoWrap_A	7444491	6988080	0	0
DetectStDropOut_A	7444491	4	0	0
DetectedOut_A	7444491	3231	0	0
DetectedPulseOut_A	7444491	30	0	0
DisabledIdleSt_A	7444491	5658788	0	0
DisabledNoDetection_A	7444491	5660687	0	0
EnterDebounceSt_A	7444491	70	0	0
EnterDetectSt_A	7444491	34	0	0
EnterStableSt_A	7444491	30	0	0
PulseIsPulse_A	7444491	30	0	0
StayInStableSt	7444491	3201	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_sticky_sva.StableStDropOut_A	7444491	706260	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	104	0	0
T8	1193	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T35	0	2	0	0
T53	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	2	0	0
T70	0	2	0	0
T75	0	2	0	0
T76	0	4	0	0
T77	0	2	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	3624	0	0
T8	1193	41	0	0
T9	0	53	0	0
T10	0	63	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T35	0	76	0	0
T53	0	29	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	25	0	0
T70	0	44	0	0
T75	0	69	0	0
T76	0	74	0	0
T77	0	11	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988080	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	4	0	0
T121	677	1	0	0
T122	0	3	0	0
T183	2799	0	0	0
T184	424	0	0	0
T185	531	0	0	0
T186	461	0	0	0
T187	2967	0	0	0
T188	894	0	0	0
T189	572	0	0	0
T190	503	0	0	0
T191	489	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	3231	0	0
T8	1193	39	0	0
T9	0	43	0	0
T10	0	17	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	71	0	0
T70	0	19	0	0
T75	0	447	0	0
T76	0	165	0	0
T77	0	21	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T108	0	59	0	0
T162	0	14	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	30	0	0
T8	1193	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T108	0	1	0	0
T162	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	5658788	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	5660687	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	70	0	0
T8	1193	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T35	0	2	0	0
T53	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	34	0	0
T8	1193	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T108	0	1	0	0
T162	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	30	0	0
T8	1193	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T108	0	1	0	0
T162	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	30	0	0
T8	1193	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	2	0	0
T77	0	1	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T108	0	1	0	0
T162	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	3201	0	0
T8	1193	38	0	0
T9	0	42	0	0
T10	0	16	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	70	0	0
T70	0	18	0	0
T75	0	446	0	0
T76	0	163	0	0
T77	0	20	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T108	0	58	0	0
T162	0	13	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	706260	0	0
T8	1193	40	0	0
T9	0	30	0	0
T10	0	28	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	148	0	0
T70	0	80	0	0
T75	0	85	0	0
T76	0	79	0	0
T77	0	238	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T108	0	27	0	0
T162	0	32	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T6 T19 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T5 T6 T19 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T9 T10 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T8 T9 T10 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T8 T9 T10 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T6 T19 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T6 T19 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T6 T19 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T6 T19 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T6 T19 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T6 T19 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T6 T19 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T6 T19 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T9 T10 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T9 T10 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T10 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T9 T10 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T9 T10 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T9 T10 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T9 T10 
168        1/1                      state_d = DetectSt;
           Tests:       T10 T64 T75 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T8 T9 T64 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T10 T64 T75 
182        1/1                  cnt_en = 1'b1;
           Tests:       T10 T64 T75 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T10 T64 T75 
186        1/1                    state_d = IdleSt;
           Tests:       T76 T110 T112 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T76 T110 T112 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T10 T64 T75 
191        1/1                      state_d = StableSt;
           Tests:       T10 T64 T75 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T10 T64 T75 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T10 T64 T75 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T10 T64 T75 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T10 T64 T75 
206        1/1                    state_d = IdleSt;
           Tests:       T10 T64 T75 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T10 T64 T75 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T64,T75

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T5,T6,T19
1	1	Covered	T8,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T64,T75
0	1	Covered	T76,T110,T112
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T64,T75
0	1	Unreachable
1	0	Covered	T10,T64,T75

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T8,T9,T10
DetectSt	168	Covered	T10,T64,T75
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T10,T64,T75

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T64,T75
DebounceSt->IdleSt	163	Covered	T8,T9,T64
DetectSt->IdleSt	186	Covered	T76,T110,T112
DetectSt->StableSt	191	Covered	T10,T64,T75
IdleSt->DebounceSt	148	Covered	T8,T9,T10
StableSt->IdleSt	206	Covered	T10,T64,T75

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		19	19	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T8,T9,T10
0	1	Covered	T8,T9,T10
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T64,T75
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T8,T9,T10
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T19
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T64,T75
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T9,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T8,T9,T10
DetectSt	-	-	-	-	1	-	-	Covered	T76,T110,T112
DetectSt	-	-	-	-	0	1	-	Covered	T10,T64,T75
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T64,T75
StableSt	-	-	-	-	-	-	0	Covered	T10,T64,T75
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	96	0	0
CntIncr_A	7444491	183038	0	0
CntNoWrap_A	7444491	6988088	0	0
DetectStDropOut_A	7444491	6	0	0
DetectedOut_A	7444491	548416	0	0
DetectedPulseOut_A	7444491	31	0	0
DisabledIdleSt_A	7444491	5658788	0	0
DisabledNoDetection_A	7444491	5660687	0	0
EnterDebounceSt_A	7444491	59	0	0
EnterDetectSt_A	7444491	37	0	0
EnterStableSt_A	7444491	31	0	0
PulseIsPulse_A	7444491	31	0	0
StayInStableSt	7444491	548385	0	0
gen_high_event_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_sticky_sva.StableStDropOut_A	7444491	596172	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	96	0	0
T8	1193	1	0	0
T9	0	1	0	0
T10	0	2	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T35	0	2	0	0
T53	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	4	0	0
T70	0	2	0	0
T75	0	2	0	0
T76	0	6	0	0
T77	0	2	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	183038	0	0
T8	1193	22	0	0
T9	0	11	0	0
T10	0	13	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T35	0	78	0	0
T53	0	32	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	198	0	0
T70	0	69	0	0
T75	0	91	0	0
T76	0	87	0	0
T77	0	85	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988088	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6	0	0
T36	18914	0	0	0
T53	6728	0	0	0
T56	12687	0	0	0
T59	5418	0	0	0
T76	1158	2	0	0
T77	3051	0	0	0
T102	5218	0	0	0
T110	0	1	0	0
T112	0	2	0	0
T192	0	1	0	0
T193	2932	0	0	0
T194	103912	0	0	0
T195	8410	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	548416	0	0
T10	1319	1	0	0
T11	630	0	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T64	0	1	0	0
T70	0	65	0	0
T75	0	479	0	0
T76	0	32	0	0
T77	0	173	0	0
T87	487	0	0	0
T96	522	0	0	0
T108	0	21	0	0
T109	0	101	0	0
T123	0	16	0	0
T162	0	16	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	31	0	0
T10	1319	1	0	0
T11	630	0	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T64	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T87	487	0	0	0
T96	522	0	0	0
T108	0	1	0	0
T109	0	1	0	0
T123	0	1	0	0
T162	0	1	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	5658788	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	5660687	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	59	0	0
T8	1193	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T33	462	0	0	0
T35	0	2	0	0
T53	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T64	0	3	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	3	0	0
T77	0	1	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	37	0	0
T10	1319	1	0	0
T11	630	0	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T64	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	3	0	0
T77	0	1	0	0
T87	487	0	0	0
T96	522	0	0	0
T108	0	1	0	0
T109	0	1	0	0
T123	0	1	0	0
T162	0	1	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	31	0	0
T10	1319	1	0	0
T11	630	0	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T64	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T87	487	0	0	0
T96	522	0	0	0
T108	0	1	0	0
T109	0	1	0	0
T123	0	1	0	0
T162	0	1	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	31	0	0
T10	1319	1	0	0
T11	630	0	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T64	0	1	0	0
T70	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T87	487	0	0	0
T96	522	0	0	0
T108	0	1	0	0
T109	0	1	0	0
T123	0	1	0	0
T162	0	1	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	548385	0	0
T70	0	64	0	0
T75	1663	478	0	0
T76	0	31	0	0
T77	0	172	0	0
T91	498	0	0	0
T108	0	20	0	0
T109	0	100	0	0
T123	0	15	0	0
T162	0	15	0	0
T163	0	119	0	0
T174	8451	0	0	0
T175	804	0	0	0
T176	438	0	0	0
T177	524	0	0	0
T178	427	0	0	0
T179	505	0	0	0
T180	423	0	0	0
T181	502	0	0	0
T182	0	38	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	596172	0	0
T10	1319	101	0	0
T11	630	0	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T64	0	28	0	0
T70	0	27	0	0
T75	0	41	0	0
T76	0	105	0	0
T77	0	32	0	0
T87	487	0	0	0
T96	522	0	0	0
T108	0	144	0	0
T109	0	163	0	0
T123	0	73	0	0
T162	0	47	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T35 T52 T53 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T35 T52 T53 
149        1/1                    cnt_en = 1'b1;
           Tests:       T35 T52 T53 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T35 T52 T53 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T35 T52 T53 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T35 T52 T53 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T52 T53 
167        1/1                    if (trigger_active) begin
           Tests:       T35 T52 T53 
168        1/1                      state_d = DetectSt;
           Tests:       T35 T52 T53 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T196 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T35 T52 T53 
182        1/1                  cnt_en = 1'b1;
           Tests:       T35 T52 T53 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T35 T52 T53 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T35 T52 T53 
191        1/1                      state_d = StableSt;
           Tests:       T35 T52 T53 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T35 T52 T53 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T35 T52 T53 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T35 T52 T53 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T35 T52 T53 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T53 T197 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T35 T52 T53 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T52,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T52,T53

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T52,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T49,T35
1	0	Covered	T4,T5,T6
1	1	Covered	T35,T52,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T52,T53
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T52,T53
0	1	Covered	T197,T188,T198
1	0	Covered	T35,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T52,T53
1	-	Covered	T197,T188,T198

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T52,T53
DetectSt	168	Covered	T35,T52,T53
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T52,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T52,T53
DebounceSt->IdleSt	163	Covered	T196
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T35,T52,T53
IdleSt->DebounceSt	148	Covered	T35,T52,T53
StableSt->IdleSt	206	Covered	T35,T53,T197

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T52,T53
0	1	Covered	T35,T52,T53
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T52,T53
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T52,T53
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T52,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T196
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T52,T53
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T35,T52,T53
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T53,T197
StableSt	-	-	-	-	-	-	0	Covered	T35,T52,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	35	0	0
CntIncr_A	7444491	11251	0	0
CntNoWrap_A	7444491	6988149	0	0
DetectStDropOut_A	7444491	0	0	0
DetectedOut_A	7444491	2881	0	0
DetectedPulseOut_A	7444491	17	0	0
DisabledIdleSt_A	7444491	6929081	0	0
DisabledNoDetection_A	7444491	6930955	0	0
EnterDebounceSt_A	7444491	18	0	0
EnterDetectSt_A	7444491	17	0	0
EnterStableSt_A	7444491	17	0	0
PulseIsPulse_A	7444491	17	0	0
StayInStableSt	7444491	2855	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	6	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	35	0	0
T35	6681	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T55	0	2	0	0
T92	493	0	0	0
T93	493	0	0	0
T117	0	2	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T188	0	4	0	0
T197	0	2	0	0
T198	0	2	0	0
T199	0	2	0	0
T200	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	11251	0	0
T35	6681	26	0	0
T52	0	68	0	0
T53	0	20	0	0
T54	0	82	0	0
T55	0	96	0	0
T92	493	0	0	0
T93	493	0	0	0
T117	0	25	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T188	0	164	0	0
T197	0	22	0	0
T198	0	38	0	0
T199	0	79	0	0
T200	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988149	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	2881	0	0
T35	6681	2	0	0
T52	0	476	0	0
T53	0	4	0	0
T54	0	53	0	0
T55	0	44	0	0
T92	493	0	0	0
T93	493	0	0	0
T117	0	41	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T188	0	86	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	52	0	0
T200	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	17	0	0
T35	6681	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T92	493	0	0	0
T93	493	0	0	0
T117	0	1	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T188	0	2	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6929081	0	0
T1	865	3	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6930955	0	0
T1	865	3	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	18	0	0
T35	6681	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T92	493	0	0	0
T93	493	0	0	0
T117	0	1	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T188	0	2	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	17	0	0
T35	6681	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T92	493	0	0	0
T93	493	0	0	0
T117	0	1	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T188	0	2	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	17	0	0
T35	6681	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T92	493	0	0	0
T93	493	0	0	0
T117	0	1	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T188	0	2	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	17	0	0
T35	6681	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T55	0	1	0	0
T92	493	0	0	0
T93	493	0	0	0
T117	0	1	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T188	0	2	0	0
T197	0	1	0	0
T198	0	1	0	0
T199	0	1	0	0
T200	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	2855	0	0
T35	6681	1	0	0
T52	0	474	0	0
T53	0	3	0	0
T54	0	51	0	0
T55	0	42	0	0
T92	493	0	0	0
T93	493	0	0	0
T117	0	39	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T188	0	83	0	0
T199	0	50	0	0
T200	422	0	0	0
T201	0	365	0	0
T202	0	107	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6	0	0
T188	0	1	0	0
T197	695	1	0	0
T198	0	1	0	0
T202	0	1	0	0
T203	0	1	0	0
T204	0	1	0	0
T205	493	0	0	0
T206	560	0	0	0
T207	417	0	0	0
T208	501	0	0	0
T209	404	0	0	0
T210	596	0	0	0
T211	1617	0	0	0
T212	735	0	0	0
T213	494	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T7 T11 T48 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T7 T11 T48 
149        1/1                    cnt_en = 1'b1;
           Tests:       T7 T11 T48 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T7 T11 T48 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T7 T11 T48 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T7 T11 T48 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T7 T11 T48 
167        1/1                    if (trigger_active) begin
           Tests:       T7 T11 T48 
168        1/1                      state_d = DetectSt;
           Tests:       T7 T11 T48 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T116 T214 T215 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T7 T11 T48 
182        1/1                  cnt_en = 1'b1;
           Tests:       T7 T11 T48 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T7 T11 T48 
186        1/1                    state_d = IdleSt;
           Tests:       T7 T117 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T7 T117 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T7 T11 T48 
191        1/1                      state_d = StableSt;
           Tests:       T7 T11 T48 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T7 T11 T48 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T7 T11 T48 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T7 T11 T48 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T7 T11 T48 
206        1/1                    state_d = IdleSt;
           Tests:       T7 T11 T35 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T7 T11 T48 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T11,T48

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T11,T48

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T11,T48

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T11,T48
1	0	Covered	T5,T6,T19
1	1	Covered	T7,T11,T48

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T48
0	1	Covered	T7,T117
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T11,T48
0	1	Covered	T7,T11,T55
1	0	Covered	T35,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T11,T48
1	-	Covered	T7,T11,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T11,T48
DetectSt	168	Covered	T7,T11,T48
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T11,T48

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T11,T48
DebounceSt->IdleSt	163	Covered	T116,T214,T215
DetectSt->IdleSt	186	Covered	T7,T117
DetectSt->StableSt	191	Covered	T7,T11,T48
IdleSt->DebounceSt	148	Covered	T7,T11,T48
StableSt->IdleSt	206	Covered	T7,T11,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T11,T48
0	1	Covered	T7,T11,T48
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T11,T48
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T11,T48
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T11,T48
DebounceSt	-	0	1	0	-	-	-	Covered	T116,T214,T215
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T11,T48
DetectSt	-	-	-	-	1	-	-	Covered	T7,T117
DetectSt	-	-	-	-	0	1	-	Covered	T7,T11,T48
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T7,T11,T35
StableSt	-	-	-	-	-	-	0	Covered	T7,T11,T48
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	63	0	0
CntIncr_A	7444491	21872	0	0
CntNoWrap_A	7444491	6988121	0	0
DetectStDropOut_A	7444491	2	0	0
DetectedOut_A	7444491	19524	0	0
DetectedPulseOut_A	7444491	28	0	0
DisabledIdleSt_A	7444491	6930720	0	0
DisabledNoDetection_A	7444491	6932593	0	0
EnterDebounceSt_A	7444491	33	0	0
EnterDetectSt_A	7444491	30	0	0
EnterStableSt_A	7444491	28	0	0
PulseIsPulse_A	7444491	28	0	0
StayInStableSt	7444491	19480	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7444491	1615	0	0
gen_low_level_sva.LowLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	63	0	0
T7	830	4	0	0
T8	1193	0	0	0
T11	0	2	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T51	0	2	0	0
T53	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	3	0	0
T216	0	2	0	0
T217	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	21872	0	0
T7	830	82	0	0
T8	1193	0	0	0
T11	0	52	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	26	0	0
T47	0	47	0	0
T48	0	49	0	0
T51	0	94	0	0
T53	0	20	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	38	0	0
T216	0	19	0	0
T217	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988121	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	2	0	0
T7	830	1	0	0
T8	1193	0	0	0
T27	496	0	0	0
T30	524	0	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T117	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	19524	0	0
T7	830	28	0	0
T8	1193	0	0	0
T11	0	73	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	2	0	0
T47	0	40	0	0
T48	0	42	0	0
T51	0	41	0	0
T53	0	3	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	72	0	0
T216	0	47	0	0
T217	0	248	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	28	0	0
T7	830	1	0	0
T8	1193	0	0	0
T11	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6930720	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6932593	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	33	0	0
T7	830	2	0	0
T8	1193	0	0	0
T11	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	2	0	0
T216	0	1	0	0
T217	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	30	0	0
T7	830	2	0	0
T8	1193	0	0	0
T11	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	28	0	0
T7	830	1	0	0
T8	1193	0	0	0
T11	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	28	0	0
T7	830	1	0	0
T8	1193	0	0	0
T11	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	19480	0	0
T7	830	27	0	0
T8	1193	0	0	0
T11	0	72	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	38	0	0
T48	0	40	0	0
T51	0	39	0	0
T53	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	70	0	0
T216	0	45	0	0
T217	0	246	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	1615	0	0
T1	865	1	0	0
T2	506	0	0	0
T5	429	3	0	0
T6	430	5	0	0
T7	0	2	0	0
T14	426	2	0	0
T15	462	0	0	0
T16	726	0	0	0
T18	0	5	0	0
T19	505	7	0	0
T20	418	1	0	0
T21	406	0	0	0
T27	0	4	0	0
T30	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	10	0	0
T7	830	1	0	0
T8	1193	0	0	0
T11	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T55	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T111	0	1	0	0
T196	0	1	0	0
T197	0	1	0	0
T204	0	1	0	0
T218	0	1	0	0
T219	0	1	0	0
T220	0	1	0	0