Unified Coverage Report :: Module

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.18	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	LINE
98.95	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	LINE
97.27	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.95	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	LINE
92.55	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.95	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	LINE
85.23	89.13

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	LINE
92.55	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	LINE
89.95	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00



57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T16 T7 T9 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T16 T7 T9 
149        1/1                    cnt_en = 1'b1;
           Tests:       T16 T7 T9 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T16 T7 T9 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T16 T7 T9 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T16 T7 T9 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T16 T7 T9 
167        1/1                    if (trigger_active) begin
           Tests:       T16 T7 T9 
168        1/1                      state_d = DetectSt;
           Tests:       T16 T7 T9 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T64 T67 T108 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T16 T7 T9 
182        1/1                  cnt_en = 1'b1;
           Tests:       T16 T7 T9 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T16 T7 T9 
186        1/1                    state_d = IdleSt;
           Tests:       T7 T10 T109 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T7 T10 T109 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T16 T7 T9 
191        1/1                      state_d = StableSt;
           Tests:       T16 T7 T9 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T16 T7 T9 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T16 T7 T9 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T16 T7 T9 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T16 T7 T9 
206        1/1                    state_d = IdleSt;
           Tests:       T16 T7 T9 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T16 T7 T9 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.95	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	LINE
89.87	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	LINE
93.46	93.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.27	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	LINE
89.87	91.30

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.27	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	LINE
98.18	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	LINE
97.27	95.65

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00



59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T7 T8 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T7 T8 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T7 T8 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T7 T8 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T7 T8 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T7 T8 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T8 T9 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T8 T9 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T8 T9 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T13 T109 T110 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T8 T9 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T8 T9 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T8 T9 
186        1/1                    state_d = IdleSt;
           Tests:       T51 T35 T111 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T51 T35 T111 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T8 T9 
191        1/1                      state_d = StableSt;
           Tests:       T1 T8 T9 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T8 T9 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T8 T9 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T8 T9 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T8 T9 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T8 T9 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T8 T9 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :

SCORE	LINE
98.75	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00



59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T6 T19 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T5 T6 T19 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T8 T9 T10 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T8 T9 T10 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T8 T9 T10 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T6 T19 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T6 T19 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T6 T19 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T6 T19 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T6 T19 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T6 T19 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T6 T19 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T6 T19 
148        1/1                    state_d = DebounceSt;
           Tests:       T8 T9 T10 
149        1/1                    cnt_en = 1'b1;
           Tests:       T8 T9 T10 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T8 T9 T10 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T8 T9 T10 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T8 T9 T10 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T8 T9 T10 
167        1/1                    if (trigger_active) begin
           Tests:       T8 T9 T10 
168        1/1                      state_d = DetectSt;
           Tests:       T10 T64 T75 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T8 T9 T64 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T10 T64 T75 
182        1/1                  cnt_en = 1'b1;
           Tests:       T10 T64 T75 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T10 T64 T75 
186        1/1                    state_d = IdleSt;
           Tests:       T76 T110 T112 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T76 T110 T112 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T10 T64 T75 
191        1/1                      state_d = StableSt;
           Tests:       T10 T64 T75 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T10 T64 T75 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T10 T64 T75 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T10 T64 T75 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T10 T64 T75 
206        1/1                    state_d = IdleSt;
           Tests:       T10 T64 T75 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T10 T64 T75 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00



59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T35 T36 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T15 T33 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T2 T15 T33 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T2 T15 T33 
129        1/1              cnt_en = 1'b0;
           Tests:       T2 T15 T33 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T2 T15 T33 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T2 T15 T33 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T2 T15 T33 
139                     
140        1/1              unique case (state_q)
           Tests:       T2 T15 T33 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T2 T15 T33 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T15 T33 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T15 T33 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T15 T33 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T15 T33 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T15 T33 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T15 T33 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T15 T33 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T15 T33 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T35 T59 T53 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T15 T33 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T15 T33 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T15 T33 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T59 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T59 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T15 T33 
191        1/1                      state_d = StableSt;
           Tests:       T2 T15 T33 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T15 T33 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T15 T33 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T15 T33 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T15 T33 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T59 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T15 T33 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6

Line Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	LINE
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00



59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T2 T15 T3 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T15 T3 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T15 T3 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T15 T3 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T15 T3 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T15 T3 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T15 T3 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T15 T3 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T15 T3 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T3 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T15 T60 T61 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T3 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T3 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T3 T12 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T53 T57 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 T57 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T3 T12 
191        1/1                      state_d = StableSt;
           Tests:       T2 T3 T12 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T3 T12 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T3 T12 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T3 T12 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T3 T12 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T3 T12 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T3 T12 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T15,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T3
1	0	Covered	T78,T113,T64
1	1	Covered	T2,T15,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T12
0	1	Covered	T57,T58,T114
1	0	Covered	T35,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T12
0	1	Covered	T2,T3,T12
1	0	Covered	T35,T53,T115

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T12
1	-	Covered	T2,T3,T12

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.18	90.91

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	COND
97.27	95.45

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.95	90.91

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	COND
92.55	95.45

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.95	90.91

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	COND
85.23	90.91

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	COND
92.55	95.45

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	COND
89.95	90.91

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T16,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T16,T7

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T16,T7

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T16,T7
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T16,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T7
0	1	Covered	T7,T116,T117
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T16,T7
0	1	Covered	T1,T16,T7
1	0	Covered	T35,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T16,T7
1	-	Covered	T1,T16,T7

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	COND
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T33

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T36,T53
1	1	Covered	T2,T15,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T33
0	1	Covered	T34,T35,T59
1	0	Covered	T35,T53,T118

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T33
0	1	Covered	T35,T36,T59
1	0	Covered	T53,T119,T120

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T15,T33
1	-	Covered	T35,T36,T59

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.75	93.75

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T10,T64,T75

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T5,T6,T19
1	1	Covered	T8,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T64,T75
0	1	Covered	T76,T110,T112
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T64,T75
0	1	Unreachable
1	0	Covered	T10,T64,T75

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
89.87	90.91

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	COND
93.46	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.27	95.45

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	COND
89.87	90.91

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.27	95.45

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	COND
98.18	100.00

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	COND
97.27	95.45

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T11
1	0	Covered	T4,T5,T6
1	1	Covered	T1,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T51,T111,T117
1	0	Covered	T35

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T1,T50,T52
1	0	Covered	T35,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T11
1	-	Covered	T1,T50,T52

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.95	94.74

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T19

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T19
1	1	Covered	T5,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T10

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T10

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T8,T9,T10

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T5,T6,T19
1	1	Covered	T8,T9,T10

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T10
0	1	Covered	T121,T122
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T8,T9,T10
0	1	Unreachable
1	0	Covered	T8,T9,T10

Cond Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :

SCORE	COND
98.95	94.74

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T10,T64

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T10,T64

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T9,T10,T75

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T8,T9,T10
1	0	Covered	T5,T6,T19
1	1	Covered	T9,T10,T64

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T9,T75,T70
0	1	Covered	T10,T109,T123
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T9,T75,T70
0	1	Unreachable
1	0	Covered	T9,T75,T70

FSM Coverage for Module : sysrst_ctrl_detect

**Summary for FSM :: state_q**
	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T16,T7
DetectSt	168	Covered	T1,T16,T7
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T16,T7

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T16,T7
DebounceSt->IdleSt	163	Covered	T11,T64,T67
DetectSt->IdleSt	186	Covered	T7,T10,T35
DetectSt->StableSt	191	Covered	T1,T16,T7
IdleSt->DebounceSt	148	Covered	T1,T16,T7
StableSt->IdleSt	206	Covered	T1,T16,T7

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.18	100.00

tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

SCORE	BRANCH
97.27	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.95	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
92.55	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.95	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
85.23	85.71

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
92.55	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
89.95	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

SCORE	BRANCH
98.95	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

SCORE	BRANCH
98.95	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

SCORE	BRANCH
89.87	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
93.46	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[1].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.27	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[2].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
89.87	90.48

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[3].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.27	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
98.18	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
97.27	95.24

tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		23	22	95.65
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00
IF	69	2	2	100.00



92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T16,T7
0	1	Covered	T1,T16,T7
0	0	Covered	T4,T5,T6



99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T16,T7
0	Covered	T4,T5,T6



104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T1,T16,T7
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T16,T7
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T64,T67
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T16,T7
DetectSt	-	-	-	-	1	-	-	Covered	T7,T10,T51
DetectSt	-	-	-	-	0	1	-	Covered	T1,T16,T7
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T12
StableSt	-	-	-	-	-	-	1	Covered	T1,T16,T7
StableSt	-	-	-	-	-	-	0	Covered	T1,T16,T7
default	-	-	-	-	-	-	-	Not Covered



219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Branch Coverage for Module : sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :

SCORE	BRANCH
98.75	100.00

tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

SCORE	BRANCH
100.00	100.00

tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[3].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	12	11	91.67
IF	219	2	2	100.00



92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T8
0	1	Covered	T2,T15,T8
0	0	Covered	T4,T5,T6



99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T33
0	Covered	T4,T5,T6



104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6



140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==>

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests
IdleSt	1	-	-	-	-	-	-	Covered	T2,T15,T8
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T19
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T15,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T8,T9,T64
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T15,T8
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T76
DetectSt	-	-	-	-	0	1	-	Covered	T2,T15,T33
DetectSt	-	-	-	-	0	0	-	Covered	T2,T15,T33
StableSt	-	-	-	-	-	-	1	Covered	T10,T64,T75
StableSt	-	-	-	-	-	-	0	Covered	T2,T15,T33
default	-	-	-	-	-	-	-	Not Covered



219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

Assert Coverage for Module : sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	19	19	100.00	19	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	19	19	100.00	19	100.00

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	193556766	15843	0	0
CntIncr_A	193556766	1669827	0	0
CntNoWrap_A	193556766	181676941	0	0
DetectStDropOut_A	193556766	1808	0	0
DetectedOut_A	193556766	1683305	0	0
DetectedPulseOut_A	193556766	5022	0	0
DisabledIdleSt_A	193556766	172184642	0	0
DisabledNoDetection_A	193556766	172230509	0	0
EnterDebounceSt_A	193556766	8172	0	0
EnterDetectSt_A	193556766	7683	0	0
EnterStableSt_A	193556766	5022	0	0
PulseIsPulse_A	193556766	5022	0	0
StayInStableSt	193556766	1677549	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	67000419	38946	0	0
gen_high_event_sva.HighLevelEvent_A	37222455	34950415	0	0
gen_high_level_sva.HighLevelEvent_A	126556347	118831411	0	0
gen_low_level_sva.LowLevelEvent_A	67000419	62910747	0	0
gen_not_sticky_sva.StableStDropOut_A	171223293	4112	0	0
gen_sticky_sva.StableStDropOut_A	22333473	1883814	0	0

CntClr_A

Name	Attempts	Real Successes
Total	193556766	15843
T2	1012	4
T3	1461	2
T7	2490	0
T8	3579	0
T12	0	2
T14	852	0
T15	924	3
T16	2178	4
T17	1212	0
T18	1521	0
T27	496	0
T30	524	0
T32	0	4
T33	0	3
T34	0	38
T35	6681	17
T60	1293	1
T61	438	1
T62	0	3
T63	0	1
T64	0	4
T65	0	2
T66	0	2
T67	0	2
T68	0	2
T69	0	4
T92	493	0
T101	0	2
T124	686	2
T125	402	0
T126	406	0
T127	507	0
T128	526	0
T129	2074	0

CntIncr_A

Name	Attempts	Real Successes
Total	193556766	1669827
T2	1012	46
T3	1461	25
T7	2490	0
T8	3579	0
T12	0	25
T14	852	0
T15	924	41
T16	2178	141
T17	1212	0
T18	1521	0
T27	496	0
T30	524	0
T32	0	165
T33	0	41
T34	0	993
T35	6681	383
T60	1293	20
T61	438	20
T62	0	41
T63	0	20
T64	0	110
T65	0	30
T66	0	52
T67	0	99
T68	0	98
T69	0	198
T92	493	0
T101	0	21
T124	686	71
T125	402	0
T126	406	0
T127	507	0
T128	526	0
T129	2074	0

CntNoWrap_A

Name	Attempts	Real Successes
Total	193556766	181676941
T1	22490	12042
T2	13156	2726
T4	15574	5148
T5	11154	728
T6	11180	754
T14	11076	650
T15	12012	1583
T19	13130	2704
T20	10868	442
T21	10556	130

DetectStDropOut_A

Name	Attempts	Real Successes
Total	193556766	1808
T34	5270	19
T35	0	1
T57	0	9
T58	0	6
T102	0	18
T103	0	7
T104	0	9
T105	0	22
T122	1245	0
T130	0	27
T131	0	6
T132	0	8
T133	0	5
T134	0	11
T135	17228	6
T136	593	1
T137	14603	12
T138	0	4
T139	0	4
T140	0	7
T141	0	9
T142	0	6
T143	1175	0
T144	507	0
T145	422	0
T146	418	0
T147	522	0
T148	13816	0
T149	496	0
T150	424	0
T151	526	0
T152	664	0
T153	449	0
T154	13804	0
T155	2674	0
T156	734	0
T157	524	0
T158	334625	0

DetectedOut_A

Name	Attempts	Real Successes
Total	193556766	1683305
T2	1012	83
T3	1461	3
T7	2490	0
T8	3579	0
T12	0	3
T14	852	0
T15	924	37
T16	2178	16
T17	1212	0
T18	1521	0
T27	496	0
T30	524	0
T32	0	18
T33	0	37
T35	6681	426
T36	0	724
T47	0	3
T56	0	6
T60	1293	0
T61	438	0
T64	0	5
T65	0	10
T66	0	9
T68	0	11
T69	0	10
T92	493	0
T124	686	13
T125	402	0
T126	406	0
T127	507	0
T128	526	0
T129	2074	3
T159	0	3
T160	0	3
T161	0	11

DetectedPulseOut_A

Name	Attempts	Real Successes
Total	193556766	5022
T2	1012	2
T3	1461	1
T7	2490	0
T8	3579	0
T12	0	1
T14	852	0
T15	924	1
T16	2178	2
T17	1212	0
T18	1521	0
T27	496	0
T30	524	0
T32	0	2
T33	0	1
T35	6681	6
T36	0	6
T47	0	1
T56	0	1
T60	1293	0
T61	438	0
T64	0	1
T65	0	1
T66	0	1
T68	0	1
T69	0	2
T92	493	0
T124	686	1
T125	402	0
T126	406	0
T127	507	0
T128	526	0
T129	2074	1
T159	0	1
T160	0	1
T161	0	2

DisabledIdleSt_A

Name	Attempts	Real Successes
Total	193556766	172184642
T1	22490	7454
T2	13156	2550
T4	15574	5148
T5	11154	728
T6	11180	754
T14	11076	650
T15	12012	1492
T19	13130	2704
T20	10868	442
T21	10556	130

DisabledNoDetection_A

Name	Attempts	Real Successes
Total	193556766	172230509
T1	22490	7470
T2	13156	2574
T4	15574	5174
T5	11154	754
T6	11180	780
T14	11076	676
T15	12012	1516
T19	13130	2730
T20	10868	468
T21	10556	156

EnterDebounceSt_A

Name	Attempts	Real Successes
Total	193556766	8172
T2	1012	2
T3	1461	1
T7	2490	0
T8	3579	0
T12	0	1
T14	852	0
T15	924	2
T16	2178	2
T17	1212	0
T18	1521	0
T27	496	0
T30	524	0
T32	0	2
T33	0	2
T34	0	19
T35	6681	10
T60	1293	1
T61	438	1
T62	0	2
T63	0	1
T64	0	3
T65	0	1
T66	0	1
T67	0	2
T68	0	1
T69	0	2
T92	493	0
T101	0	1
T124	686	1
T125	402	0
T126	406	0
T127	507	0
T128	526	0
T129	2074	0

EnterDetectSt_A

Name	Attempts	Real Successes
Total	193556766	7683
T2	1012	2
T3	1461	1
T7	2490	0
T8	3579	0
T12	0	1
T14	852	0
T15	924	1
T16	2178	2
T17	1212	0
T18	1521	0
T27	496	0
T30	524	0
T32	0	2
T33	0	1
T35	6681	10
T36	0	6
T47	0	1
T56	0	1
T60	1293	0
T61	438	0
T64	0	1
T65	0	1
T66	0	1
T68	0	1
T69	0	2
T92	493	0
T124	686	1
T125	402	0
T126	406	0
T127	507	0
T128	526	0
T129	2074	1
T159	0	1
T160	0	1
T161	0	2

EnterStableSt_A

Name	Attempts	Real Successes
Total	193556766	5022
T2	1012	2
T3	1461	1
T7	2490	0
T8	3579	0
T12	0	1
T14	852	0
T15	924	1
T16	2178	2
T17	1212	0
T18	1521	0
T27	496	0
T30	524	0
T32	0	2
T33	0	1
T35	6681	6
T36	0	6
T47	0	1
T56	0	1
T60	1293	0
T61	438	0
T64	0	1
T65	0	1
T66	0	1
T68	0	1
T69	0	2
T92	493	0
T124	686	1
T125	402	0
T126	406	0
T127	507	0
T128	526	0
T129	2074	1
T159	0	1
T160	0	1
T161	0	2

PulseIsPulse_A

Name	Attempts	Real Successes
Total	193556766	5022
T2	1012	2
T3	1461	1
T7	2490	0
T8	3579	0
T12	0	1
T14	852	0
T15	924	1
T16	2178	2
T17	1212	0
T18	1521	0
T27	496	0
T30	524	0
T32	0	2
T33	0	1
T35	6681	6
T36	0	6
T47	0	1
T56	0	1
T60	1293	0
T61	438	0
T64	0	1
T65	0	1
T66	0	1
T68	0	1
T69	0	2
T92	493	0
T124	686	1
T125	402	0
T126	406	0
T127	507	0
T128	526	0
T129	2074	1
T159	0	1
T160	0	1
T161	0	2

StayInStableSt

Name	Attempts	Real Successes
Total	193556766	1677549
T2	1012	80
T3	1461	2
T7	2490	0
T8	3579	0
T12	0	2
T14	852	0
T15	924	35
T16	2178	14
T17	1212	0
T18	1521	0
T27	496	0
T30	524	0
T32	0	16
T33	0	35
T35	6681	420
T36	0	717
T47	0	2
T56	0	5
T60	1293	0
T61	438	0
T64	0	4
T65	0	9
T66	0	8
T68	0	10
T69	0	8
T92	493	0
T124	686	12
T125	402	0
T126	406	0
T127	507	0
T128	526	0
T129	2074	2
T159	0	2
T160	0	2
T161	0	9

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes
Total	67000419	38946
T1	7785	12
T2	4554	3
T3	0	3
T4	599	4
T5	3861	17
T6	3870	31
T7	0	10
T8	0	25
T14	3834	20
T15	4158	3
T16	5808	9
T18	0	51
T19	4545	46
T20	3762	9
T21	3654	0
T27	0	10
T30	0	13
T79	0	6

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	37222455	34950415
T1	4325	2325
T2	2530	530
T4	2995	995
T5	2145	145
T6	2150	150
T14	2130	130
T15	2310	310
T19	2525	525
T20	2090	90
T21	2030	30

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes
Total	126556347	118831411
T1	14705	7905
T2	8602	1802
T4	10183	3383
T5	7293	493
T6	7310	510
T14	7242	442
T15	7854	1054
T19	8585	1785
T20	7106	306
T21	6902	102

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes
Total	67000419	62910747
T1	7785	4185
T2	4554	954
T4	5391	1791
T5	3861	261
T6	3870	270
T14	3834	234
T15	4158	558
T19	4545	945
T20	3762	162
T21	3654	54

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	171223293	4112
T2	506	1
T3	974	1
T7	1660	0
T8	2386	0
T12	0	1
T14	426	0
T15	462	0
T16	1452	2
T17	808	0
T18	1014	0
T27	496	0
T30	524	0
T32	0	2
T35	6681	5
T36	0	5
T41	0	2
T47	0	1
T53	0	4
T56	0	1
T60	862	0
T61	438	0
T64	0	1
T65	0	1
T66	0	1
T68	0	1
T69	0	2
T92	493	0
T124	686	1
T125	402	0
T126	406	0
T127	507	0
T128	526	0
T129	2074	1
T159	0	1
T160	0	1
T161	0	2

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes
Total	22333473	1883814
T8	1193	40
T9	571	85
T10	2638	129
T11	1260	0
T12	960	0
T27	496	0
T30	524	0
T31	608	0
T32	754	0
T33	462	0
T60	431	0
T61	438	0
T64	0	176
T70	0	187
T75	0	297
T76	0	438
T77	0	406
T78	4414	0
T79	528	0
T80	510	0
T81	679	0
T87	487	0
T96	1044	0
T108	0	171
T109	0	163
T110	0	199
T121	0	86
T123	0	73
T162	0	79
T163	0	104
T164	0	123
T165	0	140
T166	808	0
T167	844	0
T168	431	0