Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.23	89.13	90.91		66.67	85.71	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
85.23	89.13	90.91		66.67	85.71	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	95.65	100.00		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	95.65	100.00		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.55	93.48	95.45		83.33	90.48	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.55	93.48	95.45		83.33	90.48	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T6 T19 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T5 T6 T19 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T13 T49 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T6 T19 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T6 T19 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T6 T19 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T6 T19 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T6 T19 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T6 T19 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T6 T19 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T6 T19 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T13 T49 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T13 T49 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T13 T49 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T13 T49 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T13 T49 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T13 T49 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T13 T49 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T49 T47 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T13 T263 T264 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T49 T47 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T49 T47 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T49 T47 
186        1/1                    state_d = IdleSt;
           Tests:       T51 T111 T117 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T51 T111 T117 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T49 T47 
191        1/1                      state_d = StableSt;
           Tests:       T1 T49 T47 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T49 T47 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T49 T47 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T49 T47 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T49 T47 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T47 T50 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T49 T47 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T19

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T19
1	1	Covered	T5,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T13,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T13,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T49,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T11,T13
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T13,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T49,T47
0	1	Covered	T51,T111,T117
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T49,T47
0	1	Covered	T1,T47,T50
1	0	Covered	T35,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T49,T47
1	-	Covered	T1,T47,T50

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T13,T49
DetectSt	168	Covered	T1,T49,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T49,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T49,T47
DebounceSt->IdleSt	163	Covered	T13,T263,T264
DetectSt->IdleSt	186	Covered	T51,T111,T117
DetectSt->StableSt	191	Covered	T1,T49,T47
IdleSt->DebounceSt	148	Covered	T1,T13,T49
StableSt->IdleSt	206	Covered	T1,T47,T50

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T13,T49
0	1	Covered	T1,T13,T49
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T49,T47
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T13,T49
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T19
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T49,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T13,T263,T264
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T13,T49
DetectSt	-	-	-	-	1	-	-	Covered	T51,T111,T117
DetectSt	-	-	-	-	0	1	-	Covered	T1,T49,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T47,T50
StableSt	-	-	-	-	-	-	0	Covered	T1,T49,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	81	0	0
CntIncr_A	7444491	44821	0	0
CntNoWrap_A	7444491	6988103	0	0
DetectStDropOut_A	7444491	3	0	0
DetectedOut_A	7444491	17006	0	0
DetectedPulseOut_A	7444491	36	0	0
DisabledIdleSt_A	7444491	6832626	0	0
DisabledNoDetection_A	7444491	6834490	0	0
EnterDebounceSt_A	7444491	42	0	0
EnterDetectSt_A	7444491	39	0	0
EnterStableSt_A	7444491	36	0	0
PulseIsPulse_A	7444491	36	0	0
StayInStableSt	7444491	16958	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	22	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	81	0	0
T1	865	2	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T49	0	2	0	0
T50	0	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T217	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	44821	0	0
T1	865	71	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	78	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	26	0	0
T47	0	47	0	0
T49	0	72	0	0
T50	0	61	0	0
T51	0	94	0	0
T52	0	68	0	0
T53	0	20	0	0
T217	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988103	0	0
T1	865	462	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	3	0	0
T35	6681	0	0	0
T51	640	1	0	0
T73	408	0	0	0
T74	522	0	0	0
T106	556	0	0	0
T107	1649	0	0	0
T111	0	1	0	0
T117	0	1	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T243	1541	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	17006	0	0
T1	865	57	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	45	0	0
T49	0	43	0	0
T50	0	137	0	0
T52	0	277	0	0
T53	0	4	0	0
T197	0	130	0	0
T214	0	81	0	0
T217	0	249	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	36	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T197	0	2	0	0
T214	0	2	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6832626	0	0
T1	865	3	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6834490	0	0
T1	865	3	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	42	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T217	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	39	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T197	0	2	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	36	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T197	0	2	0	0
T214	0	2	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	36	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T49	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T197	0	2	0	0
T214	0	2	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	16958	0	0
T1	865	56	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T47	0	44	0	0
T49	0	41	0	0
T50	0	136	0	0
T52	0	276	0	0
T53	0	3	0	0
T197	0	127	0	0
T214	0	78	0	0
T217	0	247	0	0
T244	0	40	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	22	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T47	0	1	0	0
T50	0	1	0	0
T52	0	1	0	0
T111	0	1	0	0
T188	0	2	0	0
T197	0	1	0	0
T214	0	1	0	0
T232	0	1	0	0
T244	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	41	89.13
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	27	84.38
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T5 T6 T19 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T13 T47 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T13 T47 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T13 T47 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T13 T47 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T13 T47 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T13 T47 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T13 T47 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T13 T47 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T13 T47 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T13 T47 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T13 T47 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T13 T47 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T13 T47 
191        1/1                      state_d = StableSt;
           Tests:       T1 T13 T47 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T13 T47 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T13 T47 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T13 T47 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T13 T47 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T53 T111 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T13 T47 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T13,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T13,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T13,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T49
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T13,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T47
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T13,T47
0	1	Covered	T111,T188,T201
1	0	Covered	T35,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T13,T47
1	-	Covered	T111,T188,T201

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	4	66.67
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T13,T47
DetectSt	168	Covered	T1,T13,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T13,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T13,T47
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T1,T13,T47
IdleSt->DebounceSt	148	Covered	T1,T13,T47
StableSt->IdleSt	206	Covered	T47,T35,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	18	85.71
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	7	70.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T13,T47
0	1	Covered	T1,T13,T47
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T13,T47
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T13,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T13,T47
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T13,T47
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T1,T13,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T53,T111
StableSt	-	-	-	-	-	-	0	Covered	T1,T13,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	54	0	0
CntIncr_A	7444491	11644	0	0
CntNoWrap_A	7444491	6988130	0	0
DetectStDropOut_A	7444491	0	0	0
DetectedOut_A	7444491	14133	0	0
DetectedPulseOut_A	7444491	27	0	0
DisabledIdleSt_A	7444491	6927717	0	0
DisabledNoDetection_A	7444491	6929586	0	0
EnterDebounceSt_A	7444491	27	0	0
EnterDetectSt_A	7444491	27	0	0
EnterStableSt_A	7444491	27	0	0
PulseIsPulse_A	7444491	27	0	0
StayInStableSt	7444491	14087	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7444491	4840	0	0
gen_low_level_sva.LowLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	6	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	54	0	0
T1	865	2	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	2	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T55	0	2	0	0
T111	0	4	0	0
T244	0	2	0	0
T265	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	11644	0	0
T1	865	71	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	78	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	26	0	0
T47	0	47	0	0
T52	0	68	0	0
T53	0	20	0	0
T55	0	96	0	0
T111	0	70	0	0
T244	0	77	0	0
T265	0	13	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988130	0	0
T1	865	462	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	14133	0	0
T1	865	256	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	42	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	40	0	0
T52	0	260	0	0
T53	0	3	0	0
T55	0	216	0	0
T111	0	195	0	0
T244	0	43	0	0
T265	0	50	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	27	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T111	0	2	0	0
T244	0	1	0	0
T265	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6927717	0	0
T1	865	3	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6929586	0	0
T1	865	3	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	27	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T111	0	2	0	0
T244	0	1	0	0
T265	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	27	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T111	0	2	0	0
T244	0	1	0	0
T265	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	27	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T111	0	2	0	0
T244	0	1	0	0
T265	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	27	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T55	0	1	0	0
T111	0	2	0	0
T244	0	1	0	0
T265	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	14087	0	0
T1	865	254	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T13	0	40	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T47	0	38	0	0
T52	0	258	0	0
T53	0	2	0	0
T55	0	214	0	0
T111	0	192	0	0
T188	0	82	0	0
T244	0	41	0	0
T265	0	48	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	4840	0	0
T1	865	1	0	0
T2	506	1	0	0
T3	0	1	0	0
T5	429	2	0	0
T6	430	3	0	0
T14	426	1	0	0
T15	462	1	0	0
T16	726	0	0	0
T18	0	5	0	0
T19	505	4	0	0
T20	418	2	0	0
T21	406	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6	0	0
T44	13545	0	0	0
T111	764	1	0	0
T188	0	1	0	0
T201	0	1	0	0
T203	0	1	0	0
T221	704	0	0	0
T222	405	0	0	0
T223	426	0	0	0
T224	8300	0	0	0
T225	419	0	0	0
T226	507	0	0	0
T227	405	0	0	0
T228	492	0	0	0
T242	0	1	0	0
T257	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T6 T19 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T5 T6 T19 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T48 T49 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T6 T19 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T6 T19 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T6 T19 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T6 T19 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T6 T19 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T6 T19 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T6 T19 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T6 T19 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T48 T49 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T48 T49 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T48 T49 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T48 T49 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T48 T49 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T48 T49 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T48 T49 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T48 T49 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T266 T215 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T48 T49 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T48 T49 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T48 T49 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T111 T254 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T111 T254 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T48 T49 
191        1/1                      state_d = StableSt;
           Tests:       T11 T48 T49 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T48 T49 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T48 T49 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T48 T49 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T48 T49 
206        1/1                    state_d = IdleSt;
           Tests:       T48 T49 T47 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T48 T49 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T19

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T19
1	1	Covered	T5,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T48,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T48,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T48,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T48,T49
1	0	Covered	T5,T6,T19
1	1	Covered	T11,T48,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T48,T49
0	1	Covered	T111,T254
1	0	Covered	T35

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T48,T49
0	1	Covered	T48,T49,T47
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T48,T49
1	-	Covered	T48,T49,T47

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T48,T49
DetectSt	168	Covered	T11,T48,T49
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T48,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T48,T49
DebounceSt->IdleSt	163	Covered	T266,T215
DetectSt->IdleSt	186	Covered	T35,T111,T254
DetectSt->StableSt	191	Covered	T11,T48,T49
IdleSt->DebounceSt	148	Covered	T11,T48,T49
StableSt->IdleSt	206	Covered	T48,T49,T47

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T48,T49
0	1	Covered	T11,T48,T49
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T48,T49
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T48,T49
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T19
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T48,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T266,T215
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T48,T49
DetectSt	-	-	-	-	1	-	-	Covered	T35,T111,T254
DetectSt	-	-	-	-	0	1	-	Covered	T11,T48,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T49,T47
StableSt	-	-	-	-	-	-	0	Covered	T11,T48,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	70	0	0
CntIncr_A	7444491	18298	0	0
CntNoWrap_A	7444491	6988114	0	0
DetectStDropOut_A	7444491	2	0	0
DetectedOut_A	7444491	32971	0	0
DetectedPulseOut_A	7444491	31	0	0
DisabledIdleSt_A	7444491	6885987	0	0
DisabledNoDetection_A	7444491	6887863	0	0
EnterDebounceSt_A	7444491	36	0	0
EnterDetectSt_A	7444491	34	0	0
EnterStableSt_A	7444491	31	0	0
PulseIsPulse_A	7444491	31	0	0
StayInStableSt	7444491	32928	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	70	0	0
T11	630	2	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T50	0	4	0	0
T53	0	2	0	0
T87	487	0	0	0
T96	522	0	0	0
T97	502	0	0	0
T111	0	4	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0
T216	0	2	0	0
T217	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	18298	0	0
T11	630	52	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T35	0	26	0	0
T47	0	47	0	0
T48	0	49	0	0
T49	0	72	0	0
T50	0	122	0	0
T53	0	20	0	0
T87	487	0	0	0
T96	522	0	0	0
T97	502	0	0	0
T111	0	70	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0
T216	0	19	0	0
T217	0	54	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988114	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	2	0	0
T44	13545	0	0	0
T111	764	1	0	0
T221	704	0	0	0
T222	405	0	0	0
T223	426	0	0	0
T224	8300	0	0	0
T225	419	0	0	0
T226	507	0	0	0
T227	405	0	0	0
T228	492	0	0	0
T254	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	32971	0	0
T11	630	164	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T47	0	45	0	0
T48	0	42	0	0
T49	0	22	0	0
T50	0	345	0	0
T53	0	3	0	0
T87	487	0	0	0
T96	522	0	0	0
T97	502	0	0	0
T111	0	91	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0
T186	0	38	0	0
T216	0	74	0	0
T217	0	40	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	31	0	0
T11	630	1	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T87	487	0	0	0
T96	522	0	0	0
T97	502	0	0	0
T111	0	1	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0
T186	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6885987	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6887863	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	36	0	0
T11	630	1	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T87	487	0	0	0
T96	522	0	0	0
T97	502	0	0	0
T111	0	2	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0
T216	0	1	0	0
T217	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	34	0	0
T11	630	1	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T87	487	0	0	0
T96	522	0	0	0
T97	502	0	0	0
T111	0	2	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0
T216	0	1	0	0
T217	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	31	0	0
T11	630	1	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T87	487	0	0	0
T96	522	0	0	0
T97	502	0	0	0
T111	0	1	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0
T186	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	31	0	0
T11	630	1	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T87	487	0	0	0
T96	522	0	0	0
T97	502	0	0	0
T111	0	1	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0
T186	0	1	0	0
T216	0	1	0	0
T217	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	32928	0	0
T11	630	162	0	0
T12	480	0	0	0
T31	608	0	0	0
T32	754	0	0	0
T47	0	44	0	0
T48	0	41	0	0
T49	0	21	0	0
T50	0	342	0	0
T53	0	2	0	0
T87	487	0	0	0
T96	522	0	0	0
T97	502	0	0	0
T111	0	90	0	0
T166	404	0	0	0
T167	422	0	0	0
T168	431	0	0	0
T186	0	36	0	0
T216	0	72	0	0
T217	0	38	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	18	0	0
T47	0	1	0	0
T48	593	1	0	0
T49	620	1	0	0
T50	0	1	0	0
T66	684	0	0	0
T75	1663	0	0	0
T85	1007	0	0	0
T91	498	0	0	0
T111	0	1	0	0
T174	8451	0	0	0
T175	804	0	0	0
T188	0	1	0	0
T201	0	2	0	0
T254	0	1	0	0
T255	0	2	0	0
T257	0	1	0	0
T267	424	0	0	0
T268	717	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	43	93.48
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	29	90.62
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T5 T6 T19 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T48 T49 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T48 T49 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T48 T49 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T48 T49 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T48 T49 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T48 T49 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T48 T49 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T48 T49 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T48 T49 
169                               end else begin
170        0/1     ==>              state_d = IdleSt;
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T48 T49 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T48 T49 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T48 T49 
186        1/1                    state_d = IdleSt;
           Tests:       T116 T201 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T116 T201 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T48 T49 
191        1/1                      state_d = StableSt;
           Tests:       T1 T48 T49 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T48 T49 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T48 T49 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T48 T49 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T48 T49 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T53 T116 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T48 T49 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T48,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T48,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T48,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T13,T48
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T48,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T48,T49
0	1	Covered	T116,T201
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T48,T49
0	1	Covered	T116,T188,T229
1	0	Covered	T35,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T48,T49
1	-	Covered	T116,T188,T229

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T48,T49
DetectSt	168	Covered	T1,T48,T49
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T48,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T48,T49
DebounceSt->IdleSt	163	Not Covered
DetectSt->IdleSt	186	Covered	T116,T201
DetectSt->StableSt	191	Covered	T1,T48,T49
IdleSt->DebounceSt	148	Covered	T1,T48,T49
StableSt->IdleSt	206	Covered	T47,T35,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T48,T49
0	1	Covered	T1,T48,T49
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T48,T49
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T48,T49
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T48,T49
DebounceSt	-	0	1	0	-	-	-	Not Covered
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T48,T49
DetectSt	-	-	-	-	1	-	-	Covered	T116,T201
DetectSt	-	-	-	-	0	1	-	Covered	T1,T48,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T53,T116
StableSt	-	-	-	-	-	-	0	Covered	T1,T48,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	60	0	0
CntIncr_A	7444491	52601	0	0
CntNoWrap_A	7444491	6988124	0	0
DetectStDropOut_A	7444491	2	0	0
DetectedOut_A	7444491	36767	0	0
DetectedPulseOut_A	7444491	28	0	0
DisabledIdleSt_A	7444491	6723718	0	0
DisabledNoDetection_A	7444491	6725584	0	0
EnterDebounceSt_A	7444491	30	0	0
EnterDetectSt_A	7444491	30	0	0
EnterStableSt_A	7444491	28	0	0
PulseIsPulse_A	7444491	28	0	0
StayInStableSt	7444491	36723	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7444491	4834	0	0
gen_low_level_sva.LowLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	60	0	0
T1	865	2	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T48	0	2	0	0
T49	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T116	0	4	0	0
T188	0	2	0	0
T218	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	52601	0	0
T1	865	71	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	26	0	0
T47	0	47	0	0
T48	0	49	0	0
T49	0	72	0	0
T53	0	20	0	0
T54	0	82	0	0
T116	0	38	0	0
T188	0	82	0	0
T218	0	61	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988124	0	0
T1	865	462	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	2	0	0
T41	19844	0	0	0
T42	19913	0	0	0
T58	28743	0	0	0
T103	6666	0	0	0
T104	4966	0	0	0
T105	5316	0	0	0
T116	6059	1	0	0
T130	9623	0	0	0
T201	0	1	0	0
T269	676	0	0	0
T270	44841	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	36767	0	0
T1	865	141	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	2	0	0
T47	0	40	0	0
T48	0	42	0	0
T49	0	43	0	0
T53	0	3	0	0
T54	0	52	0	0
T116	0	49	0	0
T188	0	166	0	0
T218	0	45	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	28	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T116	0	1	0	0
T188	0	1	0	0
T218	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6723718	0	0
T1	865	3	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6725584	0	0
T1	865	3	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	30	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T116	0	2	0	0
T188	0	1	0	0
T218	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	30	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T116	0	2	0	0
T188	0	1	0	0
T218	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	28	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T116	0	1	0	0
T188	0	1	0	0
T218	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	28	0	0
T1	865	1	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T48	0	1	0	0
T49	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T116	0	1	0	0
T188	0	1	0	0
T218	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	36723	0	0
T1	865	139	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T47	0	38	0	0
T48	0	40	0	0
T49	0	41	0	0
T53	0	2	0	0
T54	0	50	0	0
T116	0	48	0	0
T188	0	165	0	0
T218	0	43	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	4834	0	0
T1	865	1	0	0
T2	506	1	0	0
T3	0	1	0	0
T5	429	1	0	0
T6	430	2	0	0
T7	0	2	0	0
T14	426	3	0	0
T15	462	1	0	0
T16	726	0	0	0
T18	0	5	0	0
T19	505	5	0	0
T20	418	0	0	0
T21	406	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	10	0	0
T41	19844	0	0	0
T42	19913	0	0	0
T58	28743	0	0	0
T103	6666	0	0	0
T104	4966	0	0	0
T105	5316	0	0	0
T116	6059	1	0	0
T130	9623	0	0	0
T188	0	1	0	0
T215	0	1	0	0
T229	0	1	0	0
T230	0	1	0	0
T254	0	2	0	0
T257	0	1	0	0
T269	676	0	0	0
T270	44841	0	0	0
T271	0	1	0	0
T272	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T5 T6 T19 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T5 T6 T19 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T7 T11 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T6 T19 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T6 T19 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T6 T19 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T6 T19 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T6 T19 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T6 T19 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T6 T19 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T6 T19 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T7 T11 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T7 T11 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T7 T11 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T7 T11 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T7 T11 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T7 T11 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T7 T11 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T7 T11 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T272 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T7 T11 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T7 T11 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T7 T11 
186        1/1                    state_d = IdleSt;
           Tests:       T111 T201 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T111 T201 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T7 T11 
191        1/1                      state_d = StableSt;
           Tests:       T1 T7 T11 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T7 T11 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T7 T11 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T7 T11 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T7 T11 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T7 T11 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T7 T11 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T5,T6,T19

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T5,T6,T19
1	1	Covered	T5,T6,T19

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T7,T11

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T7,T11
1	0	Covered	T5,T6,T19
1	1	Covered	T1,T7,T11

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T111,T201
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
1	0	Covered	T35,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T11
1	-	Covered	T1,T7,T11

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T7,T11
DetectSt	168	Covered	T1,T7,T11
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T7,T11

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T11
DebounceSt->IdleSt	163	Covered	T272
DetectSt->IdleSt	186	Covered	T111,T201
DetectSt->StableSt	191	Covered	T1,T7,T11
IdleSt->DebounceSt	148	Covered	T1,T7,T11
StableSt->IdleSt	206	Covered	T1,T7,T11

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T7,T11
0	1	Covered	T1,T7,T11
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T11
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T7,T11
IdleSt	0	-	-	-	-	-	-	Covered	T5,T6,T19
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T11
DebounceSt	-	0	1	0	-	-	-	Covered	T272
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T7,T11
DetectSt	-	-	-	-	1	-	-	Covered	T111,T201
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T11
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T11
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T11
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	71	0	0
CntIncr_A	7444491	71346	0	0
CntNoWrap_A	7444491	6988113	0	0
DetectStDropOut_A	7444491	2	0	0
DetectedOut_A	7444491	22664	0	0
DetectedPulseOut_A	7444491	33	0	0
DisabledIdleSt_A	7444491	6817082	0	0
DisabledNoDetection_A	7444491	6818948	0	0
EnterDebounceSt_A	7444491	36	0	0
EnterDetectSt_A	7444491	35	0	0
EnterStableSt_A	7444491	33	0	0
PulseIsPulse_A	7444491	33	0	0
StayInStableSt	7444491	22620	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	20	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	71	0	0
T1	865	4	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	2	0	0
T8	1193	0	0	0
T11	0	2	0	0
T13	0	2	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	2	0	0
T48	0	2	0	0
T50	0	4	0	0
T53	0	2	0	0
T55	0	2	0	0
T116	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	71346	0	0
T1	865	142	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	41	0	0
T8	1193	0	0	0
T11	0	52	0	0
T13	0	78	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	26	0	0
T48	0	49	0	0
T50	0	122	0	0
T53	0	20	0	0
T55	0	96	0	0
T116	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988113	0	0
T1	865	460	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	2	0	0
T44	13545	0	0	0
T111	764	1	0	0
T201	0	1	0	0
T221	704	0	0	0
T222	405	0	0	0
T223	426	0	0	0
T224	8300	0	0	0
T225	419	0	0	0
T226	507	0	0	0
T227	405	0	0	0
T228	492	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	22664	0	0
T1	865	78	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	82	0	0
T8	1193	0	0	0
T11	0	71	0	0
T13	0	66	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T48	0	43	0	0
T50	0	189	0	0
T53	0	4	0	0
T55	0	43	0	0
T116	0	101	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	33	0	0
T1	865	2	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	1	0	0
T8	1193	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T116	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6817082	0	0
T1	865	3	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6818948	0	0
T1	865	3	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	36	0	0
T1	865	2	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	1	0	0
T8	1193	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T116	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	35	0	0
T1	865	2	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	1	0	0
T8	1193	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T116	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	33	0	0
T1	865	2	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	1	0	0
T8	1193	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T116	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	33	0	0
T1	865	2	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	1	0	0
T8	1193	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T48	0	1	0	0
T50	0	2	0	0
T53	0	1	0	0
T55	0	1	0	0
T116	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	22620	0	0
T1	865	76	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	81	0	0
T8	1193	0	0	0
T11	0	70	0	0
T13	0	65	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T48	0	41	0	0
T50	0	186	0	0
T53	0	3	0	0
T55	0	41	0	0
T111	0	77	0	0
T116	0	99	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	20	0	0
T1	865	2	0	0
T2	506	0	0	0
T3	487	0	0	0
T7	830	1	0	0
T8	1193	0	0	0
T11	0	1	0	0
T13	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T50	0	1	0	0
T111	0	1	0	0
T116	0	2	0	0
T196	0	2	0	0
T232	0	1	0	0
T255	0	2	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T5 T6 T19 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T7 T13 T47 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T7 T13 T47 
149        1/1                    cnt_en = 1'b1;
           Tests:       T7 T13 T47 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T7 T13 T47 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T7 T13 T47 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T7 T13 T47 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T7 T13 T47 
167        1/1                    if (trigger_active) begin
           Tests:       T7 T13 T47 
168        1/1                      state_d = DetectSt;
           Tests:       T7 T13 T47 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T116 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T7 T13 T47 
182        1/1                  cnt_en = 1'b1;
           Tests:       T7 T13 T47 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T7 T13 T47 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T7 T13 T47 
191        1/1                      state_d = StableSt;
           Tests:       T7 T13 T47 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T7 T13 T47 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T7 T13 T47 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T7 T13 T47 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T7 T13 T47 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T52 T273 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T7 T13 T47 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T5,T6,T19
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T5,T6,T19
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T13,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T13,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T13,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T13,T49
1	0	Covered	T5,T6,T19
1	1	Covered	T7,T13,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T13,T47
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T13,T47
0	1	Covered	T52,T273,T111
1	0	Covered	T35,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T13,T47
1	-	Covered	T52,T273,T111

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T13,T47
DetectSt	168	Covered	T7,T13,T47
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T13,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T13,T47
DebounceSt->IdleSt	163	Covered	T116
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T7,T13,T47
IdleSt->DebounceSt	148	Covered	T7,T13,T47
StableSt->IdleSt	206	Covered	T47,T35,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T13,T47
0	1	Covered	T7,T13,T47
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T13,T47
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T13,T47
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T13,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T116
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T13,T47
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T7,T13,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T35,T52,T273
StableSt	-	-	-	-	-	-	0	Covered	T7,T13,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	59	0	0
CntIncr_A	7444491	87070	0	0
CntNoWrap_A	7444491	6988125	0	0
DetectStDropOut_A	7444491	0	0	0
DetectedOut_A	7444491	16529	0	0
DetectedPulseOut_A	7444491	29	0	0
DisabledIdleSt_A	7444491	6723600	0	0
DisabledNoDetection_A	7444491	6725466	0	0
EnterDebounceSt_A	7444491	30	0	0
EnterDetectSt_A	7444491	29	0	0
EnterStableSt_A	7444491	29	0	0
PulseIsPulse_A	7444491	29	0	0
StayInStableSt	7444491	16484	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	7444491	5272	0	0
gen_low_level_sva.LowLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	59	0	0
T7	830	2	0	0
T8	1193	0	0	0
T13	0	2	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	2	0	0
T47	0	2	0	0
T52	0	4	0	0
T53	0	2	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	3	0	0
T214	0	2	0	0
T216	0	2	0	0
T273	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	87070	0	0
T7	830	41	0	0
T8	1193	0	0	0
T13	0	78	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	26	0	0
T47	0	47	0	0
T52	0	136	0	0
T53	0	20	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	38	0	0
T214	0	22	0	0
T216	0	19	0	0
T273	0	36	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6988125	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	16529	0	0
T7	830	256	0	0
T8	1193	0	0	0
T13	0	41	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	2	0	0
T47	0	39	0	0
T52	0	190	0	0
T53	0	5	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	52	0	0
T214	0	42	0	0
T216	0	47	0	0
T273	0	101	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	29	0	0
T7	830	1	0	0
T8	1193	0	0	0
T13	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	1	0	0
T214	0	1	0	0
T216	0	1	0	0
T273	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6723600	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6725466	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	30	0	0
T7	830	1	0	0
T8	1193	0	0	0
T13	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	2	0	0
T214	0	1	0	0
T216	0	1	0	0
T273	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	29	0	0
T7	830	1	0	0
T8	1193	0	0	0
T13	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	1	0	0
T214	0	1	0	0
T216	0	1	0	0
T273	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	29	0	0
T7	830	1	0	0
T8	1193	0	0	0
T13	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	1	0	0
T214	0	1	0	0
T216	0	1	0	0
T273	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	29	0	0
T7	830	1	0	0
T8	1193	0	0	0
T13	0	1	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	1	0	0
T52	0	2	0	0
T53	0	1	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	1	0	0
T214	0	1	0	0
T216	0	1	0	0
T273	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	16484	0	0
T7	830	254	0	0
T8	1193	0	0	0
T13	0	39	0	0
T27	496	0	0	0
T30	524	0	0	0
T35	0	1	0	0
T47	0	37	0	0
T52	0	187	0	0
T53	0	4	0	0
T60	431	0	0	0
T61	438	0	0	0
T78	4414	0	0	0
T79	528	0	0	0
T80	510	0	0	0
T81	679	0	0	0
T116	0	50	0	0
T214	0	40	0	0
T216	0	45	0	0
T273	0	100	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	5272	0	0
T1	865	2	0	0
T2	506	0	0	0
T5	429	2	0	0
T6	430	4	0	0
T7	0	1	0	0
T8	0	6	0	0
T14	426	1	0	0
T15	462	0	0	0
T16	726	3	0	0
T18	0	6	0	0
T19	505	5	0	0
T20	418	1	0	0
T21	406	0	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	11	0	0
T36	18914	0	0	0
T52	1083	1	0	0
T76	1158	0	0	0
T77	3051	0	0	0
T111	0	2	0	0
T193	2932	0	0	0
T219	0	1	0	0
T229	0	1	0	0
T231	0	1	0	0
T242	0	1	0	0
T255	0	1	0	0
T272	0	1	0	0
T273	763	1	0	0
T274	0	1	0	0
T275	407	0	0	0
T276	694	0	0	0
T277	862	0	0	0
T278	467	0	0	0