Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T35 T36 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T15 T33 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T2 T15 T33 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T2 T15 T33 
129        1/1              cnt_en = 1'b0;
           Tests:       T2 T15 T33 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T2 T15 T33 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T2 T15 T33 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T2 T15 T33 
139                     
140        1/1              unique case (state_q)
           Tests:       T2 T15 T33 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T2 T15 T33 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T15 T33 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T15 T33 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T15 T33 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T15 T33 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T15 T33 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T15 T33 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T15 T33 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T15 T33 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T35 T59 T53 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T15 T33 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T15 T33 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T15 T33 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T102 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T102 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T15 T33 
191        1/1                      state_d = StableSt;
           Tests:       T2 T15 T33 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T15 T33 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T15 T33 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T15 T33 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T15 T33 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T53 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T15 T33 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T33

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T33

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T33

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T36,T53
1	1	Covered	T2,T15,T33

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T33
0	1	Covered	T34,T35,T102
1	0	Covered	T35,T224,T115

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T15,T33
0	1	Covered	T35,T36,T53
1	0	Covered	T53,T279

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T15,T33
1	-	Covered	T35,T36,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T15,T33
DetectSt	168	Covered	T2,T15,T33
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T15,T33

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T15,T33
DebounceSt->IdleSt	163	Covered	T35,T59,T53
DetectSt->IdleSt	186	Covered	T34,T35,T102
DetectSt->StableSt	191	Covered	T2,T15,T33
IdleSt->DebounceSt	148	Covered	T2,T15,T33
StableSt->IdleSt	206	Covered	T35,T36,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T33
0	1	Covered	T2,T15,T33
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T15,T33
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T15,T33
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T15,T33
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T59,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T15,T33
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T102
DetectSt	-	-	-	-	0	1	-	Covered	T2,T15,T33
DetectSt	-	-	-	-	0	0	-	Covered	T2,T15,T33
StableSt	-	-	-	-	-	-	1	Covered	T35,T36,T53
StableSt	-	-	-	-	-	-	0	Covered	T2,T15,T33
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	2936	0	0
CntIncr_A	7444491	100432	0	0
CntNoWrap_A	7444491	6985248	0	0
DetectStDropOut_A	7444491	408	0	0
DetectedOut_A	7444491	67112	0	0
DetectedPulseOut_A	7444491	846	0	0
DisabledIdleSt_A	7444491	6561662	0	0
DisabledNoDetection_A	7444491	6563383	0	0
EnterDebounceSt_A	7444491	1498	0	0
EnterDetectSt_A	7444491	1440	0	0
EnterStableSt_A	7444491	846	0	0
PulseIsPulse_A	7444491	846	0	0
StayInStableSt	7444491	66178	0	0
gen_high_event_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	753	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	2936	0	0
T2	506	2	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	2	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	2	0	0
T34	0	38	0	0
T35	0	16	0	0
T36	0	10	0	0
T53	0	15	0	0
T59	0	4	0	0
T60	431	0	0	0
T62	0	2	0	0
T101	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	100432	0	0
T2	506	21	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	21	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	21	0	0
T34	0	993	0	0
T35	0	362	0	0
T36	0	235	0	0
T53	0	285	0	0
T59	0	344	0	0
T60	431	0	0	0
T62	0	21	0	0
T101	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6985248	0	0
T1	865	464	0	0
T2	506	103	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	59	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	408	0	0
T34	5270	19	0	0
T35	0	1	0	0
T50	982	0	0	0
T51	640	0	0	0
T70	1176	0	0	0
T71	417	0	0	0
T72	1861	0	0	0
T73	408	0	0	0
T74	522	0	0	0
T102	0	18	0	0
T103	0	7	0	0
T104	0	9	0	0
T105	0	22	0	0
T106	556	0	0	0
T107	1649	0	0	0
T130	0	27	0	0
T131	0	6	0	0
T132	0	8	0	0
T134	0	11	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	67112	0	0
T2	506	80	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	37	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	37	0	0
T35	0	346	0	0
T36	0	676	0	0
T42	0	546	0	0
T53	0	405	0	0
T60	431	0	0	0
T62	0	37	0	0
T101	0	29	0	0
T118	0	2293	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	846	0	0
T2	506	1	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	1	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	1	0	0
T35	0	5	0	0
T36	0	5	0	0
T42	0	19	0	0
T53	0	5	0	0
T60	431	0	0	0
T62	0	1	0	0
T101	0	1	0	0
T118	0	26	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6561662	0	0
T1	865	464	0	0
T2	506	4	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	3	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6563383	0	0
T1	865	465	0	0
T2	506	4	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	3	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	1498	0	0
T2	506	1	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	1	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	1	0	0
T34	0	19	0	0
T35	0	9	0	0
T36	0	5	0	0
T53	0	10	0	0
T59	0	4	0	0
T60	431	0	0	0
T62	0	1	0	0
T101	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	1440	0	0
T2	506	1	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	1	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	1	0	0
T34	0	19	0	0
T35	0	7	0	0
T36	0	5	0	0
T53	0	5	0	0
T60	431	0	0	0
T62	0	1	0	0
T101	0	1	0	0
T102	0	18	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	846	0	0
T2	506	1	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	1	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	1	0	0
T35	0	5	0	0
T36	0	5	0	0
T42	0	19	0	0
T53	0	5	0	0
T60	431	0	0	0
T62	0	1	0	0
T101	0	1	0	0
T118	0	26	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	846	0	0
T2	506	1	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	1	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	1	0	0
T35	0	5	0	0
T36	0	5	0	0
T42	0	19	0	0
T53	0	5	0	0
T60	431	0	0	0
T62	0	1	0	0
T101	0	1	0	0
T118	0	26	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	66178	0	0
T2	506	78	0	0
T3	487	0	0	0
T7	830	0	0	0
T8	1193	0	0	0
T14	426	0	0	0
T15	462	35	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	35	0	0
T35	0	341	0	0
T36	0	670	0	0
T42	0	526	0	0
T53	0	400	0	0
T60	431	0	0	0
T62	0	35	0	0
T101	0	27	0	0
T118	0	2263	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	753	0	0
T35	6681	5	0	0
T36	0	4	0	0
T42	0	18	0	0
T53	0	4	0	0
T92	493	0	0	0
T93	493	0	0	0
T118	0	22	0	0
T119	0	6	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T148	0	7	0	0
T154	0	11	0	0
T200	422	0	0	0
T280	0	3	0	0
T281	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T2 T15 T3 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T15 T3 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T15 T3 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T15 T3 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T15 T3 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T15 T3 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T15 T3 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T15 T3 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T15 T3 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T3 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T15 T60 T61 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T3 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T3 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T3 T12 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T53 T135 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 T135 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T3 T12 
191        1/1                      state_d = StableSt;
           Tests:       T2 T3 T12 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T3 T12 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T3 T12 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T3 T12 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T3 T12 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T3 T12 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T3 T12 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T2,T15,T3
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T3
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T3

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T15,T3

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T3,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T15,T3
1	0	Covered	T78,T113,T64
1	1	Covered	T2,T15,T3

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T12
0	1	Covered	T135,T137,T138
1	0	Covered	T35,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T3,T12
0	1	Covered	T2,T3,T12
1	0	Covered	T35,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T3,T12
1	-	Covered	T2,T3,T12

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T15,T3
DetectSt	168	Covered	T2,T3,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T3,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T3,T12
DebounceSt->IdleSt	163	Covered	T15,T60,T61
DetectSt->IdleSt	186	Covered	T35,T53,T135
DetectSt->StableSt	191	Covered	T2,T3,T12
IdleSt->DebounceSt	148	Covered	T2,T15,T3
StableSt->IdleSt	206	Covered	T2,T3,T12

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T15,T3
0	1	Covered	T2,T15,T3
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T3,T12
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T15,T3
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T3,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T60,T61
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T15,T3
DetectSt	-	-	-	-	1	-	-	Covered	T35,T53,T135
DetectSt	-	-	-	-	0	1	-	Covered	T2,T3,T12
DetectSt	-	-	-	-	0	0	-	Covered	T2,T3,T12
StableSt	-	-	-	-	-	-	1	Covered	T2,T3,T12
StableSt	-	-	-	-	-	-	0	Covered	T2,T3,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	747	0	0
CntIncr_A	7444491	40379	0	0
CntNoWrap_A	7444491	6987437	0	0
DetectStDropOut_A	7444491	39	0	0
DetectedOut_A	7444491	12763	0	0
DetectedPulseOut_A	7444491	305	0	0
DisabledIdleSt_A	7444491	6675031	0	0
DisabledNoDetection_A	7444491	6676346	0	0
EnterDebounceSt_A	7444491	399	0	0
EnterDetectSt_A	7444491	348	0	0
EnterStableSt_A	7444491	305	0	0
PulseIsPulse_A	7444491	305	0	0
StayInStableSt	7444491	12432	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	276	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	747	0	0
T2	506	2	0	0
T3	487	2	0	0
T7	830	0	0	0
T8	1193	0	0	0
T12	0	2	0	0
T14	426	0	0	0
T15	462	1	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	1	0	0
T60	431	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	40379	0	0
T2	506	25	0	0
T3	487	25	0	0
T7	830	0	0	0
T8	1193	0	0	0
T12	0	25	0	0
T14	426	0	0	0
T15	462	20	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	20	0	0
T60	431	20	0	0
T61	0	20	0	0
T62	0	20	0	0
T63	0	20	0	0
T64	0	20	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6987437	0	0
T1	865	464	0	0
T2	506	103	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	60	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	39	0	0
T135	17228	6	0	0
T137	0	5	0	0
T138	0	4	0	0
T139	0	4	0	0
T140	0	5	0	0
T141	0	9	0	0
T142	0	6	0	0
T143	1175	0	0	0
T144	507	0	0	0
T145	422	0	0	0
T146	418	0	0	0
T147	522	0	0	0
T148	13816	0	0	0
T149	496	0	0	0
T150	424	0	0	0
T151	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	12763	0	0
T2	506	3	0	0
T3	487	3	0	0
T7	830	0	0	0
T8	1193	0	0	0
T12	0	3	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	80	0	0
T36	0	48	0	0
T47	0	3	0	0
T56	0	6	0	0
T60	431	0	0	0
T129	0	3	0	0
T159	0	3	0	0
T161	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	305	0	0
T2	506	1	0	0
T3	487	1	0	0
T7	830	0	0	0
T8	1193	0	0	0
T12	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T47	0	1	0	0
T56	0	1	0	0
T60	431	0	0	0
T129	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6675031	0	0
T1	865	464	0	0
T2	506	26	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	25	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6676346	0	0
T1	865	465	0	0
T2	506	26	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	25	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	399	0	0
T2	506	1	0	0
T3	487	1	0	0
T7	830	0	0	0
T8	1193	0	0	0
T12	0	1	0	0
T14	426	0	0	0
T15	462	1	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T33	0	1	0	0
T60	431	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	348	0	0
T2	506	1	0	0
T3	487	1	0	0
T7	830	0	0	0
T8	1193	0	0	0
T12	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	3	0	0
T36	0	1	0	0
T47	0	1	0	0
T56	0	1	0	0
T60	431	0	0	0
T129	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	305	0	0
T2	506	1	0	0
T3	487	1	0	0
T7	830	0	0	0
T8	1193	0	0	0
T12	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T47	0	1	0	0
T56	0	1	0	0
T60	431	0	0	0
T129	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	305	0	0
T2	506	1	0	0
T3	487	1	0	0
T7	830	0	0	0
T8	1193	0	0	0
T12	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	1	0	0
T36	0	1	0	0
T47	0	1	0	0
T56	0	1	0	0
T60	431	0	0	0
T129	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	12432	0	0
T2	506	2	0	0
T3	487	2	0	0
T7	830	0	0	0
T8	1193	0	0	0
T12	0	2	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T35	0	79	0	0
T36	0	47	0	0
T47	0	2	0	0
T56	0	5	0	0
T60	431	0	0	0
T129	0	2	0	0
T159	0	2	0	0
T161	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	276	0	0
T2	506	1	0	0
T3	487	1	0	0
T7	830	0	0	0
T8	1193	0	0	0
T12	0	1	0	0
T14	426	0	0	0
T15	462	0	0	0
T16	726	0	0	0
T17	404	0	0	0
T18	507	0	0	0
T36	0	1	0	0
T41	0	2	0	0
T47	0	1	0	0
T56	0	1	0	0
T60	431	0	0	0
T129	0	1	0	0
T159	0	1	0	0
T161	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T35 T36 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T35 T36 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T34 T35 T36 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T34 T35 T36 
129        1/1              cnt_en = 1'b0;
           Tests:       T34 T35 T36 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T34 T35 T36 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T34 T35 T36 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T34 T35 T36 
139                     
140        1/1              unique case (state_q)
           Tests:       T34 T35 T36 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T34 T35 T36 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T35 T36 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T35 T36 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T35 T36 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T35 T36 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T35 T36 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T35 T36 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T35 T59 T53 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T35 T36 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T35 T36 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T53 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T53 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T35 T36 
191        1/1                      state_d = StableSt;
           Tests:       T35 T36 T59 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T35 T36 T59 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T35 T36 T59 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T35 T36 T59 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T35 T36 T59 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T59 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T35 T36 T59 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T36,T53
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T34,T35,T53
1	0	Covered	T35,T53,T118

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T59
0	1	Covered	T35,T36,T59
1	0	Covered	T120,T282,T283

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T59
1	-	Covered	T35,T36,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T36,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T35,T59,T53
DetectSt->IdleSt	186	Covered	T34,T35,T53
DetectSt->StableSt	191	Covered	T35,T36,T59
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T35,T36,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T59,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T53
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T59
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	1	Covered	T35,T36,T59
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	2889	0	0
CntIncr_A	7444491	99771	0	0
CntNoWrap_A	7444491	6985295	0	0
DetectStDropOut_A	7444491	409	0	0
DetectedOut_A	7444491	66749	0	0
DetectedPulseOut_A	7444491	755	0	0
DisabledIdleSt_A	7444491	6561953	0	0
DisabledNoDetection_A	7444491	6563663	0	0
EnterDebounceSt_A	7444491	1469	0	0
EnterDetectSt_A	7444491	1421	0	0
EnterStableSt_A	7444491	755	0	0
PulseIsPulse_A	7444491	755	0	0
StayInStableSt	7444491	65893	0	0
gen_high_event_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	633	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	2889	0	0
T34	5270	48	0	0
T35	0	16	0	0
T36	0	32	0	0
T42	0	34	0	0
T50	982	0	0	0
T51	640	0	0	0
T53	0	16	0	0
T59	0	11	0	0
T70	1176	0	0	0
T71	417	0	0	0
T72	1861	0	0	0
T73	408	0	0	0
T74	522	0	0	0
T102	0	30	0	0
T103	0	13	0	0
T104	0	21	0	0
T105	0	50	0	0
T106	556	0	0	0
T107	1649	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	99771	0	0
T34	5270	1275	0	0
T35	0	432	0	0
T36	0	688	0	0
T42	0	595	0	0
T50	982	0	0	0
T51	640	0	0	0
T53	0	554	0	0
T59	0	878	0	0
T70	1176	0	0	0
T71	417	0	0	0
T72	1861	0	0	0
T73	408	0	0	0
T74	522	0	0	0
T102	0	772	0	0
T103	0	2206	0	0
T104	0	613	0	0
T105	0	1353	0	0
T106	556	0	0	0
T107	1649	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6985295	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	409	0	0
T34	5270	24	0	0
T35	0	1	0	0
T50	982	0	0	0
T51	640	0	0	0
T53	0	1	0	0
T70	1176	0	0	0
T71	417	0	0	0
T72	1861	0	0	0
T73	408	0	0	0
T74	522	0	0	0
T102	0	15	0	0
T103	0	4	0	0
T104	0	8	0	0
T105	0	25	0	0
T106	556	0	0	0
T107	1649	0	0	0
T118	0	9	0	0
T130	0	27	0	0
T284	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	66749	0	0
T35	6681	344	0	0
T36	0	1049	0	0
T42	0	1125	0	0
T53	0	328	0	0
T59	0	11	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	362	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T131	0	20	0	0
T132	0	696	0	0
T200	422	0	0	0
T280	0	3608	0	0
T285	0	270	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	755	0	0
T35	6681	5	0	0
T36	0	16	0	0
T42	0	17	0	0
T53	0	5	0	0
T59	0	1	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	12	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T131	0	3	0	0
T132	0	4	0	0
T200	422	0	0	0
T280	0	30	0	0
T285	0	17	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6561953	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6563663	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	1469	0	0
T34	5270	24	0	0
T35	0	9	0	0
T36	0	16	0	0
T42	0	17	0	0
T50	982	0	0	0
T51	640	0	0	0
T53	0	9	0	0
T59	0	10	0	0
T70	1176	0	0	0
T71	417	0	0	0
T72	1861	0	0	0
T73	408	0	0	0
T74	522	0	0	0
T102	0	15	0	0
T103	0	9	0	0
T104	0	13	0	0
T105	0	25	0	0
T106	556	0	0	0
T107	1649	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	1421	0	0
T34	5270	24	0	0
T35	0	7	0	0
T36	0	16	0	0
T42	0	17	0	0
T50	982	0	0	0
T51	640	0	0	0
T53	0	7	0	0
T59	0	1	0	0
T70	1176	0	0	0
T71	417	0	0	0
T72	1861	0	0	0
T73	408	0	0	0
T74	522	0	0	0
T102	0	15	0	0
T103	0	4	0	0
T104	0	8	0	0
T105	0	25	0	0
T106	556	0	0	0
T107	1649	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	755	0	0
T35	6681	5	0	0
T36	0	16	0	0
T42	0	17	0	0
T53	0	5	0	0
T59	0	1	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	12	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T131	0	3	0	0
T132	0	4	0	0
T200	422	0	0	0
T280	0	30	0	0
T285	0	17	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	755	0	0
T35	6681	5	0	0
T36	0	16	0	0
T42	0	17	0	0
T53	0	5	0	0
T59	0	1	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	12	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T131	0	3	0	0
T132	0	4	0	0
T200	422	0	0	0
T280	0	30	0	0
T285	0	17	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	65893	0	0
T35	6681	339	0	0
T36	0	1031	0	0
T42	0	1106	0	0
T53	0	323	0	0
T59	0	10	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	350	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T131	0	17	0	0
T132	0	690	0	0
T200	422	0	0	0
T280	0	3566	0	0
T285	0	253	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	633	0	0
T35	6681	5	0	0
T36	0	14	0	0
T42	0	15	0	0
T53	0	5	0	0
T59	0	1	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	12	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T131	0	3	0	0
T132	0	2	0	0
T200	422	0	0	0
T280	0	18	0	0
T285	0	17	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T35 T36 T56 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T35 T56 T53 
149        1/1                    cnt_en = 1'b1;
           Tests:       T35 T56 T53 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T35 T56 T53 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T35 T56 T53 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T35 T56 T53 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T56 T53 
167        1/1                    if (trigger_active) begin
           Tests:       T35 T56 T53 
168        1/1                      state_d = DetectSt;
           Tests:       T35 T56 T53 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T46 T286 T135 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T35 T56 T53 
182        1/1                  cnt_en = 1'b1;
           Tests:       T35 T56 T53 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T35 T56 T53 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T53 T57 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 T57 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T35 T56 T53 
191        1/1                      state_d = StableSt;
           Tests:       T35 T56 T53 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T35 T56 T53 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T35 T56 T53 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T35 T56 T53 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T35 T56 T53 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T56 T53 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T35 T56 T53 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T56,T53

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T56,T53

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T56,T53

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T56
1	0	Covered	T78,T113,T64
1	1	Covered	T35,T56,T53

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T56,T53
0	1	Covered	T57,T58,T133
1	0	Covered	T35,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T56,T53
0	1	Covered	T56,T40,T41
1	0	Covered	T35,T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T56,T53
1	-	Covered	T56,T40,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T56,T53
DetectSt	168	Covered	T35,T56,T53
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T56,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T56,T53
DebounceSt->IdleSt	163	Covered	T35,T53,T46
DetectSt->IdleSt	186	Covered	T35,T53,T57
DetectSt->StableSt	191	Covered	T35,T56,T53
IdleSt->DebounceSt	148	Covered	T35,T56,T53
StableSt->IdleSt	206	Covered	T35,T56,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T56,T53
0	1	Covered	T35,T56,T53
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T56,T53
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T56,T53
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T56,T53
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T286,T135
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T56,T53
DetectSt	-	-	-	-	1	-	-	Covered	T35,T53,T57
DetectSt	-	-	-	-	0	1	-	Covered	T35,T56,T53
DetectSt	-	-	-	-	0	0	-	Covered	T35,T56,T53
StableSt	-	-	-	-	-	-	1	Covered	T35,T56,T53
StableSt	-	-	-	-	-	-	0	Covered	T35,T56,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	652	0	0
CntIncr_A	7444491	37179	0	0
CntNoWrap_A	7444491	6987532	0	0
DetectStDropOut_A	7444491	58	0	0
DetectedOut_A	7444491	9705	0	0
DetectedPulseOut_A	7444491	246	0	0
DisabledIdleSt_A	7444491	6672573	0	0
DisabledNoDetection_A	7444491	6673903	0	0
EnterDebounceSt_A	7444491	344	0	0
EnterDetectSt_A	7444491	309	0	0
EnterStableSt_A	7444491	246	0	0
PulseIsPulse_A	7444491	246	0	0
StayInStableSt	7444491	9424	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	209	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	652	0	0
T35	6681	8	0	0
T40	0	2	0	0
T41	0	2	0	0
T42	0	6	0	0
T43	0	2	0	0
T53	0	8	0	0
T56	0	6	0	0
T57	0	18	0	0
T58	0	12	0	0
T92	493	0	0	0
T93	493	0	0	0
T114	0	4	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T200	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	37179	0	0
T35	6681	196	0	0
T40	0	84	0	0
T41	0	172	0	0
T42	0	195	0	0
T43	0	91	0	0
T53	0	164	0	0
T56	0	435	0	0
T57	0	1030	0	0
T58	0	877	0	0
T92	493	0	0	0
T93	493	0	0	0
T114	0	244	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T200	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6987532	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	58	0	0
T40	8619	0	0	0
T57	9681	9	0	0
T58	0	6	0	0
T133	0	5	0	0
T137	0	7	0	0
T140	0	2	0	0
T216	502	0	0	0
T287	0	11	0	0
T288	0	1	0	0
T289	0	14	0	0
T290	0	3	0	0
T291	26204	0	0	0
T292	520	0	0	0
T293	409	0	0	0
T294	510	0	0	0
T295	527	0	0	0
T296	405	0	0	0
T297	436	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	9705	0	0
T35	6681	79	0	0
T40	0	70	0	0
T41	0	29	0	0
T42	0	173	0	0
T43	0	68	0	0
T44	0	156	0	0
T45	0	130	0	0
T53	0	95	0	0
T56	0	65	0	0
T92	493	0	0	0
T93	493	0	0	0
T114	0	141	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T200	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	246	0	0
T35	6681	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	6	0	0
T53	0	1	0	0
T56	0	3	0	0
T92	493	0	0	0
T93	493	0	0	0
T114	0	2	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T200	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6672573	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6673903	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	344	0	0
T35	6681	5	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T53	0	5	0	0
T56	0	3	0	0
T57	0	9	0	0
T58	0	6	0	0
T92	493	0	0	0
T93	493	0	0	0
T114	0	2	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T200	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	309	0	0
T35	6681	3	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T53	0	3	0	0
T56	0	3	0	0
T57	0	9	0	0
T58	0	6	0	0
T92	493	0	0	0
T93	493	0	0	0
T114	0	2	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T200	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	246	0	0
T35	6681	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	6	0	0
T53	0	1	0	0
T56	0	3	0	0
T92	493	0	0	0
T93	493	0	0	0
T114	0	2	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T200	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	246	0	0
T35	6681	1	0	0
T40	0	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	6	0	0
T53	0	1	0	0
T56	0	3	0	0
T92	493	0	0	0
T93	493	0	0	0
T114	0	2	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T200	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	9424	0	0
T35	6681	78	0	0
T40	0	69	0	0
T41	0	28	0	0
T42	0	170	0	0
T43	0	67	0	0
T44	0	154	0	0
T45	0	124	0	0
T53	0	94	0	0
T56	0	62	0	0
T92	493	0	0	0
T93	493	0	0	0
T114	0	139	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T200	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	209	0	0
T40	8619	1	0	0
T41	0	1	0	0
T42	0	3	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	6	0	0
T46	0	1	0	0
T53	6728	0	0	0
T56	12687	3	0	0
T57	9681	0	0	0
T59	5418	0	0	0
T102	5218	0	0	0
T114	0	2	0	0
T194	103912	0	0	0
T195	8410	0	0	0
T291	26204	0	0	0
T292	520	0	0	0
T298	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T35 T36 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T35 T36 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T34 T35 T36 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T34 T35 T36 
129        1/1              cnt_en = 1'b0;
           Tests:       T34 T35 T36 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T34 T35 T36 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T34 T35 T36 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T34 T35 T36 
139                     
140        1/1              unique case (state_q)
           Tests:       T34 T35 T36 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T34 T35 T36 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T35 T36 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T35 T36 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T35 T36 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T35 T36 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T35 T36 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T35 T36 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T35 T59 T53 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T35 T36 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T35 T36 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T59 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T59 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T35 T36 
191        1/1                      state_d = StableSt;
           Tests:       T35 T36 T53 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T35 T36 T53 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T35 T36 T53 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T35 T36 T53 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T35 T36 T53 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T53 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T35 T36 T53 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T35,T36,T53
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T34,T35,T59
1	0	Covered	T35,T53,T118

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T53
0	1	Covered	T35,T36,T53
1	0	Covered	T53

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T53
1	-	Covered	T35,T36,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T36,T53

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T35,T59,T53
DetectSt->IdleSt	186	Covered	T34,T35,T59
DetectSt->StableSt	191	Covered	T35,T36,T53
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T35,T36,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T35,T59,T53
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T59
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T53
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	1	Covered	T35,T36,T53
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T53
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	2964	0	0
CntIncr_A	7444491	101874	0	0
CntNoWrap_A	7444491	6985220	0	0
DetectStDropOut_A	7444491	350	0	0
DetectedOut_A	7444491	79097	0	0
DetectedPulseOut_A	7444491	897	0	0
DisabledIdleSt_A	7444491	6553497	0	0
DisabledNoDetection_A	7444491	6555197	0	0
EnterDebounceSt_A	7444491	1511	0	0
EnterDetectSt_A	7444491	1454	0	0
EnterStableSt_A	7444491	897	0	0
PulseIsPulse_A	7444491	897	0	0
StayInStableSt	7444491	78089	0	0
gen_high_event_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	785	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	2964	0	0
T34	5270	26	0	0
T35	0	16	0	0
T36	0	52	0	0
T42	0	58	0	0
T50	982	0	0	0
T51	640	0	0	0
T53	0	16	0	0
T59	0	23	0	0
T70	1176	0	0	0
T71	417	0	0	0
T72	1861	0	0	0
T73	408	0	0	0
T74	522	0	0	0
T102	0	24	0	0
T103	0	19	0	0
T104	0	57	0	0
T105	0	60	0	0
T106	556	0	0	0
T107	1649	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	101874	0	0
T34	5270	685	0	0
T35	0	418	0	0
T36	0	1820	0	0
T42	0	1711	0	0
T50	982	0	0	0
T51	640	0	0	0
T53	0	351	0	0
T59	0	1472	0	0
T70	1176	0	0	0
T71	417	0	0	0
T72	1861	0	0	0
T73	408	0	0	0
T74	522	0	0	0
T102	0	620	0	0
T103	0	3191	0	0
T104	0	1514	0	0
T105	0	1628	0	0
T106	556	0	0	0
T107	1649	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6985220	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	350	0	0
T34	5270	13	0	0
T35	0	1	0	0
T50	982	0	0	0
T51	640	0	0	0
T53	0	1	0	0
T59	0	9	0	0
T70	1176	0	0	0
T71	417	0	0	0
T72	1861	0	0	0
T73	408	0	0	0
T74	522	0	0	0
T102	0	12	0	0
T103	0	6	0	0
T104	0	25	0	0
T105	0	30	0	0
T106	556	0	0	0
T107	1649	0	0	0
T119	0	8	0	0
T131	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	79097	0	0
T35	6681	344	0	0
T36	0	1284	0	0
T42	0	1644	0	0
T53	0	389	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	1841	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	821	0	0
T131	0	5	0	0
T132	0	442	0	0
T200	422	0	0	0
T224	0	1210	0	0
T280	0	1340	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	897	0	0
T35	6681	5	0	0
T36	0	26	0	0
T42	0	29	0	0
T53	0	5	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	25	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	4	0	0
T131	0	4	0	0
T132	0	2	0	0
T200	422	0	0	0
T224	0	23	0	0
T280	0	11	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6553497	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6555197	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	1511	0	0
T34	5270	13	0	0
T35	0	9	0	0
T36	0	26	0	0
T42	0	29	0	0
T50	982	0	0	0
T51	640	0	0	0
T53	0	9	0	0
T59	0	14	0	0
T70	1176	0	0	0
T71	417	0	0	0
T72	1861	0	0	0
T73	408	0	0	0
T74	522	0	0	0
T102	0	12	0	0
T103	0	13	0	0
T104	0	32	0	0
T105	0	30	0	0
T106	556	0	0	0
T107	1649	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	1454	0	0
T34	5270	13	0	0
T35	0	7	0	0
T36	0	26	0	0
T42	0	29	0	0
T50	982	0	0	0
T51	640	0	0	0
T53	0	7	0	0
T59	0	9	0	0
T70	1176	0	0	0
T71	417	0	0	0
T72	1861	0	0	0
T73	408	0	0	0
T74	522	0	0	0
T102	0	12	0	0
T103	0	6	0	0
T104	0	25	0	0
T105	0	30	0	0
T106	556	0	0	0
T107	1649	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	897	0	0
T35	6681	5	0	0
T36	0	26	0	0
T42	0	29	0	0
T53	0	5	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	25	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	4	0	0
T131	0	4	0	0
T132	0	2	0	0
T200	422	0	0	0
T224	0	23	0	0
T280	0	11	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	897	0	0
T35	6681	5	0	0
T36	0	26	0	0
T42	0	29	0	0
T53	0	5	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	25	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	4	0	0
T131	0	4	0	0
T132	0	2	0	0
T200	422	0	0	0
T224	0	23	0	0
T280	0	11	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	78089	0	0
T35	6681	339	0	0
T36	0	1254	0	0
T42	0	1609	0	0
T53	0	384	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	1816	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	815	0	0
T131	0	1	0	0
T132	0	438	0	0
T200	422	0	0	0
T224	0	1186	0	0
T280	0	1325	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	785	0	0
T35	6681	5	0	0
T36	0	22	0	0
T42	0	23	0	0
T53	0	4	0	0
T92	493	0	0	0
T93	493	0	0	0
T115	0	25	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	2	0	0
T131	0	4	0	0
T200	422	0	0	0
T224	0	22	0	0
T280	0	7	0	0
T285	0	25	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T35 T36 T56 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T2 T15 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T2 T15 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T35 T36 T56 
149        1/1                    cnt_en = 1'b1;
           Tests:       T35 T36 T56 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T35 T36 T56 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T35 T36 T56 
163        1/1                    state_d = IdleSt;
           Tests:       T35 T53 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 
165        1/1                  end else if (cnt_done) begin
           Tests:       T35 T36 T56 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T36 T56 
167        1/1                    if (trigger_active) begin
           Tests:       T35 T36 T56 
168        1/1                      state_d = DetectSt;
           Tests:       T35 T36 T56 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T56 T40 T41 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T35 T36 T56 
182        1/1                  cnt_en = 1'b1;
           Tests:       T35 T36 T56 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T35 T36 T56 
186        1/1                    state_d = IdleSt;
           Tests:       T35 T53 T114 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T35 T53 T114 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T35 T36 T56 
191        1/1                      state_d = StableSt;
           Tests:       T35 T36 T56 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T35 T36 T56 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T35 T36 T56 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T35 T36 T56 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T35 T36 T56 
206        1/1                    state_d = IdleSt;
           Tests:       T35 T36 T56 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T35 T36 T56 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T36,T56

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T36,T56

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T35,T36,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T35,T36,T56
1	0	Covered	T78,T113,T64
1	1	Covered	T35,T36,T56

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T56
0	1	Covered	T114,T298,T288
1	0	Covered	T35,T53

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T35,T36,T56
0	1	Covered	T36,T56,T57
1	0	Covered	T35,T53,T115

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T35,T36,T56
1	-	Covered	T36,T56,T57

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T35,T36,T56
DetectSt	168	Covered	T35,T36,T56
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T35,T36,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T35,T36,T56
DebounceSt->IdleSt	163	Covered	T35,T56,T53
DetectSt->IdleSt	186	Covered	T35,T53,T114
DetectSt->StableSt	191	Covered	T35,T36,T56
IdleSt->DebounceSt	148	Covered	T35,T36,T56
StableSt->IdleSt	206	Covered	T35,T36,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T35,T36,T56
0	1	Covered	T35,T36,T56
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T35,T36,T56
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T35,T36,T56
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T35,T53
DebounceSt	-	0	1	1	-	-	-	Covered	T35,T36,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T56,T40,T41
DebounceSt	-	0	0	-	-	-	-	Covered	T35,T36,T56
DetectSt	-	-	-	-	1	-	-	Covered	T35,T53,T114
DetectSt	-	-	-	-	0	1	-	Covered	T35,T36,T56
DetectSt	-	-	-	-	0	0	-	Covered	T35,T36,T56
StableSt	-	-	-	-	-	-	1	Covered	T35,T36,T56
StableSt	-	-	-	-	-	-	0	Covered	T35,T36,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	7444491	834	0	0
CntIncr_A	7444491	46029	0	0
CntNoWrap_A	7444491	6987350	0	0
DetectStDropOut_A	7444491	46	0	0
DetectedOut_A	7444491	14348	0	0
DetectedPulseOut_A	7444491	348	0	0
DisabledIdleSt_A	7444491	6665948	0	0
DisabledNoDetection_A	7444491	6667286	0	0
EnterDebounceSt_A	7444491	436	0	0
EnterDetectSt_A	7444491	398	0	0
EnterStableSt_A	7444491	348	0	0
PulseIsPulse_A	7444491	348	0	0
StayInStableSt	7444491	13969	0	0
gen_high_level_sva.HighLevelEvent_A	7444491	6990083	0	0
gen_not_sticky_sva.StableStDropOut_A	7444491	311	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	834	0	0
T35	6681	8	0	0
T36	0	6	0	0
T40	0	2	0	0
T41	0	10	0	0
T42	0	12	0	0
T53	0	8	0	0
T56	0	12	0	0
T57	0	4	0	0
T58	0	22	0	0
T92	493	0	0	0
T93	493	0	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	4	0	0
T200	422	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	46029	0	0
T35	6681	197	0	0
T36	0	135	0	0
T40	0	134	0	0
T41	0	802	0	0
T42	0	468	0	0
T53	0	224	0	0
T56	0	717	0	0
T57	0	190	0	0
T58	0	1155	0	0
T92	493	0	0	0
T93	493	0	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	148	0	0
T200	422	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6987350	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	46	0	0
T43	13023	0	0	0
T45	19280	0	0	0
T114	11566	6	0	0
T118	16287	0	0	0
T288	0	7	0	0
T298	0	9	0	0
T299	0	17	0	0
T300	0	7	0	0
T301	427	0	0	0
T302	19681	0	0	0
T303	408	0	0	0
T304	508	0	0	0
T305	524	0	0	0
T306	424	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	14348	0	0
T35	6681	80	0	0
T36	0	205	0	0
T41	0	199	0	0
T42	0	266	0	0
T43	0	9	0	0
T53	0	95	0	0
T56	0	299	0	0
T57	0	38	0	0
T58	0	462	0	0
T92	493	0	0	0
T93	493	0	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	78	0	0
T200	422	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	348	0	0
T35	6681	1	0	0
T36	0	3	0	0
T41	0	4	0	0
T42	0	6	0	0
T43	0	1	0	0
T53	0	1	0	0
T56	0	5	0	0
T57	0	2	0	0
T58	0	11	0	0
T92	493	0	0	0
T93	493	0	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	2	0	0
T200	422	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6665948	0	0
T1	865	464	0	0
T2	506	105	0	0
T4	599	198	0	0
T5	429	28	0	0
T6	430	29	0	0
T14	426	25	0	0
T15	462	61	0	0
T19	505	104	0	0
T20	418	17	0	0
T21	406	5	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6667286	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	436	0	0
T35	6681	5	0	0
T36	0	3	0	0
T40	0	2	0	0
T41	0	6	0	0
T42	0	6	0	0
T53	0	5	0	0
T56	0	7	0	0
T57	0	2	0	0
T58	0	11	0	0
T92	493	0	0	0
T93	493	0	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	2	0	0
T200	422	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	398	0	0
T35	6681	3	0	0
T36	0	3	0	0
T41	0	4	0	0
T42	0	6	0	0
T53	0	3	0	0
T56	0	5	0	0
T57	0	2	0	0
T58	0	11	0	0
T92	493	0	0	0
T93	493	0	0	0
T114	0	6	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	2	0	0
T200	422	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	348	0	0
T35	6681	1	0	0
T36	0	3	0	0
T41	0	4	0	0
T42	0	6	0	0
T43	0	1	0	0
T53	0	1	0	0
T56	0	5	0	0
T57	0	2	0	0
T58	0	11	0	0
T92	493	0	0	0
T93	493	0	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	2	0	0
T200	422	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	348	0	0
T35	6681	1	0	0
T36	0	3	0	0
T41	0	4	0	0
T42	0	6	0	0
T43	0	1	0	0
T53	0	1	0	0
T56	0	5	0	0
T57	0	2	0	0
T58	0	11	0	0
T92	493	0	0	0
T93	493	0	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	2	0	0
T200	422	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	13969	0	0
T35	6681	79	0	0
T36	0	202	0	0
T41	0	195	0	0
T42	0	258	0	0
T43	0	8	0	0
T53	0	94	0	0
T56	0	294	0	0
T57	0	36	0	0
T58	0	450	0	0
T92	493	0	0	0
T93	493	0	0	0
T124	686	0	0	0
T125	402	0	0	0
T126	406	0	0	0
T127	507	0	0	0
T128	526	0	0	0
T129	2074	0	0	0
T130	0	74	0	0
T200	422	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	6990083	0	0
T1	865	465	0	0
T2	506	106	0	0
T4	599	199	0	0
T5	429	29	0	0
T6	430	30	0	0
T14	426	26	0	0
T15	462	62	0	0
T19	505	105	0	0
T20	418	18	0	0
T21	406	6	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	7444491	311	0	0
T36	18914	3	0	0
T41	0	4	0	0
T42	0	4	0	0
T43	0	1	0	0
T44	0	2	0	0
T45	0	8	0	0
T53	6728	0	0	0
T56	12687	5	0	0
T57	9681	2	0	0
T58	0	10	0	0
T59	5418	0	0	0
T77	3051	0	0	0
T102	5218	0	0	0
T193	2932	0	0	0
T194	103912	0	0	0
T195	8410	0	0	0
T302	0	7	0	0