| T507 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.3453374464 |
|
|
Aug 28 08:05:19 PM UTC 24 |
Aug 28 08:05:27 PM UTC 24 |
2009880534 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.3597751623 |
|
|
Aug 28 08:05:18 PM UTC 24 |
Aug 28 08:05:27 PM UTC 24 |
2507310364 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3232930113 |
|
|
Aug 28 08:05:21 PM UTC 24 |
Aug 28 08:05:27 PM UTC 24 |
2616940955 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3131766129 |
|
|
Aug 28 08:05:15 PM UTC 24 |
Aug 28 08:05:27 PM UTC 24 |
5952265812 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1229148940 |
|
|
Aug 28 08:05:11 PM UTC 24 |
Aug 28 08:05:27 PM UTC 24 |
4267943674 ps |
| T314 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.3493442166 |
|
|
Aug 28 08:05:10 PM UTC 24 |
Aug 28 08:05:27 PM UTC 24 |
10577810629 ps |
| T182 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.922874064 |
|
|
Aug 28 08:05:21 PM UTC 24 |
Aug 28 08:05:28 PM UTC 24 |
6861999115 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.681664942 |
|
|
Aug 28 08:05:25 PM UTC 24 |
Aug 28 08:05:28 PM UTC 24 |
2038961117 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3472114859 |
|
|
Aug 28 08:05:21 PM UTC 24 |
Aug 28 08:05:28 PM UTC 24 |
7631451331 ps |
| T111 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1281902400 |
|
|
Aug 28 08:05:18 PM UTC 24 |
Aug 28 08:05:28 PM UTC 24 |
3819911072 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2315701212 |
|
|
Aug 28 08:05:16 PM UTC 24 |
Aug 28 08:05:28 PM UTC 24 |
3518509626 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.1630674090 |
|
|
Aug 28 08:05:21 PM UTC 24 |
Aug 28 08:05:29 PM UTC 24 |
2025577995 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.1337407024 |
|
|
Aug 28 08:05:25 PM UTC 24 |
Aug 28 08:05:29 PM UTC 24 |
2131435670 ps |
| T44 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.838015131 |
|
|
Aug 28 08:05:10 PM UTC 24 |
Aug 28 08:05:29 PM UTC 24 |
67726863114 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2280072947 |
|
|
Aug 28 08:05:10 PM UTC 24 |
Aug 28 08:05:30 PM UTC 24 |
41504388554 ps |
| T225 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.4280642014 |
|
|
Aug 28 08:05:34 PM UTC 24 |
Aug 28 08:05:37 PM UTC 24 |
2099105043 ps |
| T226 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.699443571 |
|
|
Aug 28 08:05:25 PM UTC 24 |
Aug 28 08:05:30 PM UTC 24 |
2537948560 ps |
| T227 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.2451436569 |
|
|
Aug 28 08:05:31 PM UTC 24 |
Aug 28 08:05:35 PM UTC 24 |
2032154277 ps |
| T228 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.929789542 |
|
|
Aug 28 08:05:21 PM UTC 24 |
Aug 28 08:05:30 PM UTC 24 |
2459205498 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3792086778 |
|
|
Aug 28 08:05:21 PM UTC 24 |
Aug 28 08:05:30 PM UTC 24 |
2224844654 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.3970357944 |
|
|
Aug 28 08:05:21 PM UTC 24 |
Aug 28 08:05:30 PM UTC 24 |
2476601553 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.183986107 |
|
|
Aug 28 08:05:21 PM UTC 24 |
Aug 28 08:05:31 PM UTC 24 |
3579962866 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.3754108008 |
|
|
Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:05:31 PM UTC 24 |
2337806741 ps |
| T348 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1418608200 |
|
|
Aug 28 08:05:21 PM UTC 24 |
Aug 28 08:05:31 PM UTC 24 |
5526714252 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.3070722290 |
|
|
Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:05:35 PM UTC 24 |
2015760018 ps |
| T121 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3969921983 |
|
|
Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:05:31 PM UTC 24 |
3387726174 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.1050575447 |
|
|
Aug 28 08:05:13 PM UTC 24 |
Aug 28 08:05:31 PM UTC 24 |
13998954470 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.35257687 |
|
|
Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:05:32 PM UTC 24 |
2125544360 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3556909238 |
|
|
Aug 28 08:05:30 PM UTC 24 |
Aug 28 08:05:32 PM UTC 24 |
2655446506 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.2069154196 |
|
|
Aug 28 08:05:24 PM UTC 24 |
Aug 28 08:05:32 PM UTC 24 |
2304438404 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.2421175470 |
|
|
Aug 28 08:05:10 PM UTC 24 |
Aug 28 08:05:33 PM UTC 24 |
14834785301 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.958402720 |
|
|
Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:05:33 PM UTC 24 |
4474176754 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3904995514 |
|
|
Aug 28 08:05:30 PM UTC 24 |
Aug 28 08:05:33 PM UTC 24 |
2865364078 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.2453251996 |
|
|
Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:05:33 PM UTC 24 |
2518265007 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.2211002750 |
|
|
Aug 28 08:05:25 PM UTC 24 |
Aug 28 08:05:34 PM UTC 24 |
2447341835 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.3352107901 |
|
|
Aug 28 08:05:25 PM UTC 24 |
Aug 28 08:05:34 PM UTC 24 |
2224852353 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3826468969 |
|
|
Aug 28 08:05:26 PM UTC 24 |
Aug 28 08:05:34 PM UTC 24 |
2609517473 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1707231064 |
|
|
Aug 28 08:05:30 PM UTC 24 |
Aug 28 08:05:34 PM UTC 24 |
3358134377 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.680578227 |
|
|
Aug 28 08:05:31 PM UTC 24 |
Aug 28 08:05:35 PM UTC 24 |
2046680156 ps |
| T199 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.3151409541 |
|
|
Aug 28 08:05:31 PM UTC 24 |
Aug 28 08:05:35 PM UTC 24 |
8400397932 ps |
| T339 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1351413667 |
|
|
Aug 28 08:05:25 PM UTC 24 |
Aug 28 08:05:35 PM UTC 24 |
5863314746 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2957639095 |
|
|
Aug 28 08:05:31 PM UTC 24 |
Aug 28 08:05:35 PM UTC 24 |
2651093619 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2625135884 |
|
|
Aug 28 08:05:33 PM UTC 24 |
Aug 28 08:05:36 PM UTC 24 |
3618151552 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.2487388273 |
|
|
Aug 28 08:05:31 PM UTC 24 |
Aug 28 08:05:37 PM UTC 24 |
2466257194 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3571151138 |
|
|
Aug 28 08:05:33 PM UTC 24 |
Aug 28 08:05:37 PM UTC 24 |
3564238862 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3803990704 |
|
|
Aug 28 08:05:24 PM UTC 24 |
Aug 28 08:05:37 PM UTC 24 |
3477720620 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1079974520 |
|
|
Aug 28 08:05:54 PM UTC 24 |
Aug 28 08:06:02 PM UTC 24 |
10195207520 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.1617933044 |
|
|
Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:05:37 PM UTC 24 |
9363860710 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3274158632 |
|
|
Aug 28 08:05:23 PM UTC 24 |
Aug 28 08:05:38 PM UTC 24 |
4123968791 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3587078516 |
|
|
Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:05:39 PM UTC 24 |
3679160564 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.241204515 |
|
|
Aug 28 08:05:34 PM UTC 24 |
Aug 28 08:05:39 PM UTC 24 |
2472251641 ps |
| T117 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.2985034953 |
|
|
Aug 28 08:05:33 PM UTC 24 |
Aug 28 08:05:40 PM UTC 24 |
2512341929 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.771313117 |
|
|
Aug 28 08:05:38 PM UTC 24 |
Aug 28 08:05:41 PM UTC 24 |
2064265594 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.1671164569 |
|
|
Aug 28 08:05:34 PM UTC 24 |
Aug 28 08:05:41 PM UTC 24 |
2114255545 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.204686439 |
|
|
Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:05:41 PM UTC 24 |
2460406194 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2425636863 |
|
|
Aug 28 08:05:38 PM UTC 24 |
Aug 28 08:05:42 PM UTC 24 |
3271722804 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.2309327956 |
|
|
Aug 28 08:05:34 PM UTC 24 |
Aug 28 08:05:43 PM UTC 24 |
2183981205 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.664691643 |
|
|
Aug 28 08:05:38 PM UTC 24 |
Aug 28 08:05:43 PM UTC 24 |
3108202501 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.4050575025 |
|
|
Aug 28 08:05:38 PM UTC 24 |
Aug 28 08:05:43 PM UTC 24 |
2529258027 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1322153875 |
|
|
Aug 28 08:05:37 PM UTC 24 |
Aug 28 08:05:43 PM UTC 24 |
2114836721 ps |
| T46 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.3142373111 |
|
|
Aug 28 08:05:21 PM UTC 24 |
Aug 28 08:05:44 PM UTC 24 |
62448811785 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.526441369 |
|
|
Aug 28 08:05:31 PM UTC 24 |
Aug 28 08:05:44 PM UTC 24 |
2512555770 ps |
| T171 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.918176163 |
|
|
Aug 28 08:05:33 PM UTC 24 |
Aug 28 08:05:45 PM UTC 24 |
4393140134 ps |
| T198 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3673164634 |
|
|
Aug 28 08:05:37 PM UTC 24 |
Aug 28 08:05:45 PM UTC 24 |
3257017491 ps |
| T164 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1271396620 |
|
|
Aug 28 08:05:36 PM UTC 24 |
Aug 28 08:05:45 PM UTC 24 |
5837130131 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.1158546426 |
|
|
Aug 28 08:05:40 PM UTC 24 |
Aug 28 08:05:45 PM UTC 24 |
6473410748 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1979273202 |
|
|
Aug 28 08:05:43 PM UTC 24 |
Aug 28 08:05:45 PM UTC 24 |
2241580331 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2126893736 |
|
|
Aug 28 08:05:42 PM UTC 24 |
Aug 28 08:05:46 PM UTC 24 |
2036025365 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3681736803 |
|
|
Aug 28 08:05:30 PM UTC 24 |
Aug 28 08:05:46 PM UTC 24 |
5803362168 ps |
| T298 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3542118145 |
|
|
Aug 28 08:05:09 PM UTC 24 |
Aug 28 08:05:46 PM UTC 24 |
55314713262 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2604273842 |
|
|
Aug 28 08:05:35 PM UTC 24 |
Aug 28 08:05:47 PM UTC 24 |
2608753168 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1942851694 |
|
|
Aug 28 08:05:30 PM UTC 24 |
Aug 28 08:05:47 PM UTC 24 |
4209675000 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2090532944 |
|
|
Aug 28 08:05:44 PM UTC 24 |
Aug 28 08:05:47 PM UTC 24 |
2501111579 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.706066826 |
|
|
Aug 28 08:05:37 PM UTC 24 |
Aug 28 08:05:48 PM UTC 24 |
2008895156 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.2760674762 |
|
|
Aug 28 08:05:35 PM UTC 24 |
Aug 28 08:05:48 PM UTC 24 |
2511661739 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.2757868067 |
|
|
Aug 28 08:05:42 PM UTC 24 |
Aug 28 08:05:49 PM UTC 24 |
2111994104 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.4124150060 |
|
|
Aug 28 08:05:41 PM UTC 24 |
Aug 28 08:05:49 PM UTC 24 |
6752516092 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1813565280 |
|
|
Aug 28 08:05:44 PM UTC 24 |
Aug 28 08:05:49 PM UTC 24 |
2626179334 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1056492547 |
|
|
Aug 28 08:05:35 PM UTC 24 |
Aug 28 08:05:49 PM UTC 24 |
3882853176 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1564132150 |
|
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Aug 28 08:05:43 PM UTC 24 |
Aug 28 08:05:49 PM UTC 24 |
2462837089 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3608744622 |
|
|
Aug 28 08:05:36 PM UTC 24 |
Aug 28 08:05:49 PM UTC 24 |
3418543397 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.1015341061 |
|
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Aug 28 08:05:37 PM UTC 24 |
Aug 28 08:05:50 PM UTC 24 |
2459707475 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3330017647 |
|
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Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:05:50 PM UTC 24 |
9863549184 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.129584332 |
|
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Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:05:50 PM UTC 24 |
24849731619 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.3219708279 |
|
|
Aug 28 08:05:44 PM UTC 24 |
Aug 28 08:05:51 PM UTC 24 |
2521659792 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.272347238 |
|
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Aug 28 08:05:52 PM UTC 24 |
Aug 28 08:06:02 PM UTC 24 |
2053519302 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.2548206675 |
|
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Aug 28 08:05:47 PM UTC 24 |
Aug 28 08:05:51 PM UTC 24 |
2039006550 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.1694297028 |
|
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Aug 28 08:05:47 PM UTC 24 |
Aug 28 08:05:52 PM UTC 24 |
2122162227 ps |
| T201 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2001056290 |
|
|
Aug 28 08:05:46 PM UTC 24 |
Aug 28 08:05:52 PM UTC 24 |
5721560962 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.2817279883 |
|
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Aug 28 08:05:47 PM UTC 24 |
Aug 28 08:05:52 PM UTC 24 |
2493531807 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2315251135 |
|
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Aug 28 08:05:38 PM UTC 24 |
Aug 28 08:05:52 PM UTC 24 |
2985986778 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3202440917 |
|
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Aug 28 08:05:38 PM UTC 24 |
Aug 28 08:05:52 PM UTC 24 |
2612242879 ps |
| T196 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1830954243 |
|
|
Aug 28 08:05:34 PM UTC 24 |
Aug 28 08:05:53 PM UTC 24 |
18208607911 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.1802529269 |
|
|
Aug 28 08:05:48 PM UTC 24 |
Aug 28 08:05:53 PM UTC 24 |
2523895725 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.952260694 |
|
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Aug 28 08:05:25 PM UTC 24 |
Aug 28 08:05:53 PM UTC 24 |
36401330990 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.3341738329 |
|
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Aug 28 08:05:47 PM UTC 24 |
Aug 28 08:05:55 PM UTC 24 |
2014127536 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3225603929 |
|
|
Aug 28 08:05:37 PM UTC 24 |
Aug 28 08:05:55 PM UTC 24 |
5026984802 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.3411544721 |
|
|
Aug 28 08:05:51 PM UTC 24 |
Aug 28 08:05:55 PM UTC 24 |
2025966453 ps |
| T280 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1036086766 |
|
|
Aug 28 08:05:11 PM UTC 24 |
Aug 28 08:05:55 PM UTC 24 |
176511253999 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.932859361 |
|
|
Aug 28 08:05:57 PM UTC 24 |
Aug 28 08:06:02 PM UTC 24 |
2637385216 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2524537046 |
|
|
Aug 28 08:05:49 PM UTC 24 |
Aug 28 08:05:55 PM UTC 24 |
3339671030 ps |
| T312 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2689432442 |
|
|
Aug 28 08:05:16 PM UTC 24 |
Aug 28 08:05:56 PM UTC 24 |
48981031204 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1729134213 |
|
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Aug 28 08:05:48 PM UTC 24 |
Aug 28 08:05:56 PM UTC 24 |
2618511459 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3909981711 |
|
|
Aug 28 08:05:51 PM UTC 24 |
Aug 28 08:05:56 PM UTC 24 |
2121956813 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.1616269505 |
|
|
Aug 28 08:05:52 PM UTC 24 |
Aug 28 08:05:56 PM UTC 24 |
2541975663 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1952346946 |
|
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Aug 28 08:05:52 PM UTC 24 |
Aug 28 08:05:56 PM UTC 24 |
2648867039 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3461917068 |
|
|
Aug 28 08:05:45 PM UTC 24 |
Aug 28 08:05:57 PM UTC 24 |
3271448231 ps |
| T132 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1423401970 |
|
|
Aug 28 08:05:19 PM UTC 24 |
Aug 28 08:05:58 PM UTC 24 |
55942474154 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3144346906 |
|
|
Aug 28 08:05:53 PM UTC 24 |
Aug 28 08:05:59 PM UTC 24 |
3275772567 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.144004944 |
|
|
Aug 28 08:05:42 PM UTC 24 |
Aug 28 08:06:00 PM UTC 24 |
14159496917 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.3988063739 |
|
|
Aug 28 08:05:51 PM UTC 24 |
Aug 28 08:06:02 PM UTC 24 |
11912989228 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.248381750 |
|
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Aug 28 08:05:57 PM UTC 24 |
Aug 28 08:06:03 PM UTC 24 |
3479275337 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.843211267 |
|
|
Aug 28 08:05:54 PM UTC 24 |
Aug 28 08:06:03 PM UTC 24 |
2349550478 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.418719087 |
|
|
Aug 28 08:05:49 PM UTC 24 |
Aug 28 08:06:04 PM UTC 24 |
3770406830 ps |
| T202 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.2925937220 |
|
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Aug 28 08:05:59 PM UTC 24 |
Aug 28 08:06:04 PM UTC 24 |
3817845365 ps |
| T245 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.2781529585 |
|
|
Aug 28 08:05:52 PM UTC 24 |
Aug 28 08:06:05 PM UTC 24 |
2448354930 ps |
| T246 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2648215679 |
|
|
Aug 28 08:05:54 PM UTC 24 |
Aug 28 08:06:05 PM UTC 24 |
10001116266 ps |
| T247 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.1296096476 |
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|
Aug 28 08:05:56 PM UTC 24 |
Aug 28 08:06:06 PM UTC 24 |
2010459832 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.823607765 |
|
|
Aug 28 08:05:51 PM UTC 24 |
Aug 28 08:06:07 PM UTC 24 |
4141101188 ps |
| T249 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1396962090 |
|
|
Aug 28 08:06:03 PM UTC 24 |
Aug 28 08:06:07 PM UTC 24 |
2123856688 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.3721294442 |
|
|
Aug 28 08:05:56 PM UTC 24 |
Aug 28 08:06:07 PM UTC 24 |
2113985372 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.1104758986 |
|
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Aug 28 08:06:03 PM UTC 24 |
Aug 28 08:06:08 PM UTC 24 |
2490059585 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.717835063 |
|
|
Aug 28 08:05:56 PM UTC 24 |
Aug 28 08:06:08 PM UTC 24 |
2171879881 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.4115519650 |
|
|
Aug 28 08:06:03 PM UTC 24 |
Aug 28 08:06:08 PM UTC 24 |
2029379119 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.2363916914 |
|
|
Aug 28 08:05:57 PM UTC 24 |
Aug 28 08:06:09 PM UTC 24 |
2513976669 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.2831710953 |
|
|
Aug 28 08:05:56 PM UTC 24 |
Aug 28 08:06:10 PM UTC 24 |
2458752014 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.99057817 |
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Aug 28 08:06:03 PM UTC 24 |
Aug 28 08:06:10 PM UTC 24 |
2012637930 ps |
| T285 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.4265500253 |
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Aug 28 08:05:10 PM UTC 24 |
Aug 28 08:06:12 PM UTC 24 |
77597906633 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.2681447120 |
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|
Aug 28 08:06:04 PM UTC 24 |
Aug 28 08:06:12 PM UTC 24 |
2519538321 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.3575200848 |
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|
Aug 28 08:06:10 PM UTC 24 |
Aug 28 08:06:14 PM UTC 24 |
2572943992 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.2201337322 |
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Aug 28 08:06:09 PM UTC 24 |
Aug 28 08:06:14 PM UTC 24 |
2474111728 ps |
| T242 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.1192975772 |
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|
Aug 28 08:06:08 PM UTC 24 |
Aug 28 08:06:14 PM UTC 24 |
4331585805 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.1431928450 |
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|
Aug 28 08:06:09 PM UTC 24 |
Aug 28 08:06:14 PM UTC 24 |
11982457211 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.352731175 |
|
|
Aug 28 08:06:10 PM UTC 24 |
Aug 28 08:06:15 PM UTC 24 |
2622408721 ps |
| T437 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2925095162 |
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Aug 28 08:05:49 PM UTC 24 |
Aug 28 08:06:15 PM UTC 24 |
1689920836668 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.3394638943 |
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Aug 28 08:05:34 PM UTC 24 |
Aug 28 08:06:15 PM UTC 24 |
17840060976 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1729692336 |
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Aug 28 08:06:04 PM UTC 24 |
Aug 28 08:06:18 PM UTC 24 |
2609641396 ps |
| T119 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1040673604 |
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Aug 28 08:05:30 PM UTC 24 |
Aug 28 08:06:18 PM UTC 24 |
60872736289 ps |
| T349 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1023681414 |
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Aug 28 08:06:01 PM UTC 24 |
Aug 28 08:06:18 PM UTC 24 |
5396156577 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3087390349 |
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Aug 28 08:06:12 PM UTC 24 |
Aug 28 08:06:18 PM UTC 24 |
4016975581 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1210658820 |
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Aug 28 08:06:11 PM UTC 24 |
Aug 28 08:06:19 PM UTC 24 |
5078871998 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.844696270 |
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Aug 28 08:06:09 PM UTC 24 |
Aug 28 08:06:19 PM UTC 24 |
2012553349 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.183894687 |
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Aug 28 08:06:08 PM UTC 24 |
Aug 28 08:06:20 PM UTC 24 |
3309033355 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3632079774 |
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Aug 28 08:06:16 PM UTC 24 |
Aug 28 08:06:20 PM UTC 24 |
2033801655 ps |
| T232 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.3008062243 |
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Aug 28 08:06:03 PM UTC 24 |
Aug 28 08:06:20 PM UTC 24 |
14786392383 ps |
| T165 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1365609780 |
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Aug 28 08:06:12 PM UTC 24 |
Aug 28 08:06:20 PM UTC 24 |
6123228580 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.72215383 |
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Aug 28 08:06:09 PM UTC 24 |
Aug 28 08:06:21 PM UTC 24 |
2114298169 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.1909554313 |
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Aug 28 08:06:10 PM UTC 24 |
Aug 28 08:06:21 PM UTC 24 |
2023948462 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.544349696 |
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Aug 28 08:06:18 PM UTC 24 |
Aug 28 08:06:22 PM UTC 24 |
2450658439 ps |
| T133 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.2586872666 |
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Aug 28 08:01:23 PM UTC 24 |
Aug 28 08:06:23 PM UTC 24 |
124815335134 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.490822921 |
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Aug 28 08:06:18 PM UTC 24 |
Aug 28 08:06:23 PM UTC 24 |
2169843584 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1031194343 |
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Aug 28 08:06:19 PM UTC 24 |
Aug 28 08:06:24 PM UTC 24 |
2631425493 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.258582984 |
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Aug 28 08:06:16 PM UTC 24 |
Aug 28 08:06:24 PM UTC 24 |
2115269745 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1035812095 |
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Aug 28 08:06:23 PM UTC 24 |
Aug 28 08:06:26 PM UTC 24 |
2098275210 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.29279534 |
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Aug 28 08:06:05 PM UTC 24 |
Aug 28 08:06:26 PM UTC 24 |
4166293064 ps |
| T229 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.537122431 |
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Aug 28 08:06:21 PM UTC 24 |
Aug 28 08:06:27 PM UTC 24 |
4734560967 ps |
| T350 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.830282409 |
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Aug 28 08:06:15 PM UTC 24 |
Aug 28 08:06:27 PM UTC 24 |
17319959919 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3292523549 |
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Aug 28 08:06:15 PM UTC 24 |
Aug 28 08:06:28 PM UTC 24 |
4738287793 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2023169366 |
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Aug 28 08:06:20 PM UTC 24 |
Aug 28 08:06:28 PM UTC 24 |
2731976409 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.211974963 |
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Aug 28 08:01:34 PM UTC 24 |
Aug 28 08:06:29 PM UTC 24 |
109830498768 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.3196334287 |
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Aug 28 08:06:25 PM UTC 24 |
Aug 28 08:06:29 PM UTC 24 |
2535795151 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2623579755 |
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Aug 28 08:06:21 PM UTC 24 |
Aug 28 08:06:29 PM UTC 24 |
3501363440 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.3709589446 |
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Aug 28 08:06:24 PM UTC 24 |
Aug 28 08:06:32 PM UTC 24 |
2455962946 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2359489487 |
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Aug 28 08:06:19 PM UTC 24 |
Aug 28 08:06:32 PM UTC 24 |
2513533922 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.912305844 |
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Aug 28 08:06:22 PM UTC 24 |
Aug 28 08:06:32 PM UTC 24 |
3757902883 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.957767634 |
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Aug 28 08:06:30 PM UTC 24 |
Aug 28 08:06:34 PM UTC 24 |
2645319305 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.3433400888 |
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Aug 28 08:06:25 PM UTC 24 |
Aug 28 08:06:35 PM UTC 24 |
2048508144 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.1582506274 |
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Aug 28 08:06:24 PM UTC 24 |
Aug 28 08:06:36 PM UTC 24 |
2110879444 ps |
| T134 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.4274364048 |
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Aug 28 08:06:15 PM UTC 24 |
Aug 28 08:06:36 PM UTC 24 |
59465889274 ps |
| T371 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1887557434 |
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Aug 28 08:05:51 PM UTC 24 |
Aug 28 08:06:36 PM UTC 24 |
63656392078 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.397112135 |
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Aug 28 08:05:10 PM UTC 24 |
Aug 28 08:06:37 PM UTC 24 |
1739975598561 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.3539630908 |
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Aug 28 08:06:33 PM UTC 24 |
Aug 28 08:06:38 PM UTC 24 |
2121840033 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.406065962 |
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Aug 28 08:06:26 PM UTC 24 |
Aug 28 08:06:38 PM UTC 24 |
2610816122 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.333977464 |
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Aug 28 08:06:26 PM UTC 24 |
Aug 28 08:06:39 PM UTC 24 |
4359121553 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.3741642389 |
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Aug 28 08:06:35 PM UTC 24 |
Aug 28 08:06:39 PM UTC 24 |
2242137303 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3966786571 |
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Aug 28 08:06:30 PM UTC 24 |
Aug 28 08:06:40 PM UTC 24 |
6851925271 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.829858019 |
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Aug 28 08:06:33 PM UTC 24 |
Aug 28 08:06:41 PM UTC 24 |
2014844987 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.3565887054 |
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Aug 28 08:06:36 PM UTC 24 |
Aug 28 08:06:41 PM UTC 24 |
2538580750 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.687757558 |
|
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Aug 28 08:06:36 PM UTC 24 |
Aug 28 08:06:41 PM UTC 24 |
2640032391 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.609821425 |
|
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Aug 28 08:06:28 PM UTC 24 |
Aug 28 08:06:41 PM UTC 24 |
3336433984 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.2160265015 |
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Aug 28 08:06:33 PM UTC 24 |
Aug 28 08:06:41 PM UTC 24 |
2459976155 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2937847383 |
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Aug 28 08:06:38 PM UTC 24 |
Aug 28 08:06:43 PM UTC 24 |
3954508574 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.987597010 |
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Aug 28 08:06:39 PM UTC 24 |
Aug 28 08:06:43 PM UTC 24 |
4707882718 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2406703668 |
|
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Aug 28 08:06:38 PM UTC 24 |
Aug 28 08:06:44 PM UTC 24 |
4401540659 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.2820384133 |
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Aug 28 08:06:39 PM UTC 24 |
Aug 28 08:06:44 PM UTC 24 |
3755753920 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.1876151460 |
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Aug 28 08:06:41 PM UTC 24 |
Aug 28 08:06:45 PM UTC 24 |
2030691565 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.1772236836 |
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Aug 28 08:06:41 PM UTC 24 |
Aug 28 08:06:45 PM UTC 24 |
2128243463 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.26607606 |
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Aug 28 08:06:42 PM UTC 24 |
Aug 28 08:06:45 PM UTC 24 |
2506673553 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.1920727262 |
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Aug 28 08:06:22 PM UTC 24 |
Aug 28 08:06:46 PM UTC 24 |
9239288595 ps |
| T286 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3428030704 |
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Aug 28 08:05:10 PM UTC 24 |
Aug 28 08:06:47 PM UTC 24 |
127723820190 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.833586397 |
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Aug 28 08:06:42 PM UTC 24 |
Aug 28 08:06:47 PM UTC 24 |
2534318869 ps |
| T135 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.850030828 |
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Aug 28 08:05:24 PM UTC 24 |
Aug 28 08:06:48 PM UTC 24 |
86139691459 ps |
| T143 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2494046673 |
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Aug 28 08:06:45 PM UTC 24 |
Aug 28 08:06:49 PM UTC 24 |
5874455758 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.334664350 |
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Aug 28 08:06:45 PM UTC 24 |
Aug 28 08:06:49 PM UTC 24 |
2537667753 ps |
| T145 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.7769657 |
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Aug 28 08:07:11 PM UTC 24 |
Aug 28 08:07:23 PM UTC 24 |
2113940052 ps |
| T146 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.2572426072 |
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Aug 28 08:06:48 PM UTC 24 |
Aug 28 08:06:51 PM UTC 24 |
2092832036 ps |
| T147 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3066422793 |
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Aug 28 08:06:43 PM UTC 24 |
Aug 28 08:06:52 PM UTC 24 |
2610719376 ps |
| T148 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2853834141 |
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Aug 28 08:05:51 PM UTC 24 |
Aug 28 08:06:53 PM UTC 24 |
69081212136 ps |
| T149 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.1381482495 |
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Aug 28 08:06:49 PM UTC 24 |
Aug 28 08:06:54 PM UTC 24 |
2486963375 ps |
| T150 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.2328471205 |
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Aug 28 08:06:42 PM UTC 24 |
Aug 28 08:06:54 PM UTC 24 |
2122150777 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1808786965 |
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Aug 28 08:06:51 PM UTC 24 |
Aug 28 08:06:55 PM UTC 24 |
2633381365 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1470722929 |
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Aug 28 08:06:40 PM UTC 24 |
Aug 28 08:06:56 PM UTC 24 |
20547001056 ps |
| T370 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.420663928 |
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Aug 28 08:06:07 PM UTC 24 |
Aug 28 08:06:56 PM UTC 24 |
150691255811 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2160470789 |
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Aug 28 08:06:45 PM UTC 24 |
Aug 28 08:06:57 PM UTC 24 |
3689370475 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.654095748 |
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Aug 28 08:06:05 PM UTC 24 |
Aug 28 08:06:58 PM UTC 24 |
274010477879 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2814857579 |
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Aug 28 08:06:46 PM UTC 24 |
Aug 28 08:06:59 PM UTC 24 |
5687770681 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.3062502780 |
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Aug 28 08:06:48 PM UTC 24 |
Aug 28 08:07:00 PM UTC 24 |
13584002720 ps |
| T281 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3099063833 |
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Aug 28 08:06:46 PM UTC 24 |
Aug 28 08:07:00 PM UTC 24 |
72028317481 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.1558318474 |
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Aug 28 08:06:49 PM UTC 24 |
Aug 28 08:07:01 PM UTC 24 |
2114585045 ps |
| T230 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.1642772548 |
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Aug 28 08:06:56 PM UTC 24 |
Aug 28 08:07:01 PM UTC 24 |
3585804312 ps |
| T308 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1347809874 |
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Aug 28 08:01:09 PM UTC 24 |
Aug 28 08:07:01 PM UTC 24 |
128911857383 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.2686494648 |
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Aug 28 08:06:50 PM UTC 24 |
Aug 28 08:07:02 PM UTC 24 |
2205704122 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.3638742943 |
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Aug 28 08:06:59 PM UTC 24 |
Aug 28 08:07:02 PM UTC 24 |
2108924599 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.1643770638 |
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Aug 28 08:07:00 PM UTC 24 |
Aug 28 08:07:03 PM UTC 24 |
2615451440 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.2360513548 |
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Aug 28 08:06:51 PM UTC 24 |
Aug 28 08:07:03 PM UTC 24 |
2513661237 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.4059521932 |
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Aug 28 08:05:47 PM UTC 24 |
Aug 28 08:07:03 PM UTC 24 |
112006221761 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.317955647 |
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Aug 28 08:06:59 PM UTC 24 |
Aug 28 08:07:04 PM UTC 24 |
2133473108 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.3046505754 |
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Aug 28 08:06:16 PM UTC 24 |
Aug 28 08:07:04 PM UTC 24 |
16083050719 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.503288887 |
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Aug 28 08:06:57 PM UTC 24 |
Aug 28 08:07:04 PM UTC 24 |
7298141929 ps |
| T136 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1221508844 |
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Aug 28 08:06:54 PM UTC 24 |
Aug 28 08:07:04 PM UTC 24 |
2966556936 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1166637491 |
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Aug 28 08:07:14 PM UTC 24 |
Aug 28 08:07:23 PM UTC 24 |
3323752397 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3103256101 |
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Aug 28 08:07:01 PM UTC 24 |
Aug 28 08:07:06 PM UTC 24 |
2248122260 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3078893127 |
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Aug 28 08:06:40 PM UTC 24 |
Aug 28 08:07:06 PM UTC 24 |
69023597792 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3007811740 |
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Aug 28 08:06:30 PM UTC 24 |
Aug 28 08:07:06 PM UTC 24 |
13374574437 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1757068731 |
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Aug 28 08:06:47 PM UTC 24 |
Aug 28 08:07:06 PM UTC 24 |
3672396432 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1802410677 |
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Aug 28 08:07:02 PM UTC 24 |
Aug 28 08:07:06 PM UTC 24 |
2623135942 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3477362434 |
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Aug 28 08:06:05 PM UTC 24 |
Aug 28 08:07:07 PM UTC 24 |
1673126404327 ps |
| T137 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.1118795167 |
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Aug 28 08:06:21 PM UTC 24 |
Aug 28 08:07:07 PM UTC 24 |
73016196013 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3947245712 |
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Aug 28 08:07:03 PM UTC 24 |
Aug 28 08:07:08 PM UTC 24 |
6229161113 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3339074567 |
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Aug 28 08:07:06 PM UTC 24 |
Aug 28 08:07:09 PM UTC 24 |
2318586021 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1225855737 |
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Aug 28 08:06:55 PM UTC 24 |
Aug 28 08:07:09 PM UTC 24 |
8905768982 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2268774490 |
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Aug 28 08:06:53 PM UTC 24 |
Aug 28 08:07:09 PM UTC 24 |
4683363621 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.522548147 |
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Aug 28 08:07:06 PM UTC 24 |
Aug 28 08:07:10 PM UTC 24 |
2538273196 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.3145173702 |
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Aug 28 08:07:05 PM UTC 24 |
Aug 28 08:07:10 PM UTC 24 |
2016795921 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.632203048 |
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Aug 28 08:06:41 PM UTC 24 |
Aug 28 08:07:11 PM UTC 24 |
6493791786 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1672717461 |
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Aug 28 08:07:08 PM UTC 24 |
Aug 28 08:07:12 PM UTC 24 |
8025671123 ps |
| T639 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.2377096212 |
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Aug 28 08:07:01 PM UTC 24 |
Aug 28 08:07:12 PM UTC 24 |
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| T640 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.1468283404 |
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Aug 28 08:07:12 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.414539077 |
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Aug 28 08:07:09 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3414043578 |
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Aug 28 08:07:08 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1540986968 |
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Aug 28 08:06:21 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3355855507 |
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Aug 28 08:07:08 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.1378610222 |
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Aug 28 08:07:06 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3576258158 |
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Aug 28 08:07:05 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3766991926 |
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Aug 28 08:07:11 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2748226024 |
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Aug 28 08:07:05 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.2981234590 |
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Aug 28 08:07:12 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1814195308 |
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Aug 28 08:05:53 PM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2815429353 |
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Aug 28 08:07:05 PM UTC 24 |
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| T649 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2502399251 |
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Aug 28 08:07:03 PM UTC 24 |
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