| T650 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3097334973 |
|
|
Aug 28 08:07:08 PM UTC 24 |
Aug 28 08:07:19 PM UTC 24 |
3732902694 ps |
| T651 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.4251673620 |
|
|
Aug 28 08:07:15 PM UTC 24 |
Aug 28 08:07:20 PM UTC 24 |
3115134394 ps |
| T215 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.358366495 |
|
|
Aug 28 08:07:04 PM UTC 24 |
Aug 28 08:07:20 PM UTC 24 |
4711772900 ps |
| T652 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.33816476 |
|
|
Aug 28 08:07:14 PM UTC 24 |
Aug 28 08:07:22 PM UTC 24 |
2610137657 ps |
| T375 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4168590857 |
|
|
Aug 28 08:01:26 PM UTC 24 |
Aug 28 08:07:23 PM UTC 24 |
130038405835 ps |
| T653 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.385341799 |
|
|
Aug 28 08:07:14 PM UTC 24 |
Aug 28 08:07:24 PM UTC 24 |
4673160999 ps |
| T654 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.4280602032 |
|
|
Aug 28 08:07:19 PM UTC 24 |
Aug 28 08:07:25 PM UTC 24 |
2112576136 ps |
| T391 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2475140135 |
|
|
Aug 28 08:05:10 PM UTC 24 |
Aug 28 08:07:26 PM UTC 24 |
87343717478 ps |
| T655 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.1365116896 |
|
|
Aug 28 08:07:13 PM UTC 24 |
Aug 28 08:07:27 PM UTC 24 |
2510892616 ps |
| T656 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.1167123245 |
|
|
Aug 28 08:07:19 PM UTC 24 |
Aug 28 08:07:28 PM UTC 24 |
2471774699 ps |
| T397 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.925765306 |
|
|
Aug 28 08:05:54 PM UTC 24 |
Aug 28 08:07:28 PM UTC 24 |
64556287158 ps |
| T657 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.4067709417 |
|
|
Aug 28 08:07:23 PM UTC 24 |
Aug 28 08:07:29 PM UTC 24 |
3474577637 ps |
| T658 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2644380267 |
|
|
Aug 28 08:07:20 PM UTC 24 |
Aug 28 08:07:29 PM UTC 24 |
2514955867 ps |
| T659 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.1309089429 |
|
|
Aug 28 08:07:18 PM UTC 24 |
Aug 28 08:07:29 PM UTC 24 |
2016342279 ps |
| T660 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2890504250 |
|
|
Aug 28 08:07:24 PM UTC 24 |
Aug 28 08:07:31 PM UTC 24 |
4826211862 ps |
| T203 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1830422428 |
|
|
Aug 28 08:07:24 PM UTC 24 |
Aug 28 08:07:31 PM UTC 24 |
4247083502 ps |
| T661 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.4150876047 |
|
|
Aug 28 08:07:28 PM UTC 24 |
Aug 28 08:07:32 PM UTC 24 |
2122388456 ps |
| T662 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.3638673175 |
|
|
Aug 28 08:07:28 PM UTC 24 |
Aug 28 08:07:32 PM UTC 24 |
2501855319 ps |
| T663 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.1937145924 |
|
|
Aug 28 08:07:20 PM UTC 24 |
Aug 28 08:07:32 PM UTC 24 |
2263454395 ps |
| T37 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2651538966 |
|
|
Aug 28 08:07:10 PM UTC 24 |
Aug 28 08:07:33 PM UTC 24 |
6351475576 ps |
| T664 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3128403206 |
|
|
Aug 28 08:07:21 PM UTC 24 |
Aug 28 08:07:33 PM UTC 24 |
2614833957 ps |
| T373 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2372251089 |
|
|
Aug 28 08:05:57 PM UTC 24 |
Aug 28 08:07:34 PM UTC 24 |
91686995034 ps |
| T665 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3708672837 |
|
|
Aug 28 08:07:16 PM UTC 24 |
Aug 28 08:07:34 PM UTC 24 |
4594511812 ps |
| T666 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.430095404 |
|
|
Aug 28 08:07:25 PM UTC 24 |
Aug 28 08:07:34 PM UTC 24 |
7808232095 ps |
| T667 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1977229966 |
|
|
Aug 28 08:07:30 PM UTC 24 |
Aug 28 08:07:34 PM UTC 24 |
3953661764 ps |
| T668 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1583740619 |
|
|
Aug 28 08:07:22 PM UTC 24 |
Aug 28 08:07:36 PM UTC 24 |
2576794233 ps |
| T284 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2143080284 |
|
|
Aug 28 08:06:57 PM UTC 24 |
Aug 28 08:07:36 PM UTC 24 |
26332537161 ps |
| T669 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.914545155 |
|
|
Aug 28 08:07:33 PM UTC 24 |
Aug 28 08:07:37 PM UTC 24 |
3306495487 ps |
| T670 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.3768889884 |
|
|
Aug 28 08:07:27 PM UTC 24 |
Aug 28 08:07:37 PM UTC 24 |
2011567903 ps |
| T671 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.2491336841 |
|
|
Aug 28 08:07:26 PM UTC 24 |
Aug 28 08:07:37 PM UTC 24 |
9179354907 ps |
| T112 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3057635012 |
|
|
Aug 28 08:07:32 PM UTC 24 |
Aug 28 08:07:38 PM UTC 24 |
5266584160 ps |
| T672 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1557565757 |
|
|
Aug 28 08:07:29 PM UTC 24 |
Aug 28 08:07:40 PM UTC 24 |
2098693930 ps |
| T673 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1936197353 |
|
|
Aug 28 08:07:35 PM UTC 24 |
Aug 28 08:07:41 PM UTC 24 |
2251749134 ps |
| T674 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.2800835321 |
|
|
Aug 28 08:07:32 PM UTC 24 |
Aug 28 08:07:41 PM UTC 24 |
3380940499 ps |
| T675 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.2567478424 |
|
|
Aug 28 08:07:30 PM UTC 24 |
Aug 28 08:07:42 PM UTC 24 |
2511168763 ps |
| T676 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3971619997 |
|
|
Aug 28 08:07:38 PM UTC 24 |
Aug 28 08:07:42 PM UTC 24 |
2981602190 ps |
| T677 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2403111933 |
|
|
Aug 28 08:07:37 PM UTC 24 |
Aug 28 08:07:43 PM UTC 24 |
2617893323 ps |
| T678 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1422216929 |
|
|
Aug 28 08:07:30 PM UTC 24 |
Aug 28 08:07:43 PM UTC 24 |
2610123332 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2824178058 |
|
|
Aug 28 08:05:46 PM UTC 24 |
Aug 28 08:07:43 PM UTC 24 |
1777596192746 ps |
| T679 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.875609904 |
|
|
Aug 28 08:07:37 PM UTC 24 |
Aug 28 08:07:44 PM UTC 24 |
2517601729 ps |
| T680 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1324063853 |
|
|
Aug 28 08:05:15 PM UTC 24 |
Aug 28 08:07:44 PM UTC 24 |
235514964780 ps |
| T681 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.3932606320 |
|
|
Aug 28 08:07:34 PM UTC 24 |
Aug 28 08:07:44 PM UTC 24 |
2112933004 ps |
| T682 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.444544056 |
|
|
Aug 28 08:07:33 PM UTC 24 |
Aug 28 08:07:45 PM UTC 24 |
10095237756 ps |
| T683 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.956957015 |
|
|
Aug 28 08:07:34 PM UTC 24 |
Aug 28 08:07:45 PM UTC 24 |
2012382406 ps |
| T684 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.4067624843 |
|
|
Aug 28 08:07:34 PM UTC 24 |
Aug 28 08:07:46 PM UTC 24 |
2469824303 ps |
| T685 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.1782608853 |
|
|
Aug 28 08:07:17 PM UTC 24 |
Aug 28 08:07:46 PM UTC 24 |
6621195246 ps |
| T309 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2099389894 |
|
|
Aug 28 08:05:37 PM UTC 24 |
Aug 28 08:07:49 PM UTC 24 |
37806487869 ps |
| T686 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.259402085 |
|
|
Aug 28 08:07:44 PM UTC 24 |
Aug 28 08:07:49 PM UTC 24 |
2045882274 ps |
| T687 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.1005597226 |
|
|
Aug 28 08:07:43 PM UTC 24 |
Aug 28 08:07:50 PM UTC 24 |
2026345690 ps |
| T688 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.3538083687 |
|
|
Aug 28 08:07:44 PM UTC 24 |
Aug 28 08:07:50 PM UTC 24 |
2481987487 ps |
| T689 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3873935703 |
|
|
Aug 28 08:07:39 PM UTC 24 |
Aug 28 08:07:50 PM UTC 24 |
4609936438 ps |
| T690 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2589600997 |
|
|
Aug 28 08:07:39 PM UTC 24 |
Aug 28 08:07:51 PM UTC 24 |
3479073797 ps |
| T691 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.336094763 |
|
|
Aug 28 08:07:45 PM UTC 24 |
Aug 28 08:07:51 PM UTC 24 |
2516813908 ps |
| T692 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.205180603 |
|
|
Aug 28 08:07:43 PM UTC 24 |
Aug 28 08:07:52 PM UTC 24 |
2111672588 ps |
| T693 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.772144301 |
|
|
Aug 28 08:07:45 PM UTC 24 |
Aug 28 08:07:53 PM UTC 24 |
2620545188 ps |
| T694 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.772106607 |
|
|
Aug 28 08:07:51 PM UTC 24 |
Aug 28 08:07:55 PM UTC 24 |
2044919107 ps |
| T695 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.415092707 |
|
|
Aug 28 08:07:51 PM UTC 24 |
Aug 28 08:07:55 PM UTC 24 |
2138396463 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.2320126789 |
|
|
Aug 28 08:06:29 PM UTC 24 |
Aug 28 08:07:56 PM UTC 24 |
95454934055 ps |
| T696 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.2348406303 |
|
|
Aug 28 08:07:51 PM UTC 24 |
Aug 28 08:07:56 PM UTC 24 |
2269636226 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1072940771 |
|
|
Aug 28 08:07:46 PM UTC 24 |
Aug 28 08:07:57 PM UTC 24 |
2509925752 ps |
| T263 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.3575358627 |
|
|
Aug 28 08:07:41 PM UTC 24 |
Aug 28 08:07:58 PM UTC 24 |
3524334454 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.2258558515 |
|
|
Aug 28 08:07:47 PM UTC 24 |
Aug 28 08:07:58 PM UTC 24 |
3364873100 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3731231980 |
|
|
Aug 28 08:07:52 PM UTC 24 |
Aug 28 08:07:58 PM UTC 24 |
2517309004 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3343447091 |
|
|
Aug 28 08:07:54 PM UTC 24 |
Aug 28 08:07:58 PM UTC 24 |
2632009275 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1780194121 |
|
|
Aug 28 08:07:46 PM UTC 24 |
Aug 28 08:07:58 PM UTC 24 |
3604761623 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.2089954416 |
|
|
Aug 28 08:07:51 PM UTC 24 |
Aug 28 08:07:59 PM UTC 24 |
2472393453 ps |
| T392 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.95823558 |
|
|
Aug 28 08:01:24 PM UTC 24 |
Aug 28 08:08:00 PM UTC 24 |
148345638036 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1442002518 |
|
|
Aug 28 08:07:58 PM UTC 24 |
Aug 28 08:08:03 PM UTC 24 |
2028006361 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.1201576049 |
|
|
Aug 28 08:08:01 PM UTC 24 |
Aug 28 08:08:03 PM UTC 24 |
2761235766 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3958031720 |
|
|
Aug 28 08:08:01 PM UTC 24 |
Aug 28 08:08:03 PM UTC 24 |
2681106481 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.3573204070 |
|
|
Aug 28 08:07:59 PM UTC 24 |
Aug 28 08:08:04 PM UTC 24 |
2490925901 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3835138603 |
|
|
Aug 28 08:07:56 PM UTC 24 |
Aug 28 08:08:05 PM UTC 24 |
3267011843 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.2012585678 |
|
|
Aug 28 08:07:59 PM UTC 24 |
Aug 28 08:08:06 PM UTC 24 |
2223680383 ps |
| T415 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.1833505100 |
|
|
Aug 28 08:05:54 PM UTC 24 |
Aug 28 08:08:07 PM UTC 24 |
158145061187 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1741984392 |
|
|
Aug 28 08:07:50 PM UTC 24 |
Aug 28 08:08:07 PM UTC 24 |
5943852270 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.310921724 |
|
|
Aug 28 08:07:57 PM UTC 24 |
Aug 28 08:08:08 PM UTC 24 |
4770110727 ps |
| T233 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2266199866 |
|
|
Aug 28 08:05:10 PM UTC 24 |
Aug 28 08:08:08 PM UTC 24 |
115297523389 ps |
| T234 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3631805255 |
|
|
Aug 28 08:07:54 PM UTC 24 |
Aug 28 08:08:08 PM UTC 24 |
3067730154 ps |
| T235 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.2589003081 |
|
|
Aug 28 08:07:59 PM UTC 24 |
Aug 28 08:08:09 PM UTC 24 |
2109848302 ps |
| T236 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2365249324 |
|
|
Aug 28 08:07:33 PM UTC 24 |
Aug 28 08:08:10 PM UTC 24 |
35046813670 ps |
| T237 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3403517108 |
|
|
Aug 28 08:08:04 PM UTC 24 |
Aug 28 08:08:12 PM UTC 24 |
3009441945 ps |
| T238 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.889361158 |
|
|
Aug 28 08:08:08 PM UTC 24 |
Aug 28 08:08:13 PM UTC 24 |
2121901993 ps |
| T239 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.2075909516 |
|
|
Aug 28 08:08:06 PM UTC 24 |
Aug 28 08:08:14 PM UTC 24 |
3048088693 ps |
| T240 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.2936958628 |
|
|
Aug 28 08:07:50 PM UTC 24 |
Aug 28 08:08:15 PM UTC 24 |
11648405338 ps |
| T241 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.636730877 |
|
|
Aug 28 08:08:12 PM UTC 24 |
Aug 28 08:08:16 PM UTC 24 |
2533041897 ps |
| T138 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.2481762944 |
|
|
Aug 28 08:07:47 PM UTC 24 |
Aug 28 08:08:17 PM UTC 24 |
70411879760 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1961005533 |
|
|
Aug 28 08:08:09 PM UTC 24 |
Aug 28 08:08:17 PM UTC 24 |
2466063561 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.55347090 |
|
|
Aug 28 08:08:14 PM UTC 24 |
Aug 28 08:08:18 PM UTC 24 |
3349113440 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.667598426 |
|
|
Aug 28 08:07:58 PM UTC 24 |
Aug 28 08:08:18 PM UTC 24 |
3953098259 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2306578987 |
|
|
Aug 28 08:08:08 PM UTC 24 |
Aug 28 08:08:19 PM UTC 24 |
2017808847 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.537576938 |
|
|
Aug 28 08:07:58 PM UTC 24 |
Aug 28 08:08:20 PM UTC 24 |
12045639604 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2081286058 |
|
|
Aug 28 08:08:04 PM UTC 24 |
Aug 28 08:08:20 PM UTC 24 |
3473478735 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1528815195 |
|
|
Aug 28 08:08:16 PM UTC 24 |
Aug 28 08:08:20 PM UTC 24 |
6015827541 ps |
| T395 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.679915358 |
|
|
Aug 28 08:07:42 PM UTC 24 |
Aug 28 08:08:20 PM UTC 24 |
58952433530 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.3047062672 |
|
|
Aug 28 08:08:19 PM UTC 24 |
Aug 28 08:08:54 PM UTC 24 |
12895663087 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3559276711 |
|
|
Aug 28 08:08:10 PM UTC 24 |
Aug 28 08:08:21 PM UTC 24 |
2020019638 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2596307620 |
|
|
Aug 28 08:05:21 PM UTC 24 |
Aug 28 08:08:22 PM UTC 24 |
71919594307 ps |
| T139 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.3162068338 |
|
|
Aug 28 08:07:43 PM UTC 24 |
Aug 28 08:08:23 PM UTC 24 |
75406186628 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.403515346 |
|
|
Aug 28 08:08:20 PM UTC 24 |
Aug 28 08:08:24 PM UTC 24 |
2033075510 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.484545044 |
|
|
Aug 28 08:08:18 PM UTC 24 |
Aug 28 08:08:24 PM UTC 24 |
5125819385 ps |
| T403 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1117046316 |
|
|
Aug 28 08:07:04 PM UTC 24 |
Aug 28 08:08:24 PM UTC 24 |
74777465603 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2354183925 |
|
|
Aug 28 08:08:14 PM UTC 24 |
Aug 28 08:08:24 PM UTC 24 |
2606939696 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.791500842 |
|
|
Aug 28 08:07:57 PM UTC 24 |
Aug 28 08:08:25 PM UTC 24 |
21850846309 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.2771518493 |
|
|
Aug 28 08:08:22 PM UTC 24 |
Aug 28 08:08:25 PM UTC 24 |
2559182452 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.11863641 |
|
|
Aug 28 08:08:20 PM UTC 24 |
Aug 28 08:08:25 PM UTC 24 |
2473835343 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2493083299 |
|
|
Aug 28 08:08:15 PM UTC 24 |
Aug 28 08:08:25 PM UTC 24 |
3688184520 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2949135336 |
|
|
Aug 28 08:08:23 PM UTC 24 |
Aug 28 08:08:25 PM UTC 24 |
2651988280 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1417734246 |
|
|
Aug 28 08:08:24 PM UTC 24 |
Aug 28 08:08:26 PM UTC 24 |
2838948870 ps |
| T374 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.985489025 |
|
|
Aug 28 08:01:29 PM UTC 24 |
Aug 28 08:08:27 PM UTC 24 |
156108807305 ps |
| T426 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.1915768724 |
|
|
Aug 28 08:06:46 PM UTC 24 |
Aug 28 08:08:28 PM UTC 24 |
181284486538 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.3478382186 |
|
|
Aug 28 08:08:25 PM UTC 24 |
Aug 28 08:08:28 PM UTC 24 |
2035822553 ps |
| T274 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.4236507741 |
|
|
Aug 28 08:08:25 PM UTC 24 |
Aug 28 08:08:30 PM UTC 24 |
4384505051 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.3354746273 |
|
|
Aug 28 08:08:20 PM UTC 24 |
Aug 28 08:08:32 PM UTC 24 |
2114344474 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.1849654231 |
|
|
Aug 28 08:08:20 PM UTC 24 |
Aug 28 08:08:32 PM UTC 24 |
2264018541 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.4021762244 |
|
|
Aug 28 08:08:29 PM UTC 24 |
Aug 28 08:08:32 PM UTC 24 |
2730273242 ps |
| T418 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.3026028374 |
|
|
Aug 28 08:06:55 PM UTC 24 |
Aug 28 08:08:33 PM UTC 24 |
119495994418 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2648428582 |
|
|
Aug 28 08:08:28 PM UTC 24 |
Aug 28 08:08:33 PM UTC 24 |
2632963156 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3578633241 |
|
|
Aug 28 08:08:29 PM UTC 24 |
Aug 28 08:08:33 PM UTC 24 |
3582351911 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.4105780675 |
|
|
Aug 28 08:08:27 PM UTC 24 |
Aug 28 08:08:33 PM UTC 24 |
2246182899 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.2242594819 |
|
|
Aug 28 08:08:28 PM UTC 24 |
Aug 28 08:08:34 PM UTC 24 |
2516399330 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3129212991 |
|
|
Aug 28 08:08:26 PM UTC 24 |
Aug 28 08:08:34 PM UTC 24 |
2111824291 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.584941444 |
|
|
Aug 28 08:08:31 PM UTC 24 |
Aug 28 08:08:36 PM UTC 24 |
7253063977 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1508738112 |
|
|
Aug 28 08:08:08 PM UTC 24 |
Aug 28 08:08:36 PM UTC 24 |
6884639523 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3297500159 |
|
|
Aug 28 08:08:25 PM UTC 24 |
Aug 28 08:08:36 PM UTC 24 |
2104028500 ps |
| T330 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1848319554 |
|
|
Aug 28 08:08:19 PM UTC 24 |
Aug 28 08:08:37 PM UTC 24 |
22942162669 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.1518378200 |
|
|
Aug 28 08:08:34 PM UTC 24 |
Aug 28 08:08:38 PM UTC 24 |
2032474218 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1009302241 |
|
|
Aug 28 08:08:23 PM UTC 24 |
Aug 28 08:08:38 PM UTC 24 |
3236370934 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.2440863906 |
|
|
Aug 28 08:08:41 PM UTC 24 |
Aug 28 08:08:54 PM UTC 24 |
17067985260 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.2402566826 |
|
|
Aug 28 08:08:35 PM UTC 24 |
Aug 28 08:08:38 PM UTC 24 |
2089876589 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.3496778890 |
|
|
Aug 28 08:08:35 PM UTC 24 |
Aug 28 08:08:39 PM UTC 24 |
2473161683 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3215329896 |
|
|
Aug 28 08:08:27 PM UTC 24 |
Aug 28 08:08:39 PM UTC 24 |
2442545854 ps |
| T372 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4186632863 |
|
|
Aug 28 08:08:07 PM UTC 24 |
Aug 28 08:08:40 PM UTC 24 |
37664668599 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.2193423198 |
|
|
Aug 28 08:08:35 PM UTC 24 |
Aug 28 08:08:42 PM UTC 24 |
2115251345 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3782809754 |
|
|
Aug 28 08:08:37 PM UTC 24 |
Aug 28 08:08:42 PM UTC 24 |
2635782413 ps |
| T264 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.80700086 |
|
|
Aug 28 08:08:33 PM UTC 24 |
Aug 28 08:08:42 PM UTC 24 |
2888070839 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.3252134910 |
|
|
Aug 28 08:08:39 PM UTC 24 |
Aug 28 08:08:42 PM UTC 24 |
3238817880 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3483535788 |
|
|
Aug 28 08:08:23 PM UTC 24 |
Aug 28 08:08:42 PM UTC 24 |
5401928128 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.380915748 |
|
|
Aug 28 08:08:25 PM UTC 24 |
Aug 28 08:08:44 PM UTC 24 |
12598693664 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.948600911 |
|
|
Aug 28 08:08:39 PM UTC 24 |
Aug 28 08:08:46 PM UTC 24 |
3751707350 ps |
| T440 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1571133900 |
|
|
Aug 28 08:08:05 PM UTC 24 |
Aug 28 08:08:46 PM UTC 24 |
1663385467338 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.200598765 |
|
|
Aug 28 08:08:43 PM UTC 24 |
Aug 28 08:08:46 PM UTC 24 |
2043621577 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2449790412 |
|
|
Aug 28 08:08:37 PM UTC 24 |
Aug 28 08:08:46 PM UTC 24 |
3744295490 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1998148339 |
|
|
Aug 28 08:07:25 PM UTC 24 |
Aug 28 08:08:47 PM UTC 24 |
34602717188 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.1037349759 |
|
|
Aug 28 08:08:37 PM UTC 24 |
Aug 28 08:08:50 PM UTC 24 |
2510957929 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.4260691770 |
|
|
Aug 28 08:08:34 PM UTC 24 |
Aug 28 08:08:50 PM UTC 24 |
11134143991 ps |
| T310 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2699536167 |
|
|
Aug 28 08:05:11 PM UTC 24 |
Aug 28 08:08:51 PM UTC 24 |
75583103297 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.179733996 |
|
|
Aug 28 08:08:05 PM UTC 24 |
Aug 28 08:08:51 PM UTC 24 |
108346394448 ps |
| T756 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.3152460214 |
|
|
Aug 28 08:07:57 PM UTC 24 |
Aug 28 08:08:54 PM UTC 24 |
88896272571 ps |
| T757 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.750891580 |
|
|
Aug 28 08:08:40 PM UTC 24 |
Aug 28 08:08:56 PM UTC 24 |
6291047965 ps |
| T758 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.506496925 |
|
|
Aug 28 08:08:38 PM UTC 24 |
Aug 28 08:08:56 PM UTC 24 |
3723050960 ps |
| T417 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.3420346671 |
|
|
Aug 28 08:05:36 PM UTC 24 |
Aug 28 08:08:59 PM UTC 24 |
65191555005 ps |
| T405 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1559028181 |
|
|
Aug 28 08:06:21 PM UTC 24 |
Aug 28 08:09:00 PM UTC 24 |
151140674111 ps |
| T414 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.2951283786 |
|
|
Aug 28 08:07:24 PM UTC 24 |
Aug 28 08:09:01 PM UTC 24 |
213334698298 ps |
| T331 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3313096274 |
|
|
Aug 28 08:08:33 PM UTC 24 |
Aug 28 08:09:01 PM UTC 24 |
7562437401 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.1745982978 |
|
|
Aug 28 08:08:33 PM UTC 24 |
Aug 28 08:09:04 PM UTC 24 |
31853233285 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.111353328 |
|
|
Aug 28 08:07:04 PM UTC 24 |
Aug 28 08:09:09 PM UTC 24 |
34416121748 ps |
| T759 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.1320693974 |
|
|
Aug 28 08:07:39 PM UTC 24 |
Aug 28 08:09:12 PM UTC 24 |
86637151470 ps |
| T760 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.1938770133 |
|
|
Aug 28 08:07:10 PM UTC 24 |
Aug 28 08:09:21 PM UTC 24 |
62365482506 ps |
| T761 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4138635306 |
|
|
Aug 28 08:07:56 PM UTC 24 |
Aug 28 08:09:22 PM UTC 24 |
823077481015 ps |
| T396 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3232927721 |
|
|
Aug 28 08:08:43 PM UTC 24 |
Aug 28 08:09:24 PM UTC 24 |
51701435471 ps |
| T289 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.1324782322 |
|
|
Aug 28 08:08:17 PM UTC 24 |
Aug 28 08:09:25 PM UTC 24 |
70734086892 ps |
| T762 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.671136864 |
|
|
Aug 28 08:09:04 PM UTC 24 |
Aug 28 08:09:25 PM UTC 24 |
26615358802 ps |
| T428 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3028556891 |
|
|
Aug 28 08:09:00 PM UTC 24 |
Aug 28 08:09:27 PM UTC 24 |
63811499554 ps |
| T412 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3672008798 |
|
|
Aug 28 08:08:43 PM UTC 24 |
Aug 28 08:09:29 PM UTC 24 |
39882227655 ps |
| T400 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1501557169 |
|
|
Aug 28 08:09:30 PM UTC 24 |
Aug 28 08:11:56 PM UTC 24 |
56242463045 ps |
| T763 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.935095580 |
|
|
Aug 28 08:01:55 PM UTC 24 |
Aug 28 08:09:35 PM UTC 24 |
160188856324 ps |
| T764 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.4252593827 |
|
|
Aug 28 08:08:55 PM UTC 24 |
Aug 28 08:09:41 PM UTC 24 |
75860181653 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.31692348 |
|
|
Aug 28 08:08:08 PM UTC 24 |
Aug 28 08:09:42 PM UTC 24 |
77514814554 ps |
| T765 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2413453240 |
|
|
Aug 28 08:07:16 PM UTC 24 |
Aug 28 08:09:43 PM UTC 24 |
46009999508 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2907219543 |
|
|
Aug 28 08:08:47 PM UTC 24 |
Aug 28 08:09:44 PM UTC 24 |
63193018931 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1390013006 |
|
|
Aug 28 08:07:46 PM UTC 24 |
Aug 28 08:09:44 PM UTC 24 |
1686635066801 ps |
| T425 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.1125084797 |
|
|
Aug 28 08:05:19 PM UTC 24 |
Aug 28 08:09:45 PM UTC 24 |
96144934507 ps |
| T766 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.709046377 |
|
|
Aug 28 08:08:55 PM UTC 24 |
Aug 28 08:09:51 PM UTC 24 |
34356335450 ps |
| T767 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.2404351489 |
|
|
Aug 28 08:01:46 PM UTC 24 |
Aug 28 08:09:51 PM UTC 24 |
169774458636 ps |
| T385 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1709824234 |
|
|
Aug 28 08:07:10 PM UTC 24 |
Aug 28 08:09:52 PM UTC 24 |
79532105346 ps |
| T120 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.668256089 |
|
|
Aug 28 08:09:13 PM UTC 24 |
Aug 28 08:10:02 PM UTC 24 |
40321615429 ps |
| T768 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2787470864 |
|
|
Aug 28 08:09:41 PM UTC 24 |
Aug 28 08:10:02 PM UTC 24 |
26855641994 ps |
| T408 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.258286452 |
|
|
Aug 28 08:06:00 PM UTC 24 |
Aug 28 08:10:04 PM UTC 24 |
75624737231 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.2367209438 |
|
|
Aug 28 08:05:10 PM UTC 24 |
Aug 28 08:10:06 PM UTC 24 |
182140651083 ps |
| T427 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.576212970 |
|
|
Aug 28 08:09:45 PM UTC 24 |
Aug 28 08:10:08 PM UTC 24 |
23096357559 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1752892005 |
|
|
Aug 28 08:09:45 PM UTC 24 |
Aug 28 08:12:19 PM UTC 24 |
91576078554 ps |
| T769 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3725250497 |
|
|
Aug 28 08:09:02 PM UTC 24 |
Aug 28 08:10:09 PM UTC 24 |
18328420399 ps |
| T311 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.3436013914 |
|
|
Aug 28 08:07:33 PM UTC 24 |
Aug 28 08:10:18 PM UTC 24 |
70536910829 ps |
| T401 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3152600962 |
|
|
Aug 28 08:05:37 PM UTC 24 |
Aug 28 08:10:19 PM UTC 24 |
87391937008 ps |
| T770 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1785532320 |
|
|
Aug 28 08:08:45 PM UTC 24 |
Aug 28 08:10:21 PM UTC 24 |
69137062029 ps |
| T771 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3850245748 |
|
|
Aug 28 08:10:09 PM UTC 24 |
Aug 28 08:10:27 PM UTC 24 |
31014582324 ps |
| T772 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2996919150 |
|
|
Aug 28 08:08:44 PM UTC 24 |
Aug 28 08:10:29 PM UTC 24 |
28079237324 ps |
| T430 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.913834261 |
|
|
Aug 28 08:10:02 PM UTC 24 |
Aug 28 08:10:30 PM UTC 24 |
21348714889 ps |
| T413 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2196413532 |
|
|
Aug 28 08:08:25 PM UTC 24 |
Aug 28 08:10:30 PM UTC 24 |
149373616777 ps |
| T773 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2895275807 |
|
|
Aug 28 08:08:47 PM UTC 24 |
Aug 28 08:10:32 PM UTC 24 |
52665148524 ps |
| T774 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2042683253 |
|
|
Aug 28 08:09:46 PM UTC 24 |
Aug 28 08:10:38 PM UTC 24 |
47037064527 ps |
| T775 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.466791431 |
|
|
Aug 28 08:09:35 PM UTC 24 |
Aug 28 08:10:39 PM UTC 24 |
24831482609 ps |
| T404 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3245246915 |
|
|
Aug 28 08:08:55 PM UTC 24 |
Aug 28 08:10:39 PM UTC 24 |
94089991441 ps |
| T776 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3780989996 |
|
|
Aug 28 08:07:03 PM UTC 24 |
Aug 28 08:10:43 PM UTC 24 |
71315145829 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2893042205 |
|
|
Aug 28 08:07:15 PM UTC 24 |
Aug 28 08:10:45 PM UTC 24 |
136828041366 ps |
| T409 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1132396618 |
|
|
Aug 28 08:09:01 PM UTC 24 |
Aug 28 08:10:50 PM UTC 24 |
73022835327 ps |
| T777 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.659823302 |
|
|
Aug 28 08:10:09 PM UTC 24 |
Aug 28 08:10:52 PM UTC 24 |
64021191862 ps |
| T282 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1478929392 |
|
|
Aug 28 08:08:18 PM UTC 24 |
Aug 28 08:10:56 PM UTC 24 |
35459669762 ps |
| T778 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.2916555775 |
|
|
Aug 28 08:05:33 PM UTC 24 |
Aug 28 08:10:56 PM UTC 24 |
97227873596 ps |
| T300 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.3572789490 |
|
|
Aug 28 08:05:18 PM UTC 24 |
Aug 28 08:11:00 PM UTC 24 |
115309750818 ps |
| T419 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.4177807539 |
|
|
Aug 28 08:05:46 PM UTC 24 |
Aug 28 08:11:08 PM UTC 24 |
136935911787 ps |
| T779 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3262012945 |
|
|
Aug 28 08:10:07 PM UTC 24 |
Aug 28 08:11:19 PM UTC 24 |
40197113081 ps |
| T780 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.307476373 |
|
|
Aug 28 08:08:51 PM UTC 24 |
Aug 28 08:11:23 PM UTC 24 |
162081090413 ps |
| T781 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3786931441 |
|
|
Aug 28 08:05:16 PM UTC 24 |
Aug 28 08:11:23 PM UTC 24 |
114326320405 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.1276143500 |
|
|
Aug 28 08:05:56 PM UTC 24 |
Aug 28 08:11:28 PM UTC 24 |
109013363892 ps |
| T431 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.71535567 |
|
|
Aug 28 08:09:52 PM UTC 24 |
Aug 28 08:11:30 PM UTC 24 |
25579031312 ps |
| T782 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2383818526 |
|
|
Aug 28 08:09:26 PM UTC 24 |
Aug 28 08:11:32 PM UTC 24 |
43322374594 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.761547742 |
|
|
Aug 28 08:06:30 PM UTC 24 |
Aug 28 08:11:34 PM UTC 24 |
76489219039 ps |
| T140 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.402736531 |
|
|
Aug 28 08:06:39 PM UTC 24 |
Aug 28 08:11:37 PM UTC 24 |
198535885002 ps |
| T429 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2923675224 |
|
|
Aug 28 08:08:53 PM UTC 24 |
Aug 28 08:11:38 PM UTC 24 |
54599237505 ps |
| T283 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3158276033 |
|
|
Aug 28 08:09:26 PM UTC 24 |
Aug 28 08:11:43 PM UTC 24 |
62613491848 ps |
| T410 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1753599352 |
|
|
Aug 28 08:09:52 PM UTC 24 |
Aug 28 08:11:46 PM UTC 24 |
148465910193 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2345417865 |
|
|
Aug 28 08:08:47 PM UTC 24 |
Aug 28 08:11:49 PM UTC 24 |
58678274359 ps |
| T442 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3359019764 |
|
|
Aug 28 08:06:29 PM UTC 24 |
Aug 28 08:11:52 PM UTC 24 |
2316809240258 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3352996387 |
|
|
Aug 28 08:09:35 PM UTC 24 |
Aug 28 08:12:26 PM UTC 24 |
69097976466 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2680473688 |
|
|
Aug 28 08:08:43 PM UTC 24 |
Aug 28 08:12:46 PM UTC 24 |
124765649810 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3988217300 |
|
|
Aug 28 08:08:47 PM UTC 24 |
Aug 28 08:12:58 PM UTC 24 |
67442482140 ps |
| T783 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3688495343 |
|
|
Aug 28 08:09:42 PM UTC 24 |
Aug 28 08:13:07 PM UTC 24 |
129593586468 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.178896592 |
|
|
Aug 28 08:05:46 PM UTC 24 |
Aug 28 08:13:09 PM UTC 24 |
2213158029902 ps |
| T402 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1314905606 |
|
|
Aug 28 08:09:27 PM UTC 24 |
Aug 28 08:13:15 PM UTC 24 |
146841247552 ps |
| T784 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3563305269 |
|
|
Aug 28 08:08:57 PM UTC 24 |
Aug 28 08:13:16 PM UTC 24 |
90868816936 ps |
| T785 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2362683374 |
|
|
Aug 28 08:09:23 PM UTC 24 |
Aug 28 08:13:28 PM UTC 24 |
65267187746 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2407238854 |
|
|
Aug 28 08:05:40 PM UTC 24 |
Aug 28 08:13:34 PM UTC 24 |
141007332733 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2017734201 |
|
|
Aug 28 08:08:51 PM UTC 24 |
Aug 28 08:13:36 PM UTC 24 |
77300696928 ps |
| T393 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.202328585 |
|
|
Aug 28 08:09:24 PM UTC 24 |
Aug 28 08:13:43 PM UTC 24 |
77775985442 ps |
| T407 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.993917890 |
|
|
Aug 28 08:10:03 PM UTC 24 |
Aug 28 08:13:58 PM UTC 24 |
88688960597 ps |
| T376 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.1335230218 |
|
|
Aug 28 08:05:30 PM UTC 24 |
Aug 28 08:14:05 PM UTC 24 |
167482248676 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3917592691 |
|
|
Aug 28 08:09:45 PM UTC 24 |
Aug 28 08:14:06 PM UTC 24 |
72229347713 ps |
| T786 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2420691189 |
|
|
Aug 28 08:09:10 PM UTC 24 |
Aug 28 08:14:27 PM UTC 24 |
74572310110 ps |
| T141 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.2979960435 |
|
|
Aug 28 08:08:39 PM UTC 24 |
Aug 28 08:14:41 PM UTC 24 |
101488196856 ps |
| T787 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.2283254736 |
|
|
Aug 28 08:05:28 PM UTC 24 |
Aug 28 08:14:55 PM UTC 24 |
173244487481 ps |
| T788 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.3950748111 |
|
|
Aug 28 08:07:09 PM UTC 24 |
Aug 28 08:15:11 PM UTC 24 |
162852406816 ps |
| T204 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.3720211134 |
|
|
Aug 28 08:07:34 PM UTC 24 |
Aug 28 08:15:16 PM UTC 24 |
260338709857 ps |
| T789 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3965808260 |
|
|
Aug 28 08:09:25 PM UTC 24 |
Aug 28 08:15:24 PM UTC 24 |
134428787024 ps |
| T142 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.2612769152 |
|
|
Aug 28 08:06:15 PM UTC 24 |
Aug 28 08:15:33 PM UTC 24 |
174205948320 ps |
| T790 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.445328165 |
|
|
Aug 28 08:08:57 PM UTC 24 |
Aug 28 08:15:42 PM UTC 24 |
94958983338 ps |
| T791 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2247212307 |
|
|
Aug 28 08:09:01 PM UTC 24 |
Aug 28 08:16:10 PM UTC 24 |
111642586274 ps |
| T411 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1830683420 |
|
|
Aug 28 08:08:40 PM UTC 24 |
Aug 28 08:17:27 PM UTC 24 |
159862055519 ps |
| T792 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3567230328 |
|
|
Aug 28 08:07:14 PM UTC 24 |
Aug 28 08:17:38 PM UTC 24 |
753979153638 ps |
| T394 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.843960613 |
|
|
Aug 28 08:08:47 PM UTC 24 |
Aug 28 08:17:43 PM UTC 24 |
140193422209 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2106799040 |
|
|
Aug 28 08:10:05 PM UTC 24 |
Aug 28 08:18:36 PM UTC 24 |
144105492610 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.300371274 |
|
|
Aug 28 08:05:57 PM UTC 24 |
Aug 28 08:20:50 PM UTC 24 |
241454160254 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.2086480638 |
|
|
Aug 28 08:08:25 PM UTC 24 |
Aug 28 08:22:16 PM UTC 24 |
188272527046 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.3717859983 |
|
|
Aug 28 08:01:20 PM UTC 24 |
Aug 28 08:27:41 PM UTC 24 |
799176660020 ps |
| T231 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.3348205518 |
|
|
Aug 28 08:05:51 PM UTC 24 |
Aug 28 08:35:03 PM UTC 24 |
473929680049 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.1325790009 |
|
|
Aug 28 08:01:27 PM UTC 24 |
Aug 28 08:54:18 PM UTC 24 |
838530736146 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3969012752 |
|
|
Aug 28 08:05:26 PM UTC 24 |
Aug 28 08:59:57 PM UTC 24 |
954413622208 ps |
| T316 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.160692489 |
|
|
Aug 28 08:10:11 PM UTC 24 |
Aug 28 08:10:19 PM UTC 24 |
2052311449 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1311440565 |
|
|
Aug 28 08:10:20 PM UTC 24 |
Aug 28 08:10:26 PM UTC 24 |
2024208314 ps |
| T38 |
/workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1805823061 |
|
|
Aug 28 08:10:20 PM UTC 24 |
Aug 28 08:10:30 PM UTC 24 |
4035024523 ps |