Tests
dashboard | hierarchy | modlist | groups | tests | asserts
Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
96.73 98.73 98.03 100.00 93.59 98.96 99.42 88.34


Total test records in report: 912
tests.html | tests1.html | tests2.html | tests3.html | tests4.html | tests5.html | tests6.html | tests7.html | tests8.html | tests9.html | tests10.html | tests11.html | tests12.html | tests13.html | tests14.html | tests15.html | tests16.html | tests17.html | tests18.html
T22 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3392419987 Aug 28 08:10:22 PM UTC 24 Aug 28 08:10:31 PM UTC 24 2053216311 ps
T39 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2529415851 Aug 28 08:10:28 PM UTC 24 Aug 28 08:10:33 PM UTC 24 4505616894 ps
T345 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3443276159 Aug 28 08:10:30 PM UTC 24 Aug 28 08:10:35 PM UTC 24 2094194582 ps
T23 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3798467473 Aug 28 08:10:29 PM UTC 24 Aug 28 08:10:35 PM UTC 24 4891786732 ps
T797 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2866022951 Aug 28 08:10:31 PM UTC 24 Aug 28 08:10:36 PM UTC 24 2032326891 ps
T354 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2510506381 Aug 28 08:10:34 PM UTC 24 Aug 28 08:10:37 PM UTC 24 2074890675 ps
T317 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2295710900 Aug 28 08:10:30 PM UTC 24 Aug 28 08:10:37 PM UTC 24 2201937099 ps
T322 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2001966145 Aug 28 08:10:33 PM UTC 24 Aug 28 08:10:39 PM UTC 24 4067608881 ps
T24 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.433935279 Aug 28 08:10:36 PM UTC 24 Aug 28 08:10:42 PM UTC 24 5364292179 ps
T318 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1516372708 Aug 28 08:10:19 PM UTC 24 Aug 28 08:10:43 PM UTC 24 42869852755 ps
T355 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1248860712 Aug 28 08:10:39 PM UTC 24 Aug 28 08:10:44 PM UTC 24 2118789797 ps
T369 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3793692071 Aug 28 08:10:39 PM UTC 24 Aug 28 08:10:44 PM UTC 24 6211232605 ps
T323 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3878315028 Aug 28 08:10:36 PM UTC 24 Aug 28 08:10:48 PM UTC 24 3192289488 ps
T321 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2726224242 Aug 28 08:10:38 PM UTC 24 Aug 28 08:10:50 PM UTC 24 2025955066 ps
T798 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1611651051 Aug 28 08:10:38 PM UTC 24 Aug 28 08:10:50 PM UTC 24 2014569386 ps
T352 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.523449018 Aug 28 08:10:45 PM UTC 24 Aug 28 08:10:50 PM UTC 24 2184492950 ps
T353 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2323290178 Aug 28 08:10:37 PM UTC 24 Aug 28 08:10:50 PM UTC 24 2035887498 ps
T356 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.4059275953 Aug 28 08:10:42 PM UTC 24 Aug 28 08:10:51 PM UTC 24 3788009286 ps
T326 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.69973452 Aug 28 08:10:45 PM UTC 24 Aug 28 08:10:51 PM UTC 24 2287994734 ps
T799 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3696205547 Aug 28 08:10:46 PM UTC 24 Aug 28 08:10:52 PM UTC 24 2027814105 ps
T357 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3652941113 Aug 28 08:10:50 PM UTC 24 Aug 28 08:10:54 PM UTC 24 2076216232 ps
T319 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.137335272 Aug 28 08:10:38 PM UTC 24 Aug 28 08:10:58 PM UTC 24 43008362292 ps
T421 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.2139275888 Aug 28 08:10:51 PM UTC 24 Aug 28 08:11:01 PM UTC 24 2697036878 ps
T800 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1112195103 Aug 28 08:10:53 PM UTC 24 Aug 28 08:11:02 PM UTC 24 2016168280 ps
T358 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1977883522 Aug 28 08:10:54 PM UTC 24 Aug 28 08:11:02 PM UTC 24 6099857910 ps
T801 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1477364788 Aug 28 08:10:59 PM UTC 24 Aug 28 08:11:02 PM UTC 24 2422820894 ps
T359 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3920400791 Aug 28 08:10:49 PM UTC 24 Aug 28 08:11:02 PM UTC 24 4011632500 ps
T329 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1454004452 Aug 28 08:10:51 PM UTC 24 Aug 28 08:11:02 PM UTC 24 2041442891 ps
T324 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1226379010 Aug 28 08:10:52 PM UTC 24 Aug 28 08:11:04 PM UTC 24 2152362203 ps
T360 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2448288818 Aug 28 08:11:02 PM UTC 24 Aug 28 08:11:06 PM UTC 24 2083734544 ps
T327 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.582199564 Aug 28 08:11:01 PM UTC 24 Aug 28 08:11:07 PM UTC 24 2303835345 ps
T368 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1683694017 Aug 28 08:10:55 PM UTC 24 Aug 28 08:11:07 PM UTC 24 2057021366 ps
T802 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1600873040 Aug 28 08:10:57 PM UTC 24 Aug 28 08:11:07 PM UTC 24 3172615733 ps
T423 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2391064664 Aug 28 08:11:03 PM UTC 24 Aug 28 08:11:08 PM UTC 24 2107378113 ps
T25 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.477085599 Aug 28 08:11:03 PM UTC 24 Aug 28 08:11:10 PM UTC 24 4578709392 ps
T803 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.78275955 Aug 28 08:11:37 PM UTC 24 Aug 28 08:11:41 PM UTC 24 2019635254 ps
T804 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3881742844 Aug 28 08:11:07 PM UTC 24 Aug 28 08:11:11 PM UTC 24 2027633190 ps
T26 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2376131572 Aug 28 08:10:51 PM UTC 24 Aug 28 08:11:12 PM UTC 24 5232604283 ps
T805 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3860385680 Aug 28 08:11:02 PM UTC 24 Aug 28 08:11:14 PM UTC 24 2015057016 ps
T361 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.599524675 Aug 28 08:11:08 PM UTC 24 Aug 28 08:11:15 PM UTC 24 2032328880 ps
T422 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.996559329 Aug 28 08:11:08 PM UTC 24 Aug 28 08:11:15 PM UTC 24 2066697330 ps
T328 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1118933898 Aug 28 08:11:09 PM UTC 24 Aug 28 08:11:16 PM UTC 24 2384053530 ps
T806 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.4076490511 Aug 28 08:11:11 PM UTC 24 Aug 28 08:11:16 PM UTC 24 2108745859 ps
T807 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.688798864 Aug 28 08:11:08 PM UTC 24 Aug 28 08:11:16 PM UTC 24 5059450110 ps
T325 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1871224992 Aug 28 08:11:03 PM UTC 24 Aug 28 08:11:17 PM UTC 24 2034705368 ps
T808 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1543746778 Aug 28 08:11:11 PM UTC 24 Aug 28 08:11:18 PM UTC 24 2020059652 ps
T424 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2223149890 Aug 28 08:11:17 PM UTC 24 Aug 28 08:11:21 PM UTC 24 2083001220 ps
T809 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.868406849 Aug 28 08:10:57 PM UTC 24 Aug 28 08:11:23 PM UTC 24 4920714211 ps
T810 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4139696596 Aug 28 08:11:15 PM UTC 24 Aug 28 08:11:23 PM UTC 24 2080561373 ps
T811 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3026407427 Aug 28 08:11:17 PM UTC 24 Aug 28 08:11:23 PM UTC 24 2021775104 ps
T812 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2862979694 Aug 28 08:11:15 PM UTC 24 Aug 28 08:11:24 PM UTC 24 2174383427 ps
T813 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1899710791 Aug 28 08:11:13 PM UTC 24 Aug 28 08:11:24 PM UTC 24 4557791132 ps
T320 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3558041275 Aug 28 08:10:46 PM UTC 24 Aug 28 08:11:25 PM UTC 24 42820199911 ps
T814 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1635591488 Aug 28 08:10:44 PM UTC 24 Aug 28 08:11:27 PM UTC 24 9235503008 ps
T815 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.374543691 Aug 28 08:11:23 PM UTC 24 Aug 28 08:11:28 PM UTC 24 4614115816 ps
T816 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2470159666 Aug 28 08:11:18 PM UTC 24 Aug 28 08:11:28 PM UTC 24 2084354417 ps
T817 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3109227423 Aug 28 08:11:22 PM UTC 24 Aug 28 08:11:28 PM UTC 24 2019374027 ps
T818 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.837589219 Aug 28 08:11:25 PM UTC 24 Aug 28 08:11:29 PM UTC 24 2060657703 ps
T819 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.652336806 Aug 28 08:11:24 PM UTC 24 Aug 28 08:11:31 PM UTC 24 2117234873 ps
T820 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3481700424 Aug 28 08:11:19 PM UTC 24 Aug 28 08:11:31 PM UTC 24 2050109159 ps
T821 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.424346563 Aug 28 08:11:24 PM UTC 24 Aug 28 08:11:32 PM UTC 24 2019045693 ps
T362 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3410818374 Aug 28 08:10:35 PM UTC 24 Aug 28 08:11:33 PM UTC 24 51234190762 ps
T822 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3387292095 Aug 28 08:11:29 PM UTC 24 Aug 28 08:11:38 PM UTC 24 2117569022 ps
T823 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2934989876 Aug 28 08:11:29 PM UTC 24 Aug 28 08:11:33 PM UTC 24 2043049897 ps
T824 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.14461682 Aug 28 08:11:28 PM UTC 24 Aug 28 08:11:35 PM UTC 24 2103600911 ps
T825 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2988559115 Aug 28 08:11:23 PM UTC 24 Aug 28 08:11:36 PM UTC 24 2056117963 ps
T826 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.61426326 Aug 28 08:11:18 PM UTC 24 Aug 28 08:11:36 PM UTC 24 5950804368 ps
T827 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.4152358393 Aug 28 08:11:24 PM UTC 24 Aug 28 08:11:36 PM UTC 24 2041821639 ps
T363 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1897441314 Aug 28 08:11:29 PM UTC 24 Aug 28 08:11:36 PM UTC 24 2046140980 ps
T828 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2008252656 Aug 28 08:11:33 PM UTC 24 Aug 28 08:11:36 PM UTC 24 2076142369 ps
T829 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1296853165 Aug 28 08:11:32 PM UTC 24 Aug 28 08:11:37 PM UTC 24 2051111599 ps
T830 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3154967150 Aug 28 08:11:35 PM UTC 24 Aug 28 08:11:40 PM UTC 24 2587499201 ps
T831 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.760325465 Aug 28 08:11:27 PM UTC 24 Aug 28 08:11:38 PM UTC 24 7694369816 ps
T832 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1687804767 Aug 28 08:11:34 PM UTC 24 Aug 28 08:11:41 PM UTC 24 4949138363 ps
T833 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2672600917 Aug 28 08:11:34 PM UTC 24 Aug 28 08:11:42 PM UTC 24 2047362255 ps
T387 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1296019754 Aug 28 08:10:52 PM UTC 24 Aug 28 08:11:42 PM UTC 24 42776841987 ps
T834 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2387777684 Aug 28 08:11:31 PM UTC 24 Aug 28 08:11:42 PM UTC 24 2068486487 ps
T835 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.206059339 Aug 28 08:11:24 PM UTC 24 Aug 28 08:11:42 PM UTC 24 22529151775 ps
T836 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.248217422 Aug 28 08:11:38 PM UTC 24 Aug 28 08:11:42 PM UTC 24 2025409120 ps
T837 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.99834113 Aug 28 08:11:37 PM UTC 24 Aug 28 08:11:43 PM UTC 24 2468297153 ps
T838 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1218527077 Aug 28 08:11:40 PM UTC 24 Aug 28 08:11:43 PM UTC 24 2104888303 ps
T364 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2597203446 Aug 28 08:11:38 PM UTC 24 Aug 28 08:11:44 PM UTC 24 2068390300 ps
T839 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.129788948 Aug 28 08:11:31 PM UTC 24 Aug 28 08:11:44 PM UTC 24 2068587514 ps
T840 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1752358837 Aug 28 08:11:43 PM UTC 24 Aug 28 08:11:47 PM UTC 24 2060574771 ps
T841 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2398183588 Aug 28 08:11:43 PM UTC 24 Aug 28 08:11:48 PM UTC 24 2188932096 ps
T842 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.736531783 Aug 28 08:11:43 PM UTC 24 Aug 28 08:11:48 PM UTC 24 2091032776 ps
T843 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1295728688 Aug 28 08:11:37 PM UTC 24 Aug 28 08:11:49 PM UTC 24 10911324853 ps
T844 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2633458374 Aug 28 08:11:37 PM UTC 24 Aug 28 08:11:49 PM UTC 24 2034512791 ps
T365 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1615546299 Aug 28 08:11:37 PM UTC 24 Aug 28 08:11:49 PM UTC 24 2043387740 ps
T845 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2433563441 Aug 28 08:11:44 PM UTC 24 Aug 28 08:11:50 PM UTC 24 2068546159 ps
T846 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.748125255 Aug 28 08:11:42 PM UTC 24 Aug 28 08:11:50 PM UTC 24 22478451853 ps
T847 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.397114768 Aug 28 08:11:32 PM UTC 24 Aug 28 08:11:50 PM UTC 24 22254424460 ps
T848 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.80239549 Aug 28 08:11:44 PM UTC 24 Aug 28 08:11:51 PM UTC 24 2024091728 ps
T849 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.156702577 Aug 28 08:11:41 PM UTC 24 Aug 28 08:11:51 PM UTC 24 2075840545 ps
T366 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3997744582 Aug 28 08:11:49 PM UTC 24 Aug 28 08:11:53 PM UTC 24 2081733898 ps
T850 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1029333948 Aug 28 08:11:40 PM UTC 24 Aug 28 08:11:54 PM UTC 24 4734058452 ps
T851 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2768073287 Aug 28 08:11:43 PM UTC 24 Aug 28 08:11:54 PM UTC 24 2007662971 ps
T852 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1618462994 Aug 28 08:11:46 PM UTC 24 Aug 28 08:11:54 PM UTC 24 2161620735 ps
T853 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3293685828 Aug 28 08:11:48 PM UTC 24 Aug 28 08:11:55 PM UTC 24 2018886478 ps
T854 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1243072774 Aug 28 08:11:29 PM UTC 24 Aug 28 08:11:55 PM UTC 24 22322208194 ps
T855 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1911999223 Aug 28 08:11:50 PM UTC 24 Aug 28 08:11:55 PM UTC 24 2048801421 ps
T856 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.147680071 Aug 28 08:11:50 PM UTC 24 Aug 28 08:11:55 PM UTC 24 2070342148 ps
T857 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2464524056 Aug 28 08:11:50 PM UTC 24 Aug 28 08:11:55 PM UTC 24 2076645440 ps
T858 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1766054307 Aug 28 08:11:52 PM UTC 24 Aug 28 08:11:56 PM UTC 24 2035383562 ps
T859 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3810621362 Aug 28 08:11:45 PM UTC 24 Aug 28 08:11:56 PM UTC 24 2040907331 ps
T860 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.4223054870 Aug 28 08:11:30 PM UTC 24 Aug 28 08:11:58 PM UTC 24 9892339637 ps
T861 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3165270141 Aug 28 08:11:53 PM UTC 24 Aug 28 08:11:59 PM UTC 24 2025904444 ps
T862 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.663220301 Aug 28 08:11:56 PM UTC 24 Aug 28 08:11:59 PM UTC 24 2044929887 ps
T863 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1833874936 Aug 28 08:11:55 PM UTC 24 Aug 28 08:11:59 PM UTC 24 2041085047 ps
T864 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.417537173 Aug 28 08:11:55 PM UTC 24 Aug 28 08:12:00 PM UTC 24 2019491953 ps
T865 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3301940316 Aug 28 08:11:56 PM UTC 24 Aug 28 08:12:00 PM UTC 24 2024629959 ps
T866 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.674483027 Aug 28 08:11:49 PM UTC 24 Aug 28 08:12:01 PM UTC 24 5063932289 ps
T867 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1783503770 Aug 28 08:11:58 PM UTC 24 Aug 28 08:12:02 PM UTC 24 2040056087 ps
T868 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3166822515 Aug 28 08:12:00 PM UTC 24 Aug 28 08:12:02 PM UTC 24 2159915709 ps
T869 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.563851363 Aug 28 08:11:52 PM UTC 24 Aug 28 08:12:03 PM UTC 24 2042389317 ps
T870 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.221556473 Aug 28 08:12:00 PM UTC 24 Aug 28 08:12:03 PM UTC 24 2079419088 ps
T871 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1320192669 Aug 28 08:12:00 PM UTC 24 Aug 28 08:12:03 PM UTC 24 2043129812 ps
T872 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2352480451 Aug 28 08:11:50 PM UTC 24 Aug 28 08:12:03 PM UTC 24 2077176854 ps
T873 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.565374884 Aug 28 08:11:55 PM UTC 24 Aug 28 08:12:03 PM UTC 24 2011721435 ps
T874 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1708111613 Aug 28 08:11:56 PM UTC 24 Aug 28 08:12:03 PM UTC 24 2020165756 ps
T875 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2145633421 Aug 28 08:11:50 PM UTC 24 Aug 28 08:12:04 PM UTC 24 4678722244 ps
T876 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.39103755 Aug 28 08:12:01 PM UTC 24 Aug 28 08:12:04 PM UTC 24 2095712215 ps
T877 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1779447982 Aug 28 08:11:59 PM UTC 24 Aug 28 08:12:05 PM UTC 24 2014354470 ps
T878 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2459367769 Aug 28 08:12:01 PM UTC 24 Aug 28 08:12:06 PM UTC 24 2029855997 ps
T879 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2923425452 Aug 28 08:11:54 PM UTC 24 Aug 28 08:12:06 PM UTC 24 2032015982 ps
T880 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1513101632 Aug 28 08:12:03 PM UTC 24 Aug 28 08:12:06 PM UTC 24 2103022710 ps
T388 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1166373108 Aug 28 08:11:20 PM UTC 24 Aug 28 08:12:24 PM UTC 24 42400136221 ps
T881 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1734806392 Aug 28 08:11:55 PM UTC 24 Aug 28 08:12:07 PM UTC 24 2041684884 ps
T882 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2833651233 Aug 28 08:11:56 PM UTC 24 Aug 28 08:12:07 PM UTC 24 2014971522 ps
T883 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.887341167 Aug 28 08:12:01 PM UTC 24 Aug 28 08:12:08 PM UTC 24 2018688974 ps
T884 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.4130219105 Aug 28 08:12:05 PM UTC 24 Aug 28 08:12:08 PM UTC 24 2033056716 ps
T885 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1231130256 Aug 28 08:12:05 PM UTC 24 Aug 28 08:12:08 PM UTC 24 2052566635 ps
T389 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.221515189 Aug 28 08:11:16 PM UTC 24 Aug 28 08:12:08 PM UTC 24 42839749424 ps
T886 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1054476045 Aug 28 08:11:58 PM UTC 24 Aug 28 08:12:09 PM UTC 24 2014228828 ps
T887 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3926392543 Aug 28 08:11:44 PM UTC 24 Aug 28 08:12:09 PM UTC 24 9731042527 ps
T888 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.976363761 Aug 28 08:12:04 PM UTC 24 Aug 28 08:12:09 PM UTC 24 2025567020 ps
T889 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3241871927 Aug 28 08:12:04 PM UTC 24 Aug 28 08:12:10 PM UTC 24 2025740279 ps
T890 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2651234997 Aug 28 08:12:06 PM UTC 24 Aug 28 08:12:10 PM UTC 24 2038361549 ps
T891 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1997139799 Aug 28 08:12:04 PM UTC 24 Aug 28 08:12:10 PM UTC 24 2019889188 ps
T892 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2296433208 Aug 28 08:12:07 PM UTC 24 Aug 28 08:12:11 PM UTC 24 2036621706 ps
T893 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3937089506 Aug 28 08:11:43 PM UTC 24 Aug 28 08:12:11 PM UTC 24 4907763334 ps
T894 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3262008818 Aug 28 08:12:05 PM UTC 24 Aug 28 08:12:11 PM UTC 24 2019810193 ps
T895 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2204324045 Aug 28 08:12:02 PM UTC 24 Aug 28 08:12:13 PM UTC 24 2013446777 ps
T896 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1745412130 Aug 28 08:12:06 PM UTC 24 Aug 28 08:12:14 PM UTC 24 2014129263 ps
T897 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.241690893 Aug 28 08:11:52 PM UTC 24 Aug 28 08:12:14 PM UTC 24 22302675391 ps
T898 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2270966551 Aug 28 08:12:07 PM UTC 24 Aug 28 08:12:15 PM UTC 24 2010148251 ps
T899 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1030026044 Aug 28 08:12:04 PM UTC 24 Aug 28 08:12:16 PM UTC 24 2009523635 ps
T900 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.4201384062 Aug 28 08:12:05 PM UTC 24 Aug 28 08:12:17 PM UTC 24 2012937140 ps
T901 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.729083504 Aug 28 08:11:09 PM UTC 24 Aug 28 08:12:21 PM UTC 24 42609278983 ps
T390 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2001086122 Aug 28 08:11:43 PM UTC 24 Aug 28 08:12:25 PM UTC 24 22220132049 ps
T902 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.4095874556 Aug 28 08:11:02 PM UTC 24 Aug 28 08:12:38 PM UTC 24 42561169418 ps
T903 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3236068063 Aug 28 08:11:36 PM UTC 24 Aug 28 08:12:43 PM UTC 24 22184249733 ps
T904 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2124601183 Aug 28 08:11:54 PM UTC 24 Aug 28 08:12:47 PM UTC 24 7544489700 ps
T905 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2963722153 Aug 28 08:10:55 PM UTC 24 Aug 28 08:12:49 PM UTC 24 39499742570 ps
T367 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1967216161 Aug 28 08:10:27 PM UTC 24 Aug 28 08:13:04 PM UTC 24 55470376252 ps
T906 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.907478490 Aug 28 08:10:31 PM UTC 24 Aug 28 08:13:11 PM UTC 24 42418416835 ps
T907 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2345478250 Aug 28 08:10:40 PM UTC 24 Aug 28 08:13:39 PM UTC 24 76086944136 ps
T908 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.4118280842 Aug 28 08:11:50 PM UTC 24 Aug 28 08:13:40 PM UTC 24 42468093018 ps
T909 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2117339485 Aug 28 08:11:05 PM UTC 24 Aug 28 08:13:44 PM UTC 24 42389425115 ps
T910 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.179908276 Aug 28 08:11:47 PM UTC 24 Aug 28 08:14:11 PM UTC 24 42379112742 ps
T911 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.928543018 Aug 28 08:11:37 PM UTC 24 Aug 28 08:14:15 PM UTC 24 42419618757 ps
T912 /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1729489231 Aug 28 08:10:50 PM UTC 24 Aug 28 08:17:13 PM UTC 24 75470853455 ps

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3437977347
Short name T2
Test name
Test status
Simulation time 2534763485 ps
CPU time 2.67 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:13 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3437977347 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.3437977347
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_feature_disable.1055816941
Short name T35
Test name
Test status
Simulation time 33405644056 ps
CPU time 30.33 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:41 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1055816941 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_feature_disable.1055816941
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_feature_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_override_test.2561375910
Short name T18
Test name
Test status
Simulation time 2534278586 ps
CPU time 3.16 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:01:14 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2561375910 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_override_test.2561375910
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all_with_rand_reset.1622662435
Short name T64
Test name
Test status
Simulation time 20972096531 ps
CPU time 16 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:26 PM UTC 24
Peak memory 220856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1622662435 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 0.sysrst_ctrl_stress_all_with_rand_reset.1622662435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect_with_pre_cond.948117626
Short name T42
Test name
Test status
Simulation time 99567675763 ps
CPU time 57.76 seconds
Started Aug 28 08:01:47 PM UTC 24
Finished Aug 28 08:03:21 PM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948117626 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect_with_pre_cond.948117626
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_in_out_inverted.4191498261
Short name T28
Test name
Test status
Simulation time 2471396968 ps
CPU time 8.63 seconds
Started Aug 28 08:01:08 PM UTC 24
Finished Aug 28 08:01:18 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191498261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_in_out_inverted.4191498261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all_with_rand_reset.1690116339
Short name T110
Test name
Test status
Simulation time 22729922053 ps
CPU time 6.26 seconds
Started Aug 28 08:05:19 PM UTC 24
Finished Aug 28 08:05:26 PM UTC 24
Peak memory 227064 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1690116339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 18.sysrst_ctrl_stress_all_with_rand_reset.1690116339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all_with_rand_reset.878674893
Short name T116
Test name
Test status
Simulation time 30297902983 ps
CPU time 10.53 seconds
Started Aug 28 08:01:47 PM UTC 24
Finished Aug 28 08:02:32 PM UTC 24
Peak memory 220744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=878674893 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 11.sysrst_ctrl_stress_all_with_rand_reset.878674893
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_intg_err.1516372708
Short name T318
Test name
Test status
Simulation time 42869852755 ps
CPU time 23.42 seconds
Started Aug 28 08:10:19 PM UTC 24
Finished Aug 28 08:10:43 PM UTC 24
Peak memory 211392 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1516372708 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_intg_err.1516372708
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.4093615704
Short name T36
Test name
Test status
Simulation time 94572154262 ps
CPU time 24.56 seconds
Started Aug 28 08:01:26 PM UTC 24
Finished Aug 28 08:01:52 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4093615704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect_with_pre_cond.4093615704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_edge_detect.1281902400
Short name T111
Test name
Test status
Simulation time 3819911072 ps
CPU time 8.47 seconds
Started Aug 28 08:05:18 PM UTC 24
Finished Aug 28 08:05:28 PM UTC 24
Peak memory 209936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1281902400 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_edge_detect.1281902400
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all_with_rand_reset.1756673713
Short name T107
Test name
Test status
Simulation time 8251510013 ps
CPU time 29.05 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:01:40 PM UTC 24
Peak memory 222528 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1756673713 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 2.sysrst_ctrl_stress_all_with_rand_reset.1756673713
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect.490448793
Short name T56
Test name
Test status
Simulation time 63437019750 ps
CPU time 48.36 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:59 PM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490448793 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect.490448793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_edge_detect.1996740245
Short name T13
Test name
Test status
Simulation time 4054130169 ps
CPU time 14.43 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:24 PM UTC 24
Peak memory 209852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1996740245 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_edge_detect.1996740245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_override_test.165515562
Short name T99
Test name
Test status
Simulation time 2531950758 ps
CPU time 2.8 seconds
Started Aug 28 08:01:17 PM UTC 24
Finished Aug 28 08:01:22 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165515562 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_override_test.165515562
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2638888248
Short name T58
Test name
Test status
Simulation time 143721989856 ps
CPU time 100.87 seconds
Started Aug 28 08:01:20 PM UTC 24
Finished Aug 28 08:03:03 PM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2638888248 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect.2638888248
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.2372251089
Short name T373
Test name
Test status
Simulation time 91686995034 ps
CPU time 94.3 seconds
Started Aug 28 08:05:57 PM UTC 24
Finished Aug 28 08:07:34 PM UTC 24
Peak memory 210112 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2372251089 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect.2372251089
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all_with_rand_reset.1830954243
Short name T196
Test name
Test status
Simulation time 18208607911 ps
CPU time 17.05 seconds
Started Aug 28 08:05:34 PM UTC 24
Finished Aug 28 08:05:53 PM UTC 24
Peak memory 226620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1830954243 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 23.sysrst_ctrl_stress_all_with_rand_reset.1830954243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_sec_cm.2538445851
Short name T313
Test name
Test status
Simulation time 22068690805 ps
CPU time 18.31 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:28 PM UTC 24
Peak memory 240280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2538445851 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_sec_cm.2538445851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.1423401970
Short name T132
Test name
Test status
Simulation time 55942474154 ps
CPU time 37.69 seconds
Started Aug 28 08:05:19 PM UTC 24
Finished Aug 28 08:05:58 PM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423401970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect_with_pre_cond.1423401970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ultra_low_pwr.4213383130
Short name T10
Test name
Test status
Simulation time 6599009036 ps
CPU time 2.06 seconds
Started Aug 28 08:01:23 PM UTC 24
Finished Aug 28 08:01:27 PM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4213383130 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ultra_low_pwr.4213383130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.1848319554
Short name T330
Test name
Test status
Simulation time 22942162669 ps
CPU time 16.85 seconds
Started Aug 28 08:08:19 PM UTC 24
Finished Aug 28 08:08:37 PM UTC 24
Peak memory 224696 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1848319554 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 46.sysrst_ctrl_stress_all_with_rand_reset.1848319554
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_aliasing.4059275953
Short name T356
Test name
Test status
Simulation time 3788009286 ps
CPU time 7.45 seconds
Started Aug 28 08:10:42 PM UTC 24
Finished Aug 28 08:10:51 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059275953 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_aliasing.4059275953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_access_test.2663178712
Short name T6
Test name
Test status
Simulation time 2155099100 ps
CPU time 2.28 seconds
Started Aug 28 08:01:08 PM UTC 24
Finished Aug 28 08:01:12 PM UTC 24
Peak memory 209956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2663178712 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_access_test.2663178712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.2925937220
Short name T202
Test name
Test status
Simulation time 3817845365 ps
CPU time 4.55 seconds
Started Aug 28 08:05:59 PM UTC 24
Finished Aug 28 08:06:04 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925937220 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_edge_detect.2925937220
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_errors.2295710900
Short name T317
Test name
Test status
Simulation time 2201937099 ps
CPU time 5.95 seconds
Started Aug 28 08:10:30 PM UTC 24
Finished Aug 28 08:10:37 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2295710900 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_errors.2295710900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.4168590857
Short name T375
Test name
Test status
Simulation time 130038405835 ps
CPU time 352.03 seconds
Started Aug 28 08:01:26 PM UTC 24
Finished Aug 28 08:07:23 PM UTC 24
Peak memory 210120 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4168590857 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_combo_detect.4168590857
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_edge_detect.3377275597
Short name T7
Test name
Test status
Simulation time 4153098041 ps
CPU time 3.6 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:01:15 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3377275597 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_edge_detect.3377275597
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.3394638943
Short name T433
Test name
Test status
Simulation time 17840060976 ps
CPU time 39.74 seconds
Started Aug 28 08:05:34 PM UTC 24
Finished Aug 28 08:06:15 PM UTC 24
Peak memory 209936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3394638943 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_stress_all.3394638943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_override_test.1334568846
Short name T80
Test name
Test status
Simulation time 2548673499 ps
CPU time 2.74 seconds
Started Aug 28 08:01:13 PM UTC 24
Finished Aug 28 08:01:17 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1334568846 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_override_test.1334568846
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.1221243607
Short name T45
Test name
Test status
Simulation time 96403060066 ps
CPU time 123.23 seconds
Started Aug 28 08:01:59 PM UTC 24
Finished Aug 28 08:04:25 PM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221243607 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_combo_detect.1221243607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.310921724
Short name T220
Test name
Test status
Simulation time 4770110727 ps
CPU time 9.51 seconds
Started Aug 28 08:07:57 PM UTC 24
Finished Aug 28 08:08:08 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=310921724 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_edge_detect.310921724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.3969921983
Short name T121
Test name
Test status
Simulation time 3387726174 ps
CPU time 2.48 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:05:31 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969921983 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ultra_low_pwr.3969921983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.1221508844
Short name T136
Test name
Test status
Simulation time 2966556936 ps
CPU time 9.44 seconds
Started Aug 28 08:06:54 PM UTC 24
Finished Aug 28 08:07:04 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221508844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_auto_blk_key_output.1221508844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_edge_detect.3717859983
Short name T272
Test name
Test status
Simulation time 799176660020 ps
CPU time 1565.69 seconds
Started Aug 28 08:01:20 PM UTC 24
Finished Aug 28 08:27:41 PM UTC 24
Peak memory 212604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3717859983 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_edge_detect.3717859983
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.3151409541
Short name T199
Test name
Test status
Simulation time 8400397932 ps
CPU time 2.81 seconds
Started Aug 28 08:05:31 PM UTC 24
Finished Aug 28 08:05:35 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3151409541 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_stress_all.3151409541
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.843211267
Short name T266
Test name
Test status
Simulation time 2349550478 ps
CPU time 8.44 seconds
Started Aug 28 08:05:54 PM UTC 24
Finished Aug 28 08:06:03 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843211267 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_edge_detect.843211267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_override_test.225743770
Short name T337
Test name
Test status
Simulation time 2528882984 ps
CPU time 3.48 seconds
Started Aug 28 08:01:24 PM UTC 24
Finished Aug 28 08:01:28 PM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=225743770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_override_test.225743770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect_with_pre_cond.3099063833
Short name T281
Test name
Test status
Simulation time 72028317481 ps
CPU time 13.04 seconds
Started Aug 28 08:06:46 PM UTC 24
Finished Aug 28 08:07:00 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099063833 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect_with_pre_cond.3099063833
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_intg_err.3558041275
Short name T320
Test name
Test status
Simulation time 42820199911 ps
CPU time 37.9 seconds
Started Aug 28 08:10:46 PM UTC 24
Finished Aug 28 08:11:25 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3558041275 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_intg_err.3558041275
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_stress_all.3162068338
Short name T139
Test name
Test status
Simulation time 75406186628 ps
CPU time 38.67 seconds
Started Aug 28 08:07:43 PM UTC 24
Finished Aug 28 08:08:23 PM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3162068338 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_stress_all.3162068338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_same_csr_outstanding.3798467473
Short name T23
Test name
Test status
Simulation time 4891786732 ps
CPU time 4.81 seconds
Started Aug 28 08:10:29 PM UTC 24
Finished Aug 28 08:10:35 PM UTC 24
Peak memory 211176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3798467473 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_same_csr_outstanding.3798467473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect_with_pre_cond.2196413532
Short name T413
Test name
Test status
Simulation time 149373616777 ps
CPU time 122.68 seconds
Started Aug 28 08:08:25 PM UTC 24
Finished Aug 28 08:10:30 PM UTC 24
Peak memory 210640 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2196413532 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect_with_pre_cond.2196413532
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_auto_blk_key_output.1361991809
Short name T124
Test name
Test status
Simulation time 3432161049 ps
CPU time 12.55 seconds
Started Aug 28 08:01:29 PM UTC 24
Finished Aug 28 08:01:43 PM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1361991809 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_auto_blk_key_output.1361991809
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_feature_disable.271734249
Short name T53
Test name
Test status
Simulation time 33641615421 ps
CPU time 50.44 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:02:01 PM UTC 24
Peak memory 210072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=271734249 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_feature_disable_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_feature_disable.271734249
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_feature_disable/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_alert_test.1054596900
Short name T21
Test name
Test status
Simulation time 2033541933 ps
CPU time 2.56 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:13 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054596900 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_alert_test.1054596900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.3152600962
Short name T401
Test name
Test status
Simulation time 87391937008 ps
CPU time 277.85 seconds
Started Aug 28 08:05:37 PM UTC 24
Finished Aug 28 08:10:19 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152600962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect_with_pre_cond.3152600962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/88.sysrst_ctrl_combo_detect_with_pre_cond.1752892005
Short name T399
Test name
Test status
Simulation time 91576078554 ps
CPU time 151.93 seconds
Started Aug 28 08:09:45 PM UTC 24
Finished Aug 28 08:12:19 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752892005 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 88.sysrst_ctrl_combo_detect_with_pre_cond.1752892005
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/88.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_combo_detect.2086480638
Short name T379
Test name
Test status
Simulation time 188272527046 ps
CPU time 821.9 seconds
Started Aug 28 08:08:25 PM UTC 24
Finished Aug 28 08:22:16 PM UTC 24
Peak memory 213160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2086480638 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_combo_detect.2086480638
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.3572789490
Short name T300
Test name
Test status
Simulation time 115309750818 ps
CPU time 337.29 seconds
Started Aug 28 08:05:18 PM UTC 24
Finished Aug 28 08:11:00 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3572789490 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_combo_detect.3572789490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.2824178058
Short name T434
Test name
Test status
Simulation time 1777596192746 ps
CPU time 115.4 seconds
Started Aug 28 08:05:46 PM UTC 24
Finished Aug 28 08:07:43 PM UTC 24
Peak memory 220800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2824178058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 26.sysrst_ctrl_stress_all_with_rand_reset.2824178058
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect_with_pre_cond.1117046316
Short name T403
Test name
Test status
Simulation time 74777465603 ps
CPU time 78.69 seconds
Started Aug 28 08:07:04 PM UTC 24
Finished Aug 28 08:08:24 PM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1117046316 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect_with_pre_cond.1117046316
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.2586872666
Short name T133
Test name
Test status
Simulation time 124815335134 ps
CPU time 295.23 seconds
Started Aug 28 08:01:23 PM UTC 24
Finished Aug 28 08:06:23 PM UTC 24
Peak memory 212760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2586872666 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect.2586872666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.3313096274
Short name T331
Test name
Test status
Simulation time 7562437401 ps
CPU time 26.45 seconds
Started Aug 28 08:08:33 PM UTC 24
Finished Aug 28 08:09:01 PM UTC 24
Peak memory 220452 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3313096274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 48.sysrst_ctrl_stress_all_with_rand_reset.3313096274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_combo_detect.3087612818
Short name T41
Test name
Test status
Simulation time 99221455071 ps
CPU time 29.67 seconds
Started Aug 28 08:01:41 PM UTC 24
Finished Aug 28 08:02:52 PM UTC 24
Peak memory 210504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087612818 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_combo_detect.3087612818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all.540276543
Short name T86
Test name
Test status
Simulation time 13310414005 ps
CPU time 3.73 seconds
Started Aug 28 08:01:43 PM UTC 24
Finished Aug 28 08:02:24 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=540276543 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_stress_all.540276543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.1833505100
Short name T415
Test name
Test status
Simulation time 158145061187 ps
CPU time 130.82 seconds
Started Aug 28 08:05:54 PM UTC 24
Finished Aug 28 08:08:07 PM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833505100 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect.1833505100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect.3026028374
Short name T418
Test name
Test status
Simulation time 119495994418 ps
CPU time 96.16 seconds
Started Aug 28 08:06:55 PM UTC 24
Finished Aug 28 08:08:33 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026028374 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect.3026028374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/60.sysrst_ctrl_combo_detect_with_pre_cond.2017734201
Short name T382
Test name
Test status
Simulation time 77300696928 ps
CPU time 280.27 seconds
Started Aug 28 08:08:51 PM UTC 24
Finished Aug 28 08:13:36 PM UTC 24
Peak memory 210320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2017734201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 60.sysrst_ctrl_combo_detect_with_pre_cond.2017734201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/60.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/96.sysrst_ctrl_combo_detect_with_pre_cond.2106799040
Short name T406
Test name
Test status
Simulation time 144105492610 ps
CPU time 504.91 seconds
Started Aug 28 08:10:05 PM UTC 24
Finished Aug 28 08:18:36 PM UTC 24
Peak memory 212904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2106799040 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 96.sysrst_ctrl_combo_detect_with_pre_cond.2106799040
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/96.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ultra_low_pwr.3470164920
Short name T109
Test name
Test status
Simulation time 4252084611 ps
CPU time 8.03 seconds
Started Aug 28 08:01:46 PM UTC 24
Finished Aug 28 08:02:32 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3470164920 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ultra_low_pwr.3470164920
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/79.sysrst_ctrl_combo_detect_with_pre_cond.3158276033
Short name T283
Test name
Test status
Simulation time 62613491848 ps
CPU time 135.09 seconds
Started Aug 28 08:09:26 PM UTC 24
Finished Aug 28 08:11:43 PM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3158276033 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 79.sysrst_ctrl_combo_detect_with_pre_cond.3158276033
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/79.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_auto_blk_key_output.3337017000
Short name T16
Test name
Test status
Simulation time 3631797622 ps
CPU time 3.11 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:13 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3337017000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_auto_blk_key_output.3337017000
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_override_test.1227646339
Short name T97
Test name
Test status
Simulation time 2511067970 ps
CPU time 10.02 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:20 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1227646339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_override_test.1227646339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.1125084797
Short name T425
Test name
Test status
Simulation time 96144934507 ps
CPU time 263.27 seconds
Started Aug 28 08:05:19 PM UTC 24
Finished Aug 28 08:09:45 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1125084797 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_stress_all.1125084797
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect_with_pre_cond.258286452
Short name T408
Test name
Test status
Simulation time 75624737231 ps
CPU time 241.48 seconds
Started Aug 28 08:06:00 PM UTC 24
Finished Aug 28 08:10:04 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258286452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_combo_detect_with_pre_cond.258286452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.420663928
Short name T370
Test name
Test status
Simulation time 150691255811 ps
CPU time 48.55 seconds
Started Aug 28 08:06:07 PM UTC 24
Finished Aug 28 08:06:56 PM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=420663928 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_combo_detect.420663928
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.3477362434
Short name T158
Test name
Test status
Simulation time 1673126404327 ps
CPU time 59.75 seconds
Started Aug 28 08:06:05 PM UTC 24
Finished Aug 28 08:07:07 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3477362434 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ultra_low_pwr.3477362434
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.3359019764
Short name T442
Test name
Test status
Simulation time 2316809240258 ps
CPU time 319.1 seconds
Started Aug 28 08:06:29 PM UTC 24
Finished Aug 28 08:11:52 PM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359019764 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ultra_low_pwr.3359019764
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1709824234
Short name T385
Test name
Test status
Simulation time 79532105346 ps
CPU time 159.35 seconds
Started Aug 28 08:07:10 PM UTC 24
Finished Aug 28 08:09:52 PM UTC 24
Peak memory 210380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1709824234 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect_with_pre_cond.1709824234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect.2893042205
Short name T381
Test name
Test status
Simulation time 136828041366 ps
CPU time 207.41 seconds
Started Aug 28 08:07:15 PM UTC 24
Finished Aug 28 08:10:45 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2893042205 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect.2893042205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect_with_pre_cond.1830683420
Short name T411
Test name
Test status
Simulation time 159862055519 ps
CPU time 520.94 seconds
Started Aug 28 08:08:40 PM UTC 24
Finished Aug 28 08:17:27 PM UTC 24
Peak memory 210324 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830683420 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect_with_pre_cond.1830683420
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.95823558
Short name T392
Test name
Test status
Simulation time 148345638036 ps
CPU time 391.47 seconds
Started Aug 28 08:01:24 PM UTC 24
Finished Aug 28 08:08:00 PM UTC 24
Peak memory 212908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=95823558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_combo_detect_with_pre_cond.95823558
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/51.sysrst_ctrl_combo_detect_with_pre_cond.3232927721
Short name T396
Test name
Test status
Simulation time 51701435471 ps
CPU time 40.32 seconds
Started Aug 28 08:08:43 PM UTC 24
Finished Aug 28 08:09:24 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232927721 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 51.sysrst_ctrl_combo_detect_with_pre_cond.3232927721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/51.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/56.sysrst_ctrl_combo_detect_with_pre_cond.2345417865
Short name T386
Test name
Test status
Simulation time 58678274359 ps
CPU time 179.74 seconds
Started Aug 28 08:08:47 PM UTC 24
Finished Aug 28 08:11:49 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345417865 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 56.sysrst_ctrl_combo_detect_with_pre_cond.2345417865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/56.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/57.sysrst_ctrl_combo_detect_with_pre_cond.2907219543
Short name T398
Test name
Test status
Simulation time 63193018931 ps
CPU time 54.96 seconds
Started Aug 28 08:08:47 PM UTC 24
Finished Aug 28 08:09:44 PM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2907219543 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 57.sysrst_ctrl_combo_detect_with_pre_cond.2907219543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/57.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/84.sysrst_ctrl_combo_detect_with_pre_cond.3352996387
Short name T384
Test name
Test status
Simulation time 69097976466 ps
CPU time 168.12 seconds
Started Aug 28 08:09:35 PM UTC 24
Finished Aug 28 08:12:26 PM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352996387 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 84.sysrst_ctrl_combo_detect_with_pre_cond.3352996387
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/84.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/87.sysrst_ctrl_combo_detect_with_pre_cond.3917592691
Short name T432
Test name
Test status
Simulation time 72229347713 ps
CPU time 258.2 seconds
Started Aug 28 08:09:45 PM UTC 24
Finished Aug 28 08:14:06 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3917592691 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 87.sysrst_ctrl_combo_detect_with_pre_cond.3917592691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/87.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/91.sysrst_ctrl_combo_detect_with_pre_cond.1753599352
Short name T410
Test name
Test status
Simulation time 148465910193 ps
CPU time 111.93 seconds
Started Aug 28 08:09:52 PM UTC 24
Finished Aug 28 08:11:46 PM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1753599352 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 91.sysrst_ctrl_combo_detect_with_pre_cond.1753599352
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/91.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_tl_errors.160692489
Short name T316
Test name
Test status
Simulation time 2052311449 ps
CPU time 6.96 seconds
Started Aug 28 08:10:11 PM UTC 24
Finished Aug 28 08:10:19 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=160692489 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_tl_errors.160692489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_edge_detect.2576841851
Short name T1
Test name
Test status
Simulation time 4327777204 ps
CPU time 2.13 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:13 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2576841851 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_edge_detect.2576841851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_aliasing.2529415851
Short name T39
Test name
Test status
Simulation time 4505616894 ps
CPU time 3.62 seconds
Started Aug 28 08:10:28 PM UTC 24
Finished Aug 28 08:10:33 PM UTC 24
Peak memory 211220 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2529415851 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_aliasing.2529415851
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_bit_bash.1967216161
Short name T367
Test name
Test status
Simulation time 55470376252 ps
CPU time 154.67 seconds
Started Aug 28 08:10:27 PM UTC 24
Finished Aug 28 08:13:04 PM UTC 24
Peak memory 211280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1967216161 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_bit_bash.1967216161
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_hw_reset.1805823061
Short name T38
Test name
Test status
Simulation time 4035024523 ps
CPU time 8.92 seconds
Started Aug 28 08:10:20 PM UTC 24
Finished Aug 28 08:10:30 PM UTC 24
Peak memory 211076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1805823061 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_hw_reset.1805823061
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_mem_rw_with_rand_reset.3443276159
Short name T345
Test name
Test status
Simulation time 2094194582 ps
CPU time 3.1 seconds
Started Aug 28 08:10:30 PM UTC 24
Finished Aug 28 08:10:35 PM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3443276159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0
.sysrst_ctrl_csr_mem_rw_with_rand_reset.3443276159
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_csr_rw.3392419987
Short name T22
Test name
Test status
Simulation time 2053216311 ps
CPU time 7.87 seconds
Started Aug 28 08:10:22 PM UTC 24
Finished Aug 28 08:10:31 PM UTC 24
Peak memory 210940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3392419987 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_csr_rw.3392419987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/0.sysrst_ctrl_intr_test.1311440565
Short name T796
Test name
Test status
Simulation time 2024208314 ps
CPU time 5.19 seconds
Started Aug 28 08:10:20 PM UTC 24
Finished Aug 28 08:10:26 PM UTC 24
Peak memory 210536 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1311440565 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_intr_test.1311440565
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_aliasing.3878315028
Short name T323
Test name
Test status
Simulation time 3192289488 ps
CPU time 10.93 seconds
Started Aug 28 08:10:36 PM UTC 24
Finished Aug 28 08:10:48 PM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3878315028 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_aliasing.3878315028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_bit_bash.3410818374
Short name T362
Test name
Test status
Simulation time 51234190762 ps
CPU time 56.23 seconds
Started Aug 28 08:10:35 PM UTC 24
Finished Aug 28 08:11:33 PM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3410818374 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_bit_bash.3410818374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_hw_reset.2001966145
Short name T322
Test name
Test status
Simulation time 4067608881 ps
CPU time 5.16 seconds
Started Aug 28 08:10:33 PM UTC 24
Finished Aug 28 08:10:39 PM UTC 24
Peak memory 211004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001966145 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_hw_reset.2001966145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_mem_rw_with_rand_reset.2323290178
Short name T353
Test name
Test status
Simulation time 2035887498 ps
CPU time 11.75 seconds
Started Aug 28 08:10:37 PM UTC 24
Finished Aug 28 08:10:50 PM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2323290178 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2323290178
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_csr_rw.2510506381
Short name T354
Test name
Test status
Simulation time 2074890675 ps
CPU time 2.39 seconds
Started Aug 28 08:10:34 PM UTC 24
Finished Aug 28 08:10:37 PM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2510506381 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_csr_rw.2510506381
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_intr_test.2866022951
Short name T797
Test name
Test status
Simulation time 2032326891 ps
CPU time 3.26 seconds
Started Aug 28 08:10:31 PM UTC 24
Finished Aug 28 08:10:36 PM UTC 24
Peak memory 210544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2866022951 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_intr_test.2866022951
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_same_csr_outstanding.433935279
Short name T24
Test name
Test status
Simulation time 5364292179 ps
CPU time 5.2 seconds
Started Aug 28 08:10:36 PM UTC 24
Finished Aug 28 08:10:42 PM UTC 24
Peak memory 211264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=433935279 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_same_csr_outstanding.433935279
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/1.sysrst_ctrl_tl_intg_err.907478490
Short name T906
Test name
Test status
Simulation time 42418416835 ps
CPU time 156.78 seconds
Started Aug 28 08:10:31 PM UTC 24
Finished Aug 28 08:13:11 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=907478490 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_tl_intg_err.907478490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_mem_rw_with_rand_reset.14461682
Short name T824
Test name
Test status
Simulation time 2103600911 ps
CPU time 6.65 seconds
Started Aug 28 08:11:28 PM UTC 24
Finished Aug 28 08:11:35 PM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=14461682 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.
sysrst_ctrl_csr_mem_rw_with_rand_reset.14461682
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_csr_rw.837589219
Short name T818
Test name
Test status
Simulation time 2060657703 ps
CPU time 3.28 seconds
Started Aug 28 08:11:25 PM UTC 24
Finished Aug 28 08:11:29 PM UTC 24
Peak memory 211020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=837589219 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_csr_rw.837589219
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_intr_test.424346563
Short name T821
Test name
Test status
Simulation time 2019045693 ps
CPU time 6.15 seconds
Started Aug 28 08:11:24 PM UTC 24
Finished Aug 28 08:11:32 PM UTC 24
Peak memory 210676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=424346563 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_intr_test.424346563
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_same_csr_outstanding.760325465
Short name T831
Test name
Test status
Simulation time 7694369816 ps
CPU time 10.75 seconds
Started Aug 28 08:11:27 PM UTC 24
Finished Aug 28 08:11:38 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=760325465 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_same_csr_outstanding.760325465
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_errors.4152358393
Short name T827
Test name
Test status
Simulation time 2041821639 ps
CPU time 10.52 seconds
Started Aug 28 08:11:24 PM UTC 24
Finished Aug 28 08:11:36 PM UTC 24
Peak memory 211160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4152358393 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_errors.4152358393
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/10.sysrst_ctrl_tl_intg_err.206059339
Short name T835
Test name
Test status
Simulation time 22529151775 ps
CPU time 16.58 seconds
Started Aug 28 08:11:24 PM UTC 24
Finished Aug 28 08:11:42 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=206059339 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_tl_intg_err.206059339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_mem_rw_with_rand_reset.129788948
Short name T839
Test name
Test status
Simulation time 2068587514 ps
CPU time 11.78 seconds
Started Aug 28 08:11:31 PM UTC 24
Finished Aug 28 08:11:44 PM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=129788948 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11
.sysrst_ctrl_csr_mem_rw_with_rand_reset.129788948
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_csr_rw.1897441314
Short name T363
Test name
Test status
Simulation time 2046140980 ps
CPU time 6.12 seconds
Started Aug 28 08:11:29 PM UTC 24
Finished Aug 28 08:11:36 PM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1897441314 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_csr_rw.1897441314
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_intr_test.2934989876
Short name T823
Test name
Test status
Simulation time 2043049897 ps
CPU time 2.87 seconds
Started Aug 28 08:11:29 PM UTC 24
Finished Aug 28 08:11:33 PM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934989876 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_intr_test.2934989876
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_same_csr_outstanding.4223054870
Short name T860
Test name
Test status
Simulation time 9892339637 ps
CPU time 26.34 seconds
Started Aug 28 08:11:30 PM UTC 24
Finished Aug 28 08:11:58 PM UTC 24
Peak memory 211352 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4223054870 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_same_csr_outstanding.4223054870
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_errors.3387292095
Short name T822
Test name
Test status
Simulation time 2117569022 ps
CPU time 8.06 seconds
Started Aug 28 08:11:29 PM UTC 24
Finished Aug 28 08:11:38 PM UTC 24
Peak memory 211200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3387292095 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_errors.3387292095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/11.sysrst_ctrl_tl_intg_err.1243072774
Short name T854
Test name
Test status
Simulation time 22322208194 ps
CPU time 24.48 seconds
Started Aug 28 08:11:29 PM UTC 24
Finished Aug 28 08:11:55 PM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1243072774 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_tl_intg_err.1243072774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_mem_rw_with_rand_reset.2672600917
Short name T833
Test name
Test status
Simulation time 2047362255 ps
CPU time 6.95 seconds
Started Aug 28 08:11:34 PM UTC 24
Finished Aug 28 08:11:42 PM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2672600917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
2.sysrst_ctrl_csr_mem_rw_with_rand_reset.2672600917
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_csr_rw.2008252656
Short name T828
Test name
Test status
Simulation time 2076142369 ps
CPU time 2.92 seconds
Started Aug 28 08:11:33 PM UTC 24
Finished Aug 28 08:11:36 PM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2008252656 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_csr_rw.2008252656
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_intr_test.1296853165
Short name T829
Test name
Test status
Simulation time 2051111599 ps
CPU time 3.16 seconds
Started Aug 28 08:11:32 PM UTC 24
Finished Aug 28 08:11:37 PM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296853165 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_intr_test.1296853165
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_same_csr_outstanding.1687804767
Short name T832
Test name
Test status
Simulation time 4949138363 ps
CPU time 6.07 seconds
Started Aug 28 08:11:34 PM UTC 24
Finished Aug 28 08:11:41 PM UTC 24
Peak memory 211292 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1687804767 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_same_csr_outstanding.1687804767
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_errors.2387777684
Short name T834
Test name
Test status
Simulation time 2068486487 ps
CPU time 9.59 seconds
Started Aug 28 08:11:31 PM UTC 24
Finished Aug 28 08:11:42 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2387777684 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_errors.2387777684
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/12.sysrst_ctrl_tl_intg_err.397114768
Short name T847
Test name
Test status
Simulation time 22254424460 ps
CPU time 16.85 seconds
Started Aug 28 08:11:32 PM UTC 24
Finished Aug 28 08:11:50 PM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397114768 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_tl_intg_err.397114768
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_mem_rw_with_rand_reset.2633458374
Short name T844
Test name
Test status
Simulation time 2034512791 ps
CPU time 11.08 seconds
Started Aug 28 08:11:37 PM UTC 24
Finished Aug 28 08:11:49 PM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2633458374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
3.sysrst_ctrl_csr_mem_rw_with_rand_reset.2633458374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_csr_rw.1615546299
Short name T365
Test name
Test status
Simulation time 2043387740 ps
CPU time 11.34 seconds
Started Aug 28 08:11:37 PM UTC 24
Finished Aug 28 08:11:49 PM UTC 24
Peak memory 210932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1615546299 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_csr_rw.1615546299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_intr_test.78275955
Short name T803
Test name
Test status
Simulation time 2019635254 ps
CPU time 3.41 seconds
Started Aug 28 08:11:37 PM UTC 24
Finished Aug 28 08:11:41 PM UTC 24
Peak memory 210612 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=78275955 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_intr_test.78275955
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_same_csr_outstanding.1295728688
Short name T843
Test name
Test status
Simulation time 10911324853 ps
CPU time 10.81 seconds
Started Aug 28 08:11:37 PM UTC 24
Finished Aug 28 08:11:49 PM UTC 24
Peak memory 211160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1295728688 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_same_csr_outstanding.1295728688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_errors.3154967150
Short name T830
Test name
Test status
Simulation time 2587499201 ps
CPU time 4.06 seconds
Started Aug 28 08:11:35 PM UTC 24
Finished Aug 28 08:11:40 PM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3154967150 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_errors.3154967150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/13.sysrst_ctrl_tl_intg_err.3236068063
Short name T903
Test name
Test status
Simulation time 22184249733 ps
CPU time 65.8 seconds
Started Aug 28 08:11:36 PM UTC 24
Finished Aug 28 08:12:43 PM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3236068063 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_tl_intg_err.3236068063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_mem_rw_with_rand_reset.1218527077
Short name T838
Test name
Test status
Simulation time 2104888303 ps
CPU time 2.75 seconds
Started Aug 28 08:11:40 PM UTC 24
Finished Aug 28 08:11:43 PM UTC 24
Peak memory 221160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1218527077 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1218527077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_csr_rw.2597203446
Short name T364
Test name
Test status
Simulation time 2068390300 ps
CPU time 4.46 seconds
Started Aug 28 08:11:38 PM UTC 24
Finished Aug 28 08:11:44 PM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2597203446 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_csr_rw.2597203446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_intr_test.248217422
Short name T836
Test name
Test status
Simulation time 2025409120 ps
CPU time 3.09 seconds
Started Aug 28 08:11:38 PM UTC 24
Finished Aug 28 08:11:42 PM UTC 24
Peak memory 210616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248217422 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_intr_test.248217422
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_same_csr_outstanding.1029333948
Short name T850
Test name
Test status
Simulation time 4734058452 ps
CPU time 12.9 seconds
Started Aug 28 08:11:40 PM UTC 24
Finished Aug 28 08:11:54 PM UTC 24
Peak memory 211216 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1029333948 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_same_csr_outstanding.1029333948
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_errors.99834113
Short name T837
Test name
Test status
Simulation time 2468297153 ps
CPU time 4.97 seconds
Started Aug 28 08:11:37 PM UTC 24
Finished Aug 28 08:11:43 PM UTC 24
Peak memory 211412 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99834113 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_errors.99834113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/14.sysrst_ctrl_tl_intg_err.928543018
Short name T911
Test name
Test status
Simulation time 42419618757 ps
CPU time 155.61 seconds
Started Aug 28 08:11:37 PM UTC 24
Finished Aug 28 08:14:15 PM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=928543018 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_tl_intg_err.928543018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_mem_rw_with_rand_reset.2398183588
Short name T841
Test name
Test status
Simulation time 2188932096 ps
CPU time 4.05 seconds
Started Aug 28 08:11:43 PM UTC 24
Finished Aug 28 08:11:48 PM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2398183588 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2398183588
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_csr_rw.1752358837
Short name T840
Test name
Test status
Simulation time 2060574771 ps
CPU time 3.35 seconds
Started Aug 28 08:11:43 PM UTC 24
Finished Aug 28 08:11:47 PM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1752358837 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_csr_rw.1752358837
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_intr_test.2768073287
Short name T851
Test name
Test status
Simulation time 2007662971 ps
CPU time 9.89 seconds
Started Aug 28 08:11:43 PM UTC 24
Finished Aug 28 08:11:54 PM UTC 24
Peak memory 210544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2768073287 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_intr_test.2768073287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_same_csr_outstanding.3937089506
Short name T893
Test name
Test status
Simulation time 4907763334 ps
CPU time 26.82 seconds
Started Aug 28 08:11:43 PM UTC 24
Finished Aug 28 08:12:11 PM UTC 24
Peak memory 211224 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3937089506 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_same_csr_outstanding.3937089506
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_errors.156702577
Short name T849
Test name
Test status
Simulation time 2075840545 ps
CPU time 9.39 seconds
Started Aug 28 08:11:41 PM UTC 24
Finished Aug 28 08:11:51 PM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=156702577 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_errors.156702577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/15.sysrst_ctrl_tl_intg_err.748125255
Short name T846
Test name
Test status
Simulation time 22478451853 ps
CPU time 6.96 seconds
Started Aug 28 08:11:42 PM UTC 24
Finished Aug 28 08:11:50 PM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=748125255 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_tl_intg_err.748125255
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_mem_rw_with_rand_reset.3810621362
Short name T859
Test name
Test status
Simulation time 2040907331 ps
CPU time 10.79 seconds
Started Aug 28 08:11:45 PM UTC 24
Finished Aug 28 08:11:56 PM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=3810621362 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
6.sysrst_ctrl_csr_mem_rw_with_rand_reset.3810621362
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_csr_rw.2433563441
Short name T845
Test name
Test status
Simulation time 2068546159 ps
CPU time 4.1 seconds
Started Aug 28 08:11:44 PM UTC 24
Finished Aug 28 08:11:50 PM UTC 24
Peak memory 211076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2433563441 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_csr_rw.2433563441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_intr_test.80239549
Short name T848
Test name
Test status
Simulation time 2024091728 ps
CPU time 5.31 seconds
Started Aug 28 08:11:44 PM UTC 24
Finished Aug 28 08:11:51 PM UTC 24
Peak memory 210540 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80239549 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_intr_test.80239549
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_same_csr_outstanding.3926392543
Short name T887
Test name
Test status
Simulation time 9731042527 ps
CPU time 23.3 seconds
Started Aug 28 08:11:44 PM UTC 24
Finished Aug 28 08:12:09 PM UTC 24
Peak memory 211376 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3926392543 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_same_csr_outstanding.3926392543
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_errors.736531783
Short name T842
Test name
Test status
Simulation time 2091032776 ps
CPU time 4.15 seconds
Started Aug 28 08:11:43 PM UTC 24
Finished Aug 28 08:11:48 PM UTC 24
Peak memory 211228 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=736531783 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_errors.736531783
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/16.sysrst_ctrl_tl_intg_err.2001086122
Short name T390
Test name
Test status
Simulation time 22220132049 ps
CPU time 40.64 seconds
Started Aug 28 08:11:43 PM UTC 24
Finished Aug 28 08:12:25 PM UTC 24
Peak memory 211348 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001086122 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_tl_intg_err.2001086122
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_mem_rw_with_rand_reset.147680071
Short name T856
Test name
Test status
Simulation time 2070342148 ps
CPU time 3.83 seconds
Started Aug 28 08:11:50 PM UTC 24
Finished Aug 28 08:11:55 PM UTC 24
Peak memory 210708 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=147680071 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17
.sysrst_ctrl_csr_mem_rw_with_rand_reset.147680071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_csr_rw.3997744582
Short name T366
Test name
Test status
Simulation time 2081733898 ps
CPU time 2.89 seconds
Started Aug 28 08:11:49 PM UTC 24
Finished Aug 28 08:11:53 PM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3997744582 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_csr_rw.3997744582
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_intr_test.3293685828
Short name T853
Test name
Test status
Simulation time 2018886478 ps
CPU time 5.71 seconds
Started Aug 28 08:11:48 PM UTC 24
Finished Aug 28 08:11:55 PM UTC 24
Peak memory 210684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3293685828 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_intr_test.3293685828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_same_csr_outstanding.674483027
Short name T866
Test name
Test status
Simulation time 5063932289 ps
CPU time 10.52 seconds
Started Aug 28 08:11:49 PM UTC 24
Finished Aug 28 08:12:01 PM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=674483027 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_same_csr_outstanding.674483027
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_errors.1618462994
Short name T852
Test name
Test status
Simulation time 2161620735 ps
CPU time 7.68 seconds
Started Aug 28 08:11:46 PM UTC 24
Finished Aug 28 08:11:54 PM UTC 24
Peak memory 211264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1618462994 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_errors.1618462994
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/17.sysrst_ctrl_tl_intg_err.179908276
Short name T910
Test name
Test status
Simulation time 42379112742 ps
CPU time 141.54 seconds
Started Aug 28 08:11:47 PM UTC 24
Finished Aug 28 08:14:11 PM UTC 24
Peak memory 211408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179908276 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_tl_intg_err.179908276
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_mem_rw_with_rand_reset.563851363
Short name T869
Test name
Test status
Simulation time 2042389317 ps
CPU time 9.99 seconds
Started Aug 28 08:11:52 PM UTC 24
Finished Aug 28 08:12:03 PM UTC 24
Peak memory 211152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=563851363 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18
.sysrst_ctrl_csr_mem_rw_with_rand_reset.563851363
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_csr_rw.2464524056
Short name T857
Test name
Test status
Simulation time 2076645440 ps
CPU time 3.92 seconds
Started Aug 28 08:11:50 PM UTC 24
Finished Aug 28 08:11:55 PM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2464524056 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_csr_rw.2464524056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_intr_test.1911999223
Short name T855
Test name
Test status
Simulation time 2048801421 ps
CPU time 3.6 seconds
Started Aug 28 08:11:50 PM UTC 24
Finished Aug 28 08:11:55 PM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1911999223 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_intr_test.1911999223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_same_csr_outstanding.2145633421
Short name T875
Test name
Test status
Simulation time 4678722244 ps
CPU time 12.13 seconds
Started Aug 28 08:11:50 PM UTC 24
Finished Aug 28 08:12:04 PM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2145633421 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_same_csr_outstanding.2145633421
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_errors.2352480451
Short name T872
Test name
Test status
Simulation time 2077176854 ps
CPU time 11.69 seconds
Started Aug 28 08:11:50 PM UTC 24
Finished Aug 28 08:12:03 PM UTC 24
Peak memory 211000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2352480451 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_errors.2352480451
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/18.sysrst_ctrl_tl_intg_err.4118280842
Short name T908
Test name
Test status
Simulation time 42468093018 ps
CPU time 108.18 seconds
Started Aug 28 08:11:50 PM UTC 24
Finished Aug 28 08:13:40 PM UTC 24
Peak memory 211116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4118280842 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_tl_intg_err.4118280842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_mem_rw_with_rand_reset.1734806392
Short name T881
Test name
Test status
Simulation time 2041684884 ps
CPU time 10.4 seconds
Started Aug 28 08:11:55 PM UTC 24
Finished Aug 28 08:12:07 PM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1734806392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1
9.sysrst_ctrl_csr_mem_rw_with_rand_reset.1734806392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_csr_rw.2923425452
Short name T879
Test name
Test status
Simulation time 2032015982 ps
CPU time 11.09 seconds
Started Aug 28 08:11:54 PM UTC 24
Finished Aug 28 08:12:06 PM UTC 24
Peak memory 211076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923425452 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_csr_rw.2923425452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_intr_test.3165270141
Short name T861
Test name
Test status
Simulation time 2025904444 ps
CPU time 5.36 seconds
Started Aug 28 08:11:53 PM UTC 24
Finished Aug 28 08:11:59 PM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3165270141 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_intr_test.3165270141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_same_csr_outstanding.2124601183
Short name T904
Test name
Test status
Simulation time 7544489700 ps
CPU time 51.69 seconds
Started Aug 28 08:11:54 PM UTC 24
Finished Aug 28 08:12:47 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2124601183 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_same_csr_outstanding.2124601183
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_errors.1766054307
Short name T858
Test name
Test status
Simulation time 2035383562 ps
CPU time 3.69 seconds
Started Aug 28 08:11:52 PM UTC 24
Finished Aug 28 08:11:56 PM UTC 24
Peak memory 211004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1766054307 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_errors.1766054307
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/19.sysrst_ctrl_tl_intg_err.241690893
Short name T897
Test name
Test status
Simulation time 22302675391 ps
CPU time 21.09 seconds
Started Aug 28 08:11:52 PM UTC 24
Finished Aug 28 08:12:14 PM UTC 24
Peak memory 211252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241690893 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_tl_intg_err.241690893
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_bit_bash.2345478250
Short name T907
Test name
Test status
Simulation time 76086944136 ps
CPU time 176.14 seconds
Started Aug 28 08:10:40 PM UTC 24
Finished Aug 28 08:13:39 PM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2345478250 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_bit_bash.2345478250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_hw_reset.3793692071
Short name T369
Test name
Test status
Simulation time 6211232605 ps
CPU time 3.63 seconds
Started Aug 28 08:10:39 PM UTC 24
Finished Aug 28 08:10:44 PM UTC 24
Peak memory 211116 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3793692071 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_hw_reset.3793692071
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_mem_rw_with_rand_reset.523449018
Short name T352
Test name
Test status
Simulation time 2184492950 ps
CPU time 3.95 seconds
Started Aug 28 08:10:45 PM UTC 24
Finished Aug 28 08:10:50 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=523449018 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.
sysrst_ctrl_csr_mem_rw_with_rand_reset.523449018
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_csr_rw.1248860712
Short name T355
Test name
Test status
Simulation time 2118789797 ps
CPU time 3.29 seconds
Started Aug 28 08:10:39 PM UTC 24
Finished Aug 28 08:10:44 PM UTC 24
Peak memory 210976 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1248860712 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_csr_rw.1248860712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_intr_test.1611651051
Short name T798
Test name
Test status
Simulation time 2014569386 ps
CPU time 10.42 seconds
Started Aug 28 08:10:38 PM UTC 24
Finished Aug 28 08:10:50 PM UTC 24
Peak memory 210676 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611651051 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_intr_test.1611651051
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_same_csr_outstanding.1635591488
Short name T814
Test name
Test status
Simulation time 9235503008 ps
CPU time 41.26 seconds
Started Aug 28 08:10:44 PM UTC 24
Finished Aug 28 08:11:27 PM UTC 24
Peak memory 211236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1635591488 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_same_csr_outstanding.1635591488
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_errors.2726224242
Short name T321
Test name
Test status
Simulation time 2025955066 ps
CPU time 10.43 seconds
Started Aug 28 08:10:38 PM UTC 24
Finished Aug 28 08:10:50 PM UTC 24
Peak memory 211244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726224242 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_errors.2726224242
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/2.sysrst_ctrl_tl_intg_err.137335272
Short name T319
Test name
Test status
Simulation time 43008362292 ps
CPU time 18.91 seconds
Started Aug 28 08:10:38 PM UTC 24
Finished Aug 28 08:10:58 PM UTC 24
Peak memory 211400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=137335272 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_tl_intg_err.137335272
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/20.sysrst_ctrl_intr_test.417537173
Short name T864
Test name
Test status
Simulation time 2019491953 ps
CPU time 3.51 seconds
Started Aug 28 08:11:55 PM UTC 24
Finished Aug 28 08:12:00 PM UTC 24
Peak memory 210604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=417537173 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_intr_test.417537173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/21.sysrst_ctrl_intr_test.1833874936
Short name T863
Test name
Test status
Simulation time 2041085047 ps
CPU time 3.26 seconds
Started Aug 28 08:11:55 PM UTC 24
Finished Aug 28 08:11:59 PM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1833874936 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_intr_test.1833874936
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/22.sysrst_ctrl_intr_test.565374884
Short name T873
Test name
Test status
Simulation time 2011721435 ps
CPU time 7.23 seconds
Started Aug 28 08:11:55 PM UTC 24
Finished Aug 28 08:12:03 PM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=565374884 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_intr_test.565374884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/23.sysrst_ctrl_intr_test.2833651233
Short name T882
Test name
Test status
Simulation time 2014971522 ps
CPU time 9.34 seconds
Started Aug 28 08:11:56 PM UTC 24
Finished Aug 28 08:12:07 PM UTC 24
Peak memory 210744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2833651233 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_intr_test.2833651233
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/24.sysrst_ctrl_intr_test.663220301
Short name T862
Test name
Test status
Simulation time 2044929887 ps
CPU time 1.96 seconds
Started Aug 28 08:11:56 PM UTC 24
Finished Aug 28 08:11:59 PM UTC 24
Peak memory 210628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=663220301 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_intr_test.663220301
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/25.sysrst_ctrl_intr_test.1708111613
Short name T874
Test name
Test status
Simulation time 2020165756 ps
CPU time 6.08 seconds
Started Aug 28 08:11:56 PM UTC 24
Finished Aug 28 08:12:03 PM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1708111613 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_intr_test.1708111613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/26.sysrst_ctrl_intr_test.3301940316
Short name T865
Test name
Test status
Simulation time 2024629959 ps
CPU time 2.54 seconds
Started Aug 28 08:11:56 PM UTC 24
Finished Aug 28 08:12:00 PM UTC 24
Peak memory 210848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3301940316 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_intr_test.3301940316
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/27.sysrst_ctrl_intr_test.1054476045
Short name T886
Test name
Test status
Simulation time 2014228828 ps
CPU time 9.97 seconds
Started Aug 28 08:11:58 PM UTC 24
Finished Aug 28 08:12:09 PM UTC 24
Peak memory 210748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1054476045 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_intr_test.1054476045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/28.sysrst_ctrl_intr_test.1783503770
Short name T867
Test name
Test status
Simulation time 2040056087 ps
CPU time 3.08 seconds
Started Aug 28 08:11:58 PM UTC 24
Finished Aug 28 08:12:02 PM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1783503770 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_intr_test.1783503770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/29.sysrst_ctrl_intr_test.1779447982
Short name T877
Test name
Test status
Simulation time 2014354470 ps
CPU time 4.82 seconds
Started Aug 28 08:11:59 PM UTC 24
Finished Aug 28 08:12:05 PM UTC 24
Peak memory 210556 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1779447982 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_intr_test.1779447982
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_aliasing.2139275888
Short name T421
Test name
Test status
Simulation time 2697036878 ps
CPU time 8.7 seconds
Started Aug 28 08:10:51 PM UTC 24
Finished Aug 28 08:11:01 PM UTC 24
Peak memory 211296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2139275888 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_aliasing.2139275888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_bit_bash.1729489231
Short name T912
Test name
Test status
Simulation time 75470853455 ps
CPU time 378.23 seconds
Started Aug 28 08:10:50 PM UTC 24
Finished Aug 28 08:17:13 PM UTC 24
Peak memory 211284 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729489231 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_bit_bash.1729489231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_hw_reset.3920400791
Short name T359
Test name
Test status
Simulation time 4011632500 ps
CPU time 11.98 seconds
Started Aug 28 08:10:49 PM UTC 24
Finished Aug 28 08:11:02 PM UTC 24
Peak memory 211000 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3920400791 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_hw_reset.3920400791
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_mem_rw_with_rand_reset.1454004452
Short name T329
Test name
Test status
Simulation time 2041442891 ps
CPU time 9.95 seconds
Started Aug 28 08:10:51 PM UTC 24
Finished Aug 28 08:11:02 PM UTC 24
Peak memory 211016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1454004452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3
.sysrst_ctrl_csr_mem_rw_with_rand_reset.1454004452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_csr_rw.3652941113
Short name T357
Test name
Test status
Simulation time 2076216232 ps
CPU time 2.74 seconds
Started Aug 28 08:10:50 PM UTC 24
Finished Aug 28 08:10:54 PM UTC 24
Peak memory 211008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3652941113 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_csr_rw.3652941113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_intr_test.3696205547
Short name T799
Test name
Test status
Simulation time 2027814105 ps
CPU time 5.12 seconds
Started Aug 28 08:10:46 PM UTC 24
Finished Aug 28 08:10:52 PM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3696205547 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_intr_test.3696205547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_same_csr_outstanding.2376131572
Short name T26
Test name
Test status
Simulation time 5232604283 ps
CPU time 19.72 seconds
Started Aug 28 08:10:51 PM UTC 24
Finished Aug 28 08:11:12 PM UTC 24
Peak memory 211256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2376131572 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_same_csr_outstanding.2376131572
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/3.sysrst_ctrl_tl_errors.69973452
Short name T326
Test name
Test status
Simulation time 2287994734 ps
CPU time 5.11 seconds
Started Aug 28 08:10:45 PM UTC 24
Finished Aug 28 08:10:51 PM UTC 24
Peak memory 211304 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=69973452 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_tl_errors.69973452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/30.sysrst_ctrl_intr_test.221556473
Short name T870
Test name
Test status
Simulation time 2079419088 ps
CPU time 1.91 seconds
Started Aug 28 08:12:00 PM UTC 24
Finished Aug 28 08:12:03 PM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221556473 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_intr_test.221556473
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/31.sysrst_ctrl_intr_test.3166822515
Short name T868
Test name
Test status
Simulation time 2159915709 ps
CPU time 1.35 seconds
Started Aug 28 08:12:00 PM UTC 24
Finished Aug 28 08:12:02 PM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3166822515 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_intr_test.3166822515
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/32.sysrst_ctrl_intr_test.1320192669
Short name T871
Test name
Test status
Simulation time 2043129812 ps
CPU time 2.06 seconds
Started Aug 28 08:12:00 PM UTC 24
Finished Aug 28 08:12:03 PM UTC 24
Peak memory 210552 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320192669 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_intr_test.1320192669
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/33.sysrst_ctrl_intr_test.2459367769
Short name T878
Test name
Test status
Simulation time 2029855997 ps
CPU time 3.56 seconds
Started Aug 28 08:12:01 PM UTC 24
Finished Aug 28 08:12:06 PM UTC 24
Peak memory 211004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2459367769 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_intr_test.2459367769
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/34.sysrst_ctrl_intr_test.887341167
Short name T883
Test name
Test status
Simulation time 2018688974 ps
CPU time 5.36 seconds
Started Aug 28 08:12:01 PM UTC 24
Finished Aug 28 08:12:08 PM UTC 24
Peak memory 210876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=887341167 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_intr_test.887341167
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/35.sysrst_ctrl_intr_test.39103755
Short name T876
Test name
Test status
Simulation time 2095712215 ps
CPU time 1.67 seconds
Started Aug 28 08:12:01 PM UTC 24
Finished Aug 28 08:12:04 PM UTC 24
Peak memory 210688 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=39103755 -assert nopostproc +UVM_TESTNAME=sysrs
t_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_intr_test.39103755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/36.sysrst_ctrl_intr_test.2204324045
Short name T895
Test name
Test status
Simulation time 2013446777 ps
CPU time 9.41 seconds
Started Aug 28 08:12:02 PM UTC 24
Finished Aug 28 08:12:13 PM UTC 24
Peak memory 210680 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2204324045 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_intr_test.2204324045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/37.sysrst_ctrl_intr_test.1513101632
Short name T880
Test name
Test status
Simulation time 2103022710 ps
CPU time 1.73 seconds
Started Aug 28 08:12:03 PM UTC 24
Finished Aug 28 08:12:06 PM UTC 24
Peak memory 210628 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1513101632 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_intr_test.1513101632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/38.sysrst_ctrl_intr_test.976363761
Short name T888
Test name
Test status
Simulation time 2025567020 ps
CPU time 4.43 seconds
Started Aug 28 08:12:04 PM UTC 24
Finished Aug 28 08:12:09 PM UTC 24
Peak memory 210848 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=976363761 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_intr_test.976363761
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/39.sysrst_ctrl_intr_test.3241871927
Short name T889
Test name
Test status
Simulation time 2025740279 ps
CPU time 4.88 seconds
Started Aug 28 08:12:04 PM UTC 24
Finished Aug 28 08:12:10 PM UTC 24
Peak memory 210548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3241871927 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_intr_test.3241871927
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_aliasing.1600873040
Short name T802
Test name
Test status
Simulation time 3172615733 ps
CPU time 9.39 seconds
Started Aug 28 08:10:57 PM UTC 24
Finished Aug 28 08:11:07 PM UTC 24
Peak memory 211208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_aliasing +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1600873040 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_aliasing.1600873040
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_aliasing/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_bit_bash.2963722153
Short name T905
Test name
Test status
Simulation time 39499742570 ps
CPU time 111.9 seconds
Started Aug 28 08:10:55 PM UTC 24
Finished Aug 28 08:12:49 PM UTC 24
Peak memory 211128 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_bit_bash +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2963722153 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_bit_bash.2963722153
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_bit_bash/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_hw_reset.1977883522
Short name T358
Test name
Test status
Simulation time 6099857910 ps
CPU time 7.02 seconds
Started Aug 28 08:10:54 PM UTC 24
Finished Aug 28 08:11:02 PM UTC 24
Peak memory 211068 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_hw_reset +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_N
O_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977883522 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/o
s_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_hw_reset.1977883522
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_hw_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_mem_rw_with_rand_reset.1477364788
Short name T801
Test name
Test status
Simulation time 2422820894 ps
CPU time 1.81 seconds
Started Aug 28 08:10:59 PM UTC 24
Finished Aug 28 08:11:02 PM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=1477364788 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4
.sysrst_ctrl_csr_mem_rw_with_rand_reset.1477364788
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_csr_rw.1683694017
Short name T368
Test name
Test status
Simulation time 2057021366 ps
CPU time 11.36 seconds
Started Aug 28 08:10:55 PM UTC 24
Finished Aug 28 08:11:07 PM UTC 24
Peak memory 210940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683694017 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_csr_rw.1683694017
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_intr_test.1112195103
Short name T800
Test name
Test status
Simulation time 2016168280 ps
CPU time 6.94 seconds
Started Aug 28 08:10:53 PM UTC 24
Finished Aug 28 08:11:02 PM UTC 24
Peak memory 210908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1112195103 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_intr_test.1112195103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_same_csr_outstanding.868406849
Short name T809
Test name
Test status
Simulation time 4920714211 ps
CPU time 24.28 seconds
Started Aug 28 08:10:57 PM UTC 24
Finished Aug 28 08:11:23 PM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=868406849 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_same_csr_outstanding.868406849
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_errors.1226379010
Short name T324
Test name
Test status
Simulation time 2152362203 ps
CPU time 10.36 seconds
Started Aug 28 08:10:52 PM UTC 24
Finished Aug 28 08:11:04 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1226379010 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_errors.1226379010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/4.sysrst_ctrl_tl_intg_err.1296019754
Short name T387
Test name
Test status
Simulation time 42776841987 ps
CPU time 48.04 seconds
Started Aug 28 08:10:52 PM UTC 24
Finished Aug 28 08:11:42 PM UTC 24
Peak memory 211212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296019754 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_tl_intg_err.1296019754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/40.sysrst_ctrl_intr_test.1030026044
Short name T899
Test name
Test status
Simulation time 2009523635 ps
CPU time 11 seconds
Started Aug 28 08:12:04 PM UTC 24
Finished Aug 28 08:12:16 PM UTC 24
Peak memory 210876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1030026044 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_intr_test.1030026044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/41.sysrst_ctrl_intr_test.1997139799
Short name T891
Test name
Test status
Simulation time 2019889188 ps
CPU time 5.77 seconds
Started Aug 28 08:12:04 PM UTC 24
Finished Aug 28 08:12:10 PM UTC 24
Peak memory 210972 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1997139799 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_intr_test.1997139799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/42.sysrst_ctrl_intr_test.4130219105
Short name T884
Test name
Test status
Simulation time 2033056716 ps
CPU time 2.1 seconds
Started Aug 28 08:12:05 PM UTC 24
Finished Aug 28 08:12:08 PM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4130219105 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_intr_test.4130219105
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/43.sysrst_ctrl_intr_test.4201384062
Short name T900
Test name
Test status
Simulation time 2012937140 ps
CPU time 10.69 seconds
Started Aug 28 08:12:05 PM UTC 24
Finished Aug 28 08:12:17 PM UTC 24
Peak memory 210736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4201384062 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_intr_test.4201384062
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/44.sysrst_ctrl_intr_test.1231130256
Short name T885
Test name
Test status
Simulation time 2052566635 ps
CPU time 2.43 seconds
Started Aug 28 08:12:05 PM UTC 24
Finished Aug 28 08:12:08 PM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1231130256 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_intr_test.1231130256
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/45.sysrst_ctrl_intr_test.3262008818
Short name T894
Test name
Test status
Simulation time 2019810193 ps
CPU time 5.05 seconds
Started Aug 28 08:12:05 PM UTC 24
Finished Aug 28 08:12:11 PM UTC 24
Peak memory 210608 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262008818 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_intr_test.3262008818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/46.sysrst_ctrl_intr_test.2651234997
Short name T890
Test name
Test status
Simulation time 2038361549 ps
CPU time 2.88 seconds
Started Aug 28 08:12:06 PM UTC 24
Finished Aug 28 08:12:10 PM UTC 24
Peak memory 210864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2651234997 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_intr_test.2651234997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/47.sysrst_ctrl_intr_test.1745412130
Short name T896
Test name
Test status
Simulation time 2014129263 ps
CPU time 5.92 seconds
Started Aug 28 08:12:06 PM UTC 24
Finished Aug 28 08:12:14 PM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745412130 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_intr_test.1745412130
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/48.sysrst_ctrl_intr_test.2270966551
Short name T898
Test name
Test status
Simulation time 2010148251 ps
CPU time 6.54 seconds
Started Aug 28 08:12:07 PM UTC 24
Finished Aug 28 08:12:15 PM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2270966551 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_intr_test.2270966551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/49.sysrst_ctrl_intr_test.2296433208
Short name T892
Test name
Test status
Simulation time 2036621706 ps
CPU time 2.37 seconds
Started Aug 28 08:12:07 PM UTC 24
Finished Aug 28 08:12:11 PM UTC 24
Peak memory 210620 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2296433208 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_intr_test.2296433208
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_mem_rw_with_rand_reset.2391064664
Short name T423
Test name
Test status
Simulation time 2107378113 ps
CPU time 3.93 seconds
Started Aug 28 08:11:03 PM UTC 24
Finished Aug 28 08:11:08 PM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2391064664 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2391064664
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_csr_rw.2448288818
Short name T360
Test name
Test status
Simulation time 2083734544 ps
CPU time 2.86 seconds
Started Aug 28 08:11:02 PM UTC 24
Finished Aug 28 08:11:06 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2448288818 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_csr_rw.2448288818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_intr_test.3860385680
Short name T805
Test name
Test status
Simulation time 2015057016 ps
CPU time 10.7 seconds
Started Aug 28 08:11:02 PM UTC 24
Finished Aug 28 08:11:14 PM UTC 24
Peak memory 210684 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3860385680 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_intr_test.3860385680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_same_csr_outstanding.477085599
Short name T25
Test name
Test status
Simulation time 4578709392 ps
CPU time 5.52 seconds
Started Aug 28 08:11:03 PM UTC 24
Finished Aug 28 08:11:10 PM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=477085599 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_same_csr_outstanding.477085599
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_errors.582199564
Short name T327
Test name
Test status
Simulation time 2303835345 ps
CPU time 4.79 seconds
Started Aug 28 08:11:01 PM UTC 24
Finished Aug 28 08:11:07 PM UTC 24
Peak memory 211504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=582199564 -assert nopostproc +UVM_TESTNAME=sysr
st_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_errors.582199564
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/5.sysrst_ctrl_tl_intg_err.4095874556
Short name T902
Test name
Test status
Simulation time 42561169418 ps
CPU time 93.73 seconds
Started Aug 28 08:11:02 PM UTC 24
Finished Aug 28 08:12:38 PM UTC 24
Peak memory 211204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4095874556 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_tl_intg_err.4095874556
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_mem_rw_with_rand_reset.996559329
Short name T422
Test name
Test status
Simulation time 2066697330 ps
CPU time 6.52 seconds
Started Aug 28 08:11:08 PM UTC 24
Finished Aug 28 08:11:15 PM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=996559329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.
sysrst_ctrl_csr_mem_rw_with_rand_reset.996559329
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_csr_rw.599524675
Short name T361
Test name
Test status
Simulation time 2032328880 ps
CPU time 5.82 seconds
Started Aug 28 08:11:08 PM UTC 24
Finished Aug 28 08:11:15 PM UTC 24
Peak memory 210936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=599524675 -assert nopostproc +UVM_TESTNAME=s
ysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regre
ssion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_csr_rw.599524675
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_intr_test.3881742844
Short name T804
Test name
Test status
Simulation time 2027633190 ps
CPU time 2.88 seconds
Started Aug 28 08:11:07 PM UTC 24
Finished Aug 28 08:11:11 PM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3881742844 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_intr_test.3881742844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_same_csr_outstanding.688798864
Short name T807
Test name
Test status
Simulation time 5059450110 ps
CPU time 7.61 seconds
Started Aug 28 08:11:08 PM UTC 24
Finished Aug 28 08:11:16 PM UTC 24
Peak memory 211384 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=688798864 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_same_csr_outstanding.688798864
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_errors.1871224992
Short name T325
Test name
Test status
Simulation time 2034705368 ps
CPU time 12.13 seconds
Started Aug 28 08:11:03 PM UTC 24
Finished Aug 28 08:11:17 PM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871224992 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_errors.1871224992
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/6.sysrst_ctrl_tl_intg_err.2117339485
Short name T909
Test name
Test status
Simulation time 42389425115 ps
CPU time 156.64 seconds
Started Aug 28 08:11:05 PM UTC 24
Finished Aug 28 08:13:44 PM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2117339485 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_tl_intg_err.2117339485
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_mem_rw_with_rand_reset.4139696596
Short name T810
Test name
Test status
Simulation time 2080561373 ps
CPU time 6.1 seconds
Started Aug 28 08:11:15 PM UTC 24
Finished Aug 28 08:11:23 PM UTC 24
Peak memory 211156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=4139696596 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7
.sysrst_ctrl_csr_mem_rw_with_rand_reset.4139696596
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_csr_rw.4076490511
Short name T806
Test name
Test status
Simulation time 2108745859 ps
CPU time 3.72 seconds
Started Aug 28 08:11:11 PM UTC 24
Finished Aug 28 08:11:16 PM UTC 24
Peak memory 211140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4076490511 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_csr_rw.4076490511
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_intr_test.1543746778
Short name T808
Test name
Test status
Simulation time 2020059652 ps
CPU time 5.28 seconds
Started Aug 28 08:11:11 PM UTC 24
Finished Aug 28 08:11:18 PM UTC 24
Peak memory 210600 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1543746778 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_intr_test.1543746778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_same_csr_outstanding.1899710791
Short name T813
Test name
Test status
Simulation time 4557791132 ps
CPU time 9.68 seconds
Started Aug 28 08:11:13 PM UTC 24
Finished Aug 28 08:11:24 PM UTC 24
Peak memory 211132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1899710791 -assert nopostp
roc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/re
po/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_same_csr_outstanding.1899710791
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_errors.1118933898
Short name T328
Test name
Test status
Simulation time 2384053530 ps
CPU time 5.8 seconds
Started Aug 28 08:11:09 PM UTC 24
Finished Aug 28 08:11:16 PM UTC 24
Peak memory 211300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118933898 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_errors.1118933898
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/7.sysrst_ctrl_tl_intg_err.729083504
Short name T901
Test name
Test status
Simulation time 42609278983 ps
CPU time 70.5 seconds
Started Aug 28 08:11:09 PM UTC 24
Finished Aug 28 08:12:21 PM UTC 24
Peak memory 211260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=729083504 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_tl_intg_err.729083504
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_mem_rw_with_rand_reset.2470159666
Short name T816
Test name
Test status
Simulation time 2084354417 ps
CPU time 8.99 seconds
Started Aug 28 08:11:18 PM UTC 24
Finished Aug 28 08:11:28 PM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=2470159666 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8
.sysrst_ctrl_csr_mem_rw_with_rand_reset.2470159666
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_csr_rw.2223149890
Short name T424
Test name
Test status
Simulation time 2083001220 ps
CPU time 3.44 seconds
Started Aug 28 08:11:17 PM UTC 24
Finished Aug 28 08:11:21 PM UTC 24
Peak memory 211076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2223149890 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_csr_rw.2223149890
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_intr_test.3026407427
Short name T811
Test name
Test status
Simulation time 2021775104 ps
CPU time 5.47 seconds
Started Aug 28 08:11:17 PM UTC 24
Finished Aug 28 08:11:23 PM UTC 24
Peak memory 210544 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3026407427 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_intr_test.3026407427
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_same_csr_outstanding.61426326
Short name T826
Test name
Test status
Simulation time 5950804368 ps
CPU time 16.8 seconds
Started Aug 28 08:11:18 PM UTC 24
Finished Aug 28 08:11:36 PM UTC 24
Peak memory 211464 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=61426326 -assert nopostpro
c +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo
/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_same_csr_outstanding.61426326
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_errors.2862979694
Short name T812
Test name
Test status
Simulation time 2174383427 ps
CPU time 7.53 seconds
Started Aug 28 08:11:15 PM UTC 24
Finished Aug 28 08:11:24 PM UTC 24
Peak memory 211288 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2862979694 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_errors.2862979694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/8.sysrst_ctrl_tl_intg_err.221515189
Short name T389
Test name
Test status
Simulation time 42839749424 ps
CPU time 50.38 seconds
Started Aug 28 08:11:16 PM UTC 24
Finished Aug 28 08:12:08 PM UTC 24
Peak memory 211336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=221515189 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_tl_intg_err.221515189
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_mem_rw_with_rand_reset.652336806
Short name T819
Test name
Test status
Simulation time 2117234873 ps
CPU time 5.57 seconds
Started Aug 28 08:11:24 PM UTC 24
Finished Aug 28 08:11:31 PM UTC 24
Peak memory 211084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000
+en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_ran
dom_seed=652336806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.
sysrst_ctrl_csr_mem_rw_with_rand_reset.652336806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_mem_rw_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_csr_rw.2988559115
Short name T825
Test name
Test status
Simulation time 2056117963 ps
CPU time 11.32 seconds
Started Aug 28 08:11:23 PM UTC 24
Finished Aug 28 08:11:36 PM UTC 24
Peak memory 211012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +csr_rw +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RELN
OTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2988559115 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_csr_rw.2988559115
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_csr_rw/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_intr_test.3109227423
Short name T817
Test name
Test status
Simulation time 2019374027 ps
CPU time 4.99 seconds
Started Aug 28 08:11:22 PM UTC 24
Finished Aug 28 08:11:28 PM UTC 24
Peak memory 210856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_intr_test +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3109227423 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_intr_test.3109227423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_intr_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_same_csr_outstanding.374543691
Short name T815
Test name
Test status
Simulation time 4614115816 ps
CPU time 3.32 seconds
Started Aug 28 08:11:23 PM UTC 24
Finished Aug 28 08:11:28 PM UTC 24
Peak memory 211144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +cdc_instrumentation_enab
led=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=374543691 -assert nopostpr
oc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/rep
o/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_same_csr_outstanding.374543691
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_same_csr_outstanding/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_errors.3481700424
Short name T820
Test name
Test status
Simulation time 2050109159 ps
CPU time 11.02 seconds
Started Aug 28 08:11:19 PM UTC 24
Finished Aug 28 08:11:31 PM UTC 24
Peak memory 211148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_errors +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTE
S +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3481700424 -assert nopostproc +UVM_TESTNAME=sys
rst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regress
ion_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_errors.3481700424
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_errors/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top/9.sysrst_ctrl_tl_intg_err.1166373108
Short name T388
Test name
Test status
Simulation time 42400136221 ps
CPU time 62.78 seconds
Started Aug 28 08:11:20 PM UTC 24
Finished Aug 28 08:12:24 PM UTC 24
Peak memory 211248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +cdc_instrumentation_enabled=1 +UV
M_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166373108 -assert nopostproc +UVM_
TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_tl_intg_err.1166373108
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_tl_intg_err/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_auto_blk_key_output.3254859585
Short name T32
Test name
Test status
Simulation time 3773506412 ps
CPU time 10.32 seconds
Started Aug 28 08:01:08 PM UTC 24
Finished Aug 28 08:01:20 PM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3254859585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_auto_blk_key_output.3254859585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst.435119047
Short name T12
Test name
Test status
Simulation time 2403867266 ps
CPU time 9.97 seconds
Started Aug 28 08:01:08 PM UTC 24
Finished Aug 28 08:01:20 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=435119047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst.435119047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4191922681
Short name T33
Test name
Test status
Simulation time 2313414408 ps
CPU time 8.42 seconds
Started Aug 28 08:01:08 PM UTC 24
Finished Aug 28 08:01:18 PM UTC 24
Peak memory 209576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4191922681 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.4191922681
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.2849195903
Short name T130
Test name
Test status
Simulation time 48115249213 ps
CPU time 136.19 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:03:27 PM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2849195903 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_combo_detect_with_pre_cond.2849195903
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ec_pwr_on_rst.4287622457
Short name T4
Test name
Test status
Simulation time 2997161916 ps
CPU time 0.96 seconds
Started Aug 28 08:01:08 PM UTC 24
Finished Aug 28 08:01:11 PM UTC 24
Peak memory 209296 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4287622457 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ec_pwr_on_rst.4287622457
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_flash_wr_prot_out.618345918
Short name T96
Test name
Test status
Simulation time 2611904769 ps
CPU time 10.06 seconds
Started Aug 28 08:01:08 PM UTC 24
Finished Aug 28 08:01:20 PM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=618345918 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_flash_wr_prot_out.618345918
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_pin_override_test.3433397198
Short name T19
Test name
Test status
Simulation time 2527767695 ps
CPU time 2.71 seconds
Started Aug 28 08:01:08 PM UTC 24
Finished Aug 28 08:01:12 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433397198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_pin_override_test.3433397198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_smoke.4060980187
Short name T5
Test name
Test status
Simulation time 2150106416 ps
CPU time 1.84 seconds
Started Aug 28 08:01:08 PM UTC 24
Finished Aug 28 08:01:11 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4060980187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_smoke.4060980187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_stress_all.1347809874
Short name T308
Test name
Test status
Simulation time 128911857383 ps
CPU time 348.37 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:07:01 PM UTC 24
Peak memory 212824 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1347809874 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_stress_all.1347809874
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_ultra_low_pwr.3081333766
Short name T9
Test name
Test status
Simulation time 2854385214 ps
CPU time 8.28 seconds
Started Aug 28 08:01:08 PM UTC 24
Finished Aug 28 08:01:18 PM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3081333766 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 0.sysrst_ctrl_ultra_low_pwr.3081333766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/0.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_alert_test.800331218
Short name T170
Test name
Test status
Simulation time 2013177490 ps
CPU time 8.26 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:19 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=800331218 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_alert_test.800331218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect.2320645123
Short name T302
Test name
Test status
Simulation time 98411607474 ps
CPU time 245.74 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:05:18 PM UTC 24
Peak memory 212892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320645123 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect.2320645123
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_ec_rst.3290813777
Short name T3
Test name
Test status
Simulation time 2439147994 ps
CPU time 4.27 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:14 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3290813777 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_ec_rst.3290813777
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_combo_detect_with_pre_cond.1423469546
Short name T118
Test name
Test status
Simulation time 81437740594 ps
CPU time 204.84 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:04:37 PM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1423469546 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_combo_detect_with_pre_cond.1423469546
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ec_pwr_on_rst.1463111667
Short name T258
Test name
Test status
Simulation time 4104598785 ps
CPU time 14.66 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:25 PM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463111667 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ec_pwr_on_rst.1463111667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_flash_wr_prot_out.223893169
Short name T30
Test name
Test status
Simulation time 2622073926 ps
CPU time 5.23 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:16 PM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=223893169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_flash_wr_prot_out.223893169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_in_out_inverted.3728291495
Short name T29
Test name
Test status
Simulation time 2459846103 ps
CPU time 8.27 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:18 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3728291495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_in_out_inverted.3728291495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_pin_access_test.36608026
Short name T20
Test name
Test status
Simulation time 2092659988 ps
CPU time 2.23 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:12 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=36608026 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysr
st_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_pin_access_test.36608026
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_sec_cm.1211610832
Short name T174
Test name
Test status
Simulation time 42259571167 ps
CPU time 22.06 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:33 PM UTC 24
Peak memory 240060 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1211610832 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_sec_cm.1211610832
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_smoke.968104313
Short name T94
Test name
Test status
Simulation time 2110785334 ps
CPU time 8 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:18 PM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=968104313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_smoke.968104313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all.1218843862
Short name T69
Test name
Test status
Simulation time 17850637170 ps
CPU time 27.04 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:38 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1218843862 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_stress_all.1218843862
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_stress_all_with_rand_reset.3919290341
Short name T113
Test name
Test status
Simulation time 13000203084 ps
CPU time 12.48 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:23 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3919290341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 1.sysrst_ctrl_stress_all_with_rand_reset.3919290341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/1.sysrst_ctrl_ultra_low_pwr.2144263382
Short name T8
Test name
Test status
Simulation time 5968257002 ps
CPU time 5.17 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:15 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2144263382 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 1.sysrst_ctrl_ultra_low_pwr.2144263382
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/1.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_alert_test.3503533907
Short name T293
Test name
Test status
Simulation time 2044013143 ps
CPU time 2.14 seconds
Started Aug 28 08:01:43 PM UTC 24
Finished Aug 28 08:02:23 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3503533907 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_alert_test.3503533907
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_auto_blk_key_output.3612701595
Short name T453
Test name
Test status
Simulation time 3171723550 ps
CPU time 3.37 seconds
Started Aug 28 08:01:41 PM UTC 24
Finished Aug 28 08:02:26 PM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3612701595 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_auto_blk_key_output.3612701595
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ec_pwr_on_rst.2934286974
Short name T457
Test name
Test status
Simulation time 3306341129 ps
CPU time 4.97 seconds
Started Aug 28 08:01:41 PM UTC 24
Finished Aug 28 08:02:27 PM UTC 24
Peak memory 209836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2934286974 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ec_pwr_on_rst.2934286974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_edge_detect.3405837408
Short name T216
Test name
Test status
Simulation time 2515025301 ps
CPU time 2.39 seconds
Started Aug 28 08:01:41 PM UTC 24
Finished Aug 28 08:02:25 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3405837408 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_edge_detect.3405837408
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_flash_wr_prot_out.3220871711
Short name T455
Test name
Test status
Simulation time 2614732554 ps
CPU time 4.1 seconds
Started Aug 28 08:01:41 PM UTC 24
Finished Aug 28 08:02:27 PM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3220871711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_flash_wr_prot_out.3220871711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_pin_override_test.3359220605
Short name T294
Test name
Test status
Simulation time 2553434687 ps
CPU time 1.99 seconds
Started Aug 28 08:01:40 PM UTC 24
Finished Aug 28 08:02:23 PM UTC 24
Peak memory 208188 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3359220605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_pin_override_test.3359220605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_stress_all_with_rand_reset.1139597197
Short name T346
Test name
Test status
Simulation time 6998495817 ps
CPU time 10.81 seconds
Started Aug 28 08:01:42 PM UTC 24
Finished Aug 28 08:02:32 PM UTC 24
Peak memory 220804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1139597197 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 10.sysrst_ctrl_stress_all_with_rand_reset.1139597197
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/10.sysrst_ctrl_ultra_low_pwr.3921551774
Short name T456
Test name
Test status
Simulation time 2765145931 ps
CPU time 4.49 seconds
Started Aug 28 08:01:41 PM UTC 24
Finished Aug 28 08:02:27 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3921551774 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 10.sysrst_ctrl_ultra_low_pwr.3921551774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_alert_test.4189542573
Short name T296
Test name
Test status
Simulation time 2030587731 ps
CPU time 2.32 seconds
Started Aug 28 08:01:48 PM UTC 24
Finished Aug 28 08:02:24 PM UTC 24
Peak memory 209816 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4189542573 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_alert_test.4189542573
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_auto_blk_key_output.2075594132
Short name T269
Test name
Test status
Simulation time 3381958680 ps
CPU time 10.43 seconds
Started Aug 28 08:01:46 PM UTC 24
Finished Aug 28 08:02:34 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075594132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_auto_blk_key_output.2075594132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.2404351489
Short name T767
Test name
Test status
Simulation time 169774458636 ps
CPU time 443.63 seconds
Started Aug 28 08:01:46 PM UTC 24
Finished Aug 28 08:09:51 PM UTC 24
Peak memory 212900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2404351489 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_combo_detect.2404351489
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_ec_pwr_on_rst.3577881377
Short name T454
Test name
Test status
Simulation time 2881191600 ps
CPU time 2.94 seconds
Started Aug 28 08:01:45 PM UTC 24
Finished Aug 28 08:02:26 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3577881377 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_ec_pwr_on_rst.3577881377
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_edge_detect.4136025685
Short name T217
Test name
Test status
Simulation time 3564817824 ps
CPU time 5.4 seconds
Started Aug 28 08:01:46 PM UTC 24
Finished Aug 28 08:02:29 PM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4136025685 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_edge_detect.4136025685
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_flash_wr_prot_out.2157923113
Short name T459
Test name
Test status
Simulation time 2618732142 ps
CPU time 4.89 seconds
Started Aug 28 08:01:45 PM UTC 24
Finished Aug 28 08:02:29 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2157923113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_flash_wr_prot_out.2157923113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_in_out_inverted.944681798
Short name T460
Test name
Test status
Simulation time 2477349439 ps
CPU time 9 seconds
Started Aug 28 08:01:44 PM UTC 24
Finished Aug 28 08:02:31 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=944681798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_in_out_inverted.944681798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_access_test.1603878780
Short name T452
Test name
Test status
Simulation time 2170726243 ps
CPU time 3.06 seconds
Started Aug 28 08:01:44 PM UTC 24
Finished Aug 28 08:02:25 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1603878780 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_access_test.1603878780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_pin_override_test.2895023770
Short name T446
Test name
Test status
Simulation time 2556176848 ps
CPU time 2.37 seconds
Started Aug 28 08:01:45 PM UTC 24
Finished Aug 28 08:02:26 PM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895023770 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_pin_override_test.2895023770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_smoke.761320929
Short name T178
Test name
Test status
Simulation time 2139587943 ps
CPU time 2.32 seconds
Started Aug 28 08:01:44 PM UTC 24
Finished Aug 28 08:02:24 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761320929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_smoke.761320929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_stress_all.2355698345
Short name T461
Test name
Test status
Simulation time 7468904145 ps
CPU time 8.3 seconds
Started Aug 28 08:01:48 PM UTC 24
Finished Aug 28 08:02:31 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2355698345 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 11.sysrst_ctrl_stress_all.2355698345
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/11.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_alert_test.3640841404
Short name T464
Test name
Test status
Simulation time 2016752532 ps
CPU time 4.49 seconds
Started Aug 28 08:05:08 PM UTC 24
Finished Aug 28 08:05:13 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3640841404 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_alert_test.3640841404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_auto_blk_key_output.935095580
Short name T763
Test name
Test status
Simulation time 160188856324 ps
CPU time 427.4 seconds
Started Aug 28 08:01:55 PM UTC 24
Finished Aug 28 08:09:35 PM UTC 24
Peak memory 210032 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=935095580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_auto_blk_key_output.935095580
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ec_pwr_on_rst.34290319
Short name T462
Test name
Test status
Simulation time 3616363401 ps
CPU time 10.04 seconds
Started Aug 28 08:01:53 PM UTC 24
Finished Aug 28 08:02:31 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=34290319 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ec_pwr_on_rst.34290319
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_edge_detect.17791894
Short name T49
Test name
Test status
Simulation time 3101904457 ps
CPU time 3.62 seconds
Started Aug 28 08:01:59 PM UTC 24
Finished Aug 28 08:02:24 PM UTC 24
Peak memory 209736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=17791894 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_edge_detect.17791894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_flash_wr_prot_out.505599266
Short name T295
Test name
Test status
Simulation time 2640243822 ps
CPU time 2.64 seconds
Started Aug 28 08:01:50 PM UTC 24
Finished Aug 28 08:02:23 PM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=505599266 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_flash_wr_prot_out.505599266
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_in_out_inverted.1286271223
Short name T458
Test name
Test status
Simulation time 2442477414 ps
CPU time 7.67 seconds
Started Aug 28 08:01:49 PM UTC 24
Finished Aug 28 08:02:28 PM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1286271223 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_in_out_inverted.1286271223
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_access_test.794129114
Short name T297
Test name
Test status
Simulation time 2182924926 ps
CPU time 3.49 seconds
Started Aug 28 08:01:49 PM UTC 24
Finished Aug 28 08:02:24 PM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=794129114 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_access_test.794129114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_pin_override_test.3946821782
Short name T292
Test name
Test status
Simulation time 2603912419 ps
CPU time 1.28 seconds
Started Aug 28 08:01:49 PM UTC 24
Finished Aug 28 08:02:22 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3946821782 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_pin_override_test.3946821782
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_smoke.2478181120
Short name T267
Test name
Test status
Simulation time 2125019608 ps
CPU time 2.23 seconds
Started Aug 28 08:01:48 PM UTC 24
Finished Aug 28 08:02:24 PM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2478181120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_smoke.2478181120
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all.3944899590
Short name T463
Test name
Test status
Simulation time 12786951904 ps
CPU time 9.58 seconds
Started Aug 28 08:05:08 PM UTC 24
Finished Aug 28 08:05:18 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3944899590 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_stress_all.3944899590
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_stress_all_with_rand_reset.3141493637
Short name T490
Test name
Test status
Simulation time 7458587938 ps
CPU time 11.27 seconds
Started Aug 28 08:05:07 PM UTC 24
Finished Aug 28 08:05:19 PM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3141493637 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 12.sysrst_ctrl_stress_all_with_rand_reset.3141493637
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_ultra_low_pwr.3955501819
Short name T108
Test name
Test status
Simulation time 8406085262 ps
CPU time 7.28 seconds
Started Aug 28 08:01:55 PM UTC 24
Finished Aug 28 08:02:31 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3955501819 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 12.sysrst_ctrl_ultra_low_pwr.3955501819
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_alert_test.1164065183
Short name T303
Test name
Test status
Simulation time 2040910901 ps
CPU time 1.23 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:12 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1164065183 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_alert_test.1164065183
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_auto_blk_key_output.1337836452
Short name T477
Test name
Test status
Simulation time 3769292714 ps
CPU time 5.38 seconds
Started Aug 28 08:05:09 PM UTC 24
Finished Aug 28 08:05:16 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337836452 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_auto_blk_key_output.1337836452
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect.3542118145
Short name T298
Test name
Test status
Simulation time 55314713262 ps
CPU time 35.5 seconds
Started Aug 28 08:05:09 PM UTC 24
Finished Aug 28 08:05:46 PM UTC 24
Peak memory 210236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3542118145 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect.3542118145
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.2475140135
Short name T391
Test name
Test status
Simulation time 87343717478 ps
CPU time 133.87 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:07:26 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2475140135 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_combo_detect_with_pre_cond.2475140135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ec_pwr_on_rst.1426367169
Short name T474
Test name
Test status
Simulation time 5213947528 ps
CPU time 4.72 seconds
Started Aug 28 08:05:09 PM UTC 24
Finished Aug 28 08:05:15 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1426367169 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ec_pwr_on_rst.1426367169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_edge_detect.548943265
Short name T55
Test name
Test status
Simulation time 5258877474 ps
CPU time 2.93 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:14 PM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=548943265 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_edge_detect.548943265
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_flash_wr_prot_out.4147985831
Short name T305
Test name
Test status
Simulation time 2621364649 ps
CPU time 2.32 seconds
Started Aug 28 08:05:09 PM UTC 24
Finished Aug 28 08:05:13 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147985831 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_flash_wr_prot_out.4147985831
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_in_out_inverted.956723605
Short name T481
Test name
Test status
Simulation time 2443853554 ps
CPU time 7.84 seconds
Started Aug 28 08:05:08 PM UTC 24
Finished Aug 28 08:05:17 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956723605 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_in_out_inverted.956723605
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_access_test.585071196
Short name T471
Test name
Test status
Simulation time 2141518828 ps
CPU time 5.57 seconds
Started Aug 28 08:05:08 PM UTC 24
Finished Aug 28 08:05:14 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=585071196 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_access_test.585071196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_pin_override_test.410724810
Short name T342
Test name
Test status
Simulation time 2514282915 ps
CPU time 7.7 seconds
Started Aug 28 08:05:09 PM UTC 24
Finished Aug 28 08:05:18 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=410724810 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_pin_override_test.410724810
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_smoke.2237916099
Short name T301
Test name
Test status
Simulation time 2136573301 ps
CPU time 1.67 seconds
Started Aug 28 08:05:08 PM UTC 24
Finished Aug 28 08:05:10 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2237916099 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_smoke.2237916099
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all.3493442166
Short name T314
Test name
Test status
Simulation time 10577810629 ps
CPU time 16.39 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:27 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3493442166 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_stress_all.3493442166
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_stress_all_with_rand_reset.239891379
Short name T498
Test name
Test status
Simulation time 20943315060 ps
CPU time 13.43 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:24 PM UTC 24
Peak memory 220208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=239891379 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 13.sysrst_ctrl_stress_all_with_rand_reset.239891379
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_ultra_low_pwr.2473014895
Short name T162
Test name
Test status
Simulation time 2995075823 ps
CPU time 2.63 seconds
Started Aug 28 08:05:09 PM UTC 24
Finished Aug 28 08:05:13 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2473014895 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 13.sysrst_ctrl_ultra_low_pwr.2473014895
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/13.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_alert_test.2874147665
Short name T486
Test name
Test status
Simulation time 2012172020 ps
CPU time 6.62 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:18 PM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2874147665 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_alert_test.2874147665
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_auto_blk_key_output.839836132
Short name T212
Test name
Test status
Simulation time 3674410775 ps
CPU time 12.24 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:23 PM UTC 24
Peak memory 209904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=839836132 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_auto_blk_key_output.839836132
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.838015131
Short name T44
Test name
Test status
Simulation time 67726863114 ps
CPU time 18.15 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:29 PM UTC 24
Peak memory 210104 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=838015131 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect.838015131
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect_with_pre_cond.2280072947
Short name T224
Test name
Test status
Simulation time 41504388554 ps
CPU time 18.33 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:30 PM UTC 24
Peak memory 210320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2280072947 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_combo_detect_with_pre_cond.2280072947
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ec_pwr_on_rst.1621123015
Short name T466
Test name
Test status
Simulation time 2719598271 ps
CPU time 2.62 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:14 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1621123015 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ec_pwr_on_rst.1621123015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_edge_detect.1534478255
Short name T265
Test name
Test status
Simulation time 2678289729 ps
CPU time 2.91 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:14 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1534478255 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_edge_detect.1534478255
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_flash_wr_prot_out.1683697097
Short name T493
Test name
Test status
Simulation time 2609309474 ps
CPU time 8.85 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:20 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1683697097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_flash_wr_prot_out.1683697097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_in_out_inverted.236157248
Short name T465
Test name
Test status
Simulation time 2493426058 ps
CPU time 2.48 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:13 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=236157248 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_in_out_inverted.236157248
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_access_test.716622818
Short name T479
Test name
Test status
Simulation time 2081174644 ps
CPU time 5.65 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:16 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=716622818 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_access_test.716622818
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_pin_override_test.3760230693
Short name T304
Test name
Test status
Simulation time 2541627010 ps
CPU time 2.02 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:13 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3760230693 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_pin_override_test.3760230693
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_smoke.3325977085
Short name T306
Test name
Test status
Simulation time 2122009333 ps
CPU time 2.09 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:13 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3325977085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_smoke.3325977085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all.2421175470
Short name T187
Test name
Test status
Simulation time 14834785301 ps
CPU time 21.27 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:33 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2421175470 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_stress_all.2421175470
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_stress_all_with_rand_reset.528017338
Short name T335
Test name
Test status
Simulation time 6805413746 ps
CPU time 6.39 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:18 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=528017338 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 14.sysrst_ctrl_stress_all_with_rand_reset.528017338
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_ultra_low_pwr.397112135
Short name T438
Test name
Test status
Simulation time 1739975598561 ps
CPU time 85.54 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:06:37 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=397112135 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 14.sysrst_ctrl_ultra_low_pwr.397112135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/14.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_alert_test.3610021704
Short name T484
Test name
Test status
Simulation time 2016223274 ps
CPU time 5.57 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:17 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3610021704 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_alert_test.3610021704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_auto_blk_key_output.2266199866
Short name T233
Test name
Test status
Simulation time 115297523389 ps
CPU time 174.24 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:08:08 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2266199866 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_auto_blk_key_output.2266199866
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.2367209438
Short name T377
Test name
Test status
Simulation time 182140651083 ps
CPU time 291.66 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:10:06 PM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2367209438 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect.2367209438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect_with_pre_cond.4265500253
Short name T285
Test name
Test status
Simulation time 77597906633 ps
CPU time 59.4 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:06:12 PM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4265500253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_combo_detect_with_pre_cond.4265500253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ec_pwr_on_rst.3407017073
Short name T468
Test name
Test status
Simulation time 2966137403 ps
CPU time 2.1 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:14 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3407017073 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ec_pwr_on_rst.3407017073
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_edge_detect.1375337150
Short name T54
Test name
Test status
Simulation time 4517330427 ps
CPU time 1.63 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:13 PM UTC 24
Peak memory 208176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1375337150 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_edge_detect.1375337150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_flash_wr_prot_out.950350987
Short name T483
Test name
Test status
Simulation time 2611661479 ps
CPU time 5.67 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:17 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=950350987 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_flash_wr_prot_out.950350987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_in_out_inverted.4133394389
Short name T473
Test name
Test status
Simulation time 2474110920 ps
CPU time 3.67 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:15 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4133394389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_in_out_inverted.4133394389
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_access_test.1105737341
Short name T470
Test name
Test status
Simulation time 2196208925 ps
CPU time 2.83 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:14 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1105737341 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_access_test.1105737341
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_pin_override_test.941752258
Short name T208
Test name
Test status
Simulation time 2510285683 ps
CPU time 9.56 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:21 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=941752258 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_pin_override_test.941752258
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_smoke.3092802212
Short name T467
Test name
Test status
Simulation time 2137977268 ps
CPU time 2.57 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:14 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3092802212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_smoke.3092802212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all.3428030704
Short name T286
Test name
Test status
Simulation time 127723820190 ps
CPU time 94.35 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:06:47 PM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3428030704 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_stress_all.3428030704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_stress_all_with_rand_reset.2156448742
Short name T336
Test name
Test status
Simulation time 3088053365 ps
CPU time 8.58 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:20 PM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2156448742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 15.sysrst_ctrl_stress_all_with_rand_reset.2156448742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_ultra_low_pwr.3718317388
Short name T123
Test name
Test status
Simulation time 4269792342 ps
CPU time 3.75 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:15 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3718317388 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 15.sysrst_ctrl_ultra_low_pwr.3718317388
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/15.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_alert_test.2263187098
Short name T495
Test name
Test status
Simulation time 2014154565 ps
CPU time 6.42 seconds
Started Aug 28 08:05:13 PM UTC 24
Finished Aug 28 08:05:20 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2263187098 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_alert_test.2263187098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_auto_blk_key_output.1859835138
Short name T480
Test name
Test status
Simulation time 3269834336 ps
CPU time 4.5 seconds
Started Aug 28 08:05:11 PM UTC 24
Finished Aug 28 08:05:17 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1859835138 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_auto_blk_key_output.1859835138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.2699536167
Short name T310
Test name
Test status
Simulation time 75583103297 ps
CPU time 217.01 seconds
Started Aug 28 08:05:11 PM UTC 24
Finished Aug 28 08:08:51 PM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2699536167 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect.2699536167
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1036086766
Short name T280
Test name
Test status
Simulation time 176511253999 ps
CPU time 42.89 seconds
Started Aug 28 08:05:11 PM UTC 24
Finished Aug 28 08:05:55 PM UTC 24
Peak memory 210560 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1036086766 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_combo_detect_with_pre_cond.1036086766
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.3806168486
Short name T472
Test name
Test status
Simulation time 3870592816 ps
CPU time 2.68 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:15 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3806168486 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ec_pwr_on_rst.3806168486
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_edge_detect.4249791581
Short name T197
Test name
Test status
Simulation time 3474187628 ps
CPU time 8.34 seconds
Started Aug 28 08:05:11 PM UTC 24
Finished Aug 28 08:05:20 PM UTC 24
Peak memory 209936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4249791581 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_edge_detect.4249791581
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_flash_wr_prot_out.3105259000
Short name T475
Test name
Test status
Simulation time 2636962330 ps
CPU time 3.37 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:15 PM UTC 24
Peak memory 210212 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105259000 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_flash_wr_prot_out.3105259000
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_in_out_inverted.847150658
Short name T489
Test name
Test status
Simulation time 2489581261 ps
CPU time 6.83 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:19 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=847150658 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_in_out_inverted.847150658
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_access_test.1314083648
Short name T492
Test name
Test status
Simulation time 2195331403 ps
CPU time 7.58 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:19 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314083648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_access_test.1314083648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_pin_override_test.3054249929
Short name T478
Test name
Test status
Simulation time 2516253502 ps
CPU time 4.41 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:16 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3054249929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_pin_override_test.3054249929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_smoke.327697498
Short name T476
Test name
Test status
Simulation time 2119734918 ps
CPU time 3.68 seconds
Started Aug 28 08:05:10 PM UTC 24
Finished Aug 28 08:05:15 PM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=327697498 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_smoke.327697498
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all.1050575447
Short name T183
Test name
Test status
Simulation time 13998954470 ps
CPU time 17.5 seconds
Started Aug 28 08:05:13 PM UTC 24
Finished Aug 28 08:05:31 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1050575447 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_stress_all.1050575447
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.1229148940
Short name T347
Test name
Test status
Simulation time 4267943674 ps
CPU time 14.77 seconds
Started Aug 28 08:05:11 PM UTC 24
Finished Aug 28 08:05:27 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1229148940 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 16.sysrst_ctrl_stress_all_with_rand_reset.1229148940
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ultra_low_pwr.932051602
Short name T163
Test name
Test status
Simulation time 4398343666 ps
CPU time 7.95 seconds
Started Aug 28 08:05:11 PM UTC 24
Finished Aug 28 08:05:20 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932051602 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 16.sysrst_ctrl_ultra_low_pwr.932051602
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/16.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_alert_test.532681083
Short name T209
Test name
Test status
Simulation time 2023839785 ps
CPU time 4.04 seconds
Started Aug 28 08:05:16 PM UTC 24
Finished Aug 28 08:05:21 PM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=532681083 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_alert_test.532681083
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_auto_blk_key_output.1324063853
Short name T680
Test name
Test status
Simulation time 235514964780 ps
CPU time 146.34 seconds
Started Aug 28 08:05:15 PM UTC 24
Finished Aug 28 08:07:44 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324063853 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_auto_blk_key_output.1324063853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2689432442
Short name T312
Test name
Test status
Simulation time 48981031204 ps
CPU time 38.76 seconds
Started Aug 28 08:05:16 PM UTC 24
Finished Aug 28 08:05:56 PM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2689432442 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect.2689432442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.3786931441
Short name T781
Test name
Test status
Simulation time 114326320405 ps
CPU time 363.36 seconds
Started Aug 28 08:05:16 PM UTC 24
Finished Aug 28 08:11:23 PM UTC 24
Peak memory 212908 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3786931441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_combo_detect_with_pre_cond.3786931441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ec_pwr_on_rst.98457290
Short name T487
Test name
Test status
Simulation time 2779063926 ps
CPU time 1.59 seconds
Started Aug 28 08:05:15 PM UTC 24
Finished Aug 28 08:05:18 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=98457290 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ec_pwr_on_rst.98457290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_edge_detect.1648312703
Short name T214
Test name
Test status
Simulation time 2914066234 ps
CPU time 7.28 seconds
Started Aug 28 08:05:16 PM UTC 24
Finished Aug 28 08:05:24 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1648312703 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_edge_detect.1648312703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_flash_wr_prot_out.4055343723
Short name T491
Test name
Test status
Simulation time 2642059785 ps
CPU time 2.93 seconds
Started Aug 28 08:05:15 PM UTC 24
Finished Aug 28 08:05:19 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4055343723 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_flash_wr_prot_out.4055343723
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_in_out_inverted.3655211814
Short name T205
Test name
Test status
Simulation time 2465880938 ps
CPU time 4.23 seconds
Started Aug 28 08:05:15 PM UTC 24
Finished Aug 28 08:05:20 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3655211814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_in_out_inverted.3655211814
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_access_test.830249098
Short name T488
Test name
Test status
Simulation time 2268491264 ps
CPU time 1.97 seconds
Started Aug 28 08:05:15 PM UTC 24
Finished Aug 28 08:05:18 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=830249098 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_access_test.830249098
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_pin_override_test.1221165950
Short name T485
Test name
Test status
Simulation time 2564596646 ps
CPU time 1.55 seconds
Started Aug 28 08:05:15 PM UTC 24
Finished Aug 28 08:05:18 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1221165950 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_pin_override_test.1221165950
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_smoke.2130112195
Short name T469
Test name
Test status
Simulation time 2124460029 ps
CPU time 2.36 seconds
Started Aug 28 08:05:15 PM UTC 24
Finished Aug 28 08:05:19 PM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2130112195 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_smoke.2130112195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.2629402642
Short name T211
Test name
Test status
Simulation time 8089895416 ps
CPU time 6.43 seconds
Started Aug 28 08:05:16 PM UTC 24
Finished Aug 28 08:05:23 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2629402642 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_stress_all.2629402642
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all_with_rand_reset.2315701212
Short name T221
Test name
Test status
Simulation time 3518509626 ps
CPU time 11.59 seconds
Started Aug 28 08:05:16 PM UTC 24
Finished Aug 28 08:05:28 PM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2315701212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 17.sysrst_ctrl_stress_all_with_rand_reset.2315701212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_ultra_low_pwr.3131766129
Short name T510
Test name
Test status
Simulation time 5952265812 ps
CPU time 10.2 seconds
Started Aug 28 08:05:15 PM UTC 24
Finished Aug 28 08:05:27 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3131766129 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 17.sysrst_ctrl_ultra_low_pwr.3131766129
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/17.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_alert_test.3453374464
Short name T507
Test name
Test status
Simulation time 2009880534 ps
CPU time 6.87 seconds
Started Aug 28 08:05:19 PM UTC 24
Finished Aug 28 08:05:27 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3453374464 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_alert_test.3453374464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_auto_blk_key_output.1116784746
Short name T210
Test name
Test status
Simulation time 2983814986 ps
CPU time 2.39 seconds
Started Aug 28 08:05:18 PM UTC 24
Finished Aug 28 08:05:22 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1116784746 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_auto_blk_key_output.1116784746
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_ec_pwr_on_rst.831819714
Short name T500
Test name
Test status
Simulation time 4049252779 ps
CPU time 5.19 seconds
Started Aug 28 08:05:18 PM UTC 24
Finished Aug 28 08:05:25 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=831819714 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_ec_pwr_on_rst.831819714
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_flash_wr_prot_out.257958152
Short name T206
Test name
Test status
Simulation time 2800183227 ps
CPU time 1.42 seconds
Started Aug 28 08:05:18 PM UTC 24
Finished Aug 28 08:05:21 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=257958152 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_flash_wr_prot_out.257958152
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_in_out_inverted.2033948333
Short name T213
Test name
Test status
Simulation time 2476993803 ps
CPU time 4.52 seconds
Started Aug 28 08:05:18 PM UTC 24
Finished Aug 28 08:05:24 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2033948333 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_in_out_inverted.2033948333
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_access_test.1591711229
Short name T207
Test name
Test status
Simulation time 2082839417 ps
CPU time 1.56 seconds
Started Aug 28 08:05:18 PM UTC 24
Finished Aug 28 08:05:21 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1591711229 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_access_test.1591711229
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_pin_override_test.3597751623
Short name T508
Test name
Test status
Simulation time 2507310364 ps
CPU time 7.47 seconds
Started Aug 28 08:05:18 PM UTC 24
Finished Aug 28 08:05:27 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3597751623 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_pin_override_test.3597751623
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_smoke.2009913938
Short name T482
Test name
Test status
Simulation time 2124551287 ps
CPU time 2.34 seconds
Started Aug 28 08:05:16 PM UTC 24
Finished Aug 28 08:05:19 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2009913938 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 18.sysrst_ctrl_smoke.2009913938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.249068952
Short name T505
Test name
Test status
Simulation time 2027711676 ps
CPU time 3.09 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:25 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=249068952 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_alert_test.249068952
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.183986107
Short name T514
Test name
Test status
Simulation time 3579962866 ps
CPU time 8.42 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:31 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=183986107 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_auto_blk_key_output.183986107
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.3142373111
Short name T46
Test name
Test status
Simulation time 62448811785 ps
CPU time 21.95 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:44 PM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3142373111 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect.3142373111
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2596307620
Short name T380
Test name
Test status
Simulation time 71919594307 ps
CPU time 178.54 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:08:22 PM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2596307620 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_combo_detect_with_pre_cond.2596307620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ec_pwr_on_rst.1487560116
Short name T496
Test name
Test status
Simulation time 4857090826 ps
CPU time 1.57 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:24 PM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1487560116 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ec_pwr_on_rst.1487560116
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_edge_detect.2726237848
Short name T244
Test name
Test status
Simulation time 3248893406 ps
CPU time 2.63 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:25 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2726237848 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_edge_detect.2726237848
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3588246892
Short name T502
Test name
Test status
Simulation time 2623614185 ps
CPU time 2.86 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:25 PM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3588246892 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_flash_wr_prot_out.3588246892
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.3970357944
Short name T513
Test name
Test status
Simulation time 2476601553 ps
CPU time 8.39 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:30 PM UTC 24
Peak memory 209900 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3970357944 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_in_out_inverted.3970357944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_access_test.1630674090
Short name T222
Test name
Test status
Simulation time 2025577995 ps
CPU time 6.46 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:29 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1630674090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_access_test.1630674090
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_pin_override_test.2587596097
Short name T499
Test name
Test status
Simulation time 2524021440 ps
CPU time 2.41 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:24 PM UTC 24
Peak memory 209760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2587596097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_pin_override_test.2587596097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_smoke.3099420214
Short name T497
Test name
Test status
Simulation time 2128216944 ps
CPU time 2.19 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:24 PM UTC 24
Peak memory 210132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3099420214 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_smoke.3099420214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3472114859
Short name T218
Test name
Test status
Simulation time 7631451331 ps
CPU time 5.81 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:28 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3472114859 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_stress_all.3472114859
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1418608200
Short name T348
Test name
Test status
Simulation time 5526714252 ps
CPU time 8.63 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:31 PM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1418608200 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 19.sysrst_ctrl_stress_all_with_rand_reset.1418608200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.922874064
Short name T182
Test name
Test status
Simulation time 6861999115 ps
CPU time 5.94 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:28 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=922874064 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 19.sysrst_ctrl_ultra_low_pwr.922874064
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/19.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_alert_test.2481672062
Short name T17
Test name
Test status
Simulation time 2020774401 ps
CPU time 2.55 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:01:14 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481672062 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_alert_test.2481672062
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_auto_blk_key_output.195968032
Short name T291
Test name
Test status
Simulation time 131020728419 ps
CPU time 64.75 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:02:16 PM UTC 24
Peak memory 209672 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=195968032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_auto_blk_key_output.195968032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect.2228144156
Short name T114
Test name
Test status
Simulation time 57831494178 ps
CPU time 151.12 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:03:44 PM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2228144156 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect.2228144156
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst.388459878
Short name T60
Test name
Test status
Simulation time 2158963156 ps
CPU time 4.87 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:15 PM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=388459878 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst.388459878
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2278666291
Short name T15
Test name
Test status
Simulation time 2309615360 ps
CPU time 2.48 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:13 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2278666291 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.2278666291
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.2701487716
Short name T103
Test name
Test status
Simulation time 33329127959 ps
CPU time 91.27 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:02:43 PM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2701487716 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_combo_detect_with_pre_cond.2701487716
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ec_pwr_on_rst.705410888
Short name T81
Test name
Test status
Simulation time 3398046235 ps
CPU time 6.56 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:01:17 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=705410888 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ec_pwr_on_rst.705410888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_flash_wr_prot_out.2521196192
Short name T100
Test name
Test status
Simulation time 2612133412 ps
CPU time 13.52 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:01:25 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2521196192 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_flash_wr_prot_out.2521196192
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_in_out_inverted.2460767147
Short name T87
Test name
Test status
Simulation time 2436014312 ps
CPU time 9.21 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:20 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2460767147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_in_out_inverted.2460767147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_pin_access_test.886856429
Short name T168
Test name
Test status
Simulation time 2156073954 ps
CPU time 9.23 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:20 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=886856429 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_pin_access_test.886856429
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_sec_cm.3207574570
Short name T78
Test name
Test status
Simulation time 22072283103 ps
CPU time 19.07 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:01:30 PM UTC 24
Peak memory 240280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3207574570 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_sec_cm.3207574570
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_smoke.3538650441
Short name T14
Test name
Test status
Simulation time 2128597399 ps
CPU time 2.6 seconds
Started Aug 28 08:01:09 PM UTC 24
Finished Aug 28 08:01:13 PM UTC 24
Peak memory 210132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538650441 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_smoke.3538650441
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_stress_all.253223126
Short name T77
Test name
Test status
Simulation time 15257822140 ps
CPU time 46.92 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:01:58 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=253223126 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_stress_all.253223126
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_ultra_low_pwr.4002058078
Short name T83
Test name
Test status
Simulation time 2834587448 ps
CPU time 10.47 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:01:21 PM UTC 24
Peak memory 209476 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4002058078 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 2.sysrst_ctrl_ultra_low_pwr.4002058078
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/2.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.681664942
Short name T511
Test name
Test status
Simulation time 2038961117 ps
CPU time 1.86 seconds
Started Aug 28 08:05:25 PM UTC 24
Finished Aug 28 08:05:28 PM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=681664942 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_alert_test.681664942
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.3803990704
Short name T525
Test name
Test status
Simulation time 3477720620 ps
CPU time 12.28 seconds
Started Aug 28 08:05:24 PM UTC 24
Finished Aug 28 08:05:37 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3803990704 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_auto_blk_key_output.3803990704
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.850030828
Short name T135
Test name
Test status
Simulation time 86139691459 ps
CPU time 82.75 seconds
Started Aug 28 08:05:24 PM UTC 24
Finished Aug 28 08:06:48 PM UTC 24
Peak memory 210432 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=850030828 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect.850030828
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.952260694
Short name T115
Test name
Test status
Simulation time 36401330990 ps
CPU time 26.47 seconds
Started Aug 28 08:05:25 PM UTC 24
Finished Aug 28 08:05:53 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=952260694 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_combo_detect_with_pre_cond.952260694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3274158632
Short name T528
Test name
Test status
Simulation time 4123968791 ps
CPU time 14.11 seconds
Started Aug 28 08:05:23 PM UTC 24
Finished Aug 28 08:05:38 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3274158632 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ec_pwr_on_rst.3274158632
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.2069154196
Short name T186
Test name
Test status
Simulation time 2304438404 ps
CPU time 7.35 seconds
Started Aug 28 08:05:24 PM UTC 24
Finished Aug 28 08:05:32 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2069154196 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_edge_detect.2069154196
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3232930113
Short name T509
Test name
Test status
Simulation time 2616940955 ps
CPU time 4.31 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:27 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3232930113 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_flash_wr_prot_out.3232930113
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.929789542
Short name T228
Test name
Test status
Simulation time 2459205498 ps
CPU time 7.44 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:30 PM UTC 24
Peak memory 209744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=929789542 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_in_out_inverted.929789542
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_access_test.3792086778
Short name T512
Test name
Test status
Simulation time 2224844654 ps
CPU time 7.56 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:30 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3792086778 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_access_test.3792086778
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.3161979395
Short name T503
Test name
Test status
Simulation time 2526724235 ps
CPU time 2.48 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:25 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3161979395 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_pin_override_test.3161979395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.1627692655
Short name T501
Test name
Test status
Simulation time 2128973384 ps
CPU time 2.21 seconds
Started Aug 28 08:05:21 PM UTC 24
Finished Aug 28 08:05:25 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1627692655 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_smoke.1627692655
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all.2348133788
Short name T506
Test name
Test status
Simulation time 11422438176 ps
CPU time 9.31 seconds
Started Aug 28 08:05:25 PM UTC 24
Finished Aug 28 08:05:36 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348133788 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_stress_all.2348133788
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.1351413667
Short name T339
Test name
Test status
Simulation time 5863314746 ps
CPU time 9.15 seconds
Started Aug 28 08:05:25 PM UTC 24
Finished Aug 28 08:05:35 PM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1351413667 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 20.sysrst_ctrl_stress_all_with_rand_reset.1351413667
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.4227027126
Short name T494
Test name
Test status
Simulation time 5759910670 ps
CPU time 9.96 seconds
Started Aug 28 08:05:24 PM UTC 24
Finished Aug 28 08:05:35 PM UTC 24
Peak memory 210132 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4227027126 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 20.sysrst_ctrl_ultra_low_pwr.4227027126
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/20.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.3070722290
Short name T516
Test name
Test status
Simulation time 2015760018 ps
CPU time 6.15 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:05:35 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3070722290 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_alert_test.3070722290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.3587078516
Short name T169
Test name
Test status
Simulation time 3679160564 ps
CPU time 9.77 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:05:39 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3587078516 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_auto_blk_key_output.3587078516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.2283254736
Short name T787
Test name
Test status
Simulation time 173244487481 ps
CPU time 561.26 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:14:55 PM UTC 24
Peak memory 213156 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2283254736 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect.2283254736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.129584332
Short name T131
Test name
Test status
Simulation time 24849731619 ps
CPU time 21.25 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:05:50 PM UTC 24
Peak memory 210380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=129584332 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_combo_detect_with_pre_cond.129584332
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.3969012752
Short name T795
Test name
Test status
Simulation time 954413622208 ps
CPU time 3240.96 seconds
Started Aug 28 08:05:26 PM UTC 24
Finished Aug 28 08:59:57 PM UTC 24
Peak memory 212724 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3969012752 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_ec_pwr_on_rst.3969012752
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.958402720
Short name T188
Test name
Test status
Simulation time 4474176754 ps
CPU time 4 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:05:33 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=958402720 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_edge_detect.958402720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3826468969
Short name T518
Test name
Test status
Simulation time 2609517473 ps
CPU time 7.27 seconds
Started Aug 28 08:05:26 PM UTC 24
Finished Aug 28 08:05:34 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3826468969 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_flash_wr_prot_out.3826468969
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.2211002750
Short name T191
Test name
Test status
Simulation time 2447341835 ps
CPU time 7.09 seconds
Started Aug 28 08:05:25 PM UTC 24
Finished Aug 28 08:05:34 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2211002750 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_in_out_inverted.2211002750
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.3352107901
Short name T517
Test name
Test status
Simulation time 2224852353 ps
CPU time 7.4 seconds
Started Aug 28 08:05:25 PM UTC 24
Finished Aug 28 08:05:34 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3352107901 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_access_test.3352107901
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.699443571
Short name T226
Test name
Test status
Simulation time 2537948560 ps
CPU time 3.36 seconds
Started Aug 28 08:05:25 PM UTC 24
Finished Aug 28 08:05:30 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=699443571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_pin_override_test.699443571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.1337407024
Short name T223
Test name
Test status
Simulation time 2131435670 ps
CPU time 2.82 seconds
Started Aug 28 08:05:25 PM UTC 24
Finished Aug 28 08:05:29 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1337407024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_smoke.1337407024
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.1617933044
Short name T527
Test name
Test status
Simulation time 9363860710 ps
CPU time 8.11 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:05:37 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1617933044 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 21.sysrst_ctrl_stress_all.1617933044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.3330017647
Short name T340
Test name
Test status
Simulation time 9863549184 ps
CPU time 20.38 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:05:50 PM UTC 24
Peak memory 220408 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3330017647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 21.sysrst_ctrl_stress_all_with_rand_reset.3330017647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/21.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.680578227
Short name T520
Test name
Test status
Simulation time 2046680156 ps
CPU time 1.89 seconds
Started Aug 28 08:05:31 PM UTC 24
Finished Aug 28 08:05:35 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=680578227 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_alert_test.680578227
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.1707231064
Short name T519
Test name
Test status
Simulation time 3358134377 ps
CPU time 3.33 seconds
Started Aug 28 08:05:30 PM UTC 24
Finished Aug 28 08:05:34 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1707231064 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_auto_blk_key_output.1707231064
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.1335230218
Short name T376
Test name
Test status
Simulation time 167482248676 ps
CPU time 509.93 seconds
Started Aug 28 08:05:30 PM UTC 24
Finished Aug 28 08:14:05 PM UTC 24
Peak memory 212760 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1335230218 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect.1335230218
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect_with_pre_cond.1040673604
Short name T119
Test name
Test status
Simulation time 60872736289 ps
CPU time 46.16 seconds
Started Aug 28 08:05:30 PM UTC 24
Finished Aug 28 08:06:18 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1040673604 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_combo_detect_with_pre_cond.1040673604
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.3904995514
Short name T189
Test name
Test status
Simulation time 2865364078 ps
CPU time 2.29 seconds
Started Aug 28 08:05:30 PM UTC 24
Finished Aug 28 08:05:33 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3904995514 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_ec_pwr_on_rst.3904995514
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1942851694
Short name T256
Test name
Test status
Simulation time 4209675000 ps
CPU time 16.13 seconds
Started Aug 28 08:05:30 PM UTC 24
Finished Aug 28 08:05:47 PM UTC 24
Peak memory 209936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1942851694 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_edge_detect.1942851694
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.3556909238
Short name T185
Test name
Test status
Simulation time 2655446506 ps
CPU time 1.52 seconds
Started Aug 28 08:05:30 PM UTC 24
Finished Aug 28 08:05:32 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3556909238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_flash_wr_prot_out.3556909238
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.204686439
Short name T532
Test name
Test status
Simulation time 2460406194 ps
CPU time 12.03 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:05:41 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=204686439 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_in_out_inverted.204686439
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.3754108008
Short name T515
Test name
Test status
Simulation time 2337806741 ps
CPU time 1.56 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:05:31 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3754108008 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_access_test.3754108008
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.2453251996
Short name T190
Test name
Test status
Simulation time 2518265007 ps
CPU time 3.98 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:05:33 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2453251996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_pin_override_test.2453251996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.35257687
Short name T184
Test name
Test status
Simulation time 2125544360 ps
CPU time 2.27 seconds
Started Aug 28 08:05:28 PM UTC 24
Finished Aug 28 08:05:32 PM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=35257687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 22.sysrst_ctrl_smoke.35257687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.3681736803
Short name T541
Test name
Test status
Simulation time 5803362168 ps
CPU time 14.67 seconds
Started Aug 28 08:05:30 PM UTC 24
Finished Aug 28 08:05:46 PM UTC 24
Peak memory 220804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3681736803 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 22.sysrst_ctrl_stress_all_with_rand_reset.3681736803
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.4280642014
Short name T225
Test name
Test status
Simulation time 2099105043 ps
CPU time 1.51 seconds
Started Aug 28 08:05:34 PM UTC 24
Finished Aug 28 08:05:37 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280642014 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_alert_test.4280642014
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2625135884
Short name T522
Test name
Test status
Simulation time 3618151552 ps
CPU time 2.49 seconds
Started Aug 28 08:05:33 PM UTC 24
Finished Aug 28 08:05:36 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2625135884 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_auto_blk_key_output.2625135884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.2916555775
Short name T778
Test name
Test status
Simulation time 97227873596 ps
CPU time 319.68 seconds
Started Aug 28 08:05:33 PM UTC 24
Finished Aug 28 08:10:56 PM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2916555775 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_combo_detect.2916555775
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ec_pwr_on_rst.3571151138
Short name T524
Test name
Test status
Simulation time 3564238862 ps
CPU time 3.43 seconds
Started Aug 28 08:05:33 PM UTC 24
Finished Aug 28 08:05:37 PM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3571151138 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ec_pwr_on_rst.3571151138
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.2985034953
Short name T117
Test name
Test status
Simulation time 2512341929 ps
CPU time 6.45 seconds
Started Aug 28 08:05:33 PM UTC 24
Finished Aug 28 08:05:40 PM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2985034953 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_edge_detect.2985034953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.2957639095
Short name T521
Test name
Test status
Simulation time 2651093619 ps
CPU time 2.61 seconds
Started Aug 28 08:05:31 PM UTC 24
Finished Aug 28 08:05:35 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2957639095 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_flash_wr_prot_out.2957639095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.2487388273
Short name T523
Test name
Test status
Simulation time 2466257194 ps
CPU time 3.9 seconds
Started Aug 28 08:05:31 PM UTC 24
Finished Aug 28 08:05:37 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2487388273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_in_out_inverted.2487388273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.2451436569
Short name T227
Test name
Test status
Simulation time 2032154277 ps
CPU time 2.5 seconds
Started Aug 28 08:05:31 PM UTC 24
Finished Aug 28 08:05:35 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2451436569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_access_test.2451436569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.526441369
Short name T538
Test name
Test status
Simulation time 2512555770 ps
CPU time 11.52 seconds
Started Aug 28 08:05:31 PM UTC 24
Finished Aug 28 08:05:44 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=526441369 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_pin_override_test.526441369
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.2316021059
Short name T504
Test name
Test status
Simulation time 2126034626 ps
CPU time 2.09 seconds
Started Aug 28 08:05:31 PM UTC 24
Finished Aug 28 08:05:35 PM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2316021059 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_smoke.2316021059
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.918176163
Short name T171
Test name
Test status
Simulation time 4393140134 ps
CPU time 10.72 seconds
Started Aug 28 08:05:33 PM UTC 24
Finished Aug 28 08:05:45 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=918176163 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 23.sysrst_ctrl_ultra_low_pwr.918176163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.706066826
Short name T544
Test name
Test status
Simulation time 2008895156 ps
CPU time 9.44 seconds
Started Aug 28 08:05:37 PM UTC 24
Finished Aug 28 08:05:48 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=706066826 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_alert_test.706066826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.3608744622
Short name T551
Test name
Test status
Simulation time 3418543397 ps
CPU time 12.08 seconds
Started Aug 28 08:05:36 PM UTC 24
Finished Aug 28 08:05:49 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3608744622 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_auto_blk_key_output.3608744622
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.3420346671
Short name T417
Test name
Test status
Simulation time 65191555005 ps
CPU time 199.68 seconds
Started Aug 28 08:05:36 PM UTC 24
Finished Aug 28 08:08:59 PM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3420346671 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_combo_detect.3420346671
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1056492547
Short name T549
Test name
Test status
Simulation time 3882853176 ps
CPU time 11.91 seconds
Started Aug 28 08:05:35 PM UTC 24
Finished Aug 28 08:05:49 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1056492547 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ec_pwr_on_rst.1056492547
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.3673164634
Short name T198
Test name
Test status
Simulation time 3257017491 ps
CPU time 6.21 seconds
Started Aug 28 08:05:37 PM UTC 24
Finished Aug 28 08:05:45 PM UTC 24
Peak memory 210264 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3673164634 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_edge_detect.3673164634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.2604273842
Short name T542
Test name
Test status
Simulation time 2608753168 ps
CPU time 9.15 seconds
Started Aug 28 08:05:35 PM UTC 24
Finished Aug 28 08:05:47 PM UTC 24
Peak memory 210276 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2604273842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_flash_wr_prot_out.2604273842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.241204515
Short name T529
Test name
Test status
Simulation time 2472251641 ps
CPU time 3.06 seconds
Started Aug 28 08:05:34 PM UTC 24
Finished Aug 28 08:05:39 PM UTC 24
Peak memory 209852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=241204515 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_in_out_inverted.241204515
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.2309327956
Short name T534
Test name
Test status
Simulation time 2183981205 ps
CPU time 6.74 seconds
Started Aug 28 08:05:34 PM UTC 24
Finished Aug 28 08:05:43 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2309327956 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_access_test.2309327956
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.2760674762
Short name T545
Test name
Test status
Simulation time 2511661739 ps
CPU time 10.9 seconds
Started Aug 28 08:05:35 PM UTC 24
Finished Aug 28 08:05:48 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2760674762 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_pin_override_test.2760674762
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.1671164569
Short name T531
Test name
Test status
Simulation time 2114255545 ps
CPU time 5.64 seconds
Started Aug 28 08:05:34 PM UTC 24
Finished Aug 28 08:05:41 PM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1671164569 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_smoke.1671164569
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.2099389894
Short name T309
Test name
Test status
Simulation time 37806487869 ps
CPU time 129.47 seconds
Started Aug 28 08:05:37 PM UTC 24
Finished Aug 28 08:07:49 PM UTC 24
Peak memory 210160 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2099389894 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_stress_all.2099389894
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.3225603929
Short name T343
Test name
Test status
Simulation time 5026984802 ps
CPU time 16.52 seconds
Started Aug 28 08:05:37 PM UTC 24
Finished Aug 28 08:05:55 PM UTC 24
Peak memory 220388 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3225603929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 24.sysrst_ctrl_stress_all_with_rand_reset.3225603929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.1271396620
Short name T164
Test name
Test status
Simulation time 5837130131 ps
CPU time 7.55 seconds
Started Aug 28 08:05:36 PM UTC 24
Finished Aug 28 08:05:45 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1271396620 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 24.sysrst_ctrl_ultra_low_pwr.1271396620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/24.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2126893736
Short name T540
Test name
Test status
Simulation time 2036025365 ps
CPU time 2.96 seconds
Started Aug 28 08:05:42 PM UTC 24
Finished Aug 28 08:05:46 PM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2126893736 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_alert_test.2126893736
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2425636863
Short name T533
Test name
Test status
Simulation time 3271722804 ps
CPU time 2.95 seconds
Started Aug 28 08:05:38 PM UTC 24
Finished Aug 28 08:05:42 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2425636863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_auto_blk_key_output.2425636863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.2407238854
Short name T383
Test name
Test status
Simulation time 141007332733 ps
CPU time 469.2 seconds
Started Aug 28 08:05:40 PM UTC 24
Finished Aug 28 08:13:34 PM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2407238854 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_combo_detect.2407238854
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.2315251135
Short name T558
Test name
Test status
Simulation time 2985986778 ps
CPU time 12.67 seconds
Started Aug 28 08:05:38 PM UTC 24
Finished Aug 28 08:05:52 PM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2315251135 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ec_pwr_on_rst.2315251135
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.1158546426
Short name T255
Test name
Test status
Simulation time 6473410748 ps
CPU time 3.93 seconds
Started Aug 28 08:05:40 PM UTC 24
Finished Aug 28 08:05:45 PM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1158546426 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_edge_detect.1158546426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.3202440917
Short name T559
Test name
Test status
Simulation time 2612242879 ps
CPU time 12.62 seconds
Started Aug 28 08:05:38 PM UTC 24
Finished Aug 28 08:05:52 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3202440917 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_flash_wr_prot_out.3202440917
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.1015341061
Short name T552
Test name
Test status
Simulation time 2459707475 ps
CPU time 11.06 seconds
Started Aug 28 08:05:37 PM UTC 24
Finished Aug 28 08:05:50 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1015341061 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_in_out_inverted.1015341061
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.771313117
Short name T530
Test name
Test status
Simulation time 2064265594 ps
CPU time 1.76 seconds
Started Aug 28 08:05:38 PM UTC 24
Finished Aug 28 08:05:41 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=771313117 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_access_test.771313117
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.4050575025
Short name T536
Test name
Test status
Simulation time 2529258027 ps
CPU time 3.78 seconds
Started Aug 28 08:05:38 PM UTC 24
Finished Aug 28 08:05:43 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4050575025 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_pin_override_test.4050575025
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.1322153875
Short name T537
Test name
Test status
Simulation time 2114836721 ps
CPU time 4.82 seconds
Started Aug 28 08:05:37 PM UTC 24
Finished Aug 28 08:05:43 PM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1322153875 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_smoke.1322153875
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.144004944
Short name T315
Test name
Test status
Simulation time 14159496917 ps
CPU time 17.24 seconds
Started Aug 28 08:05:42 PM UTC 24
Finished Aug 28 08:06:00 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=144004944 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_stress_all.144004944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.4124150060
Short name T547
Test name
Test status
Simulation time 6752516092 ps
CPU time 7.24 seconds
Started Aug 28 08:05:41 PM UTC 24
Finished Aug 28 08:05:49 PM UTC 24
Peak memory 210336 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4124150060 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 25.sysrst_ctrl_stress_all_with_rand_reset.4124150060
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.664691643
Short name T535
Test name
Test status
Simulation time 3108202501 ps
CPU time 3.5 seconds
Started Aug 28 08:05:38 PM UTC 24
Finished Aug 28 08:05:43 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664691643 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 25.sysrst_ctrl_ultra_low_pwr.664691643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.3341738329
Short name T561
Test name
Test status
Simulation time 2014127536 ps
CPU time 6.7 seconds
Started Aug 28 08:05:47 PM UTC 24
Finished Aug 28 08:05:55 PM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3341738329 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_alert_test.3341738329
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3461917068
Short name T569
Test name
Test status
Simulation time 3271448231 ps
CPU time 10.16 seconds
Started Aug 28 08:05:45 PM UTC 24
Finished Aug 28 08:05:57 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3461917068 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_auto_blk_key_output.3461917068
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.4177807539
Short name T419
Test name
Test status
Simulation time 136935911787 ps
CPU time 318.16 seconds
Started Aug 28 08:05:46 PM UTC 24
Finished Aug 28 08:11:08 PM UTC 24
Peak memory 210236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4177807539 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_combo_detect.4177807539
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2090532944
Short name T543
Test name
Test status
Simulation time 2501111579 ps
CPU time 2.25 seconds
Started Aug 28 08:05:44 PM UTC 24
Finished Aug 28 08:05:47 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2090532944 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ec_pwr_on_rst.2090532944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.2001056290
Short name T201
Test name
Test status
Simulation time 5721560962 ps
CPU time 5.07 seconds
Started Aug 28 08:05:46 PM UTC 24
Finished Aug 28 08:05:52 PM UTC 24
Peak memory 209936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2001056290 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_edge_detect.2001056290
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.1813565280
Short name T548
Test name
Test status
Simulation time 2626179334 ps
CPU time 3.88 seconds
Started Aug 28 08:05:44 PM UTC 24
Finished Aug 28 08:05:49 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1813565280 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_flash_wr_prot_out.1813565280
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.1564132150
Short name T550
Test name
Test status
Simulation time 2462837089 ps
CPU time 5.2 seconds
Started Aug 28 08:05:43 PM UTC 24
Finished Aug 28 08:05:49 PM UTC 24
Peak memory 209784 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1564132150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_in_out_inverted.1564132150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1979273202
Short name T539
Test name
Test status
Simulation time 2241580331 ps
CPU time 1.2 seconds
Started Aug 28 08:05:43 PM UTC 24
Finished Aug 28 08:05:45 PM UTC 24
Peak memory 207776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1979273202 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_access_test.1979273202
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.3219708279
Short name T553
Test name
Test status
Simulation time 2521659792 ps
CPU time 5.37 seconds
Started Aug 28 08:05:44 PM UTC 24
Finished Aug 28 08:05:51 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3219708279 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_pin_override_test.3219708279
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.2757868067
Short name T546
Test name
Test status
Simulation time 2111994104 ps
CPU time 5.74 seconds
Started Aug 28 08:05:42 PM UTC 24
Finished Aug 28 08:05:49 PM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2757868067 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_smoke.2757868067
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.4059521932
Short name T629
Test name
Test status
Simulation time 112006221761 ps
CPU time 74.49 seconds
Started Aug 28 08:05:47 PM UTC 24
Finished Aug 28 08:07:03 PM UTC 24
Peak memory 210568 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4059521932 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_stress_all.4059521932
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.178896592
Short name T192
Test name
Test status
Simulation time 2213158029902 ps
CPU time 438.74 seconds
Started Aug 28 08:05:46 PM UTC 24
Finished Aug 28 08:13:09 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=178896592 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 26.sysrst_ctrl_ultra_low_pwr.178896592
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.3411544721
Short name T562
Test name
Test status
Simulation time 2025966453 ps
CPU time 3.28 seconds
Started Aug 28 08:05:51 PM UTC 24
Finished Aug 28 08:05:55 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3411544721 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_alert_test.3411544721
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2524537046
Short name T564
Test name
Test status
Simulation time 3339671030 ps
CPU time 4.65 seconds
Started Aug 28 08:05:49 PM UTC 24
Finished Aug 28 08:05:55 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2524537046 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_auto_blk_key_output.2524537046
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect.1887557434
Short name T371
Test name
Test status
Simulation time 63656392078 ps
CPU time 44.15 seconds
Started Aug 28 08:05:51 PM UTC 24
Finished Aug 28 08:06:36 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1887557434 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect.1887557434
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2853834141
Short name T148
Test name
Test status
Simulation time 69081212136 ps
CPU time 60.23 seconds
Started Aug 28 08:05:51 PM UTC 24
Finished Aug 28 08:06:53 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2853834141 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_combo_detect_with_pre_cond.2853834141
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.418719087
Short name T573
Test name
Test status
Simulation time 3770406830 ps
CPU time 13.04 seconds
Started Aug 28 08:05:49 PM UTC 24
Finished Aug 28 08:06:04 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=418719087 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ec_pwr_on_rst.418719087
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.3348205518
Short name T231
Test name
Test status
Simulation time 473929680049 ps
CPU time 1735.63 seconds
Started Aug 28 08:05:51 PM UTC 24
Finished Aug 28 08:35:03 PM UTC 24
Peak memory 212524 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3348205518 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_edge_detect.3348205518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.1729134213
Short name T565
Test name
Test status
Simulation time 2618511459 ps
CPU time 6.47 seconds
Started Aug 28 08:05:48 PM UTC 24
Finished Aug 28 08:05:56 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729134213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_flash_wr_prot_out.1729134213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.2817279883
Short name T557
Test name
Test status
Simulation time 2493531807 ps
CPU time 4 seconds
Started Aug 28 08:05:47 PM UTC 24
Finished Aug 28 08:05:52 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2817279883 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_in_out_inverted.2817279883
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.2548206675
Short name T555
Test name
Test status
Simulation time 2039006550 ps
CPU time 3.12 seconds
Started Aug 28 08:05:47 PM UTC 24
Finished Aug 28 08:05:51 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2548206675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_access_test.2548206675
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.1802529269
Short name T560
Test name
Test status
Simulation time 2523895725 ps
CPU time 3.3 seconds
Started Aug 28 08:05:48 PM UTC 24
Finished Aug 28 08:05:53 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802529269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_pin_override_test.1802529269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.1694297028
Short name T556
Test name
Test status
Simulation time 2122162227 ps
CPU time 3.53 seconds
Started Aug 28 08:05:47 PM UTC 24
Finished Aug 28 08:05:52 PM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1694297028 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_smoke.1694297028
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.3988063739
Short name T571
Test name
Test status
Simulation time 11912989228 ps
CPU time 10.21 seconds
Started Aug 28 08:05:51 PM UTC 24
Finished Aug 28 08:06:02 PM UTC 24
Peak memory 210108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988063739 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_stress_all.3988063739
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.823607765
Short name T248
Test name
Test status
Simulation time 4141101188 ps
CPU time 14.54 seconds
Started Aug 28 08:05:51 PM UTC 24
Finished Aug 28 08:06:07 PM UTC 24
Peak memory 220480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=823607765 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 27.sysrst_ctrl_stress_all_with_rand_reset.823607765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2925095162
Short name T437
Test name
Test status
Simulation time 1689920836668 ps
CPU time 24.4 seconds
Started Aug 28 08:05:49 PM UTC 24
Finished Aug 28 08:06:15 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2925095162 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 27.sysrst_ctrl_ultra_low_pwr.2925095162
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/27.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.1296096476
Short name T247
Test name
Test status
Simulation time 2010459832 ps
CPU time 9.32 seconds
Started Aug 28 08:05:56 PM UTC 24
Finished Aug 28 08:06:06 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1296096476 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_alert_test.1296096476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_auto_blk_key_output.3144346906
Short name T570
Test name
Test status
Simulation time 3275772567 ps
CPU time 4.56 seconds
Started Aug 28 08:05:53 PM UTC 24
Finished Aug 28 08:05:59 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3144346906 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_auto_blk_key_output.3144346906
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect_with_pre_cond.925765306
Short name T397
Test name
Test status
Simulation time 64556287158 ps
CPU time 92.37 seconds
Started Aug 28 08:05:54 PM UTC 24
Finished Aug 28 08:07:28 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=925765306 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_combo_detect_with_pre_cond.925765306
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ec_pwr_on_rst.1814195308
Short name T436
Test name
Test status
Simulation time 132683929655 ps
CPU time 83.17 seconds
Started Aug 28 08:05:53 PM UTC 24
Finished Aug 28 08:07:19 PM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1814195308 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ec_pwr_on_rst.1814195308
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.1952346946
Short name T568
Test name
Test status
Simulation time 2648867039 ps
CPU time 2.72 seconds
Started Aug 28 08:05:52 PM UTC 24
Finished Aug 28 08:05:56 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1952346946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_flash_wr_prot_out.1952346946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.2781529585
Short name T245
Test name
Test status
Simulation time 2448354930 ps
CPU time 11.49 seconds
Started Aug 28 08:05:52 PM UTC 24
Finished Aug 28 08:06:05 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2781529585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_in_out_inverted.2781529585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.272347238
Short name T554
Test name
Test status
Simulation time 2053519302 ps
CPU time 8.58 seconds
Started Aug 28 08:05:52 PM UTC 24
Finished Aug 28 08:06:02 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=272347238 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_access_test.272347238
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.1616269505
Short name T567
Test name
Test status
Simulation time 2541975663 ps
CPU time 2.65 seconds
Started Aug 28 08:05:52 PM UTC 24
Finished Aug 28 08:05:56 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1616269505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_pin_override_test.1616269505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.3909981711
Short name T566
Test name
Test status
Simulation time 2121956813 ps
CPU time 3.65 seconds
Started Aug 28 08:05:51 PM UTC 24
Finished Aug 28 08:05:56 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3909981711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_smoke.3909981711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all.1276143500
Short name T290
Test name
Test status
Simulation time 109013363892 ps
CPU time 327.6 seconds
Started Aug 28 08:05:56 PM UTC 24
Finished Aug 28 08:11:28 PM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1276143500 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_stress_all.1276143500
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.2648215679
Short name T246
Test name
Test status
Simulation time 10001116266 ps
CPU time 10.28 seconds
Started Aug 28 08:05:54 PM UTC 24
Finished Aug 28 08:06:05 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2648215679 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 28.sysrst_ctrl_stress_all_with_rand_reset.2648215679
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.1079974520
Short name T526
Test name
Test status
Simulation time 10195207520 ps
CPU time 7.25 seconds
Started Aug 28 08:05:54 PM UTC 24
Finished Aug 28 08:06:02 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1079974520 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 28.sysrst_ctrl_ultra_low_pwr.1079974520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/28.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.99057817
Short name T576
Test name
Test status
Simulation time 2012637930 ps
CPU time 5.8 seconds
Started Aug 28 08:06:03 PM UTC 24
Finished Aug 28 08:06:10 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=99057817 -assert nopostproc +UVM_TESTNAME=
sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regr
ession_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_alert_test.99057817
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.300371274
Short name T793
Test name
Test status
Simulation time 241454160254 ps
CPU time 883.01 seconds
Started Aug 28 08:05:57 PM UTC 24
Finished Aug 28 08:20:50 PM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=300371274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_auto_blk_key_output.300371274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.248381750
Short name T572
Test name
Test status
Simulation time 3479275337 ps
CPU time 4.18 seconds
Started Aug 28 08:05:57 PM UTC 24
Finished Aug 28 08:06:03 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=248381750 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_ec_pwr_on_rst.248381750
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.932859361
Short name T563
Test name
Test status
Simulation time 2637385216 ps
CPU time 3.78 seconds
Started Aug 28 08:05:57 PM UTC 24
Finished Aug 28 08:06:02 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=932859361 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_flash_wr_prot_out.932859361
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.2831710953
Short name T575
Test name
Test status
Simulation time 2458752014 ps
CPU time 12.52 seconds
Started Aug 28 08:05:56 PM UTC 24
Finished Aug 28 08:06:10 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2831710953 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_in_out_inverted.2831710953
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.717835063
Short name T252
Test name
Test status
Simulation time 2171879881 ps
CPU time 10.97 seconds
Started Aug 28 08:05:56 PM UTC 24
Finished Aug 28 08:06:08 PM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=717835063 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_access_test.717835063
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.2363916914
Short name T574
Test name
Test status
Simulation time 2513976669 ps
CPU time 10.23 seconds
Started Aug 28 08:05:57 PM UTC 24
Finished Aug 28 08:06:09 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2363916914 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_pin_override_test.2363916914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.3721294442
Short name T250
Test name
Test status
Simulation time 2113985372 ps
CPU time 10.39 seconds
Started Aug 28 08:05:56 PM UTC 24
Finished Aug 28 08:06:07 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3721294442 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_smoke.3721294442
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.3008062243
Short name T232
Test name
Test status
Simulation time 14786392383 ps
CPU time 15.9 seconds
Started Aug 28 08:06:03 PM UTC 24
Finished Aug 28 08:06:20 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3008062243 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 29.sysrst_ctrl_stress_all.3008062243
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.1023681414
Short name T349
Test name
Test status
Simulation time 5396156577 ps
CPU time 16.2 seconds
Started Aug 28 08:06:01 PM UTC 24
Finished Aug 28 08:06:18 PM UTC 24
Peak memory 226944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1023681414 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 29.sysrst_ctrl_stress_all_with_rand_reset.1023681414
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/29.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_alert_test.1241957884
Short name T447
Test name
Test status
Simulation time 2024471700 ps
CPU time 5.26 seconds
Started Aug 28 08:01:15 PM UTC 24
Finished Aug 28 08:01:22 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1241957884 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_alert_test.1241957884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_auto_blk_key_output.303288423
Short name T31
Test name
Test status
Simulation time 3040896504 ps
CPU time 4.31 seconds
Started Aug 28 08:01:15 PM UTC 24
Finished Aug 28 08:01:20 PM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=303288423 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_auto_blk_key_output.303288423
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect.1611875460
Short name T43
Test name
Test status
Simulation time 65118153483 ps
CPU time 171.43 seconds
Started Aug 28 08:01:15 PM UTC 24
Finished Aug 28 08:04:09 PM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1611875460 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect.1611875460
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst.4276063635
Short name T61
Test name
Test status
Simulation time 2193002735 ps
CPU time 3.44 seconds
Started Aug 28 08:01:12 PM UTC 24
Finished Aug 28 08:01:17 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4276063635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst.4276063635
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.653730031
Short name T62
Test name
Test status
Simulation time 2314968222 ps
CPU time 8.34 seconds
Started Aug 28 08:01:13 PM UTC 24
Finished Aug 28 08:01:23 PM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=653730031 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.653730031
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_combo_detect_with_pre_cond.3434112353
Short name T34
Test name
Test status
Simulation time 26355673694 ps
CPU time 22.24 seconds
Started Aug 28 08:01:15 PM UTC 24
Finished Aug 28 08:01:39 PM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3434112353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_combo_detect_with_pre_cond.3434112353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ec_pwr_on_rst.766928438
Short name T268
Test name
Test status
Simulation time 3591300643 ps
CPU time 14.86 seconds
Started Aug 28 08:01:14 PM UTC 24
Finished Aug 28 08:01:31 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=766928438 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ec_pwr_on_rst.766928438
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.3682696469
Short name T11
Test name
Test status
Simulation time 3153197832 ps
CPU time 3.5 seconds
Started Aug 28 08:01:15 PM UTC 24
Finished Aug 28 08:01:19 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3682696469 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_edge_detect.3682696469
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_flash_wr_prot_out.913304635
Short name T79
Test name
Test status
Simulation time 2643526491 ps
CPU time 2.52 seconds
Started Aug 28 08:01:13 PM UTC 24
Finished Aug 28 08:01:17 PM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913304635 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_flash_wr_prot_out.913304635
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_in_out_inverted.1224392163
Short name T27
Test name
Test status
Simulation time 2480448065 ps
CPU time 5.68 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:01:17 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1224392163 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_in_out_inverted.1224392163
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_pin_access_test.3785760037
Short name T95
Test name
Test status
Simulation time 2042641485 ps
CPU time 4.07 seconds
Started Aug 28 08:01:13 PM UTC 24
Finished Aug 28 08:01:18 PM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3785760037 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_pin_access_test.3785760037
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_sec_cm.1127151114
Short name T332
Test name
Test status
Simulation time 22106831235 ps
CPU time 20.15 seconds
Started Aug 28 08:01:15 PM UTC 24
Finished Aug 28 08:01:36 PM UTC 24
Peak memory 240280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1127151114 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_sec_cm.1127151114
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_smoke.3105162946
Short name T167
Test name
Test status
Simulation time 2110312579 ps
CPU time 8.65 seconds
Started Aug 28 08:01:10 PM UTC 24
Finished Aug 28 08:01:20 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3105162946 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_smoke.3105162946
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all.1229018354
Short name T243
Test name
Test status
Simulation time 7711385975 ps
CPU time 24.35 seconds
Started Aug 28 08:01:15 PM UTC 24
Finished Aug 28 08:01:41 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1229018354 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_stress_all.1229018354
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_stress_all_with_rand_reset.4287520213
Short name T159
Test name
Test status
Simulation time 11891492554 ps
CPU time 11.39 seconds
Started Aug 28 08:01:15 PM UTC 24
Finished Aug 28 08:01:28 PM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4287520213 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 3.sysrst_ctrl_stress_all_with_rand_reset.4287520213
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_ultra_low_pwr.308430173
Short name T84
Test name
Test status
Simulation time 3026110538 ps
CPU time 8.23 seconds
Started Aug 28 08:01:15 PM UTC 24
Finished Aug 28 08:01:24 PM UTC 24
Peak memory 209736 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=308430173 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 3.sysrst_ctrl_ultra_low_pwr.308430173
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/3.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.844696270
Short name T585
Test name
Test status
Simulation time 2012553349 ps
CPU time 9.07 seconds
Started Aug 28 08:06:09 PM UTC 24
Finished Aug 28 08:06:19 PM UTC 24
Peak memory 209748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=844696270 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_alert_test.844696270
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.654095748
Short name T623
Test name
Test status
Simulation time 274010477879 ps
CPU time 51.4 seconds
Started Aug 28 08:06:05 PM UTC 24
Finished Aug 28 08:06:58 PM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=654095748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_auto_blk_key_output.654095748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.29279534
Short name T594
Test name
Test status
Simulation time 4166293064 ps
CPU time 19.18 seconds
Started Aug 28 08:06:05 PM UTC 24
Finished Aug 28 08:06:26 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=29279534 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_ec_pwr_on_rst.29279534
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.1192975772
Short name T242
Test name
Test status
Simulation time 4331585805 ps
CPU time 4.97 seconds
Started Aug 28 08:06:08 PM UTC 24
Finished Aug 28 08:06:14 PM UTC 24
Peak memory 210256 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1192975772 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_edge_detect.1192975772
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1729692336
Short name T582
Test name
Test status
Simulation time 2609641396 ps
CPU time 12.28 seconds
Started Aug 28 08:06:04 PM UTC 24
Finished Aug 28 08:06:18 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1729692336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_flash_wr_prot_out.1729692336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.1104758986
Short name T251
Test name
Test status
Simulation time 2490059585 ps
CPU time 3.69 seconds
Started Aug 28 08:06:03 PM UTC 24
Finished Aug 28 08:06:08 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1104758986 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_in_out_inverted.1104758986
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.4115519650
Short name T253
Test name
Test status
Simulation time 2029379119 ps
CPU time 4.29 seconds
Started Aug 28 08:06:03 PM UTC 24
Finished Aug 28 08:06:08 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4115519650 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_access_test.4115519650
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.2681447120
Short name T577
Test name
Test status
Simulation time 2519538321 ps
CPU time 6.34 seconds
Started Aug 28 08:06:04 PM UTC 24
Finished Aug 28 08:06:12 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2681447120 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_pin_override_test.2681447120
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1396962090
Short name T249
Test name
Test status
Simulation time 2123856688 ps
CPU time 3.12 seconds
Started Aug 28 08:06:03 PM UTC 24
Finished Aug 28 08:06:07 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1396962090 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_smoke.1396962090
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.1431928450
Short name T580
Test name
Test status
Simulation time 11982457211 ps
CPU time 3.85 seconds
Started Aug 28 08:06:09 PM UTC 24
Finished Aug 28 08:06:14 PM UTC 24
Peak memory 209828 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1431928450 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 30.sysrst_ctrl_stress_all.1431928450
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.183894687
Short name T344
Test name
Test status
Simulation time 3309033355 ps
CPU time 10.76 seconds
Started Aug 28 08:06:08 PM UTC 24
Finished Aug 28 08:06:20 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=183894687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 30.sysrst_ctrl_stress_all_with_rand_reset.183894687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3632079774
Short name T586
Test name
Test status
Simulation time 2033801655 ps
CPU time 2.93 seconds
Started Aug 28 08:06:16 PM UTC 24
Finished Aug 28 08:06:20 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3632079774 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_alert_test.3632079774
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3087390349
Short name T583
Test name
Test status
Simulation time 4016975581 ps
CPU time 4.72 seconds
Started Aug 28 08:06:12 PM UTC 24
Finished Aug 28 08:06:18 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3087390349 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_auto_blk_key_output.3087390349
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.2612769152
Short name T142
Test name
Test status
Simulation time 174205948320 ps
CPU time 552.11 seconds
Started Aug 28 08:06:15 PM UTC 24
Finished Aug 28 08:15:33 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2612769152 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect.2612769152
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.4274364048
Short name T134
Test name
Test status
Simulation time 59465889274 ps
CPU time 20.38 seconds
Started Aug 28 08:06:15 PM UTC 24
Finished Aug 28 08:06:36 PM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4274364048 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_combo_detect_with_pre_cond.4274364048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.1210658820
Short name T584
Test name
Test status
Simulation time 5078871998 ps
CPU time 6.62 seconds
Started Aug 28 08:06:11 PM UTC 24
Finished Aug 28 08:06:19 PM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1210658820 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ec_pwr_on_rst.1210658820
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3292523549
Short name T219
Test name
Test status
Simulation time 4738287793 ps
CPU time 12.23 seconds
Started Aug 28 08:06:15 PM UTC 24
Finished Aug 28 08:06:28 PM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3292523549 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_edge_detect.3292523549
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.352731175
Short name T581
Test name
Test status
Simulation time 2622408721 ps
CPU time 3.9 seconds
Started Aug 28 08:06:10 PM UTC 24
Finished Aug 28 08:06:15 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=352731175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_flash_wr_prot_out.352731175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.2201337322
Short name T579
Test name
Test status
Simulation time 2474111728 ps
CPU time 3.53 seconds
Started Aug 28 08:06:09 PM UTC 24
Finished Aug 28 08:06:14 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2201337322 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_in_out_inverted.2201337322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.1909554313
Short name T588
Test name
Test status
Simulation time 2023948462 ps
CPU time 9.26 seconds
Started Aug 28 08:06:10 PM UTC 24
Finished Aug 28 08:06:21 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1909554313 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_access_test.1909554313
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.3575200848
Short name T578
Test name
Test status
Simulation time 2572943992 ps
CPU time 2.21 seconds
Started Aug 28 08:06:10 PM UTC 24
Finished Aug 28 08:06:14 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575200848 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_pin_override_test.3575200848
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.72215383
Short name T587
Test name
Test status
Simulation time 2114298169 ps
CPU time 10.62 seconds
Started Aug 28 08:06:09 PM UTC 24
Finished Aug 28 08:06:21 PM UTC 24
Peak memory 210072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=72215383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ct
rl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_smoke.72215383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.3046505754
Short name T631
Test name
Test status
Simulation time 16083050719 ps
CPU time 46.37 seconds
Started Aug 28 08:06:16 PM UTC 24
Finished Aug 28 08:07:04 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3046505754 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_stress_all.3046505754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.830282409
Short name T350
Test name
Test status
Simulation time 17319959919 ps
CPU time 11.5 seconds
Started Aug 28 08:06:15 PM UTC 24
Finished Aug 28 08:06:27 PM UTC 24
Peak memory 220604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=830282409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 31.sysrst_ctrl_stress_all_with_rand_reset.830282409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.1365609780
Short name T165
Test name
Test status
Simulation time 6123228580 ps
CPU time 6.44 seconds
Started Aug 28 08:06:12 PM UTC 24
Finished Aug 28 08:06:20 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365609780 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 31.sysrst_ctrl_ultra_low_pwr.1365609780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/31.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.1035812095
Short name T593
Test name
Test status
Simulation time 2098275210 ps
CPU time 1.52 seconds
Started Aug 28 08:06:23 PM UTC 24
Finished Aug 28 08:06:26 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1035812095 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_alert_test.1035812095
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.2623579755
Short name T597
Test name
Test status
Simulation time 3501363440 ps
CPU time 7.66 seconds
Started Aug 28 08:06:21 PM UTC 24
Finished Aug 28 08:06:29 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2623579755 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_auto_blk_key_output.2623579755
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect.1118795167
Short name T137
Test name
Test status
Simulation time 73016196013 ps
CPU time 45.42 seconds
Started Aug 28 08:06:21 PM UTC 24
Finished Aug 28 08:07:07 PM UTC 24
Peak memory 210364 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1118795167 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect.1118795167
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.1559028181
Short name T405
Test name
Test status
Simulation time 151140674111 ps
CPU time 156.79 seconds
Started Aug 28 08:06:21 PM UTC 24
Finished Aug 28 08:09:00 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1559028181 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_combo_detect_with_pre_cond.1559028181
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.2023169366
Short name T595
Test name
Test status
Simulation time 2731976409 ps
CPU time 6.84 seconds
Started Aug 28 08:06:20 PM UTC 24
Finished Aug 28 08:06:28 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2023169366 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ec_pwr_on_rst.2023169366
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.537122431
Short name T229
Test name
Test status
Simulation time 4734560967 ps
CPU time 5.05 seconds
Started Aug 28 08:06:21 PM UTC 24
Finished Aug 28 08:06:27 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537122431 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_edge_detect.537122431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.1031194343
Short name T591
Test name
Test status
Simulation time 2631425493 ps
CPU time 3.68 seconds
Started Aug 28 08:06:19 PM UTC 24
Finished Aug 28 08:06:24 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1031194343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_flash_wr_prot_out.1031194343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.544349696
Short name T589
Test name
Test status
Simulation time 2450658439 ps
CPU time 2.56 seconds
Started Aug 28 08:06:18 PM UTC 24
Finished Aug 28 08:06:22 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=544349696 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_in_out_inverted.544349696
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.490822921
Short name T590
Test name
Test status
Simulation time 2169843584 ps
CPU time 3.62 seconds
Started Aug 28 08:06:18 PM UTC 24
Finished Aug 28 08:06:23 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=490822921 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_access_test.490822921
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2359489487
Short name T599
Test name
Test status
Simulation time 2513533922 ps
CPU time 11.75 seconds
Started Aug 28 08:06:19 PM UTC 24
Finished Aug 28 08:06:32 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2359489487 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_pin_override_test.2359489487
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.258582984
Short name T592
Test name
Test status
Simulation time 2115269745 ps
CPU time 7.09 seconds
Started Aug 28 08:06:16 PM UTC 24
Finished Aug 28 08:06:24 PM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=258582984 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_smoke.258582984
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all.1920727262
Short name T619
Test name
Test status
Simulation time 9239288595 ps
CPU time 23.07 seconds
Started Aug 28 08:06:22 PM UTC 24
Finished Aug 28 08:06:46 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1920727262 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_stress_all.1920727262
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.912305844
Short name T600
Test name
Test status
Simulation time 3757902883 ps
CPU time 9.41 seconds
Started Aug 28 08:06:22 PM UTC 24
Finished Aug 28 08:06:32 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=912305844 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 32.sysrst_ctrl_stress_all_with_rand_reset.912305844
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ultra_low_pwr.1540986968
Short name T439
Test name
Test status
Simulation time 303600451539 ps
CPU time 50.98 seconds
Started Aug 28 08:06:21 PM UTC 24
Finished Aug 28 08:07:13 PM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1540986968 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 32.sysrst_ctrl_ultra_low_pwr.1540986968
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/32.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.829858019
Short name T609
Test name
Test status
Simulation time 2014844987 ps
CPU time 6.41 seconds
Started Aug 28 08:06:33 PM UTC 24
Finished Aug 28 08:06:41 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=829858019 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_alert_test.829858019
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.609821425
Short name T612
Test name
Test status
Simulation time 3336433984 ps
CPU time 12.28 seconds
Started Aug 28 08:06:28 PM UTC 24
Finished Aug 28 08:06:41 PM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=609821425 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_auto_blk_key_output.609821425
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect.2320126789
Short name T416
Test name
Test status
Simulation time 95454934055 ps
CPU time 85.14 seconds
Started Aug 28 08:06:29 PM UTC 24
Finished Aug 28 08:07:56 PM UTC 24
Peak memory 210108 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2320126789 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect.2320126789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.761547742
Short name T378
Test name
Test status
Simulation time 76489219039 ps
CPU time 299.44 seconds
Started Aug 28 08:06:30 PM UTC 24
Finished Aug 28 08:11:34 PM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=761547742 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_combo_detect_with_pre_cond.761547742
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.333977464
Short name T606
Test name
Test status
Simulation time 4359121553 ps
CPU time 11.47 seconds
Started Aug 28 08:06:26 PM UTC 24
Finished Aug 28 08:06:39 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=333977464 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_ec_pwr_on_rst.333977464
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.957767634
Short name T601
Test name
Test status
Simulation time 2645319305 ps
CPU time 3.09 seconds
Started Aug 28 08:06:30 PM UTC 24
Finished Aug 28 08:06:34 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=957767634 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_edge_detect.957767634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.406065962
Short name T605
Test name
Test status
Simulation time 2610816122 ps
CPU time 10.75 seconds
Started Aug 28 08:06:26 PM UTC 24
Finished Aug 28 08:06:38 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=406065962 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_flash_wr_prot_out.406065962
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.3709589446
Short name T598
Test name
Test status
Simulation time 2455962946 ps
CPU time 6.98 seconds
Started Aug 28 08:06:24 PM UTC 24
Finished Aug 28 08:06:32 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3709589446 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_in_out_inverted.3709589446
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.3433400888
Short name T602
Test name
Test status
Simulation time 2048508144 ps
CPU time 8.86 seconds
Started Aug 28 08:06:25 PM UTC 24
Finished Aug 28 08:06:35 PM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3433400888 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_access_test.3433400888
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.3196334287
Short name T596
Test name
Test status
Simulation time 2535795151 ps
CPU time 2.54 seconds
Started Aug 28 08:06:25 PM UTC 24
Finished Aug 28 08:06:29 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3196334287 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_pin_override_test.3196334287
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.1582506274
Short name T603
Test name
Test status
Simulation time 2110879444 ps
CPU time 10.69 seconds
Started Aug 28 08:06:24 PM UTC 24
Finished Aug 28 08:06:36 PM UTC 24
Peak memory 210072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1582506274 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_smoke.1582506274
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.3007811740
Short name T155
Test name
Test status
Simulation time 13374574437 ps
CPU time 34.73 seconds
Started Aug 28 08:06:30 PM UTC 24
Finished Aug 28 08:07:06 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3007811740 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 33.sysrst_ctrl_stress_all.3007811740
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.3966786571
Short name T608
Test name
Test status
Simulation time 6851925271 ps
CPU time 8.47 seconds
Started Aug 28 08:06:30 PM UTC 24
Finished Aug 28 08:06:40 PM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3966786571 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 33.sysrst_ctrl_stress_all_with_rand_reset.3966786571
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/33.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.1876151460
Short name T616
Test name
Test status
Simulation time 2030691565 ps
CPU time 3.04 seconds
Started Aug 28 08:06:41 PM UTC 24
Finished Aug 28 08:06:45 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1876151460 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_alert_test.1876151460
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.2937847383
Short name T614
Test name
Test status
Simulation time 3954508574 ps
CPU time 4.43 seconds
Started Aug 28 08:06:38 PM UTC 24
Finished Aug 28 08:06:43 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2937847383 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_auto_blk_key_output.2937847383
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect.402736531
Short name T140
Test name
Test status
Simulation time 198535885002 ps
CPU time 294.65 seconds
Started Aug 28 08:06:39 PM UTC 24
Finished Aug 28 08:11:37 PM UTC 24
Peak memory 210168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=402736531 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect.402736531
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_combo_detect_with_pre_cond.3078893127
Short name T154
Test name
Test status
Simulation time 69023597792 ps
CPU time 24.88 seconds
Started Aug 28 08:06:40 PM UTC 24
Finished Aug 28 08:07:06 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3078893127 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_combo_detect_with_pre_cond.3078893127
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2406703668
Short name T615
Test name
Test status
Simulation time 4401540659 ps
CPU time 5.42 seconds
Started Aug 28 08:06:38 PM UTC 24
Finished Aug 28 08:06:44 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2406703668 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ec_pwr_on_rst.2406703668
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.2820384133
Short name T257
Test name
Test status
Simulation time 3755753920 ps
CPU time 4.35 seconds
Started Aug 28 08:06:39 PM UTC 24
Finished Aug 28 08:06:44 PM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2820384133 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_edge_detect.2820384133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.687757558
Short name T611
Test name
Test status
Simulation time 2640032391 ps
CPU time 3.45 seconds
Started Aug 28 08:06:36 PM UTC 24
Finished Aug 28 08:06:41 PM UTC 24
Peak memory 209904 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=687757558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_flash_wr_prot_out.687757558
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.2160265015
Short name T613
Test name
Test status
Simulation time 2459976155 ps
CPU time 6.52 seconds
Started Aug 28 08:06:33 PM UTC 24
Finished Aug 28 08:06:41 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160265015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_in_out_inverted.2160265015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.3741642389
Short name T607
Test name
Test status
Simulation time 2242137303 ps
CPU time 2.79 seconds
Started Aug 28 08:06:35 PM UTC 24
Finished Aug 28 08:06:39 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3741642389 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_access_test.3741642389
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.3565887054
Short name T610
Test name
Test status
Simulation time 2538580750 ps
CPU time 3.23 seconds
Started Aug 28 08:06:36 PM UTC 24
Finished Aug 28 08:06:41 PM UTC 24
Peak memory 209932 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3565887054 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_pin_override_test.3565887054
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.3539630908
Short name T604
Test name
Test status
Simulation time 2121840033 ps
CPU time 3.47 seconds
Started Aug 28 08:06:33 PM UTC 24
Finished Aug 28 08:06:38 PM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3539630908 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_smoke.3539630908
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.632203048
Short name T638
Test name
Test status
Simulation time 6493791786 ps
CPU time 28.61 seconds
Started Aug 28 08:06:41 PM UTC 24
Finished Aug 28 08:07:11 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=632203048 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_stress_all.632203048
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1470722929
Short name T621
Test name
Test status
Simulation time 20547001056 ps
CPU time 15.42 seconds
Started Aug 28 08:06:40 PM UTC 24
Finished Aug 28 08:06:56 PM UTC 24
Peak memory 220520 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1470722929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 34.sysrst_ctrl_stress_all_with_rand_reset.1470722929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.987597010
Short name T173
Test name
Test status
Simulation time 4707882718 ps
CPU time 3.35 seconds
Started Aug 28 08:06:39 PM UTC 24
Finished Aug 28 08:06:43 PM UTC 24
Peak memory 209604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=987597010 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 34.sysrst_ctrl_ultra_low_pwr.987597010
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/34.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.2572426072
Short name T146
Test name
Test status
Simulation time 2092832036 ps
CPU time 1.51 seconds
Started Aug 28 08:06:48 PM UTC 24
Finished Aug 28 08:06:51 PM UTC 24
Peak memory 207984 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2572426072 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_alert_test.2572426072
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.2160470789
Short name T622
Test name
Test status
Simulation time 3689370475 ps
CPU time 11.1 seconds
Started Aug 28 08:06:45 PM UTC 24
Finished Aug 28 08:06:57 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2160470789 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_auto_blk_key_output.2160470789
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.1915768724
Short name T426
Test name
Test status
Simulation time 181284486538 ps
CPU time 100.36 seconds
Started Aug 28 08:06:46 PM UTC 24
Finished Aug 28 08:08:28 PM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1915768724 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_combo_detect.1915768724
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.334664350
Short name T144
Test name
Test status
Simulation time 2537667753 ps
CPU time 3.88 seconds
Started Aug 28 08:06:45 PM UTC 24
Finished Aug 28 08:06:49 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=334664350 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ec_pwr_on_rst.334664350
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.2814857579
Short name T254
Test name
Test status
Simulation time 5687770681 ps
CPU time 11.7 seconds
Started Aug 28 08:06:46 PM UTC 24
Finished Aug 28 08:06:59 PM UTC 24
Peak memory 209800 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2814857579 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_edge_detect.2814857579
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.3066422793
Short name T147
Test name
Test status
Simulation time 2610719376 ps
CPU time 7.59 seconds
Started Aug 28 08:06:43 PM UTC 24
Finished Aug 28 08:06:52 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3066422793 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_flash_wr_prot_out.3066422793
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.26607606
Short name T618
Test name
Test status
Simulation time 2506673553 ps
CPU time 1.95 seconds
Started Aug 28 08:06:42 PM UTC 24
Finished Aug 28 08:06:45 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=26607606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_in_out_inverted.26607606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.2328471205
Short name T150
Test name
Test status
Simulation time 2122150777 ps
CPU time 10.64 seconds
Started Aug 28 08:06:42 PM UTC 24
Finished Aug 28 08:06:54 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2328471205 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_access_test.2328471205
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.833586397
Short name T620
Test name
Test status
Simulation time 2534318869 ps
CPU time 3.72 seconds
Started Aug 28 08:06:42 PM UTC 24
Finished Aug 28 08:06:47 PM UTC 24
Peak memory 210140 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=833586397 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_pin_override_test.833586397
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.1772236836
Short name T617
Test name
Test status
Simulation time 2128243463 ps
CPU time 3.11 seconds
Started Aug 28 08:06:41 PM UTC 24
Finished Aug 28 08:06:45 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1772236836 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_smoke.1772236836
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.3062502780
Short name T420
Test name
Test status
Simulation time 13584002720 ps
CPU time 10.88 seconds
Started Aug 28 08:06:48 PM UTC 24
Finished Aug 28 08:07:00 PM UTC 24
Peak memory 209964 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3062502780 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_stress_all.3062502780
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1757068731
Short name T156
Test name
Test status
Simulation time 3672396432 ps
CPU time 18.01 seconds
Started Aug 28 08:06:47 PM UTC 24
Finished Aug 28 08:07:06 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1757068731 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 35.sysrst_ctrl_stress_all_with_rand_reset.1757068731
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.2494046673
Short name T143
Test name
Test status
Simulation time 5874455758 ps
CPU time 2.9 seconds
Started Aug 28 08:06:45 PM UTC 24
Finished Aug 28 08:06:49 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2494046673 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 35.sysrst_ctrl_ultra_low_pwr.2494046673
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/35.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.3638742943
Short name T626
Test name
Test status
Simulation time 2108924599 ps
CPU time 1.54 seconds
Started Aug 28 08:06:59 PM UTC 24
Finished Aug 28 08:07:02 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638742943 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_alert_test.3638742943
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.2143080284
Short name T284
Test name
Test status
Simulation time 26332537161 ps
CPU time 37.83 seconds
Started Aug 28 08:06:57 PM UTC 24
Finished Aug 28 08:07:36 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2143080284 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_combo_detect_with_pre_cond.2143080284
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2268774490
Short name T635
Test name
Test status
Simulation time 4683363621 ps
CPU time 15.73 seconds
Started Aug 28 08:06:53 PM UTC 24
Finished Aug 28 08:07:09 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2268774490 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ec_pwr_on_rst.2268774490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.1642772548
Short name T230
Test name
Test status
Simulation time 3585804312 ps
CPU time 4.16 seconds
Started Aug 28 08:06:56 PM UTC 24
Finished Aug 28 08:07:01 PM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1642772548 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_edge_detect.1642772548
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.1808786965
Short name T151
Test name
Test status
Simulation time 2633381365 ps
CPU time 2.9 seconds
Started Aug 28 08:06:51 PM UTC 24
Finished Aug 28 08:06:55 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1808786965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_flash_wr_prot_out.1808786965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.1381482495
Short name T149
Test name
Test status
Simulation time 2486963375 ps
CPU time 3.57 seconds
Started Aug 28 08:06:49 PM UTC 24
Finished Aug 28 08:06:54 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1381482495 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_in_out_inverted.1381482495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.2686494648
Short name T625
Test name
Test status
Simulation time 2205704122 ps
CPU time 10.28 seconds
Started Aug 28 08:06:50 PM UTC 24
Finished Aug 28 08:07:02 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2686494648 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_access_test.2686494648
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.2360513548
Short name T628
Test name
Test status
Simulation time 2513661237 ps
CPU time 10.46 seconds
Started Aug 28 08:06:51 PM UTC 24
Finished Aug 28 08:07:03 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2360513548 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_pin_override_test.2360513548
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.1558318474
Short name T624
Test name
Test status
Simulation time 2114585045 ps
CPU time 10.42 seconds
Started Aug 28 08:06:49 PM UTC 24
Finished Aug 28 08:07:01 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1558318474 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_smoke.1558318474
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.503288887
Short name T632
Test name
Test status
Simulation time 7298141929 ps
CPU time 6.01 seconds
Started Aug 28 08:06:57 PM UTC 24
Finished Aug 28 08:07:04 PM UTC 24
Peak memory 220484 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=503288887 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 36.sysrst_ctrl_stress_all_with_rand_reset.503288887
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.1225855737
Short name T634
Test name
Test status
Simulation time 8905768982 ps
CPU time 13.56 seconds
Started Aug 28 08:06:55 PM UTC 24
Finished Aug 28 08:07:09 PM UTC 24
Peak memory 210004 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1225855737 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 36.sysrst_ctrl_ultra_low_pwr.1225855737
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.3145173702
Short name T637
Test name
Test status
Simulation time 2016795921 ps
CPU time 4.11 seconds
Started Aug 28 08:07:05 PM UTC 24
Finished Aug 28 08:07:10 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3145173702 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_alert_test.3145173702
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2502399251
Short name T649
Test name
Test status
Simulation time 3199684220 ps
CPU time 15.42 seconds
Started Aug 28 08:07:03 PM UTC 24
Finished Aug 28 08:07:19 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2502399251 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_auto_blk_key_output.2502399251
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.111353328
Short name T288
Test name
Test status
Simulation time 34416121748 ps
CPU time 123.15 seconds
Started Aug 28 08:07:04 PM UTC 24
Finished Aug 28 08:09:09 PM UTC 24
Peak memory 210500 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=111353328 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_combo_detect.111353328
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.3780989996
Short name T776
Test name
Test status
Simulation time 71315145829 ps
CPU time 217.2 seconds
Started Aug 28 08:07:03 PM UTC 24
Finished Aug 28 08:10:43 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3780989996 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ec_pwr_on_rst.3780989996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.358366495
Short name T215
Test name
Test status
Simulation time 4711772900 ps
CPU time 15.4 seconds
Started Aug 28 08:07:04 PM UTC 24
Finished Aug 28 08:07:20 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=358366495 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_edge_detect.358366495
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.1802410677
Short name T157
Test name
Test status
Simulation time 2623135942 ps
CPU time 3.87 seconds
Started Aug 28 08:07:02 PM UTC 24
Finished Aug 28 08:07:06 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1802410677 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_flash_wr_prot_out.1802410677
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.1643770638
Short name T627
Test name
Test status
Simulation time 2615451440 ps
CPU time 1.6 seconds
Started Aug 28 08:07:00 PM UTC 24
Finished Aug 28 08:07:03 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1643770638 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_in_out_inverted.1643770638
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.3103256101
Short name T153
Test name
Test status
Simulation time 2248122260 ps
CPU time 3.29 seconds
Started Aug 28 08:07:01 PM UTC 24
Finished Aug 28 08:07:06 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3103256101 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_access_test.3103256101
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.2377096212
Short name T639
Test name
Test status
Simulation time 2513990581 ps
CPU time 9.69 seconds
Started Aug 28 08:07:01 PM UTC 24
Finished Aug 28 08:07:12 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2377096212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_pin_override_test.2377096212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.317955647
Short name T630
Test name
Test status
Simulation time 2133473108 ps
CPU time 3.4 seconds
Started Aug 28 08:06:59 PM UTC 24
Finished Aug 28 08:07:04 PM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=317955647 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_smoke.317955647
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.2815429353
Short name T648
Test name
Test status
Simulation time 8375673452 ps
CPU time 12.41 seconds
Started Aug 28 08:07:05 PM UTC 24
Finished Aug 28 08:07:19 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2815429353 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_stress_all.2815429353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all_with_rand_reset.3576258158
Short name T351
Test name
Test status
Simulation time 8590640600 ps
CPU time 8.63 seconds
Started Aug 28 08:07:05 PM UTC 24
Finished Aug 28 08:07:15 PM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3576258158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 37.sysrst_ctrl_stress_all_with_rand_reset.3576258158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.3947245712
Short name T122
Test name
Test status
Simulation time 6229161113 ps
CPU time 4.32 seconds
Started Aug 28 08:07:03 PM UTC 24
Finished Aug 28 08:07:08 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3947245712 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 37.sysrst_ctrl_ultra_low_pwr.3947245712
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/37.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.3766991926
Short name T645
Test name
Test status
Simulation time 2033901651 ps
CPU time 3.28 seconds
Started Aug 28 08:07:11 PM UTC 24
Finished Aug 28 08:07:16 PM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3766991926 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_alert_test.3766991926
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.3097334973
Short name T650
Test name
Test status
Simulation time 3732902694 ps
CPU time 10.68 seconds
Started Aug 28 08:07:08 PM UTC 24
Finished Aug 28 08:07:19 PM UTC 24
Peak memory 209968 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3097334973 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_auto_blk_key_output.3097334973
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect.3950748111
Short name T788
Test name
Test status
Simulation time 162852406816 ps
CPU time 476.66 seconds
Started Aug 28 08:07:09 PM UTC 24
Finished Aug 28 08:15:11 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3950748111 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_combo_detect.3950748111
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ec_pwr_on_rst.3355855507
Short name T643
Test name
Test status
Simulation time 4766269278 ps
CPU time 4.83 seconds
Started Aug 28 08:07:08 PM UTC 24
Finished Aug 28 08:07:13 PM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3355855507 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ec_pwr_on_rst.3355855507
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_edge_detect.414539077
Short name T641
Test name
Test status
Simulation time 2730330521 ps
CPU time 2.52 seconds
Started Aug 28 08:07:09 PM UTC 24
Finished Aug 28 08:07:12 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=414539077 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_edge_detect.414539077
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.3414043578
Short name T642
Test name
Test status
Simulation time 2634133687 ps
CPU time 3.76 seconds
Started Aug 28 08:07:08 PM UTC 24
Finished Aug 28 08:07:12 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3414043578 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_flash_wr_prot_out.3414043578
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.1378610222
Short name T644
Test name
Test status
Simulation time 2467820390 ps
CPU time 6.48 seconds
Started Aug 28 08:07:06 PM UTC 24
Finished Aug 28 08:07:14 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1378610222 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_in_out_inverted.1378610222
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_access_test.3339074567
Short name T633
Test name
Test status
Simulation time 2318586021 ps
CPU time 1.66 seconds
Started Aug 28 08:07:06 PM UTC 24
Finished Aug 28 08:07:09 PM UTC 24
Peak memory 208180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3339074567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_access_test.3339074567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.522548147
Short name T636
Test name
Test status
Simulation time 2538273196 ps
CPU time 2.65 seconds
Started Aug 28 08:07:06 PM UTC 24
Finished Aug 28 08:07:10 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=522548147 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_pin_override_test.522548147
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.2748226024
Short name T646
Test name
Test status
Simulation time 2112315017 ps
CPU time 10.05 seconds
Started Aug 28 08:07:05 PM UTC 24
Finished Aug 28 08:07:16 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2748226024 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_smoke.2748226024
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.1938770133
Short name T760
Test name
Test status
Simulation time 62365482506 ps
CPU time 129.13 seconds
Started Aug 28 08:07:10 PM UTC 24
Finished Aug 28 08:09:21 PM UTC 24
Peak memory 210168 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1938770133 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_stress_all.1938770133
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all_with_rand_reset.2651538966
Short name T37
Test name
Test status
Simulation time 6351475576 ps
CPU time 21.46 seconds
Started Aug 28 08:07:10 PM UTC 24
Finished Aug 28 08:07:33 PM UTC 24
Peak memory 220480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=2651538966 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 38.sysrst_ctrl_stress_all_with_rand_reset.2651538966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.1672717461
Short name T172
Test name
Test status
Simulation time 8025671123 ps
CPU time 3.17 seconds
Started Aug 28 08:07:08 PM UTC 24
Finished Aug 28 08:07:12 PM UTC 24
Peak memory 209912 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1672717461 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 38.sysrst_ctrl_ultra_low_pwr.1672717461
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/38.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.1309089429
Short name T659
Test name
Test status
Simulation time 2016342279 ps
CPU time 9.63 seconds
Started Aug 28 08:07:18 PM UTC 24
Finished Aug 28 08:07:29 PM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1309089429 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_alert_test.1309089429
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1166637491
Short name T152
Test name
Test status
Simulation time 3323752397 ps
CPU time 8.47 seconds
Started Aug 28 08:07:14 PM UTC 24
Finished Aug 28 08:07:23 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1166637491 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_auto_blk_key_output.1166637491
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_combo_detect_with_pre_cond.2413453240
Short name T765
Test name
Test status
Simulation time 46009999508 ps
CPU time 145.16 seconds
Started Aug 28 08:07:16 PM UTC 24
Finished Aug 28 08:09:43 PM UTC 24
Peak memory 210320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2413453240 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_combo_detect_with_pre_cond.2413453240
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ec_pwr_on_rst.3567230328
Short name T792
Test name
Test status
Simulation time 753979153638 ps
CPU time 617.57 seconds
Started Aug 28 08:07:14 PM UTC 24
Finished Aug 28 08:17:38 PM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567230328 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ec_pwr_on_rst.3567230328
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.4251673620
Short name T651
Test name
Test status
Simulation time 3115134394 ps
CPU time 3.9 seconds
Started Aug 28 08:07:15 PM UTC 24
Finished Aug 28 08:07:20 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4251673620 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_edge_detect.4251673620
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.33816476
Short name T652
Test name
Test status
Simulation time 2610137657 ps
CPU time 7.11 seconds
Started Aug 28 08:07:14 PM UTC 24
Finished Aug 28 08:07:22 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=33816476 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_flash_wr_prot_out.33816476
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.2981234590
Short name T647
Test name
Test status
Simulation time 2478639878 ps
CPU time 4 seconds
Started Aug 28 08:07:12 PM UTC 24
Finished Aug 28 08:07:17 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2981234590 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_in_out_inverted.2981234590
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_access_test.1468283404
Short name T640
Test name
Test status
Simulation time 2146206681 ps
CPU time 10.6 seconds
Started Aug 28 08:07:12 PM UTC 24
Finished Aug 28 08:07:24 PM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1468283404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_access_test.1468283404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.1365116896
Short name T655
Test name
Test status
Simulation time 2510892616 ps
CPU time 12.21 seconds
Started Aug 28 08:07:13 PM UTC 24
Finished Aug 28 08:07:27 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1365116896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_pin_override_test.1365116896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_smoke.7769657
Short name T145
Test name
Test status
Simulation time 2113940052 ps
CPU time 10.7 seconds
Started Aug 28 08:07:11 PM UTC 24
Finished Aug 28 08:07:23 PM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=7769657 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_
TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctr
l-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_smoke.7769657
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all.1782608853
Short name T685
Test name
Test status
Simulation time 6621195246 ps
CPU time 28.13 seconds
Started Aug 28 08:07:17 PM UTC 24
Finished Aug 28 08:07:46 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1782608853 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_stress_all.1782608853
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_stress_all_with_rand_reset.3708672837
Short name T665
Test name
Test status
Simulation time 4594511812 ps
CPU time 16.68 seconds
Started Aug 28 08:07:16 PM UTC 24
Finished Aug 28 08:07:34 PM UTC 24
Peak memory 220480 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3708672837 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 39.sysrst_ctrl_stress_all_with_rand_reset.3708672837
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.385341799
Short name T653
Test name
Test status
Simulation time 4673160999 ps
CPU time 9.73 seconds
Started Aug 28 08:07:14 PM UTC 24
Finished Aug 28 08:07:24 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=385341799 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 39.sysrst_ctrl_ultra_low_pwr.385341799
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/39.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_alert_test.3763438469
Short name T166
Test name
Test status
Simulation time 2019511842 ps
CPU time 5.23 seconds
Started Aug 28 08:01:20 PM UTC 24
Finished Aug 28 08:01:27 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3763438469 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_alert_test.3763438469
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_auto_blk_key_output.2357162365
Short name T68
Test name
Test status
Simulation time 3668724721 ps
CPU time 15.12 seconds
Started Aug 28 08:01:20 PM UTC 24
Finished Aug 28 08:01:37 PM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2357162365 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_auto_blk_key_output.2357162365
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst.2088079904
Short name T63
Test name
Test status
Simulation time 2241742921 ps
CPU time 4.62 seconds
Started Aug 28 08:01:17 PM UTC 24
Finished Aug 28 08:01:23 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2088079904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst.2088079904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1300727558
Short name T101
Test name
Test status
Simulation time 2276151853 ps
CPU time 9.7 seconds
Started Aug 28 08:01:17 PM UTC 24
Finished Aug 28 08:01:29 PM UTC 24
Peak memory 209868 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1300727558 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_ec_rst_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_r
egression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond.1300727558
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_ec_rst_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.959653577
Short name T102
Test name
Test status
Simulation time 26095495215 ps
CPU time 40.96 seconds
Started Aug 28 08:01:20 PM UTC 24
Finished Aug 28 08:02:03 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=959653577 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_combo_detect_with_pre_cond.959653577
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ec_pwr_on_rst.3567025182
Short name T82
Test name
Test status
Simulation time 2584020026 ps
CPU time 3.04 seconds
Started Aug 28 08:01:18 PM UTC 24
Finished Aug 28 08:01:22 PM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3567025182 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ec_pwr_on_rst.3567025182
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_flash_wr_prot_out.2329472209
Short name T98
Test name
Test status
Simulation time 2629466746 ps
CPU time 2.7 seconds
Started Aug 28 08:01:18 PM UTC 24
Finished Aug 28 08:01:22 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2329472209 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_flash_wr_prot_out.2329472209
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_in_out_inverted.2097813187
Short name T88
Test name
Test status
Simulation time 2478145070 ps
CPU time 3.09 seconds
Started Aug 28 08:01:17 PM UTC 24
Finished Aug 28 08:01:22 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2097813187 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_in_out_inverted.2097813187
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_pin_access_test.210152358
Short name T338
Test name
Test status
Simulation time 2245346259 ps
CPU time 10.6 seconds
Started Aug 28 08:01:17 PM UTC 24
Finished Aug 28 08:01:29 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=210152358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_pin_access_test.210152358
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_sec_cm.1697889865
Short name T195
Test name
Test status
Simulation time 42053168289 ps
CPU time 45.48 seconds
Started Aug 28 08:01:20 PM UTC 24
Finished Aug 28 08:02:07 PM UTC 24
Peak memory 240280 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_sec_cm_fi +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_REL
NOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1697889865 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_sec_cm.1697889865
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_sec_cm/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_smoke.250739212
Short name T334
Test name
Test status
Simulation time 2113705657 ps
CPU time 7.41 seconds
Started Aug 28 08:01:15 PM UTC 24
Finished Aug 28 08:01:24 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=250739212 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_smoke.250739212
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all.2250524634
Short name T193
Test name
Test status
Simulation time 14662044035 ps
CPU time 31.79 seconds
Started Aug 28 08:01:20 PM UTC 24
Finished Aug 28 08:01:54 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2250524634 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_stress_all.2250524634
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_stress_all_with_rand_reset.3141195118
Short name T65
Test name
Test status
Simulation time 8312867099 ps
CPU time 4.8 seconds
Started Aug 28 08:01:20 PM UTC 24
Finished Aug 28 08:01:26 PM UTC 24
Peak memory 210400 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3141195118 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 4.sysrst_ctrl_stress_all_with_rand_reset.3141195118
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_ultra_low_pwr.789622561
Short name T75
Test name
Test status
Simulation time 8318019301 ps
CPU time 10.89 seconds
Started Aug 28 08:01:20 PM UTC 24
Finished Aug 28 08:01:32 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=789622561 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 4.sysrst_ctrl_ultra_low_pwr.789622561
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/4.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.3768889884
Short name T670
Test name
Test status
Simulation time 2011567903 ps
CPU time 8.3 seconds
Started Aug 28 08:07:27 PM UTC 24
Finished Aug 28 08:07:37 PM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3768889884 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_alert_test.3768889884
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_auto_blk_key_output.4067709417
Short name T657
Test name
Test status
Simulation time 3474577637 ps
CPU time 4.16 seconds
Started Aug 28 08:07:23 PM UTC 24
Finished Aug 28 08:07:29 PM UTC 24
Peak memory 210332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067709417 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_auto_blk_key_output.4067709417
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.2951283786
Short name T414
Test name
Test status
Simulation time 213334698298 ps
CPU time 94.91 seconds
Started Aug 28 08:07:24 PM UTC 24
Finished Aug 28 08:09:01 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2951283786 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect.2951283786
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect_with_pre_cond.1998148339
Short name T752
Test name
Test status
Simulation time 34602717188 ps
CPU time 79.64 seconds
Started Aug 28 08:07:25 PM UTC 24
Finished Aug 28 08:08:47 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1998148339 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_combo_detect_with_pre_cond.1998148339
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.1583740619
Short name T668
Test name
Test status
Simulation time 2576794233 ps
CPU time 12.73 seconds
Started Aug 28 08:07:22 PM UTC 24
Finished Aug 28 08:07:36 PM UTC 24
Peak memory 209864 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1583740619 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ec_pwr_on_rst.1583740619
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_edge_detect.1830422428
Short name T203
Test name
Test status
Simulation time 4247083502 ps
CPU time 5.99 seconds
Started Aug 28 08:07:24 PM UTC 24
Finished Aug 28 08:07:31 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1830422428 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_edge_detect.1830422428
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.3128403206
Short name T664
Test name
Test status
Simulation time 2614833957 ps
CPU time 11.47 seconds
Started Aug 28 08:07:21 PM UTC 24
Finished Aug 28 08:07:33 PM UTC 24
Peak memory 209956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3128403206 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_flash_wr_prot_out.3128403206
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.1167123245
Short name T656
Test name
Test status
Simulation time 2471774699 ps
CPU time 7.05 seconds
Started Aug 28 08:07:19 PM UTC 24
Finished Aug 28 08:07:28 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1167123245 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_in_out_inverted.1167123245
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_access_test.1937145924
Short name T663
Test name
Test status
Simulation time 2263454395 ps
CPU time 10.77 seconds
Started Aug 28 08:07:20 PM UTC 24
Finished Aug 28 08:07:32 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1937145924 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_access_test.1937145924
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_pin_override_test.2644380267
Short name T658
Test name
Test status
Simulation time 2514955867 ps
CPU time 7 seconds
Started Aug 28 08:07:20 PM UTC 24
Finished Aug 28 08:07:29 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2644380267 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_pin_override_test.2644380267
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_smoke.4280602032
Short name T654
Test name
Test status
Simulation time 2112576136 ps
CPU time 4.63 seconds
Started Aug 28 08:07:19 PM UTC 24
Finished Aug 28 08:07:25 PM UTC 24
Peak memory 210136 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4280602032 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_smoke.4280602032
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.2491336841
Short name T671
Test name
Test status
Simulation time 9179354907 ps
CPU time 9.94 seconds
Started Aug 28 08:07:26 PM UTC 24
Finished Aug 28 08:07:37 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2491336841 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_stress_all.2491336841
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all_with_rand_reset.430095404
Short name T666
Test name
Test status
Simulation time 7808232095 ps
CPU time 7.51 seconds
Started Aug 28 08:07:25 PM UTC 24
Finished Aug 28 08:07:34 PM UTC 24
Peak memory 210084 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=430095404 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 40.sysrst_ctrl_stress_all_with_rand_reset.430095404
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ultra_low_pwr.2890504250
Short name T660
Test name
Test status
Simulation time 4826211862 ps
CPU time 5.73 seconds
Started Aug 28 08:07:24 PM UTC 24
Finished Aug 28 08:07:31 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2890504250 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 40.sysrst_ctrl_ultra_low_pwr.2890504250
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/40.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_alert_test.956957015
Short name T683
Test name
Test status
Simulation time 2012382406 ps
CPU time 9.55 seconds
Started Aug 28 08:07:34 PM UTC 24
Finished Aug 28 08:07:45 PM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=956957015 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_alert_test.956957015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_auto_blk_key_output.2800835321
Short name T674
Test name
Test status
Simulation time 3380940499 ps
CPU time 8.37 seconds
Started Aug 28 08:07:32 PM UTC 24
Finished Aug 28 08:07:41 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2800835321 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_auto_blk_key_output.2800835321
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.3436013914
Short name T311
Test name
Test status
Simulation time 70536910829 ps
CPU time 162.87 seconds
Started Aug 28 08:07:33 PM UTC 24
Finished Aug 28 08:10:18 PM UTC 24
Peak memory 210236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3436013914 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect.3436013914
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2365249324
Short name T236
Test name
Test status
Simulation time 35046813670 ps
CPU time 35.92 seconds
Started Aug 28 08:07:33 PM UTC 24
Finished Aug 28 08:08:10 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2365249324 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_combo_detect_with_pre_cond.2365249324
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ec_pwr_on_rst.1977229966
Short name T667
Test name
Test status
Simulation time 3953661764 ps
CPU time 3.01 seconds
Started Aug 28 08:07:30 PM UTC 24
Finished Aug 28 08:07:34 PM UTC 24
Peak memory 209748 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1977229966 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ec_pwr_on_rst.1977229966
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_edge_detect.914545155
Short name T669
Test name
Test status
Simulation time 3306495487 ps
CPU time 2.58 seconds
Started Aug 28 08:07:33 PM UTC 24
Finished Aug 28 08:07:37 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=914545155 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_edge_detect.914545155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_flash_wr_prot_out.1422216929
Short name T678
Test name
Test status
Simulation time 2610123332 ps
CPU time 12.06 seconds
Started Aug 28 08:07:30 PM UTC 24
Finished Aug 28 08:07:43 PM UTC 24
Peak memory 209836 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1422216929 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_flash_wr_prot_out.1422216929
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.3638673175
Short name T662
Test name
Test status
Simulation time 2501855319 ps
CPU time 2.43 seconds
Started Aug 28 08:07:28 PM UTC 24
Finished Aug 28 08:07:32 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3638673175 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_in_out_inverted.3638673175
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_access_test.1557565757
Short name T672
Test name
Test status
Simulation time 2098693930 ps
CPU time 9.05 seconds
Started Aug 28 08:07:29 PM UTC 24
Finished Aug 28 08:07:40 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1557565757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_access_test.1557565757
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_pin_override_test.2567478424
Short name T675
Test name
Test status
Simulation time 2511168763 ps
CPU time 11.04 seconds
Started Aug 28 08:07:30 PM UTC 24
Finished Aug 28 08:07:42 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2567478424 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_pin_override_test.2567478424
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_smoke.4150876047
Short name T661
Test name
Test status
Simulation time 2122388456 ps
CPU time 2.23 seconds
Started Aug 28 08:07:28 PM UTC 24
Finished Aug 28 08:07:32 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4150876047 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_smoke.4150876047
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all.3720211134
Short name T204
Test name
Test status
Simulation time 260338709857 ps
CPU time 456.52 seconds
Started Aug 28 08:07:34 PM UTC 24
Finished Aug 28 08:15:16 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3720211134 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_stress_all.3720211134
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_stress_all_with_rand_reset.444544056
Short name T682
Test name
Test status
Simulation time 10095237756 ps
CPU time 10.4 seconds
Started Aug 28 08:07:33 PM UTC 24
Finished Aug 28 08:07:45 PM UTC 24
Peak memory 220456 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=444544056 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 41.sysrst_ctrl_stress_all_with_rand_reset.444544056
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_ultra_low_pwr.3057635012
Short name T112
Test name
Test status
Simulation time 5266584160 ps
CPU time 4.6 seconds
Started Aug 28 08:07:32 PM UTC 24
Finished Aug 28 08:07:38 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3057635012 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 41.sysrst_ctrl_ultra_low_pwr.3057635012
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/41.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_alert_test.1005597226
Short name T687
Test name
Test status
Simulation time 2026345690 ps
CPU time 5.18 seconds
Started Aug 28 08:07:43 PM UTC 24
Finished Aug 28 08:07:50 PM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1005597226 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_alert_test.1005597226
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_auto_blk_key_output.2589600997
Short name T690
Test name
Test status
Simulation time 3479073797 ps
CPU time 10.49 seconds
Started Aug 28 08:07:39 PM UTC 24
Finished Aug 28 08:07:51 PM UTC 24
Peak memory 209920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589600997 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_auto_blk_key_output.2589600997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.1320693974
Short name T759
Test name
Test status
Simulation time 86637151470 ps
CPU time 91.28 seconds
Started Aug 28 08:07:39 PM UTC 24
Finished Aug 28 08:09:12 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1320693974 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect.1320693974
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect_with_pre_cond.679915358
Short name T395
Test name
Test status
Simulation time 58952433530 ps
CPU time 36.73 seconds
Started Aug 28 08:07:42 PM UTC 24
Finished Aug 28 08:08:20 PM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=679915358 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_combo_detect_with_pre_cond.679915358
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ec_pwr_on_rst.3971619997
Short name T676
Test name
Test status
Simulation time 2981602190 ps
CPU time 3.77 seconds
Started Aug 28 08:07:38 PM UTC 24
Finished Aug 28 08:07:42 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3971619997 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ec_pwr_on_rst.3971619997
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_edge_detect.3575358627
Short name T263
Test name
Test status
Simulation time 3524334454 ps
CPU time 15.18 seconds
Started Aug 28 08:07:41 PM UTC 24
Finished Aug 28 08:07:58 PM UTC 24
Peak memory 210072 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3575358627 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_edge_detect.3575358627
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_flash_wr_prot_out.2403111933
Short name T677
Test name
Test status
Simulation time 2617893323 ps
CPU time 5.14 seconds
Started Aug 28 08:07:37 PM UTC 24
Finished Aug 28 08:07:43 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2403111933 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_flash_wr_prot_out.2403111933
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_in_out_inverted.4067624843
Short name T684
Test name
Test status
Simulation time 2469824303 ps
CPU time 10.74 seconds
Started Aug 28 08:07:34 PM UTC 24
Finished Aug 28 08:07:46 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4067624843 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_in_out_inverted.4067624843
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_access_test.1936197353
Short name T673
Test name
Test status
Simulation time 2251749134 ps
CPU time 4.21 seconds
Started Aug 28 08:07:35 PM UTC 24
Finished Aug 28 08:07:41 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1936197353 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_access_test.1936197353
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_pin_override_test.875609904
Short name T679
Test name
Test status
Simulation time 2517601729 ps
CPU time 6.21 seconds
Started Aug 28 08:07:37 PM UTC 24
Finished Aug 28 08:07:44 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=875609904 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_pin_override_test.875609904
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_smoke.3932606320
Short name T681
Test name
Test status
Simulation time 2112933004 ps
CPU time 8.95 seconds
Started Aug 28 08:07:34 PM UTC 24
Finished Aug 28 08:07:44 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3932606320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_smoke.3932606320
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_ultra_low_pwr.3873935703
Short name T689
Test name
Test status
Simulation time 4609936438 ps
CPU time 10.29 seconds
Started Aug 28 08:07:39 PM UTC 24
Finished Aug 28 08:07:50 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3873935703 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 42.sysrst_ctrl_ultra_low_pwr.3873935703
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_alert_test.772106607
Short name T694
Test name
Test status
Simulation time 2044919107 ps
CPU time 2.72 seconds
Started Aug 28 08:07:51 PM UTC 24
Finished Aug 28 08:07:55 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772106607 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_alert_test.772106607
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_auto_blk_key_output.1780194121
Short name T701
Test name
Test status
Simulation time 3604761623 ps
CPU time 11.32 seconds
Started Aug 28 08:07:46 PM UTC 24
Finished Aug 28 08:07:58 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780194121 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_auto_blk_key_output.1780194121
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.2481762944
Short name T138
Test name
Test status
Simulation time 70411879760 ps
CPU time 28.56 seconds
Started Aug 28 08:07:47 PM UTC 24
Finished Aug 28 08:08:17 PM UTC 24
Peak memory 210164 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2481762944 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_combo_detect.2481762944
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ec_pwr_on_rst.1072940771
Short name T697
Test name
Test status
Simulation time 2509925752 ps
CPU time 10.18 seconds
Started Aug 28 08:07:46 PM UTC 24
Finished Aug 28 08:07:57 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1072940771 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ec_pwr_on_rst.1072940771
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.2258558515
Short name T698
Test name
Test status
Simulation time 3364873100 ps
CPU time 9.66 seconds
Started Aug 28 08:07:47 PM UTC 24
Finished Aug 28 08:07:58 PM UTC 24
Peak memory 209936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2258558515 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_edge_detect.2258558515
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_flash_wr_prot_out.772144301
Short name T693
Test name
Test status
Simulation time 2620545188 ps
CPU time 7.12 seconds
Started Aug 28 08:07:45 PM UTC 24
Finished Aug 28 08:07:53 PM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=772144301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_flash_wr_prot_out.772144301
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_in_out_inverted.3538083687
Short name T688
Test name
Test status
Simulation time 2481987487 ps
CPU time 4.5 seconds
Started Aug 28 08:07:44 PM UTC 24
Finished Aug 28 08:07:50 PM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3538083687 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_in_out_inverted.3538083687
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_access_test.259402085
Short name T686
Test name
Test status
Simulation time 2045882274 ps
CPU time 3.62 seconds
Started Aug 28 08:07:44 PM UTC 24
Finished Aug 28 08:07:49 PM UTC 24
Peak memory 209744 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=259402085 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sys
rst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_access_test.259402085
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_pin_override_test.336094763
Short name T691
Test name
Test status
Simulation time 2516813908 ps
CPU time 4.79 seconds
Started Aug 28 08:07:45 PM UTC 24
Finished Aug 28 08:07:51 PM UTC 24
Peak memory 209844 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=336094763 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_pin_override_test.336094763
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_smoke.205180603
Short name T692
Test name
Test status
Simulation time 2111672588 ps
CPU time 7.79 seconds
Started Aug 28 08:07:43 PM UTC 24
Finished Aug 28 08:07:52 PM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=205180603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_smoke.205180603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all.2936958628
Short name T240
Test name
Test status
Simulation time 11648405338 ps
CPU time 23.72 seconds
Started Aug 28 08:07:50 PM UTC 24
Finished Aug 28 08:08:15 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2936958628 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_stress_all.2936958628
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.1741984392
Short name T709
Test name
Test status
Simulation time 5943852270 ps
CPU time 15.82 seconds
Started Aug 28 08:07:50 PM UTC 24
Finished Aug 28 08:08:07 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1741984392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 43.sysrst_ctrl_stress_all_with_rand_reset.1741984392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_ultra_low_pwr.1390013006
Short name T441
Test name
Test status
Simulation time 1686635066801 ps
CPU time 115.9 seconds
Started Aug 28 08:07:46 PM UTC 24
Finished Aug 28 08:09:44 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1390013006 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 43.sysrst_ctrl_ultra_low_pwr.1390013006
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.1442002518
Short name T703
Test name
Test status
Simulation time 2028006361 ps
CPU time 3.65 seconds
Started Aug 28 08:07:58 PM UTC 24
Finished Aug 28 08:08:03 PM UTC 24
Peak memory 209812 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1442002518 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_alert_test.1442002518
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.3835138603
Short name T707
Test name
Test status
Simulation time 3267011843 ps
CPU time 8.6 seconds
Started Aug 28 08:07:56 PM UTC 24
Finished Aug 28 08:08:05 PM UTC 24
Peak memory 210332 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3835138603 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_auto_blk_key_output.3835138603
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect.3152460214
Short name T756
Test name
Test status
Simulation time 88896272571 ps
CPU time 55.72 seconds
Started Aug 28 08:07:57 PM UTC 24
Finished Aug 28 08:08:54 PM UTC 24
Peak memory 210236 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3152460214 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect.3152460214
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_combo_detect_with_pre_cond.791500842
Short name T721
Test name
Test status
Simulation time 21850846309 ps
CPU time 26.35 seconds
Started Aug 28 08:07:57 PM UTC 24
Finished Aug 28 08:08:25 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=791500842 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_combo_detect_with_pre_cond.791500842
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.3631805255
Short name T234
Test name
Test status
Simulation time 3067730154 ps
CPU time 13.51 seconds
Started Aug 28 08:07:54 PM UTC 24
Finished Aug 28 08:08:08 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3631805255 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ec_pwr_on_rst.3631805255
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_flash_wr_prot_out.3343447091
Short name T700
Test name
Test status
Simulation time 2632009275 ps
CPU time 3.62 seconds
Started Aug 28 08:07:54 PM UTC 24
Finished Aug 28 08:07:58 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3343447091 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_flash_wr_prot_out.3343447091
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.2089954416
Short name T702
Test name
Test status
Simulation time 2472393453 ps
CPU time 6.72 seconds
Started Aug 28 08:07:51 PM UTC 24
Finished Aug 28 08:07:59 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2089954416 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_in_out_inverted.2089954416
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.2348406303
Short name T696
Test name
Test status
Simulation time 2269636226 ps
CPU time 3.43 seconds
Started Aug 28 08:07:51 PM UTC 24
Finished Aug 28 08:07:56 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2348406303 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_access_test.2348406303
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3731231980
Short name T699
Test name
Test status
Simulation time 2517309004 ps
CPU time 4.52 seconds
Started Aug 28 08:07:52 PM UTC 24
Finished Aug 28 08:07:58 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3731231980 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_pin_override_test.3731231980
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_smoke.415092707
Short name T695
Test name
Test status
Simulation time 2138396463 ps
CPU time 3.01 seconds
Started Aug 28 08:07:51 PM UTC 24
Finished Aug 28 08:07:55 PM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=415092707 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_smoke.415092707
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all.537576938
Short name T714
Test name
Test status
Simulation time 12045639604 ps
CPU time 20.33 seconds
Started Aug 28 08:07:58 PM UTC 24
Finished Aug 28 08:08:20 PM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=537576938 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_stress_all.537576938
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.667598426
Short name T712
Test name
Test status
Simulation time 3953098259 ps
CPU time 19.13 seconds
Started Aug 28 08:07:58 PM UTC 24
Finished Aug 28 08:08:18 PM UTC 24
Peak memory 210340 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=667598426 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 44.sysrst_ctrl_stress_all_with_rand_reset.667598426
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.4138635306
Short name T761
Test name
Test status
Simulation time 823077481015 ps
CPU time 85 seconds
Started Aug 28 08:07:56 PM UTC 24
Finished Aug 28 08:09:22 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4138635306 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 44.sysrst_ctrl_ultra_low_pwr.4138635306
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/44.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2306578987
Short name T713
Test name
Test status
Simulation time 2017808847 ps
CPU time 9.78 seconds
Started Aug 28 08:08:08 PM UTC 24
Finished Aug 28 08:08:19 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2306578987 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_alert_test.2306578987
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.2081286058
Short name T715
Test name
Test status
Simulation time 3473478735 ps
CPU time 14.86 seconds
Started Aug 28 08:08:04 PM UTC 24
Finished Aug 28 08:08:20 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2081286058 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_auto_blk_key_output.2081286058
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.179733996
Short name T755
Test name
Test status
Simulation time 108346394448 ps
CPU time 44.78 seconds
Started Aug 28 08:08:05 PM UTC 24
Finished Aug 28 08:08:51 PM UTC 24
Peak memory 210176 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=179733996 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect.179733996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect_with_pre_cond.4186632863
Short name T372
Test name
Test status
Simulation time 37664668599 ps
CPU time 31.8 seconds
Started Aug 28 08:08:07 PM UTC 24
Finished Aug 28 08:08:40 PM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4186632863 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_combo_detect_with_pre_cond.4186632863
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3403517108
Short name T237
Test name
Test status
Simulation time 3009441945 ps
CPU time 7.57 seconds
Started Aug 28 08:08:04 PM UTC 24
Finished Aug 28 08:08:12 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3403517108 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ec_pwr_on_rst.3403517108
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.2075909516
Short name T239
Test name
Test status
Simulation time 3048088693 ps
CPU time 7.18 seconds
Started Aug 28 08:08:06 PM UTC 24
Finished Aug 28 08:08:14 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2075909516 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_edge_detect.2075909516
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.3958031720
Short name T705
Test name
Test status
Simulation time 2681106481 ps
CPU time 1.94 seconds
Started Aug 28 08:08:01 PM UTC 24
Finished Aug 28 08:08:03 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3958031720 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_flash_wr_prot_out.3958031720
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.3573204070
Short name T706
Test name
Test status
Simulation time 2490925901 ps
CPU time 3.86 seconds
Started Aug 28 08:07:59 PM UTC 24
Finished Aug 28 08:08:04 PM UTC 24
Peak memory 209856 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3573204070 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_in_out_inverted.3573204070
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.2012585678
Short name T708
Test name
Test status
Simulation time 2223680383 ps
CPU time 5.61 seconds
Started Aug 28 08:07:59 PM UTC 24
Finished Aug 28 08:08:06 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2012585678 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_access_test.2012585678
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.1201576049
Short name T704
Test name
Test status
Simulation time 2761235766 ps
CPU time 1.77 seconds
Started Aug 28 08:08:01 PM UTC 24
Finished Aug 28 08:08:03 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1201576049 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_pin_override_test.1201576049
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.2589003081
Short name T235
Test name
Test status
Simulation time 2109848302 ps
CPU time 8.95 seconds
Started Aug 28 08:07:59 PM UTC 24
Finished Aug 28 08:08:09 PM UTC 24
Peak memory 209580 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2589003081 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_smoke.2589003081
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.31692348
Short name T299
Test name
Test status
Simulation time 77514814554 ps
CPU time 91.65 seconds
Started Aug 28 08:08:08 PM UTC 24
Finished Aug 28 08:09:42 PM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=31692348 -assert nopostproc +UVM_TESTNA
ME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/
os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_stress_all.31692348
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.1508738112
Short name T737
Test name
Test status
Simulation time 6884639523 ps
CPU time 26.44 seconds
Started Aug 28 08:08:08 PM UTC 24
Finished Aug 28 08:08:36 PM UTC 24
Peak memory 220548 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1508738112 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 45.sysrst_ctrl_stress_all_with_rand_reset.1508738112
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.1571133900
Short name T440
Test name
Test status
Simulation time 1663385467338 ps
CPU time 39.69 seconds
Started Aug 28 08:08:05 PM UTC 24
Finished Aug 28 08:08:46 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1571133900 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 45.sysrst_ctrl_ultra_low_pwr.1571133900
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/45.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.403515346
Short name T719
Test name
Test status
Simulation time 2033075510 ps
CPU time 2.69 seconds
Started Aug 28 08:08:20 PM UTC 24
Finished Aug 28 08:08:24 PM UTC 24
Peak memory 209700 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=403515346 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_alert_test.403515346
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.2493083299
Short name T724
Test name
Test status
Simulation time 3688184520 ps
CPU time 9.33 seconds
Started Aug 28 08:08:15 PM UTC 24
Finished Aug 28 08:08:25 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2493083299 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_auto_blk_key_output.2493083299
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect.1324782322
Short name T289
Test name
Test status
Simulation time 70734086892 ps
CPU time 66.62 seconds
Started Aug 28 08:08:17 PM UTC 24
Finished Aug 28 08:09:25 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1324782322 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect.1324782322
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_combo_detect_with_pre_cond.1478929392
Short name T282
Test name
Test status
Simulation time 35459669762 ps
CPU time 155.48 seconds
Started Aug 28 08:08:18 PM UTC 24
Finished Aug 28 08:10:56 PM UTC 24
Peak memory 210300 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1478929392 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_combo_detect_with_pre_cond.1478929392
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.55347090
Short name T711
Test name
Test status
Simulation time 3349113440 ps
CPU time 3.36 seconds
Started Aug 28 08:08:14 PM UTC 24
Finished Aug 28 08:08:18 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=55347090 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ec_pwr_on_rst.55347090
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.484545044
Short name T271
Test name
Test status
Simulation time 5125819385 ps
CPU time 5.14 seconds
Started Aug 28 08:08:18 PM UTC 24
Finished Aug 28 08:08:24 PM UTC 24
Peak memory 209852 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=484545044 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_edge_detect.484545044
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.2354183925
Short name T720
Test name
Test status
Simulation time 2606939696 ps
CPU time 9.68 seconds
Started Aug 28 08:08:14 PM UTC 24
Finished Aug 28 08:08:24 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2354183925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_flash_wr_prot_out.2354183925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.1961005533
Short name T710
Test name
Test status
Simulation time 2466063561 ps
CPU time 6.86 seconds
Started Aug 28 08:08:09 PM UTC 24
Finished Aug 28 08:08:17 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1961005533 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_in_out_inverted.1961005533
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3559276711
Short name T718
Test name
Test status
Simulation time 2020019638 ps
CPU time 9.82 seconds
Started Aug 28 08:08:10 PM UTC 24
Finished Aug 28 08:08:21 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3559276711 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_access_test.3559276711
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.636730877
Short name T241
Test name
Test status
Simulation time 2533041897 ps
CPU time 3.58 seconds
Started Aug 28 08:08:12 PM UTC 24
Finished Aug 28 08:08:16 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=636730877 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_pin_override_test.636730877
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.889361158
Short name T238
Test name
Test status
Simulation time 2121901993 ps
CPU time 3.49 seconds
Started Aug 28 08:08:08 PM UTC 24
Finished Aug 28 08:08:13 PM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=889361158 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_smoke.889361158
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.3047062672
Short name T717
Test name
Test status
Simulation time 12895663087 ps
CPU time 33.66 seconds
Started Aug 28 08:08:19 PM UTC 24
Finished Aug 28 08:08:54 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3047062672 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_stress_all.3047062672
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ultra_low_pwr.1528815195
Short name T716
Test name
Test status
Simulation time 6015827541 ps
CPU time 3.05 seconds
Started Aug 28 08:08:16 PM UTC 24
Finished Aug 28 08:08:20 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1528815195 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 46.sysrst_ctrl_ultra_low_pwr.1528815195
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/46.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.3478382186
Short name T727
Test name
Test status
Simulation time 2035822553 ps
CPU time 1.96 seconds
Started Aug 28 08:08:25 PM UTC 24
Finished Aug 28 08:08:28 PM UTC 24
Peak memory 208244 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3478382186 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_alert_test.3478382186
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1009302241
Short name T740
Test name
Test status
Simulation time 3236370934 ps
CPU time 14.27 seconds
Started Aug 28 08:08:23 PM UTC 24
Finished Aug 28 08:08:38 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009302241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_auto_blk_key_output.1009302241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3483535788
Short name T748
Test name
Test status
Simulation time 5401928128 ps
CPU time 18.48 seconds
Started Aug 28 08:08:23 PM UTC 24
Finished Aug 28 08:08:42 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3483535788 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ec_pwr_on_rst.3483535788
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.4236507741
Short name T274
Test name
Test status
Simulation time 4384505051 ps
CPU time 3.81 seconds
Started Aug 28 08:08:25 PM UTC 24
Finished Aug 28 08:08:30 PM UTC 24
Peak memory 210192 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4236507741 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_edge_detect.4236507741
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.2949135336
Short name T725
Test name
Test status
Simulation time 2651988280 ps
CPU time 1.51 seconds
Started Aug 28 08:08:23 PM UTC 24
Finished Aug 28 08:08:25 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2949135336 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_flash_wr_prot_out.2949135336
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.11863641
Short name T723
Test name
Test status
Simulation time 2473835343 ps
CPU time 3.65 seconds
Started Aug 28 08:08:20 PM UTC 24
Finished Aug 28 08:08:25 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=11863641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_in_out_inverted.11863641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.1849654231
Short name T729
Test name
Test status
Simulation time 2264018541 ps
CPU time 10.45 seconds
Started Aug 28 08:08:20 PM UTC 24
Finished Aug 28 08:08:32 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1849654231 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_access_test.1849654231
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.2771518493
Short name T722
Test name
Test status
Simulation time 2559182452 ps
CPU time 1.99 seconds
Started Aug 28 08:08:22 PM UTC 24
Finished Aug 28 08:08:25 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2771518493 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_pin_override_test.2771518493
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.3354746273
Short name T728
Test name
Test status
Simulation time 2114344474 ps
CPU time 10.31 seconds
Started Aug 28 08:08:20 PM UTC 24
Finished Aug 28 08:08:32 PM UTC 24
Peak memory 209804 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3354746273 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_smoke.3354746273
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all.380915748
Short name T443
Test name
Test status
Simulation time 12598693664 ps
CPU time 17.8 seconds
Started Aug 28 08:08:25 PM UTC 24
Finished Aug 28 08:08:44 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=380915748 -assert nopostproc +UVM_TESTN
AME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch
/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_stress_all.380915748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.3297500159
Short name T738
Test name
Test status
Simulation time 2104028500 ps
CPU time 9.9 seconds
Started Aug 28 08:08:25 PM UTC 24
Finished Aug 28 08:08:36 PM UTC 24
Peak memory 210272 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3297500159 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 47.sysrst_ctrl_stress_all_with_rand_reset.3297500159
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1417734246
Short name T726
Test name
Test status
Simulation time 2838948870 ps
CPU time 1.35 seconds
Started Aug 28 08:08:24 PM UTC 24
Finished Aug 28 08:08:26 PM UTC 24
Peak memory 208240 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1417734246 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 47.sysrst_ctrl_ultra_low_pwr.1417734246
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/47.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.1518378200
Short name T739
Test name
Test status
Simulation time 2032474218 ps
CPU time 2.66 seconds
Started Aug 28 08:08:34 PM UTC 24
Finished Aug 28 08:08:38 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1518378200 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_alert_test.1518378200
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.3578633241
Short name T732
Test name
Test status
Simulation time 3582351911 ps
CPU time 3.15 seconds
Started Aug 28 08:08:29 PM UTC 24
Finished Aug 28 08:08:33 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3578633241 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_auto_blk_key_output.3578633241
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_combo_detect.1745982978
Short name T287
Test name
Test status
Simulation time 31853233285 ps
CPU time 29.19 seconds
Started Aug 28 08:08:33 PM UTC 24
Finished Aug 28 08:09:04 PM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1745982978 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_combo_detect.1745982978
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.4021762244
Short name T730
Test name
Test status
Simulation time 2730273242 ps
CPU time 2.45 seconds
Started Aug 28 08:08:29 PM UTC 24
Finished Aug 28 08:08:32 PM UTC 24
Peak memory 209940 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4021762244 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ec_pwr_on_rst.4021762244
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.80700086
Short name T264
Test name
Test status
Simulation time 2888070839 ps
CPU time 7.82 seconds
Started Aug 28 08:08:33 PM UTC 24
Finished Aug 28 08:08:42 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=80700086 -assert nopostproc +UVM_TES
TNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scra
tch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_edge_detect.80700086
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.2648428582
Short name T731
Test name
Test status
Simulation time 2632963156 ps
CPU time 4.03 seconds
Started Aug 28 08:08:28 PM UTC 24
Finished Aug 28 08:08:33 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2648428582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_flash_wr_prot_out.2648428582
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3215329896
Short name T744
Test name
Test status
Simulation time 2442545854 ps
CPU time 11.8 seconds
Started Aug 28 08:08:27 PM UTC 24
Finished Aug 28 08:08:39 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3215329896 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_in_out_inverted.3215329896
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.4105780675
Short name T733
Test name
Test status
Simulation time 2246182899 ps
CPU time 5.74 seconds
Started Aug 28 08:08:27 PM UTC 24
Finished Aug 28 08:08:33 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4105780675 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_access_test.4105780675
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.2242594819
Short name T734
Test name
Test status
Simulation time 2516399330 ps
CPU time 5.12 seconds
Started Aug 28 08:08:28 PM UTC 24
Finished Aug 28 08:08:34 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2242594819 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_pin_override_test.2242594819
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3129212991
Short name T735
Test name
Test status
Simulation time 2111824291 ps
CPU time 6.46 seconds
Started Aug 28 08:08:26 PM UTC 24
Finished Aug 28 08:08:34 PM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3129212991 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_smoke.3129212991
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.4260691770
Short name T754
Test name
Test status
Simulation time 11134143991 ps
CPU time 14.83 seconds
Started Aug 28 08:08:34 PM UTC 24
Finished Aug 28 08:08:50 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4260691770 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_stress_all.4260691770
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.584941444
Short name T736
Test name
Test status
Simulation time 7253063977 ps
CPU time 3.66 seconds
Started Aug 28 08:08:31 PM UTC 24
Finished Aug 28 08:08:36 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=584941444 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 48.sysrst_ctrl_ultra_low_pwr.584941444
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.200598765
Short name T750
Test name
Test status
Simulation time 2043621577 ps
CPU time 2.82 seconds
Started Aug 28 08:08:43 PM UTC 24
Finished Aug 28 08:08:46 PM UTC 24
Peak memory 209884 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=200598765 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_alert_test.200598765
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.506496925
Short name T758
Test name
Test status
Simulation time 3723050960 ps
CPU time 16.85 seconds
Started Aug 28 08:08:38 PM UTC 24
Finished Aug 28 08:08:56 PM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=506496925 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_
08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_auto_blk_key_output.506496925
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.2979960435
Short name T141
Test name
Test status
Simulation time 101488196856 ps
CPU time 357.73 seconds
Started Aug 28 08:08:39 PM UTC 24
Finished Aug 28 08:14:41 PM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2979960435 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_combo_detect.2979960435
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.2449790412
Short name T751
Test name
Test status
Simulation time 3744295490 ps
CPU time 8.56 seconds
Started Aug 28 08:08:37 PM UTC 24
Finished Aug 28 08:08:46 PM UTC 24
Peak memory 210196 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2449790412 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ec_pwr_on_rst.2449790412
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.3252134910
Short name T747
Test name
Test status
Simulation time 3238817880 ps
CPU time 2.05 seconds
Started Aug 28 08:08:39 PM UTC 24
Finished Aug 28 08:08:42 PM UTC 24
Peak memory 209936 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3252134910 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_edge_detect.3252134910
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.3782809754
Short name T746
Test name
Test status
Simulation time 2635782413 ps
CPU time 4.02 seconds
Started Aug 28 08:08:37 PM UTC 24
Finished Aug 28 08:08:42 PM UTC 24
Peak memory 209636 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3782809754 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_flash_wr_prot_out.3782809754
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.3496778890
Short name T743
Test name
Test status
Simulation time 2473161683 ps
CPU time 3.21 seconds
Started Aug 28 08:08:35 PM UTC 24
Finished Aug 28 08:08:39 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3496778890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_in_out_inverted.3496778890
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.2402566826
Short name T742
Test name
Test status
Simulation time 2089876589 ps
CPU time 2.77 seconds
Started Aug 28 08:08:35 PM UTC 24
Finished Aug 28 08:08:38 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2402566826 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_access_test.2402566826
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.1037349759
Short name T753
Test name
Test status
Simulation time 2510957929 ps
CPU time 12.33 seconds
Started Aug 28 08:08:37 PM UTC 24
Finished Aug 28 08:08:50 PM UTC 24
Peak memory 209616 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1037349759 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_pin_override_test.1037349759
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.2193423198
Short name T745
Test name
Test status
Simulation time 2115251345 ps
CPU time 5.96 seconds
Started Aug 28 08:08:35 PM UTC 24
Finished Aug 28 08:08:42 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2193423198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_smoke.2193423198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all.2440863906
Short name T741
Test name
Test status
Simulation time 17067985260 ps
CPU time 11.68 seconds
Started Aug 28 08:08:41 PM UTC 24
Finished Aug 28 08:08:54 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2440863906 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_stress_all.2440863906
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_stress_all_with_rand_reset.750891580
Short name T757
Test name
Test status
Simulation time 6291047965 ps
CPU time 14.18 seconds
Started Aug 28 08:08:40 PM UTC 24
Finished Aug 28 08:08:56 PM UTC 24
Peak memory 210012 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=750891580 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 49.sysrst_ctrl_stress_all_with_rand_reset.750891580
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ultra_low_pwr.948600911
Short name T749
Test name
Test status
Simulation time 3751707350 ps
CPU time 5.71 seconds
Started Aug 28 08:08:39 PM UTC 24
Finished Aug 28 08:08:46 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=948600911 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 49.sysrst_ctrl_ultra_low_pwr.948600911
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/49.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_alert_test.849080395
Short name T448
Test name
Test status
Simulation time 2017983326 ps
CPU time 6.96 seconds
Started Aug 28 08:01:24 PM UTC 24
Finished Aug 28 08:01:32 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=849080395 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_alert_test.849080395
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_auto_blk_key_output.1871595582
Short name T67
Test name
Test status
Simulation time 3162997305 ps
CPU time 11.27 seconds
Started Aug 28 08:01:23 PM UTC 24
Finished Aug 28 08:01:36 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1871595582 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_auto_blk_key_output.1871595582
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_ec_pwr_on_rst.737518140
Short name T179
Test name
Test status
Simulation time 2526986367 ps
CPU time 9.22 seconds
Started Aug 28 08:01:23 PM UTC 24
Finished Aug 28 08:01:34 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=737518140 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_ec_pwr_on_rst.737518140
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_edge_detect.3051544529
Short name T50
Test name
Test status
Simulation time 4910008298 ps
CPU time 14.58 seconds
Started Aug 28 08:01:24 PM UTC 24
Finished Aug 28 08:01:39 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3051544529 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_edge_detect.3051544529
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_flash_wr_prot_out.664470401
Short name T262
Test name
Test status
Simulation time 2650393037 ps
CPU time 2.71 seconds
Started Aug 28 08:01:23 PM UTC 24
Finished Aug 28 08:01:27 PM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=664470401 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_flash_wr_prot_out.664470401
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_in_out_inverted.3146730103
Short name T89
Test name
Test status
Simulation time 2473515330 ps
CPU time 2.77 seconds
Started Aug 28 08:01:21 PM UTC 24
Finished Aug 28 08:01:25 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3146730103 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_in_out_inverted.3146730103
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_access_test.2584061802
Short name T259
Test name
Test status
Simulation time 2136767085 ps
CPU time 3.26 seconds
Started Aug 28 08:01:21 PM UTC 24
Finished Aug 28 08:01:25 PM UTC 24
Peak memory 210020 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2584061802 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_access_test.2584061802
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_pin_override_test.67787329
Short name T181
Test name
Test status
Simulation time 2511958591 ps
CPU time 10.12 seconds
Started Aug 28 08:01:23 PM UTC 24
Finished Aug 28 08:01:35 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=67787329 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_pin_override_test.67787329
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_smoke.1503111530
Short name T260
Test name
Test status
Simulation time 2117035916 ps
CPU time 4.45 seconds
Started Aug 28 08:01:21 PM UTC 24
Finished Aug 28 08:01:26 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1503111530 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_smoke.1503111530
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all.3751234151
Short name T47
Test name
Test status
Simulation time 11763822119 ps
CPU time 11.33 seconds
Started Aug 28 08:01:24 PM UTC 24
Finished Aug 28 08:01:36 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3751234151 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 5.sysrst_ctrl_stress_all.3751234151
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_stress_all_with_rand_reset.665597301
Short name T333
Test name
Test status
Simulation time 4240487887 ps
CPU time 4.97 seconds
Started Aug 28 08:01:24 PM UTC 24
Finished Aug 28 08:01:30 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=665597301 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /de
v/null -cm_name 5.sysrst_ctrl_stress_all_with_rand_reset.665597301
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/5.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/50.sysrst_ctrl_combo_detect_with_pre_cond.3672008798
Short name T412
Test name
Test status
Simulation time 39882227655 ps
CPU time 45.11 seconds
Started Aug 28 08:08:43 PM UTC 24
Finished Aug 28 08:09:29 PM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3672008798 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 50.sysrst_ctrl_combo_detect_with_pre_cond.3672008798
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/50.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/52.sysrst_ctrl_combo_detect_with_pre_cond.2680473688
Short name T307
Test name
Test status
Simulation time 124765649810 ps
CPU time 240.4 seconds
Started Aug 28 08:08:43 PM UTC 24
Finished Aug 28 08:12:46 PM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2680473688 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 52.sysrst_ctrl_combo_detect_with_pre_cond.2680473688
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/52.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/53.sysrst_ctrl_combo_detect_with_pre_cond.2996919150
Short name T772
Test name
Test status
Simulation time 28079237324 ps
CPU time 102.94 seconds
Started Aug 28 08:08:44 PM UTC 24
Finished Aug 28 08:10:29 PM UTC 24
Peak memory 210380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2996919150 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 53.sysrst_ctrl_combo_detect_with_pre_cond.2996919150
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/53.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/54.sysrst_ctrl_combo_detect_with_pre_cond.1785532320
Short name T770
Test name
Test status
Simulation time 69137062029 ps
CPU time 94.1 seconds
Started Aug 28 08:08:45 PM UTC 24
Finished Aug 28 08:10:21 PM UTC 24
Peak memory 210320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1785532320 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 54.sysrst_ctrl_combo_detect_with_pre_cond.1785532320
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/54.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/55.sysrst_ctrl_combo_detect_with_pre_cond.3988217300
Short name T279
Test name
Test status
Simulation time 67442482140 ps
CPU time 247.7 seconds
Started Aug 28 08:08:47 PM UTC 24
Finished Aug 28 08:12:58 PM UTC 24
Peak memory 210564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3988217300 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 55.sysrst_ctrl_combo_detect_with_pre_cond.3988217300
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/55.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.2895275807
Short name T773
Test name
Test status
Simulation time 52665148524 ps
CPU time 102.71 seconds
Started Aug 28 08:08:47 PM UTC 24
Finished Aug 28 08:10:32 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2895275807 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 58.sysrst_ctrl_combo_detect_with_pre_cond.2895275807
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/58.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/59.sysrst_ctrl_combo_detect_with_pre_cond.843960613
Short name T394
Test name
Test status
Simulation time 140193422209 ps
CPU time 529.85 seconds
Started Aug 28 08:08:47 PM UTC 24
Finished Aug 28 08:17:43 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=843960613 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 59.sysrst_ctrl_combo_detect_with_pre_cond.843960613
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/59.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_alert_test.645454155
Short name T451
Test name
Test status
Simulation time 2008805310 ps
CPU time 8.61 seconds
Started Aug 28 08:01:27 PM UTC 24
Finished Aug 28 08:01:36 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=645454155 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_alert_test.645454155
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_auto_blk_key_output.3552744482
Short name T66
Test name
Test status
Simulation time 3421992448 ps
CPU time 3.89 seconds
Started Aug 28 08:01:26 PM UTC 24
Finished Aug 28 08:01:31 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3552744482 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_auto_blk_key_output.3552744482
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ec_pwr_on_rst.3509818100
Short name T175
Test name
Test status
Simulation time 4020080181 ps
CPU time 5.89 seconds
Started Aug 28 08:01:26 PM UTC 24
Finished Aug 28 08:01:33 PM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3509818100 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ec_pwr_on_rst.3509818100
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_edge_detect.165840117
Short name T48
Test name
Test status
Simulation time 2966331453 ps
CPU time 3.43 seconds
Started Aug 28 08:01:26 PM UTC 24
Finished Aug 28 08:01:31 PM UTC 24
Peak memory 210200 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=165840117 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_edge_detect.165840117
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_flash_wr_prot_out.1009870154
Short name T177
Test name
Test status
Simulation time 2618042756 ps
CPU time 6.33 seconds
Started Aug 28 08:01:26 PM UTC 24
Finished Aug 28 08:01:34 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1009870154 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_flash_wr_prot_out.1009870154
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_in_out_inverted.1020038553
Short name T90
Test name
Test status
Simulation time 2469708481 ps
CPU time 4.64 seconds
Started Aug 28 08:01:24 PM UTC 24
Finished Aug 28 08:01:29 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1020038553 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_in_out_inverted.1020038553
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_pin_access_test.3234932167
Short name T176
Test name
Test status
Simulation time 2190427030 ps
CPU time 8.45 seconds
Started Aug 28 08:01:24 PM UTC 24
Finished Aug 28 08:01:33 PM UTC 24
Peak memory 209956 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3234932167 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_pin_access_test.3234932167
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_smoke.3834425045
Short name T261
Test name
Test status
Simulation time 2181327562 ps
CPU time 1.64 seconds
Started Aug 28 08:01:24 PM UTC 24
Finished Aug 28 08:01:26 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3834425045 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_smoke.3834425045
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all.1325790009
Short name T794
Test name
Test status
Simulation time 838530736146 ps
CPU time 3140.55 seconds
Started Aug 28 08:01:27 PM UTC 24
Finished Aug 28 08:54:18 PM UTC 24
Peak memory 212596 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1325790009 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_stress_all.1325790009
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_stress_all_with_rand_reset.4168790551
Short name T129
Test name
Test status
Simulation time 10370372515 ps
CPU time 15.48 seconds
Started Aug 28 08:01:26 PM UTC 24
Finished Aug 28 08:01:43 PM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4168790551 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 6.sysrst_ctrl_stress_all_with_rand_reset.4168790551
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_ultra_low_pwr.498204394
Short name T85
Test name
Test status
Simulation time 5035543651 ps
CPU time 2.96 seconds
Started Aug 28 08:01:26 PM UTC 24
Finished Aug 28 08:01:30 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=498204394 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 6.sysrst_ctrl_ultra_low_pwr.498204394
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/6.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/62.sysrst_ctrl_combo_detect_with_pre_cond.307476373
Short name T780
Test name
Test status
Simulation time 162081090413 ps
CPU time 149.18 seconds
Started Aug 28 08:08:51 PM UTC 24
Finished Aug 28 08:11:23 PM UTC 24
Peak memory 210572 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=307476373 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 62.sysrst_ctrl_combo_detect_with_pre_cond.307476373
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/62.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/63.sysrst_ctrl_combo_detect_with_pre_cond.2923675224
Short name T429
Test name
Test status
Simulation time 54599237505 ps
CPU time 163.29 seconds
Started Aug 28 08:08:53 PM UTC 24
Finished Aug 28 08:11:38 PM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2923675224 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 63.sysrst_ctrl_combo_detect_with_pre_cond.2923675224
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/63.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/64.sysrst_ctrl_combo_detect_with_pre_cond.709046377
Short name T766
Test name
Test status
Simulation time 34356335450 ps
CPU time 54.68 seconds
Started Aug 28 08:08:55 PM UTC 24
Finished Aug 28 08:09:51 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=709046377 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 64.sysrst_ctrl_combo_detect_with_pre_cond.709046377
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/64.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/65.sysrst_ctrl_combo_detect_with_pre_cond.4252593827
Short name T764
Test name
Test status
Simulation time 75860181653 ps
CPU time 44.65 seconds
Started Aug 28 08:08:55 PM UTC 24
Finished Aug 28 08:09:41 PM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4252593827 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 65.sysrst_ctrl_combo_detect_with_pre_cond.4252593827
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/65.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/66.sysrst_ctrl_combo_detect_with_pre_cond.3245246915
Short name T404
Test name
Test status
Simulation time 94089991441 ps
CPU time 102.76 seconds
Started Aug 28 08:08:55 PM UTC 24
Finished Aug 28 08:10:39 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3245246915 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 66.sysrst_ctrl_combo_detect_with_pre_cond.3245246915
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/66.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/67.sysrst_ctrl_combo_detect_with_pre_cond.3563305269
Short name T784
Test name
Test status
Simulation time 90868816936 ps
CPU time 255.47 seconds
Started Aug 28 08:08:57 PM UTC 24
Finished Aug 28 08:13:16 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3563305269 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 67.sysrst_ctrl_combo_detect_with_pre_cond.3563305269
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/67.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/68.sysrst_ctrl_combo_detect_with_pre_cond.445328165
Short name T790
Test name
Test status
Simulation time 94958983338 ps
CPU time 399.83 seconds
Started Aug 28 08:08:57 PM UTC 24
Finished Aug 28 08:15:42 PM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=445328165 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 68.sysrst_ctrl_combo_detect_with_pre_cond.445328165
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/68.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/69.sysrst_ctrl_combo_detect_with_pre_cond.3028556891
Short name T428
Test name
Test status
Simulation time 63811499554 ps
CPU time 25.29 seconds
Started Aug 28 08:09:00 PM UTC 24
Finished Aug 28 08:09:27 PM UTC 24
Peak memory 210564 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3028556891 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 69.sysrst_ctrl_combo_detect_with_pre_cond.3028556891
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/69.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_alert_test.819493892
Short name T125
Test name
Test status
Simulation time 2010396838 ps
CPU time 8.4 seconds
Started Aug 28 08:01:32 PM UTC 24
Finished Aug 28 08:01:41 PM UTC 24
Peak memory 209808 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=819493892 -assert nopostproc +UVM_TESTNAME
=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_reg
ression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_alert_test.819493892
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect.985489025
Short name T374
Test name
Test status
Simulation time 156108807305 ps
CPU time 412.5 seconds
Started Aug 28 08:01:29 PM UTC 24
Finished Aug 28 08:08:27 PM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=985489025 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect.985489025
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_combo_detect_with_pre_cond.3185239757
Short name T104
Test name
Test status
Simulation time 24834547016 ps
CPU time 71.99 seconds
Started Aug 28 08:01:31 PM UTC 24
Finished Aug 28 08:02:46 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3185239757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_combo_detect_with_pre_cond.3185239757
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ec_pwr_on_rst.2889490371
Short name T276
Test name
Test status
Simulation time 3473085766 ps
CPU time 15.66 seconds
Started Aug 28 08:01:29 PM UTC 24
Finished Aug 28 08:01:46 PM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2889490371 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ec_pwr_on_rst.2889490371
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_edge_detect.533892958
Short name T51
Test name
Test status
Simulation time 3202002955 ps
CPU time 9.12 seconds
Started Aug 28 08:01:29 PM UTC 24
Finished Aug 28 08:01:40 PM UTC 24
Peak memory 209920 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=533892958 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scr
atch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_edge_detect.533892958
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_flash_wr_prot_out.3619695015
Short name T74
Test name
Test status
Simulation time 2612716922 ps
CPU time 9.85 seconds
Started Aug 28 08:01:29 PM UTC 24
Finished Aug 28 08:01:40 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3619695015 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_flash_wr_prot_out.3619695015
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_in_out_inverted.4147928641
Short name T91
Test name
Test status
Simulation time 2494372324 ps
CPU time 2.41 seconds
Started Aug 28 08:01:29 PM UTC 24
Finished Aug 28 08:01:32 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4147928641 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_in_out_inverted.4147928641
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_access_test.2961386490
Short name T71
Test name
Test status
Simulation time 2084471666 ps
CPU time 8.72 seconds
Started Aug 28 08:01:29 PM UTC 24
Finished Aug 28 08:01:39 PM UTC 24
Peak memory 210148 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2961386490 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_access_test.2961386490
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_pin_override_test.464950505
Short name T444
Test name
Test status
Simulation time 2509534960 ps
CPU time 8.28 seconds
Started Aug 28 08:01:29 PM UTC 24
Finished Aug 28 08:01:39 PM UTC 24
Peak memory 210268 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=464950505 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/s
ysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_pin_override_test.464950505
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_smoke.2797206996
Short name T180
Test name
Test status
Simulation time 2117001986 ps
CPU time 4.53 seconds
Started Aug 28 08:01:29 PM UTC 24
Finished Aug 28 08:01:35 PM UTC 24
Peak memory 210204 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2797206996 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_
ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_smoke.2797206996
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all.1984766234
Short name T161
Test name
Test status
Simulation time 12428685116 ps
CPU time 11.49 seconds
Started Aug 28 08:01:32 PM UTC 24
Finished Aug 28 08:01:45 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1984766234 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_stress_all.1984766234
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_stress_all_with_rand_reset.4170700643
Short name T106
Test name
Test status
Simulation time 2782397386 ps
CPU time 7.18 seconds
Started Aug 28 08:01:32 PM UTC 24
Finished Aug 28 08:01:40 PM UTC 24
Peak memory 210008 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=4170700643 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 7.sysrst_ctrl_stress_all_with_rand_reset.4170700643
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/7.sysrst_ctrl_ultra_low_pwr.1367722065
Short name T194
Test name
Test status
Simulation time 519563357495 ps
CPU time 30.4 seconds
Started Aug 28 08:01:29 PM UTC 24
Finished Aug 28 08:02:01 PM UTC 24
Peak memory 209952 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1367722065 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 7.sysrst_ctrl_ultra_low_pwr.1367722065
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/7.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/70.sysrst_ctrl_combo_detect_with_pre_cond.2247212307
Short name T791
Test name
Test status
Simulation time 111642586274 ps
CPU time 423.36 seconds
Started Aug 28 08:09:01 PM UTC 24
Finished Aug 28 08:16:10 PM UTC 24
Peak memory 210320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2247212307 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 70.sysrst_ctrl_combo_detect_with_pre_cond.2247212307
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/70.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/71.sysrst_ctrl_combo_detect_with_pre_cond.1132396618
Short name T409
Test name
Test status
Simulation time 73022835327 ps
CPU time 106.48 seconds
Started Aug 28 08:09:01 PM UTC 24
Finished Aug 28 08:10:50 PM UTC 24
Peak memory 210308 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1132396618 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 71.sysrst_ctrl_combo_detect_with_pre_cond.1132396618
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/71.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/72.sysrst_ctrl_combo_detect_with_pre_cond.3725250497
Short name T769
Test name
Test status
Simulation time 18328420399 ps
CPU time 65.33 seconds
Started Aug 28 08:09:02 PM UTC 24
Finished Aug 28 08:10:09 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3725250497 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 72.sysrst_ctrl_combo_detect_with_pre_cond.3725250497
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/72.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.671136864
Short name T762
Test name
Test status
Simulation time 26615358802 ps
CPU time 19.45 seconds
Started Aug 28 08:09:04 PM UTC 24
Finished Aug 28 08:09:25 PM UTC 24
Peak memory 210320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=671136864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 73.sysrst_ctrl_combo_detect_with_pre_cond.671136864
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/73.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/74.sysrst_ctrl_combo_detect_with_pre_cond.2420691189
Short name T786
Test name
Test status
Simulation time 74572310110 ps
CPU time 312.5 seconds
Started Aug 28 08:09:10 PM UTC 24
Finished Aug 28 08:14:27 PM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2420691189 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 74.sysrst_ctrl_combo_detect_with_pre_cond.2420691189
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/74.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/75.sysrst_ctrl_combo_detect_with_pre_cond.668256089
Short name T120
Test name
Test status
Simulation time 40321615429 ps
CPU time 46.5 seconds
Started Aug 28 08:09:13 PM UTC 24
Finished Aug 28 08:10:02 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=668256089 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 75.sysrst_ctrl_combo_detect_with_pre_cond.668256089
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/75.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.2362683374
Short name T785
Test name
Test status
Simulation time 65267187746 ps
CPU time 242.06 seconds
Started Aug 28 08:09:23 PM UTC 24
Finished Aug 28 08:13:28 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2362683374 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 76.sysrst_ctrl_combo_detect_with_pre_cond.2362683374
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/76.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/77.sysrst_ctrl_combo_detect_with_pre_cond.202328585
Short name T393
Test name
Test status
Simulation time 77775985442 ps
CPU time 256.22 seconds
Started Aug 28 08:09:24 PM UTC 24
Finished Aug 28 08:13:43 PM UTC 24
Peak memory 210576 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=202328585 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 77.sysrst_ctrl_combo_detect_with_pre_cond.202328585
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/77.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/78.sysrst_ctrl_combo_detect_with_pre_cond.3965808260
Short name T789
Test name
Test status
Simulation time 134428787024 ps
CPU time 354.85 seconds
Started Aug 28 08:09:25 PM UTC 24
Finished Aug 28 08:15:24 PM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3965808260 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 78.sysrst_ctrl_combo_detect_with_pre_cond.3965808260
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/78.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_alert_test.1875391022
Short name T73
Test name
Test status
Simulation time 2040542484 ps
CPU time 3.19 seconds
Started Aug 28 08:01:36 PM UTC 24
Finished Aug 28 08:01:40 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_alert_test +en_scb=0 +cdc_instrumentation_enabled=1 +UVM_NO_RE
LNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1875391022 -assert nopostproc +UVM_TESTNAM
E=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_re
gression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_alert_test.1875391022
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_alert_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.2652104097
Short name T270
Test name
Test status
Simulation time 224206771894 ps
CPU time 103.56 seconds
Started Aug 28 08:01:34 PM UTC 24
Finished Aug 28 08:03:20 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2652104097 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_auto_blk_key_output.2652104097
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect.693370836
Short name T57
Test name
Test status
Simulation time 48407043222 ps
CPU time 31.85 seconds
Started Aug 28 08:01:34 PM UTC 24
Finished Aug 28 08:02:08 PM UTC 24
Peak memory 210436 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=693370836 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect.693370836
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_combo_detect_with_pre_cond.2191718409
Short name T59
Test name
Test status
Simulation time 27090795204 ps
CPU time 22.94 seconds
Started Aug 28 08:01:34 PM UTC 24
Finished Aug 28 08:01:59 PM UTC 24
Peak memory 210144 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2191718409 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_combo_detect_with_pre_cond.2191718409
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ec_pwr_on_rst.211974963
Short name T435
Test name
Test status
Simulation time 109830498768 ps
CPU time 290.68 seconds
Started Aug 28 08:01:34 PM UTC 24
Finished Aug 28 08:06:29 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=211974963 -assert nopostproc +UVM_TE
STNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ec_pwr_on_rst.211974963
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_edge_detect.1827819654
Short name T273
Test name
Test status
Simulation time 3815997955 ps
CPU time 11.25 seconds
Started Aug 28 08:01:34 PM UTC 24
Finished Aug 28 08:01:47 PM UTC 24
Peak memory 209948 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1827819654 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_edge_detect.1827819654
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_flash_wr_prot_out.1463055965
Short name T449
Test name
Test status
Simulation time 2678419412 ps
CPU time 1.77 seconds
Started Aug 28 08:01:32 PM UTC 24
Finished Aug 28 08:01:35 PM UTC 24
Peak memory 208184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1463055965 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_flash_wr_prot_out.1463055965
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_in_out_inverted.2966313814
Short name T92
Test name
Test status
Simulation time 2466779960 ps
CPU time 10.48 seconds
Started Aug 28 08:01:32 PM UTC 24
Finished Aug 28 08:01:44 PM UTC 24
Peak memory 209872 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2966313814 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_
28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_in_out_inverted.2966313814
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_access_test.1758251201
Short name T126
Test name
Test status
Simulation time 2033627429 ps
CPU time 8.25 seconds
Started Aug 28 08:01:32 PM UTC 24
Finished Aug 28 08:01:42 PM UTC 24
Peak memory 209892 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1758251201 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_access_test.1758251201
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_pin_override_test.2632918180
Short name T445
Test name
Test status
Simulation time 2525914874 ps
CPU time 3.33 seconds
Started Aug 28 08:01:32 PM UTC 24
Finished Aug 28 08:01:37 PM UTC 24
Peak memory 209876 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2632918180 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_pin_override_test.2632918180
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_smoke.840760360
Short name T450
Test name
Test status
Simulation time 2166106096 ps
CPU time 2.34 seconds
Started Aug 28 08:01:32 PM UTC 24
Finished Aug 28 08:01:35 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=840760360 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_smoke.840760360
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all.3894315377
Short name T72
Test name
Test status
Simulation time 9306191480 ps
CPU time 3.22 seconds
Started Aug 28 08:01:34 PM UTC 24
Finished Aug 28 08:01:39 PM UTC 24
Peak memory 210076 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10000000000 +cdc_instrumentation_enabled=1 +UVM_NO
_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3894315377 -assert nopostproc +UVM_TEST
NAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratc
h/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_stress_all.3894315377
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_stress_all_with_rand_reset.1542299415
Short name T277
Test name
Test status
Simulation time 4312195979 ps
CPU time 11.67 seconds
Started Aug 28 08:01:34 PM UTC 24
Finished Aug 28 08:01:48 PM UTC 24
Peak memory 220312 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=1542299415 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 8.sysrst_ctrl_stress_all_with_rand_reset.1542299415
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_ultra_low_pwr.1906045753
Short name T70
Test name
Test status
Simulation time 5884263819 ps
CPU time 3.08 seconds
Started Aug 28 08:01:34 PM UTC 24
Finished Aug 28 08:01:39 PM UTC 24
Peak memory 209888 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1906045753 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 8.sysrst_ctrl_ultra_low_pwr.1906045753
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/8.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/80.sysrst_ctrl_combo_detect_with_pre_cond.2383818526
Short name T782
Test name
Test status
Simulation time 43322374594 ps
CPU time 123.8 seconds
Started Aug 28 08:09:26 PM UTC 24
Finished Aug 28 08:11:32 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2383818526 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 80.sysrst_ctrl_combo_detect_with_pre_cond.2383818526
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/80.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/81.sysrst_ctrl_combo_detect_with_pre_cond.1314905606
Short name T402
Test name
Test status
Simulation time 146841247552 ps
CPU time 224.73 seconds
Started Aug 28 08:09:27 PM UTC 24
Finished Aug 28 08:13:15 PM UTC 24
Peak memory 210320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1314905606 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 81.sysrst_ctrl_combo_detect_with_pre_cond.1314905606
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/81.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/82.sysrst_ctrl_combo_detect_with_pre_cond.1501557169
Short name T400
Test name
Test status
Simulation time 56242463045 ps
CPU time 143.43 seconds
Started Aug 28 08:09:30 PM UTC 24
Finished Aug 28 08:11:56 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1501557169 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 82.sysrst_ctrl_combo_detect_with_pre_cond.1501557169
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/82.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/83.sysrst_ctrl_combo_detect_with_pre_cond.466791431
Short name T775
Test name
Test status
Simulation time 24831482609 ps
CPU time 62.11 seconds
Started Aug 28 08:09:35 PM UTC 24
Finished Aug 28 08:10:39 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=466791431 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 83.sysrst_ctrl_combo_detect_with_pre_cond.466791431
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/83.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/85.sysrst_ctrl_combo_detect_with_pre_cond.2787470864
Short name T768
Test name
Test status
Simulation time 26855641994 ps
CPU time 19.99 seconds
Started Aug 28 08:09:41 PM UTC 24
Finished Aug 28 08:10:02 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2787470864 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 85.sysrst_ctrl_combo_detect_with_pre_cond.2787470864
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/85.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/86.sysrst_ctrl_combo_detect_with_pre_cond.3688495343
Short name T783
Test name
Test status
Simulation time 129593586468 ps
CPU time 201.79 seconds
Started Aug 28 08:09:42 PM UTC 24
Finished Aug 28 08:13:07 PM UTC 24
Peak memory 210180 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3688495343 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 86.sysrst_ctrl_combo_detect_with_pre_cond.3688495343
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/86.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/89.sysrst_ctrl_combo_detect_with_pre_cond.576212970
Short name T427
Test name
Test status
Simulation time 23096357559 ps
CPU time 22.32 seconds
Started Aug 28 08:09:45 PM UTC 24
Finished Aug 28 08:10:08 PM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=576212970 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 89.sysrst_ctrl_combo_detect_with_pre_cond.576212970
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/89.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_auto_blk_key_output.2737786134
Short name T160
Test name
Test status
Simulation time 3803087715 ps
CPU time 5.67 seconds
Started Aug 28 08:01:37 PM UTC 24
Finished Aug 28 08:01:44 PM UTC 24
Peak memory 210016 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2737786134 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_auto_blk_key_output_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024
_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_auto_blk_key_output.2737786134
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_auto_blk_key_output/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect.2698539680
Short name T40
Test name
Test status
Simulation time 43096746502 ps
CPU time 30.88 seconds
Started Aug 28 08:01:38 PM UTC 24
Finished Aug 28 08:02:11 PM UTC 24
Peak memory 210172 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2698539680 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_combo_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/s
cratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect.2698539680
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_combo_detect_with_pre_cond.615522574
Short name T105
Test name
Test status
Simulation time 26582259837 ps
CPU time 77.92 seconds
Started Aug 28 08:01:39 PM UTC 24
Finished Aug 28 08:02:59 PM UTC 24
Peak memory 210320 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=615522574 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_combo_detect_with_pre_cond.615522574
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ec_pwr_on_rst.1780661601
Short name T341
Test name
Test status
Simulation time 3054339229 ps
CPU time 5.85 seconds
Started Aug 28 08:01:37 PM UTC 24
Finished Aug 28 08:01:44 PM UTC 24
Peak memory 210152 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1780661601 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ec_pwr_on_rst_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ec_pwr_on_rst.1780661601
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ec_pwr_on_rst/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_edge_detect.4266866364
Short name T52
Test name
Test status
Simulation time 5416759179 ps
CPU time 5.08 seconds
Started Aug 28 08:01:38 PM UTC 24
Finished Aug 28 08:01:45 PM UTC 24
Peak memory 209944 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4266866364 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_edge_detect_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/sc
ratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_edge_detect.4266866364
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_edge_detect/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_flash_wr_prot_out.1656033757
Short name T128
Test name
Test status
Simulation time 2630669703 ps
CPU time 3.85 seconds
Started Aug 28 08:01:37 PM UTC 24
Finished Aug 28 08:01:42 PM UTC 24
Peak memory 209504 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1656033757 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_flash_wr_prot_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28
/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_flash_wr_prot_out.1656033757
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_flash_wr_prot_out/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_in_out_inverted.863489275
Short name T93
Test name
Test status
Simulation time 2468764611 ps
CPU time 6.92 seconds
Started Aug 28 08:01:36 PM UTC 24
Finished Aug 28 08:01:44 PM UTC 24
Peak memory 209880 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=863489275 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_in_out_inverted_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_2
8/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_in_out_inverted.863489275
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_in_out_inverted/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_access_test.1012127198
Short name T275
Test name
Test status
Simulation time 2038495749 ps
CPU time 8.74 seconds
Started Aug 28 08:01:36 PM UTC 24
Finished Aug 28 08:01:46 PM UTC 24
Peak memory 209820 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=1012127198 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_access_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sy
srst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_access_test.1012127198
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_access_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_pin_override_test.4006288806
Short name T127
Test name
Test status
Simulation time 2536236652 ps
CPU time 3.37 seconds
Started Aug 28 08:01:37 PM UTC 24
Finished Aug 28 08:01:42 PM UTC 24
Peak memory 209604 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=4006288806 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_pin_override_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/
sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_pin_override_test.4006288806
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_pin_override_test/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_smoke.401345176
Short name T200
Test name
Test status
Simulation time 2112512603 ps
CPU time 7.16 seconds
Started Aug 28 08:01:36 PM UTC 24
Finished Aug 28 08:01:44 PM UTC 24
Peak memory 209776 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=401345176 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_c
trl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_smoke.401345176
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_smoke/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_stress_all_with_rand_reset.3752973520
Short name T278
Test name
Test status
Simulation time 2333616774 ps
CPU time 8.55 seconds
Started Aug 28 08:01:39 PM UTC 24
Finished Aug 28 08:01:48 PM UTC 24
Peak memory 210080 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stres
s_seq=sysrst_ctrl_stress_all_vseq +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/d
v/tools/sim.tcl +ntb_random_seed=3752973520 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /d
ev/null -cm_name 9.sysrst_ctrl_stress_all_with_rand_reset.3752973520
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all_with_rand_reset/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/9.sysrst_ctrl_ultra_low_pwr.2369179319
Short name T76
Test name
Test status
Simulation time 5792302388 ps
CPU time 10.08 seconds
Started Aug 28 08:01:37 PM UTC 24
Finished Aug 28 08:01:49 PM UTC 24
Peak memory 210208 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +test_timeout_ns=10_000_000_000 +cdc_instrumentation_enabled=1 +UVM
_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2369179319 -assert nopostproc +UVM_T
ESTNAME=sysrst_ctrl_base_test +UVM_TEST_SEQ=sysrst_ctrl_ultra_low_pwr_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/
scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 9.sysrst_ctrl_ultra_low_pwr.2369179319
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_ultra_low_pwr/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/90.sysrst_ctrl_combo_detect_with_pre_cond.2042683253
Short name T774
Test name
Test status
Simulation time 47037064527 ps
CPU time 50.35 seconds
Started Aug 28 08:09:46 PM UTC 24
Finished Aug 28 08:10:38 PM UTC 24
Peak memory 210248 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=2042683253 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 90.sysrst_ctrl_combo_detect_with_pre_cond.2042683253
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/90.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/92.sysrst_ctrl_combo_detect_with_pre_cond.71535567
Short name T431
Test name
Test status
Simulation time 25579031312 ps
CPU time 96.6 seconds
Started Aug 28 08:09:52 PM UTC 24
Finished Aug 28 08:11:30 PM UTC 24
Peak memory 210260 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=71535567 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UVM
_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regression
_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 92.sysrst_ctrl_combo_detect_with_pre_cond.71535567
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/92.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/94.sysrst_ctrl_combo_detect_with_pre_cond.913834261
Short name T430
Test name
Test status
Simulation time 21348714889 ps
CPU time 26.2 seconds
Started Aug 28 08:10:02 PM UTC 24
Finished Aug 28 08:10:30 PM UTC 24
Peak memory 210184 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=913834261 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 94.sysrst_ctrl_combo_detect_with_pre_cond.913834261
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/94.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/95.sysrst_ctrl_combo_detect_with_pre_cond.993917890
Short name T407
Test name
Test status
Simulation time 88688960597 ps
CPU time 231.6 seconds
Started Aug 28 08:10:03 PM UTC 24
Finished Aug 28 08:13:58 PM UTC 24
Peak memory 210316 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=993917890 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 95.sysrst_ctrl_combo_detect_with_pre_cond.993917890
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/95.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/97.sysrst_ctrl_combo_detect_with_pre_cond.3262012945
Short name T779
Test name
Test status
Simulation time 40197113081 ps
CPU time 70.41 seconds
Started Aug 28 08:10:07 PM UTC 24
Finished Aug 28 08:11:19 PM UTC 24
Peak memory 210508 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3262012945 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 97.sysrst_ctrl_combo_detect_with_pre_cond.3262012945
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/97.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/98.sysrst_ctrl_combo_detect_with_pre_cond.3850245748
Short name T771
Test name
Test status
Simulation time 31014582324 ps
CPU time 16.46 seconds
Started Aug 28 08:10:09 PM UTC 24
Finished Aug 28 08:10:27 PM UTC 24
Peak memory 210380 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=3850245748 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +U
VM_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressi
on_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 98.sysrst_ctrl_combo_detect_with_pre_cond.3850245748
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/98.sysrst_ctrl_combo_detect_with_pre_cond/latest

Test location /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default/99.sysrst_ctrl_combo_detect_with_pre_cond.659823302
Short name T777
Test name
Test status
Simulation time 64021191862 ps
CPU time 41.13 seconds
Started Aug 28 08:10:09 PM UTC 24
Finished Aug 28 08:10:52 PM UTC 24
Peak memory 210252 kb
Host riverbear.c.edafarm-workstations-prod.internal
User miguelosorio
Command /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/default/simv +cdc_instrumentation_enabled=1 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_
LOW -licqueue -ucli -do /workspaces/repo/hw/dv/tools/sim.tcl +ntb_random_seed=659823302 -assert nopostproc +UVM_TESTNAME=sysrst_ctrl_base_test +UV
M_TEST_SEQ=sysrst_ctrl_combo_detect_with_pre_cond_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspaces/repo/scratch/os_regressio
n_2024_08_28/sysrst_ctrl-sim-vcs/coverage/default.vdb -cm_log /dev/null -cm_name 99.sysrst_ctrl_combo_detect_with_pre_cond.659823302
Directory /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/99.sysrst_ctrl_combo_detect_with_pre_cond/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%