a861deb3de| Stage | Name | Tests | Max Job Runtime | Simulated Time | Passing | Total | Pass Rate |
|---|---|---|---|---|---|---|---|
| V1 | smoke | sysrst_ctrl_smoke | 3.487m | 49 | 50 | 98.00 | |
| V1 | input_output_inverted | sysrst_ctrl_in_out_inverted | 3.486m | 49 | 50 | 98.00 | |
| V1 | combo_detect_ec_rst | sysrst_ctrl_combo_detect_ec_rst | 9.970s | 2.404ms | 5 | 5 | 100.00 |
| V1 | combo_detect_ec_rst_with_pre_cond | sysrst_ctrl_combo_detect_ec_rst_with_pre_cond | 9.700s | 2.276ms | 5 | 5 | 100.00 |
| V1 | csr_hw_reset | sysrst_ctrl_csr_hw_reset | 11.980s | 4.012ms | 5 | 5 | 100.00 |
| V1 | csr_rw | sysrst_ctrl_csr_rw | 11.360s | 2.057ms | 20 | 20 | 100.00 |
| V1 | csr_bit_bash | sysrst_ctrl_csr_bit_bash | 6.304m | 75.471ms | 5 | 5 | 100.00 |
| V1 | csr_aliasing | sysrst_ctrl_csr_aliasing | 10.930s | 3.192ms | 5 | 5 | 100.00 |
| V1 | csr_mem_rw_with_rand_reset | sysrst_ctrl_csr_mem_rw_with_rand_reset | 11.780s | 2.069ms | 20 | 20 | 100.00 |
| V1 | regwen_csr_and_corresponding_lockable_csr | sysrst_ctrl_csr_rw | 11.360s | 2.057ms | 20 | 20 | 100.00 |
| sysrst_ctrl_csr_aliasing | 10.930s | 3.192ms | 5 | 5 | 100.00 | ||
| V1 | TOTAL | 163 | 165 | 98.79 | |||
| V2 | combo_detect | sysrst_ctrl_combo_detect | 13.698m | 188.273ms | 50 | 50 | 100.00 |
| V2 | combo_detect_with_pre_cond | sysrst_ctrl_combo_detect_with_pre_cond | 8.831m | 140.193ms | 90 | 100 | 90.00 |
| V2 | auto_block_key_outputs | sysrst_ctrl_auto_blk_key_output | 14.717m | 241.454ms | 50 | 50 | 100.00 |
| V2 | keyboard_input_triggered_interrupt | sysrst_ctrl_edge_detect | 28.927m | 473.930ms | 50 | 50 | 100.00 |
| V2 | pin_output_keyboard_inversion_control | sysrst_ctrl_pin_override_test | 12.330s | 2.511ms | 50 | 50 | 100.00 |
| V2 | pin_input_value_accessibility | sysrst_ctrl_pin_access_test | 3.485m | 49 | 50 | 98.00 | |
| V2 | ec_power_on_reset | sysrst_ctrl_ec_pwr_on_rst | 54.016m | 954.414ms | 50 | 50 | 100.00 |
| V2 | flash_write_protect_output | sysrst_ctrl_flash_wr_prot_out | 13.520s | 2.612ms | 50 | 50 | 100.00 |
| V2 | ultra_low_power_test | sysrst_ctrl_ultra_low_pwr | 7.312m | 2.213s | 47 | 50 | 94.00 |
| V2 | sysrst_ctrl_feature_disable | sysrst_ctrl_feature_disable | 50.440s | 33.642ms | 2 | 2 | 100.00 |
| V2 | stress_all | sysrst_ctrl_stress_all | 52.343m | 838.531ms | 48 | 50 | 96.00 |
| V2 | alert_test | sysrst_ctrl_alert_test | 3.488m | 49 | 50 | 98.00 | |
| V2 | intr_test | sysrst_ctrl_intr_test | 11.000s | 2.010ms | 50 | 50 | 100.00 |
| V2 | tl_d_oob_addr_access | sysrst_ctrl_tl_errors | 12.130s | 2.035ms | 20 | 20 | 100.00 |
| V2 | tl_d_illegal_access | sysrst_ctrl_tl_errors | 12.130s | 2.035ms | 20 | 20 | 100.00 |
| V2 | tl_d_outstanding_access | sysrst_ctrl_csr_hw_reset | 11.980s | 4.012ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 11.360s | 2.057ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 10.930s | 3.192ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 51.690s | 7.544ms | 20 | 20 | 100.00 | ||
| V2 | tl_d_partial_access | sysrst_ctrl_csr_hw_reset | 11.980s | 4.012ms | 5 | 5 | 100.00 |
| sysrst_ctrl_csr_rw | 11.360s | 2.057ms | 20 | 20 | 100.00 | ||
| sysrst_ctrl_csr_aliasing | 10.930s | 3.192ms | 5 | 5 | 100.00 | ||
| sysrst_ctrl_same_csr_outstanding | 51.690s | 7.544ms | 20 | 20 | 100.00 | ||
| V2 | TOTAL | 675 | 692 | 97.54 | |||
| V2S | tl_intg_err | sysrst_ctrl_sec_cm | 45.480s | 42.053ms | 5 | 5 | 100.00 |
| sysrst_ctrl_tl_intg_err | 2.613m | 42.418ms | 20 | 20 | 100.00 | ||
| V2S | sec_cm_bus_integrity | sysrst_ctrl_tl_intg_err | 2.613m | 42.418ms | 20 | 20 | 100.00 |
| V2S | TOTAL | 25 | 25 | 100.00 | |||
| V3 | stress_all_with_rand_reset | sysrst_ctrl_stress_all_with_rand_reset | 1.923m | 1.778s | 49 | 50 | 98.00 |
| V3 | TOTAL | 49 | 50 | 98.00 | |||
| TOTAL | 912 | 932 | 97.85 |
| Items | Total | Written | Passing | Progress |
|---|---|---|---|---|
| V1 | 9 | 9 | 7 | 77.78 |
| V2 | 15 | 15 | 10 | 66.67 |
| V2S | 2 | 2 | 2 | 100.00 |
| V3 | 1 | 1 | 0 | 0.00 |
| SCORE | LINE | COND | TOGGLE | FSM | BRANCH | ASSERT | GROUP |
|---|---|---|---|---|---|---|---|
| 96.73 | 98.73 | 98.03 | 100.00 | 93.59 | 98.96 | 99.42 | 88.34 |
Job returned non-zero exit code has 5 failures:
Test sysrst_ctrl_stress_all has 1 failures.
9.sysrst_ctrl_stress_all.37193639244408131717646823883597930686006287182175561383410709303944293447922
Log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_stress_all/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Aug 28 20:01 2024
Feature removed during lmreread, or wrong
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Check your license file.
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make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test sysrst_ctrl_alert_test has 1 failures.
9.sysrst_ctrl_alert_test.66650082994640677622468751717087873417490821476761498663271706780036464840884
Log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/9.sysrst_ctrl_alert_test/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Aug 28 20:01 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test sysrst_ctrl_smoke has 1 failures.
10.sysrst_ctrl_smoke.26897060422244317661404007129397102026398432160664603371559324745731002879313
Log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_smoke/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Aug 28 20:01 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test sysrst_ctrl_in_out_inverted has 1 failures.
10.sysrst_ctrl_in_out_inverted.73415863553914256112613082664576855037493879471494510887268551073792132888876
Log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_in_out_inverted/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Aug 28 20:01 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
Test sysrst_ctrl_pin_access_test has 1 failures.
10.sysrst_ctrl_pin_access_test.91323560136343301519626955900002440189288640045620819103830249285651177520634
Log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_pin_access_test/latest/run.log
Chronologic VCS simulator copyright 1991-2022
Contains Synopsys proprietary information.
Compiler version T-2022.06-SP2_Full64; Runtime version T-2022.06-SP2_Full64; Aug 28 20:01 2024
Feature removed during lmreread, or wrong
SERVER line hostid.
Check your license file.
Please contact VCS Customer Support at 1-800-VERILOG for more information.
make: *** [/workspaces/repo/hw/dv/tools/dvsim/sim.mk:191: simulate] Error 255
UVM_ERROR (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup) has 4 failures:
18.sysrst_ctrl_ultra_low_pwr.49614339095062529319064224554570160393407273231917472029521624089815720153940
Line 371, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/18.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 2110121012 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 2147621012 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 5017621012 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 8532621012 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 12032621012 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
22.sysrst_ctrl_ultra_low_pwr.49018886810355826100061599669693939036122838526482347461871425813631806095632
Line 371, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/22.sysrst_ctrl_ultra_low_pwr/latest/run.log
UVM_ERROR @ 8672561125 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 9000061125 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:81) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a H2L transition on pwrb_in_i
UVM_INFO @ 11905061125 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 11919618366 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
36.sysrst_ctrl_stress_all.31214082902250250888542802784107558345602113391647215538972586438722384505320
Line 384, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/36.sysrst_ctrl_stress_all/latest/run.log
UVM_ERROR @ 13117529508 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:113) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Check failed (exp_z3_wakeup)
UVM_INFO @ 13350029508 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:66) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] z3_wakeup assertion expected for a HIGH level on ac_present_i
UVM_INFO @ 13895427824 ps: (sysrst_ctrl_ultra_low_pwr_vseq.sv:235) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_ultra_low_pwr_vseq] Disable Z3 wakeup check
UVM_INFO @ 13918235790 ps: (sysrst_ctrl_stress_all_vseq.sv:52) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_stress_all_vseq] body: executing sequence sysrst_ctrl_combo_detect_vseq
UVM_INFO @ 15915105906 ps: (sysrst_ctrl_combo_detect_vseq.sv:112) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_vseq] Starting the body from combo detect
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == * (* [*] vs * [*]) has 3 failures:
10.sysrst_ctrl_combo_detect_with_pre_cond.106241665830729473903319296195010235956356917183719592319745631404863616214754
Line 446, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/10.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 84477765812 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 84497765812 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 84517765812 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 94749471992 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x29
UVM_INFO @ 94749551992 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x1b
25.sysrst_ctrl_combo_detect_with_pre_cond.16815507605818590951986833267542147355830075698042194699250208098582697780090
Line 384, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/25.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 26794604468 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:543) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.bat_disable == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 26794604468 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 26794604468 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == * (* [*] vs * [*]) has 3 failures:
12.sysrst_ctrl_combo_detect_with_pre_cond.15723735151690687061411905896499263963374704125094978447322323273424777581154
Line 427, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/12.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 61643861401 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 61728861401 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 61748861401 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 71958744754 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x31
UVM_INFO @ 71958911418 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x30
23.sysrst_ctrl_combo_detect_with_pre_cond.87196943512938592318708319613948172426646375001144523289047747223976143580482
Line 442, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/23.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 120287286373 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:551) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.rst_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 120287286373 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_INFO @ 120287286373 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
... and 1 more failures.
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(4) +/-* has 1 failures:
26.sysrst_ctrl_combo_detect_with_pre_cond.93651022847734026747053881365523236322849142447166243234675203688647090812204
Line 384, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/26.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 13041453571 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(8) vs exp(4) +/-4
UVM_INFO @ 13101453571 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 13121453571 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 23252517907 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x1a
UVM_INFO @ 23252909209 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x16
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == * (* [*] vs * [*]) has 1 failures:
30.sysrst_ctrl_combo_detect_with_pre_cond.80596132557022939589701122183493765642305285572998379191329041548698171617150
Line 401, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/30.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 31942803220 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:559) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed cfg.vif.wkup_req == 1 (0 [0x0] vs 1 [0x1])
UVM_ERROR @ 33087877152 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:570) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed rdata == intr_actions (0 [0x0] vs 4 [0x4])
UVM_INFO @ 33087877152 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_in_out_inverted_vseq.sv:103) [sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (* [*] vs * [*]) has 1 failures:
42.sysrst_ctrl_stress_all_with_rand_reset.63954098547968886051896238987989630624038777416437003017867343813766061753029
Line 440, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/42.sysrst_ctrl_stress_all_with_rand_reset/latest/run.log
UVM_ERROR @ 9322366755 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:103) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key0_in == inv_key0_out (1 [0x1] vs 0 [0x0])
UVM_ERROR @ 9322366755 ps: (sysrst_ctrl_in_out_inverted_vseq.sv:109) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_in_out_inverted_vseq] Check failed inv_key1_in == inv_key1_out (0 [0x0] vs 1 [0x1])
UVM_INFO @ 9322366755 ps: (uvm_report_catcher.svh:705) [UVM/REPORT/CATCHER]
--- UVM Report catcher Summary ---
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-* has 1 failures:
43.sysrst_ctrl_combo_detect_with_pre_cond.46320889576000298586309559833753507338875165992089243153731417875461883448270
Line 389, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/43.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 13615255117 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:266) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) rst_req_check: inact(9) vs exp(5) +/-4
UVM_INFO @ 13750255117 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:156) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 1
UVM_INFO @ 13770255117 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:162) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] ec_rst_l2h_expected == 0
UVM_INFO @ 23931974502 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:236) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of ec_rst_ctl register:0x31
UVM_INFO @ 23932054502 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:239) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Write data of key_intr_debounce_ctl register:0x29
UVM_ERROR (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-* has 1 failures:
48.sysrst_ctrl_combo_detect_with_pre_cond.47963768067615520248700473570235817337674703105395429625319798728013349010491
Line 381, in log /workspaces/repo/scratch/os_regression_2024_08_28/sysrst_ctrl-sim-vcs/48.sysrst_ctrl_combo_detect_with_pre_cond/latest/run.log
UVM_ERROR @ 17144718848 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4
UVM_INFO @ 18034842221 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:385) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid precondition detected for combo channel: 3
UVM_INFO @ 18049718848 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:399) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] combo_precondition_mask= 17
UVM_INFO @ 19784718848 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:478) uvm_test_top.env.virtual_sequencer [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] valid combo input transition detected for channel :3
UVM_ERROR @ 19824718848 ps: (sysrst_ctrl_combo_detect_with_pre_cond_vseq.sv:280) [uvm_test_top.env.virtual_sequencer.sysrst_ctrl_combo_detect_with_pre_cond_vseq] Check failed (inactive_cycles inside {[exp_cycles - EXP_CYCLE_TOLERANCE : exp_cycles + EXP_CYCLE_TOLERANCE]}) wkup_req_check: inact(8) vs exp(3) +/-4