Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.87	95.65	86.36		83.33	95.24	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.87	95.65	86.36		83.33	95.24	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.78	95.65	86.36		83.33	95.24	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
90.78	95.65	86.36		83.33	95.24	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	100.00	90.91		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.18	100.00	90.91		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T32 T33 T63 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T19 T32 T33 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T19 T32 T33 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T32 T33 T63 
149        1/1                    cnt_en = 1'b1;
           Tests:       T32 T33 T63 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T63 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T32 T33 T63 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T32 T33 T63 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T63 
167        1/1                    if (trigger_active) begin
           Tests:       T32 T33 T63 
168        1/1                      state_d = DetectSt;
           Tests:       T32 T33 T63 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T67 T148 T55 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T32 T33 T63 
182        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T63 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T32 T33 T63 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T32 T33 T63 
191        1/1                      state_d = StableSt;
           Tests:       T32 T33 T63 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T32 T33 T63 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T32 T33 T63 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T32 T33 T63 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T32 T33 T63 
206        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T63 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T32 T33 T63 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T63

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T63

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T32,T33,T63

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T63
1	0	Covered	T4,T5,T6
1	1	Covered	T32,T33,T63

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T63
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T63
0	1	Covered	T32,T33,T63
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T32,T33,T63
1	-	Covered	T32,T33,T63

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T33,T63
DetectSt	168	Covered	T32,T33,T63
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T32,T33,T63

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T33,T63
DebounceSt->IdleSt	163	Covered	T34,T36,T67
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T32,T33,T63
IdleSt->DebounceSt	148	Covered	T32,T33,T63
StableSt->IdleSt	206	Covered	T32,T33,T63

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T32,T33,T63
0	1	Covered	T32,T33,T63
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T63
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T33,T63
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T33,T63
DebounceSt	-	0	1	0	-	-	-	Covered	T67,T148,T55
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T33,T63
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T32,T33,T63
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T32,T33,T63
StableSt	-	-	-	-	-	-	0	Covered	T32,T33,T63
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	162	0	0
CntIncr_A	8302401	75896	0	0
CntNoWrap_A	8302401	7837944	0	0
DetectStDropOut_A	8302401	0	0	0
DetectedOut_A	8302401	448	0	0
DetectedPulseOut_A	8302401	70	0	0
DisabledIdleSt_A	8302401	7758457	0	0
DisabledNoDetection_A	8302401	7760326	0	0
EnterDebounceSt_A	8302401	94	0	0
EnterDetectSt_A	8302401	70	0	0
EnterStableSt_A	8302401	70	0	0
PulseIsPulse_A	8302401	70	0	0
StayInStableSt	8302401	378	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8302401	5612	0	0
gen_low_level_sva.LowLevelEvent_A	8302401	7840005	0	0
gen_not_sticky_sva.StableStDropOut_A	8302401	70	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	162	0	0
T10	1410	0	0	0
T11	3522	0	0	0
T12	505	0	0	0
T32	604	2	0	0
T33	0	4	0	0
T34	0	1	0	0
T36	0	1	0	0
T63	0	2	0	0
T65	0	4	0	0
T66	0	4	0	0
T67	0	3	0	0
T76	0	4	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T85	753	0	0	0
T91	522	0	0	0
T117	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	75896	0	0
T10	1410	0	0	0
T11	3522	0	0	0
T12	505	0	0	0
T32	604	30	0	0
T33	0	95	0	0
T34	0	7	0	0
T36	0	12	0	0
T63	0	10	0	0
T65	0	68	0	0
T66	0	110	0	0
T67	0	140	0	0
T76	0	184	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T85	753	0	0	0
T91	522	0	0	0
T117	0	95	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7837944	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	448	0	0
T10	1410	0	0	0
T11	3522	0	0	0
T12	505	0	0	0
T32	604	2	0	0
T33	0	19	0	0
T63	0	2	0	0
T65	0	9	0	0
T66	0	13	0	0
T67	0	10	0	0
T76	0	12	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T85	753	0	0	0
T91	522	0	0	0
T117	0	12	0	0
T139	0	8	0	0
T140	0	4	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	70	0	0
T10	1410	0	0	0
T11	3522	0	0	0
T12	505	0	0	0
T32	604	1	0	0
T33	0	2	0	0
T63	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	1	0	0
T76	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T85	753	0	0	0
T91	522	0	0	0
T117	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7758457	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7760326	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	94	0	0
T10	1410	0	0	0
T11	3522	0	0	0
T12	505	0	0	0
T32	604	1	0	0
T33	0	2	0	0
T34	0	1	0	0
T36	0	1	0	0
T63	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	2	0	0
T76	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T85	753	0	0	0
T91	522	0	0	0
T117	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	70	0	0
T10	1410	0	0	0
T11	3522	0	0	0
T12	505	0	0	0
T32	604	1	0	0
T33	0	2	0	0
T63	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	1	0	0
T76	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T85	753	0	0	0
T91	522	0	0	0
T117	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	70	0	0
T10	1410	0	0	0
T11	3522	0	0	0
T12	505	0	0	0
T32	604	1	0	0
T33	0	2	0	0
T63	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	1	0	0
T76	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T85	753	0	0	0
T91	522	0	0	0
T117	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	70	0	0
T10	1410	0	0	0
T11	3522	0	0	0
T12	505	0	0	0
T32	604	1	0	0
T33	0	2	0	0
T63	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	1	0	0
T76	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T85	753	0	0	0
T91	522	0	0	0
T117	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	378	0	0
T10	1410	0	0	0
T11	3522	0	0	0
T12	505	0	0	0
T32	604	1	0	0
T33	0	17	0	0
T63	0	1	0	0
T65	0	7	0	0
T66	0	11	0	0
T67	0	9	0	0
T76	0	10	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T85	753	0	0	0
T91	522	0	0	0
T117	0	11	0	0
T139	0	7	0	0
T140	0	3	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	5612	0	0
T1	509	0	0	0
T2	655	2	0	0
T4	497	9	0	0
T5	415	1	0	0
T6	423	1	0	0
T14	424	3	0	0
T15	443	0	0	0
T16	501	4	0	0
T17	475	0	0	0
T18	0	4	0	0
T19	0	8	0	0
T23	756	0	0	0
T29	0	9	0	0
T31	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	70	0	0
T10	1410	0	0	0
T11	3522	0	0	0
T12	505	0	0	0
T32	604	1	0	0
T33	0	2	0	0
T63	0	1	0	0
T65	0	2	0	0
T66	0	2	0	0
T67	0	1	0	0
T76	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T85	753	0	0	0
T91	522	0	0	0
T117	0	1	0	0
T139	0	1	0	0
T140	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T21 T28 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T11 T27 T21 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T11 T27 T21 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T21 T28 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T21 T28 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T21 T28 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T21 T28 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T21 T28 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T21 T28 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T21 T28 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T21 T22 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T28 T73 T74 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T21 T22 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T21 T22 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T21 T22 
186        1/1                    state_d = IdleSt;
           Tests:       T74 T104 T105 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T74 T104 T105 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T21 T22 
191        1/1                      state_d = StableSt;
           Tests:       T11 T21 T22 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T21 T22 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T21 T22 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T21 T22 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T21 T22 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T21 T22 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T21 T22 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T21,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T21,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T21,T22

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T21,T28
1	0	Covered	T4,T5,T6
1	1	Covered	T11,T21,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T21,T22
0	1	Covered	T74,T104,T105
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T21,T22
0	1	Unreachable
1	0	Covered	T11,T21,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T21,T28
DetectSt	168	Covered	T11,T21,T22
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T21,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T21,T22
DebounceSt->IdleSt	163	Covered	T28,T34,T36
DetectSt->IdleSt	186	Covered	T74,T104,T105
DetectSt->StableSt	191	Covered	T11,T21,T22
IdleSt->DebounceSt	148	Covered	T11,T21,T28
StableSt->IdleSt	206	Covered	T11,T21,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T21,T28
0	1	Covered	T11,T21,T28
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T21,T22
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T21,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T21,T22
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T73,T74
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T21,T28
DetectSt	-	-	-	-	1	-	-	Covered	T74,T104,T105
DetectSt	-	-	-	-	0	1	-	Covered	T11,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T21,T22
StableSt	-	-	-	-	-	-	0	Covered	T11,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	164	0	0
CntIncr_A	8302401	81552	0	0
CntNoWrap_A	8302401	7837942	0	0
DetectStDropOut_A	8302401	21	0	0
DetectedOut_A	8302401	329258	0	0
DetectedPulseOut_A	8302401	38	0	0
DisabledIdleSt_A	8302401	5835227	0	0
DisabledNoDetection_A	8302401	5837123	0	0
EnterDebounceSt_A	8302401	105	0	0
EnterDetectSt_A	8302401	59	0	0
EnterStableSt_A	8302401	38	0	0
PulseIsPulse_A	8302401	38	0	0
StayInStableSt	8302401	329220	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8302401	5612	0	0
gen_low_level_sva.LowLevelEvent_A	8302401	7840005	0	0
gen_sticky_sva.StableStDropOut_A	8302401	1317713	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	164	0	0
T11	3522	2	0	0
T12	505	0	0	0
T21	0	2	0	0
T22	0	4	0	0
T27	20062	0	0	0
T28	0	5	0	0
T34	0	2	0	0
T36	0	2	0	0
T60	441	0	0	0
T73	0	2	0	0
T74	0	3	0	0
T75	0	3	0	0
T76	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	81552	0	0
T11	3522	76	0	0
T12	505	0	0	0
T21	0	42	0	0
T22	0	134	0	0
T27	20062	0	0	0
T28	0	190	0	0
T34	0	16	0	0
T36	0	50	0	0
T60	441	0	0	0
T73	0	142	0	0
T74	0	192	0	0
T75	0	246	0	0
T76	0	62	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7837942	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	21	0	0
T46	24205	0	0	0
T67	737	0	0	0
T74	1742	1	0	0
T104	0	3	0	0
T105	0	1	0	0
T130	817	0	0	0
T131	427	0	0	0
T132	1725	0	0	0
T133	502	0	0	0
T134	421	0	0	0
T135	413	0	0	0
T136	831	0	0	0
T149	0	1	0	0
T150	0	10	0	0
T151	0	3	0	0
T152	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	329258	0	0
T11	3522	612	0	0
T12	505	0	0	0
T21	0	4	0	0
T22	0	767	0	0
T27	20062	0	0	0
T60	441	0	0	0
T77	0	393	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	30	0	0
T107	0	22	0	0
T141	0	107	0	0
T142	0	230	0	0
T143	0	8	0	0
T144	0	51714	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	38	0	0
T11	3522	1	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	20062	0	0	0
T60	441	0	0	0
T77	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	1	0	0
T107	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	5835227	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	5837123	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	105	0	0
T11	3522	1	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	20062	0	0	0
T28	0	5	0	0
T34	0	2	0	0
T36	0	2	0	0
T60	441	0	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	3	0	0
T76	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	59	0	0
T11	3522	1	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	20062	0	0	0
T60	441	0	0	0
T74	0	1	0	0
T77	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T107	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	38	0	0
T11	3522	1	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	20062	0	0	0
T60	441	0	0	0
T77	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	1	0	0
T107	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	38	0	0
T11	3522	1	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	20062	0	0	0
T60	441	0	0	0
T77	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	1	0	0
T107	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T144	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	329220	0	0
T11	3522	611	0	0
T12	505	0	0	0
T21	0	3	0	0
T22	0	765	0	0
T27	20062	0	0	0
T60	441	0	0	0
T77	0	391	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	29	0	0
T107	0	21	0	0
T141	0	106	0	0
T142	0	229	0	0
T143	0	7	0	0
T144	0	51713	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	5612	0	0
T1	509	0	0	0
T2	655	2	0	0
T4	497	9	0	0
T5	415	1	0	0
T6	423	1	0	0
T14	424	3	0	0
T15	443	0	0	0
T16	501	4	0	0
T17	475	0	0	0
T18	0	4	0	0
T19	0	8	0	0
T23	756	0	0	0
T29	0	9	0	0
T31	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1317713	0	0
T11	3522	389	0	0
T12	505	0	0	0
T21	0	66	0	0
T22	0	154	0	0
T27	20062	0	0	0
T60	441	0	0	0
T77	0	762	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	77	0	0
T107	0	129	0	0
T141	0	518822	0	0
T142	0	571	0	0
T143	0	120	0	0
T144	0	49	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T21 T28 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T11 T27 T21 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T11 T27 T21 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T21 T28 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T21 T28 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T21 T28 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T21 T28 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T21 T28 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T21 T28 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T21 T28 
168        1/1                      state_d = DetectSt;
           Tests:       T22 T73 T74 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T11 T21 T28 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T22 T73 T74 
182        1/1                  cnt_en = 1'b1;
           Tests:       T22 T73 T74 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T22 T73 T74 
186        1/1                    state_d = IdleSt;
           Tests:       T77 T106 T115 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T77 T106 T115 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T22 T73 T74 
191        1/1                      state_d = StableSt;
           Tests:       T22 T73 T74 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T22 T73 T74 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T22 T73 T74 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T22 T73 T74 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T22 T73 T74 
206        1/1                    state_d = IdleSt;
           Tests:       T22 T73 T74 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T22 T73 T74 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T21,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T21,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T22,T73,T74

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T21,T28
1	0	Covered	T4,T5,T6
1	1	Covered	T11,T21,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T22,T73,T74
0	1	Covered	T77,T106,T115
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T22,T73,T74
0	1	Unreachable
1	0	Covered	T22,T73,T74

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T21,T28
DetectSt	168	Covered	T22,T73,T74
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T22,T73,T74

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T22,T73,T74
DebounceSt->IdleSt	163	Covered	T11,T21,T28
DetectSt->IdleSt	186	Covered	T77,T106,T115
DetectSt->StableSt	191	Covered	T22,T73,T74
IdleSt->DebounceSt	148	Covered	T11,T21,T28
StableSt->IdleSt	206	Covered	T22,T73,T74

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T21,T28
0	1	Covered	T11,T21,T28
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T22,T73,T74
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T21,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T22,T73,T74
DebounceSt	-	0	1	0	-	-	-	Covered	T11,T21,T28
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T21,T28
DetectSt	-	-	-	-	1	-	-	Covered	T77,T106,T115
DetectSt	-	-	-	-	0	1	-	Covered	T22,T73,T74
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T22,T73,T74
StableSt	-	-	-	-	-	-	0	Covered	T22,T73,T74
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	148	0	0
CntIncr_A	8302401	55679	0	0
CntNoWrap_A	8302401	7837958	0	0
DetectStDropOut_A	8302401	10	0	0
DetectedOut_A	8302401	248571	0	0
DetectedPulseOut_A	8302401	39	0	0
DisabledIdleSt_A	8302401	5835227	0	0
DisabledNoDetection_A	8302401	5837123	0	0
EnterDebounceSt_A	8302401	99	0	0
EnterDetectSt_A	8302401	49	0	0
EnterStableSt_A	8302401	39	0	0
PulseIsPulse_A	8302401	39	0	0
StayInStableSt	8302401	248532	0	0
gen_high_level_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_sticky_sva.StableStDropOut_A	8302401	1371443	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	148	0	0
T11	3522	5	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	4	0	0
T27	20062	0	0	0
T28	0	5	0	0
T34	0	2	0	0
T36	0	2	0	0
T60	441	0	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	2	0	0
T76	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	55679	0	0
T11	3522	410	0	0
T12	505	0	0	0
T21	0	89	0	0
T22	0	154	0	0
T27	20062	0	0	0
T28	0	275	0	0
T34	0	16	0	0
T36	0	50	0	0
T60	441	0	0	0
T73	0	97	0	0
T74	0	21	0	0
T75	0	61	0	0
T76	0	82	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7837958	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	10	0	0
T49	8141	0	0	0
T59	14077	0	0	0
T77	1691	1	0	0
T106	0	2	0	0
T115	0	1	0	0
T140	2117	0	0	0
T153	0	6	0	0
T154	524	0	0	0
T155	423	0	0	0
T156	504	0	0	0
T157	495	0	0	0
T158	402	0	0	0
T159	490	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	248571	0	0
T22	1545	542	0	0
T35	24747	0	0	0
T36	6770	0	0	0
T73	0	176	0	0
T74	0	44	0	0
T75	0	265	0	0
T76	0	180	0	0
T77	0	293	0	0
T88	491	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T107	0	88	0	0
T141	0	188	0	0
T142	0	567	0	0
T143	0	12	0	0
T145	502	0	0	0
T146	422	0	0	0
T147	454	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	39	0	0
T22	1545	2	0	0
T35	24747	0	0	0
T36	6770	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T88	491	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T107	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T145	502	0	0	0
T146	422	0	0	0
T147	454	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	5835227	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	5837123	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	99	0	0
T11	3522	5	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	20062	0	0	0
T28	0	5	0	0
T34	0	2	0	0
T36	0	2	0	0
T60	441	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	49	0	0
T22	1545	2	0	0
T35	24747	0	0	0
T36	6770	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T88	491	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T107	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T145	502	0	0	0
T146	422	0	0	0
T147	454	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	39	0	0
T22	1545	2	0	0
T35	24747	0	0	0
T36	6770	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T88	491	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T107	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T145	502	0	0	0
T146	422	0	0	0
T147	454	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	39	0	0
T22	1545	2	0	0
T35	24747	0	0	0
T36	6770	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T88	491	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T107	0	1	0	0
T141	0	1	0	0
T142	0	1	0	0
T143	0	1	0	0
T145	502	0	0	0
T146	422	0	0	0
T147	454	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	248532	0	0
T22	1545	540	0	0
T35	24747	0	0	0
T36	6770	0	0	0
T73	0	175	0	0
T74	0	43	0	0
T75	0	264	0	0
T76	0	179	0	0
T77	0	292	0	0
T88	491	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T107	0	87	0	0
T141	0	187	0	0
T142	0	566	0	0
T143	0	11	0	0
T145	502	0	0	0
T146	422	0	0	0
T147	454	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1371443	0	0
T22	1545	357	0	0
T35	24747	0	0	0
T36	6770	0	0	0
T73	0	91	0	0
T74	0	159	0	0
T75	0	80	0	0
T76	0	91	0	0
T77	0	145	0	0
T88	491	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T107	0	70	0	0
T141	0	518723	0	0
T142	0	201	0	0
T143	0	45	0	0
T145	502	0	0	0
T146	422	0	0	0
T147	454	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T4 T5 T6 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T21 T28 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T11 T27 T21 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T11 T27 T21 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T21 T28 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T21 T28 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T21 T28 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T21 T28 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T21 T28 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T21 T28 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T21 T28 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T21 T28 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T28 T77 T107 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T21 T28 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T21 T28 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T21 T28 
186        1/1                    state_d = IdleSt;
           Tests:       T28 T75 T107 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T28 T75 T107 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T21 T22 
191        1/1                      state_d = StableSt;
           Tests:       T11 T21 T22 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T21 T22 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T21 T22 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T21 T22 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T21 T22 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T21 T22 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T21 T22 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T21,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T21,T28

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T11,T21,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T21,T28
1	0	Covered	T4,T5,T6
1	1	Covered	T11,T21,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T21,T22
0	1	Covered	T28,T75,T107
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T21,T22
0	1	Unreachable
1	0	Covered	T11,T21,T22

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T21,T28
DetectSt	168	Covered	T11,T21,T28
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T11,T21,T22

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T21,T28
DebounceSt->IdleSt	163	Covered	T28,T34,T36
DetectSt->IdleSt	186	Covered	T28,T75,T107
DetectSt->StableSt	191	Covered	T11,T21,T22
IdleSt->DebounceSt	148	Covered	T11,T21,T28
StableSt->IdleSt	206	Covered	T11,T21,T22

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		19	19	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T21,T28
0	1	Covered	T11,T21,T28
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T21,T28
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T21,T28
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T21,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T28,T77,T107
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T21,T28
DetectSt	-	-	-	-	1	-	-	Covered	T28,T75,T107
DetectSt	-	-	-	-	0	1	-	Covered	T11,T21,T22
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T21,T22
StableSt	-	-	-	-	-	-	0	Covered	T11,T21,T22
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	152	0	0
CntIncr_A	8302401	379243	0	0
CntNoWrap_A	8302401	7837954	0	0
DetectStDropOut_A	8302401	10	0	0
DetectedOut_A	8302401	924838	0	0
DetectedPulseOut_A	8302401	43	0	0
DisabledIdleSt_A	8302401	5835227	0	0
DisabledNoDetection_A	8302401	5837123	0	0
EnterDebounceSt_A	8302401	99	0	0
EnterDetectSt_A	8302401	53	0	0
EnterStableSt_A	8302401	43	0	0
PulseIsPulse_A	8302401	43	0	0
StayInStableSt	8302401	924795	0	0
gen_high_event_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_high_level_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_sticky_sva.StableStDropOut_A	8302401	353717	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	152	0	0
T11	3522	2	0	0
T12	505	0	0	0
T21	0	2	0	0
T22	0	4	0	0
T27	20062	0	0	0
T28	0	9	0	0
T34	0	2	0	0
T36	0	2	0	0
T60	441	0	0	0
T73	0	2	0	0
T74	0	2	0	0
T75	0	4	0	0
T76	0	2	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	379243	0	0
T11	3522	87	0	0
T12	505	0	0	0
T21	0	34	0	0
T22	0	84	0	0
T27	20062	0	0	0
T28	0	240	0	0
T34	0	20	0	0
T36	0	51	0	0
T60	441	0	0	0
T73	0	94	0	0
T74	0	37	0	0
T75	0	20	0	0
T76	0	95	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7837954	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	10	0	0
T28	848	4	0	0
T63	628	0	0	0
T64	626	0	0	0
T75	0	1	0	0
T94	656	0	0	0
T95	466	0	0	0
T104	0	1	0	0
T107	0	1	0	0
T152	0	1	0	0
T160	0	2	0	0
T161	945	0	0	0
T162	501	0	0	0
T163	422	0	0	0
T164	432	0	0	0
T165	408	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	924838	0	0
T11	3522	597	0	0
T12	505	0	0	0
T21	0	24	0	0
T22	0	340	0	0
T27	20062	0	0	0
T60	441	0	0	0
T73	0	100	0	0
T74	0	65	0	0
T75	0	11	0	0
T76	0	107	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	122	0	0
T141	0	457246	0	0
T144	0	129	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	43	0	0
T11	3522	1	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	20062	0	0	0
T60	441	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	1	0	0
T141	0	1	0	0
T144	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	5835227	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	5837123	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	99	0	0
T11	3522	1	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	20062	0	0	0
T28	0	5	0	0
T34	0	2	0	0
T36	0	2	0	0
T60	441	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	53	0	0
T11	3522	1	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	20062	0	0	0
T28	0	4	0	0
T60	441	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	2	0	0
T76	0	1	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T107	0	1	0	0
T141	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	43	0	0
T11	3522	1	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	20062	0	0	0
T60	441	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	1	0	0
T141	0	1	0	0
T144	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	43	0	0
T11	3522	1	0	0
T12	505	0	0	0
T21	0	1	0	0
T22	0	2	0	0
T27	20062	0	0	0
T60	441	0	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	1	0	0
T141	0	1	0	0
T144	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	924795	0	0
T11	3522	596	0	0
T12	505	0	0	0
T21	0	23	0	0
T22	0	338	0	0
T27	20062	0	0	0
T60	441	0	0	0
T73	0	99	0	0
T74	0	64	0	0
T75	0	10	0	0
T76	0	106	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	121	0	0
T141	0	457245	0	0
T144	0	128	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	353717	0	0
T11	3522	402	0	0
T12	505	0	0	0
T21	0	66	0	0
T22	0	644	0	0
T27	20062	0	0	0
T60	441	0	0	0
T73	0	178	0	0
T74	0	142	0	0
T75	0	267	0	0
T76	0	170	0	0
T78	439	0	0	0
T79	403	0	0	0
T80	453	0	0	0
T81	495	0	0	0
T82	601	0	0	0
T83	3064	0	0	0
T104	0	36	0	0
T141	0	51	0	0
T144	0	90501	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T5 T6 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T34 T36 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T15 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T15 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T34 T36 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T34 T36 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T34 T36 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T34 T36 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T34 T36 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T51 T53 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T51 T53 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T53 T56 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T51 T166 T167 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T53 T56 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T53 T56 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T53 T56 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T53 T56 
191        1/1                      state_d = StableSt;
           Tests:       T2 T53 T56 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T53 T56 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T53 T56 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T53 T56 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T53 T56 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T56 T166 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T53 T56 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	19	86.36
Logical	22	19	86.36
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T34,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T34,T36

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T2,T53,T56

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T8,T94
1	0	Covered	T4,T5,T6
1	1	Covered	T2,T34,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T53,T56
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T53,T56
0	1	Covered	T2,T56,T166
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T2,T53,T56
1	-	Covered	T2,T56,T166

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T34,T36
DetectSt	168	Covered	T2,T53,T56
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T2,T53,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T53,T56
DebounceSt->IdleSt	163	Covered	T34,T36,T51
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T2,T53,T56
IdleSt->DebounceSt	148	Covered	T2,T34,T36
StableSt->IdleSt	206	Covered	T2,T56,T166

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T34,T36
0	1	Covered	T2,T34,T36
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T53,T56
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T34,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T53,T56
DebounceSt	-	0	1	0	-	-	-	Covered	T51,T166,T167
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T34,T36
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T2,T53,T56
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T56,T166
StableSt	-	-	-	-	-	-	0	Covered	T2,T53,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	42	0	0
CntIncr_A	8302401	1654	0	0
CntNoWrap_A	8302401	7838064	0	0
DetectStDropOut_A	8302401	0	0	0
DetectedOut_A	8302401	1850	0	0
DetectedPulseOut_A	8302401	18	0	0
DisabledIdleSt_A	8302401	7825363	0	0
DisabledNoDetection_A	8302401	7827229	0	0
EnterDebounceSt_A	8302401	24	0	0
EnterDetectSt_A	8302401	18	0	0
EnterStableSt_A	8302401	18	0	0
PulseIsPulse_A	8302401	18	0	0
StayInStableSt	8302401	1824	0	0
gen_high_level_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_not_sticky_sva.StableStDropOut_A	8302401	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	42	0	0
T2	655	6	0	0
T3	478	0	0	0
T7	711	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T29	489	0	0	0
T31	524	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T51	0	1	0	0
T53	0	2	0	0
T56	0	4	0	0
T68	407	0	0	0
T166	0	3	0	0
T167	0	1	0	0
T168	0	2	0	0
T169	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1654	0	0
T2	655	60	0	0
T3	478	0	0	0
T7	711	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T29	489	0	0	0
T31	524	0	0	0
T34	0	14	0	0
T36	0	19	0	0
T51	0	30	0	0
T53	0	84	0	0
T56	0	196	0	0
T68	407	0	0	0
T166	0	40	0	0
T167	0	88	0	0
T168	0	43	0	0
T169	0	53	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7838064	0	0
T1	509	108	0	0
T2	655	248	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1850	0	0
T2	655	119	0	0
T3	478	0	0	0
T7	711	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T29	489	0	0	0
T31	524	0	0	0
T53	0	561	0	0
T56	0	62	0	0
T68	407	0	0	0
T114	0	49	0	0
T166	0	43	0	0
T168	0	24	0	0
T170	0	120	0	0
T171	0	43	0	0
T172	0	1	0	0
T173	0	615	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	18	0	0
T2	655	3	0	0
T3	478	0	0	0
T7	711	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T29	489	0	0	0
T31	524	0	0	0
T53	0	1	0	0
T56	0	2	0	0
T68	407	0	0	0
T114	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7825363	0	0
T1	509	108	0	0
T2	655	4	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7827229	0	0
T1	509	109	0	0
T2	655	4	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	24	0	0
T2	655	3	0	0
T3	478	0	0	0
T7	711	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T29	489	0	0	0
T31	524	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T56	0	2	0	0
T68	407	0	0	0
T166	0	2	0	0
T167	0	1	0	0
T168	0	1	0	0
T169	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	18	0	0
T2	655	3	0	0
T3	478	0	0	0
T7	711	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T29	489	0	0	0
T31	524	0	0	0
T53	0	1	0	0
T56	0	2	0	0
T68	407	0	0	0
T114	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	18	0	0
T2	655	3	0	0
T3	478	0	0	0
T7	711	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T29	489	0	0	0
T31	524	0	0	0
T53	0	1	0	0
T56	0	2	0	0
T68	407	0	0	0
T114	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	18	0	0
T2	655	3	0	0
T3	478	0	0	0
T7	711	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T29	489	0	0	0
T31	524	0	0	0
T53	0	1	0	0
T56	0	2	0	0
T68	407	0	0	0
T114	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1824	0	0
T2	655	115	0	0
T3	478	0	0	0
T7	711	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T29	489	0	0	0
T31	524	0	0	0
T53	0	559	0	0
T56	0	60	0	0
T68	407	0	0	0
T114	0	47	0	0
T166	0	42	0	0
T168	0	23	0	0
T170	0	119	0	0
T171	0	41	0	0
T173	0	613	0	0
T174	0	44	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	10	0	0
T2	655	2	0	0
T3	478	0	0	0
T7	711	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T29	489	0	0	0
T31	524	0	0	0
T56	0	2	0	0
T68	407	0	0	0
T111	0	1	0	0
T112	0	1	0	0
T166	0	1	0	0
T168	0	1	0	0
T170	0	1	0	0
T172	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T5 T6 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T7 T8 T34 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T15 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T15 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T7 T8 T34 
149        1/1                    cnt_en = 1'b1;
           Tests:       T7 T8 T34 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T7 T8 T34 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T7 T8 T34 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T7 T8 T34 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T7 T8 T51 
167        1/1                    if (trigger_active) begin
           Tests:       T7 T8 T51 
168        1/1                      state_d = DetectSt;
           Tests:       T7 T8 T51 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T171 T111 T112 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T7 T8 T51 
182        1/1                  cnt_en = 1'b1;
           Tests:       T7 T8 T51 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T7 T8 T51 
186        1/1                    state_d = IdleSt;
           Tests:       T110 T111 T112 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T110 T111 T112 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T7 T8 T51 
191        1/1                      state_d = StableSt;
           Tests:       T7 T8 T51 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T7 T8 T51 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T7 T8 T51 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T7 T8 T51 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T7 T8 T51 
206        1/1                    state_d = IdleSt;
           Tests:       T51 T54 T53 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T7 T8 T51 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T5,T6
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T34

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T34

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T7,T8,T51

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T34
1	0	Covered	T4,T5,T6
1	1	Covered	T7,T8,T34

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T51
0	1	Covered	T110,T111,T112
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T7,T8,T51
0	1	Covered	T51,T54,T53
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T7,T8,T51
1	-	Covered	T51,T54,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T7,T8,T34
DetectSt	168	Covered	T7,T8,T51
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T7,T8,T51

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T7,T8,T51
DebounceSt->IdleSt	163	Covered	T34,T36,T171
DetectSt->IdleSt	186	Covered	T110,T111,T112
DetectSt->StableSt	191	Covered	T7,T8,T51
IdleSt->DebounceSt	148	Covered	T7,T8,T34
StableSt->IdleSt	206	Covered	T51,T54,T53

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T7,T8,T34
0	1	Covered	T7,T8,T34
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T51
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T7,T8,T34
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T7,T8,T51
DebounceSt	-	0	1	0	-	-	-	Covered	T171,T111,T112
DebounceSt	-	0	0	-	-	-	-	Covered	T7,T8,T34
DetectSt	-	-	-	-	1	-	-	Covered	T110,T111,T112
DetectSt	-	-	-	-	0	1	-	Covered	T7,T8,T51
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T51,T54,T53
StableSt	-	-	-	-	-	-	0	Covered	T7,T8,T51
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	88	0	0
CntIncr_A	8302401	2755	0	0
CntNoWrap_A	8302401	7838018	0	0
DetectStDropOut_A	8302401	3	0	0
DetectedOut_A	8302401	5142	0	0
DetectedPulseOut_A	8302401	38	0	0
DisabledIdleSt_A	8302401	7822234	0	0
DisabledNoDetection_A	8302401	7824092	0	0
EnterDebounceSt_A	8302401	47	0	0
EnterDetectSt_A	8302401	41	0	0
EnterStableSt_A	8302401	38	0	0
PulseIsPulse_A	8302401	38	0	0
StayInStableSt	8302401	5084	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	8302401	1634	0	0
gen_low_level_sva.LowLevelEvent_A	8302401	7840005	0	0
gen_not_sticky_sva.StableStDropOut_A	8302401	18	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	88	0	0
T7	711	2	0	0
T8	590	2	0	0
T9	489	0	0	0
T30	505	0	0	0
T32	604	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T51	0	4	0	0
T53	0	2	0	0
T54	0	4	0	0
T68	407	0	0	0
T69	502	0	0	0
T70	404	0	0	0
T84	586	0	0	0
T116	0	2	0	0
T175	0	4	0	0
T176	0	2	0	0
T177	423	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	2755	0	0
T7	711	54	0	0
T8	590	16	0	0
T9	489	0	0	0
T30	505	0	0	0
T32	604	0	0	0
T34	0	12	0	0
T36	0	20	0	0
T51	0	60	0	0
T53	0	84	0	0
T54	0	44	0	0
T68	407	0	0	0
T69	502	0	0	0
T70	404	0	0	0
T84	586	0	0	0
T116	0	75	0	0
T175	0	64	0	0
T176	0	13	0	0
T177	423	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7838018	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	3	0	0
T110	546	1	0	0
T111	0	1	0	0
T112	0	1	0	0
T178	421	0	0	0
T179	425	0	0	0
T180	774	0	0	0
T181	496	0	0	0
T182	492	0	0	0
T183	4366	0	0	0
T184	404	0	0	0
T185	508	0	0	0
T186	526	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	5142	0	0
T7	711	248	0	0
T8	590	164	0	0
T9	489	0	0	0
T30	505	0	0	0
T32	604	0	0	0
T51	0	233	0	0
T53	0	76	0	0
T54	0	83	0	0
T68	407	0	0	0
T69	502	0	0	0
T70	404	0	0	0
T84	586	0	0	0
T116	0	25	0	0
T169	0	161	0	0
T175	0	203	0	0
T176	0	52	0	0
T177	423	0	0	0
T187	0	184	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	38	0	0
T7	711	1	0	0
T8	590	1	0	0
T9	489	0	0	0
T30	505	0	0	0
T32	604	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T68	407	0	0	0
T69	502	0	0	0
T70	404	0	0	0
T84	586	0	0	0
T116	0	1	0	0
T169	0	2	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	423	0	0	0
T187	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7822234	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7824092	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	47	0	0
T7	711	1	0	0
T8	590	1	0	0
T9	489	0	0	0
T30	505	0	0	0
T32	604	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T68	407	0	0	0
T69	502	0	0	0
T70	404	0	0	0
T84	586	0	0	0
T116	0	1	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	423	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	41	0	0
T7	711	1	0	0
T8	590	1	0	0
T9	489	0	0	0
T30	505	0	0	0
T32	604	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T68	407	0	0	0
T69	502	0	0	0
T70	404	0	0	0
T84	586	0	0	0
T116	0	1	0	0
T169	0	2	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	423	0	0	0
T187	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	38	0	0
T7	711	1	0	0
T8	590	1	0	0
T9	489	0	0	0
T30	505	0	0	0
T32	604	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T68	407	0	0	0
T69	502	0	0	0
T70	404	0	0	0
T84	586	0	0	0
T116	0	1	0	0
T169	0	2	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	423	0	0	0
T187	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	38	0	0
T7	711	1	0	0
T8	590	1	0	0
T9	489	0	0	0
T30	505	0	0	0
T32	604	0	0	0
T51	0	2	0	0
T53	0	1	0	0
T54	0	2	0	0
T68	407	0	0	0
T69	502	0	0	0
T70	404	0	0	0
T84	586	0	0	0
T116	0	1	0	0
T169	0	2	0	0
T175	0	2	0	0
T176	0	1	0	0
T177	423	0	0	0
T187	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	5084	0	0
T7	711	246	0	0
T8	590	162	0	0
T9	489	0	0	0
T30	505	0	0	0
T32	604	0	0	0
T51	0	230	0	0
T53	0	75	0	0
T54	0	80	0	0
T68	407	0	0	0
T69	502	0	0	0
T70	404	0	0	0
T84	586	0	0	0
T116	0	24	0	0
T169	0	158	0	0
T175	0	200	0	0
T176	0	50	0	0
T177	423	0	0	0
T187	0	182	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1634	0	0
T1	509	0	0	0
T2	655	3	0	0
T4	497	5	0	0
T5	415	2	0	0
T6	423	2	0	0
T14	424	1	0	0
T15	443	0	0	0
T16	501	5	0	0
T17	475	0	0	0
T18	0	3	0	0
T19	0	4	0	0
T23	756	0	0	0
T29	0	6	0	0
T31	0	6	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	18	0	0
T51	730	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T73	803	0	0	0
T114	0	2	0	0
T116	0	1	0	0
T169	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0
T175	0	1	0	0
T188	0	1	0	0
T189	4403	0	0	0
T190	522	0	0	0
T191	507	0	0	0
T192	407	0	0	0
T193	458	0	0	0
T194	487	0	0	0
T195	680	0	0	0
T196	8418	0	0	0