Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T4 T5 T6
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T7 T8 T32
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T15 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T15 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T7 T8 T32
149 1/1 cnt_en = 1'b1;
Tests: T7 T8 T32
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T7 T8 T32
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T7 T8 T32
163 1/1 state_d = IdleSt;
Tests: T34 T36
164 1/1 cnt_clr = 1'b1;
Tests: T34 T36
165 1/1 end else if (cnt_done) begin
Tests: T7 T8 T32
166 1/1 cnt_clr = 1'b1;
Tests: T7 T8 T32
167 1/1 if (trigger_active) begin
Tests: T7 T8 T32
168 1/1 state_d = DetectSt;
Tests: T7 T32 T11
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T28 T73 T74
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T7 T32 T11
182 1/1 cnt_en = 1'b1;
Tests: T7 T32 T11
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T7 T32 T11
186 1/1 state_d = IdleSt;
Tests: T74 T104 T105
187 1/1 cnt_clr = 1'b1;
Tests: T74 T104 T105
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T7 T32 T11
191 1/1 state_d = StableSt;
Tests: T7 T32 T11
192 1/1 cnt_clr = 1'b1;
Tests: T7 T32 T11
193 1/1 event_detected_o = 1'b1;
Tests: T7 T32 T11
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T7 T32 T11
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T7 T32 T11
206 1/1 state_d = IdleSt;
Tests: T32 T11 T21
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T7 T32 T11
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T6
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T8 T11
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T15 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T15 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T2 T8 T11
149 1/1 cnt_en = 1'b1;
Tests: T2 T8 T11
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T8 T11
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T8 T11
163 1/1 state_d = IdleSt;
Tests: T34 T36
164 1/1 cnt_clr = 1'b1;
Tests: T34 T36
165 1/1 end else if (cnt_done) begin
Tests: T2 T8 T11
166 1/1 cnt_clr = 1'b1;
Tests: T2 T8 T11
167 1/1 if (trigger_active) begin
Tests: T2 T8 T11
168 1/1 state_d = DetectSt;
Tests: T2 T8 T22
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T11 T13 T21
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T8 T22
182 1/1 cnt_en = 1'b1;
Tests: T2 T8 T22
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T8 T22
186 1/1 state_d = IdleSt;
Tests: T52 T77 T106
187 1/1 cnt_clr = 1'b1;
Tests: T52 T77 T106
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T8 T22
191 1/1 state_d = StableSt;
Tests: T2 T8 T22
192 1/1 cnt_clr = 1'b1;
Tests: T2 T8 T22
193 1/1 event_detected_o = 1'b1;
Tests: T2 T8 T22
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T8 T22
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T8 T22
206 1/1 state_d = IdleSt;
Tests: T2 T8 T13
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T8 T22
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T5 T6
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T4 T5 T6
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T11 T21 T28
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T11 T27 T21
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T11 T27 T21
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T11 T21 T28
149 1/1 cnt_en = 1'b1;
Tests: T11 T21 T28
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T11 T21 T28
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T11 T21 T28
163 1/1 state_d = IdleSt;
Tests: T34 T36
164 1/1 cnt_clr = 1'b1;
Tests: T34 T36
165 1/1 end else if (cnt_done) begin
Tests: T11 T21 T28
166 1/1 cnt_clr = 1'b1;
Tests: T11 T21 T28
167 1/1 if (trigger_active) begin
Tests: T11 T21 T28
168 1/1 state_d = DetectSt;
Tests: T11 T21 T28
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T28 T77 T107
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T11 T21 T28
182 1/1 cnt_en = 1'b1;
Tests: T11 T21 T28
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T11 T21 T28
186 1/1 state_d = IdleSt;
Tests: T28 T75 T107
187 1/1 cnt_clr = 1'b1;
Tests: T28 T75 T107
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T11 T21 T22
191 1/1 state_d = StableSt;
Tests: T11 T21 T22
192 1/1 cnt_clr = 1'b1;
Tests: T11 T21 T22
193 1/1 event_detected_o = 1'b1;
Tests: T11 T21 T22
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T11 T21 T22
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T11 T21 T22
206 1/1 state_d = IdleSt;
Tests: T11 T21 T22
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T11 T21 T22
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T34 T35 T36
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T34 T35 T36
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T17 T12
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T15 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T15 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T17 T12
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T17 T12
129 1/1 cnt_en = 1'b0;
Tests: T1 T17 T12
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T17 T12
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T17 T12
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T17 T12
139
140 1/1 unique case (state_q)
Tests: T1 T17 T12
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T17 T12
148 1/1 state_d = DebounceSt;
Tests: T1 T17 T12
149 1/1 cnt_en = 1'b1;
Tests: T1 T17 T12
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T17 T12
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T17 T12
163 1/1 state_d = IdleSt;
Tests: T34 T36
164 1/1 cnt_clr = 1'b1;
Tests: T34 T36
165 1/1 end else if (cnt_done) begin
Tests: T1 T17 T12
166 1/1 cnt_clr = 1'b1;
Tests: T1 T17 T12
167 1/1 if (trigger_active) begin
Tests: T1 T17 T12
168 1/1 state_d = DetectSt;
Tests: T1 T17 T12
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T34 T36 T108
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T17 T12
182 1/1 cnt_en = 1'b1;
Tests: T1 T17 T12
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T17 T12
186 1/1 state_d = IdleSt;
Tests: T34 T35 T36
187 1/1 cnt_clr = 1'b1;
Tests: T34 T35 T36
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T17 T12
191 1/1 state_d = StableSt;
Tests: T1 T17 T12
192 1/1 cnt_clr = 1'b1;
Tests: T1 T17 T12
193 1/1 event_detected_o = 1'b1;
Tests: T1 T17 T12
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T17 T12
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T17 T12
206 1/1 state_d = IdleSt;
Tests: T34 T35 T36
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T17 T12
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T1 T15 T17
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
70 1/1 trigger_active_q <= 1'b0;
Tests: T4 T5 T6
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T4 T5 T6
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T4 T5 T6
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T15 T17
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T15 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T15 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
105 1/1 cnt_q <= '0;
Tests: T4 T5 T6
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T4 T5 T6
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T5 T6
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T5 T6
129 1/1 cnt_en = 1'b0;
Tests: T4 T5 T6
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T5 T6
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T5 T6
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T5 T6
139
140 1/1 unique case (state_q)
Tests: T4 T5 T6
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T5 T6
148 1/1 state_d = DebounceSt;
Tests: T1 T15 T17
149 1/1 cnt_en = 1'b1;
Tests: T1 T15 T17
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T15 T17
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T15 T17
163 1/1 state_d = IdleSt;
Tests: T34 T36
164 1/1 cnt_clr = 1'b1;
Tests: T34 T36
165 1/1 end else if (cnt_done) begin
Tests: T1 T15 T17
166 1/1 cnt_clr = 1'b1;
Tests: T1 T15 T17
167 1/1 if (trigger_active) begin
Tests: T1 T15 T17
168 1/1 state_d = DetectSt;
Tests: T1 T3 T9
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T15 T17 T60
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T3 T9
182 1/1 cnt_en = 1'b1;
Tests: T1 T3 T9
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T3 T9
186 1/1 state_d = IdleSt;
Tests: T34 T36 T46
187 1/1 cnt_clr = 1'b1;
Tests: T34 T36 T46
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T3 T9
191 1/1 state_d = StableSt;
Tests: T1 T3 T9
192 1/1 cnt_clr = 1'b1;
Tests: T1 T3 T9
193 1/1 event_detected_o = 1'b1;
Tests: T1 T3 T9
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T3 T9
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T3 T9
206 1/1 state_d = IdleSt;
Tests: T1 T3 T9
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T3 T9
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T4 T5 T6
220 1/1 state_q <= IdleSt;
Tests: T4 T5 T6
221 end else begin
222 1/1 state_q <= state_d;
Tests: T4 T5 T6
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T15,T17 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T15,T17 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T15,T17 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T15,T17 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T3,T9 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T15,T17 |
| 1 | 0 | Covered | T23,T19,T10 |
| 1 | 1 | Covered | T1,T15,T17 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T3,T9 |
| 0 | 1 | Covered | T46,T103,T47 |
| 1 | 0 | Covered | T34,T36 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T3,T9 |
| 0 | 1 | Covered | T1,T3,T9 |
| 1 | 0 | Covered | T34,T36,T109 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T3,T9 |
| 1 | - | Covered | T1,T3,T9 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 20 | 90.91 |
| Logical | 22 | 20 | 90.91 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T7,T8,T32 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T7,T8,T32 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T7,T8,T32 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T7,T8,T32 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T7,T8,T32 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T8,T32 |
| 0 | 1 | Covered | T110,T111,T112 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T7,T8,T32 |
| 0 | 1 | Covered | T8,T32,T33 |
| 1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T7,T8,T32 |
| 1 | - | Covered | T8,T32,T33 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T34,T35,T36 |
| 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T17,T12 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T17,T12 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T1,T17,T12 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T34,T35,T36 |
| 1 | 0 | Covered | T34,T35,T36 |
| 1 | 1 | Covered | T1,T17,T12 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T17,T12 |
| 0 | 1 | Covered | T34,T35,T36 |
| 1 | 0 | Covered | T34,T35,T36 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T17,T12 |
| 0 | 1 | Covered | T34,T35,T36 |
| 1 | 0 | Covered | T34,T36,T113 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T17,T12 |
| 1 | - | Covered | T34,T35,T36 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T21,T28 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T21,T28 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T21,T28 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T21,T28 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T11,T21,T28 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T11,T21,T22 |
| 0 | 1 | Covered | T28,T75,T107 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T11,T21,T22 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T11,T21,T22 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 20 | 90.91 |
| Logical | 22 | 20 | 90.91 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T8,T13 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T8,T13 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T2,T8,T13 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T8,T13 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T2,T8,T13 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T8,T13 |
| 0 | 1 | Covered | T52,T114 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T8,T13 |
| 0 | 1 | Covered | T2,T8,T13 |
| 1 | 0 | Not Covered | |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T2,T8,T13 |
| 1 | - | Covered | T2,T8,T13 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T21,T28 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T21,T28 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T22,T73,T74 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T21,T28 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T11,T21,T28 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T22,T73,T74 |
| 0 | 1 | Covered | T77,T106,T115 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T22,T73,T74 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T22,T73,T74 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T4,T5,T6 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T5,T6 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T4,T5,T6 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T21,T28 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T21,T28 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T5,T6 |
| 1 | Covered | T11,T21,T22 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T11,T21,T28 |
| 1 | 0 | Covered | T4,T5,T6 |
| 1 | 1 | Covered | T11,T21,T28 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T11,T21,T22 |
| 0 | 1 | Covered | T74,T104,T105 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T11,T21,T22 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T11,T21,T22 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DebounceSt |
148 |
Covered |
T7,T8,T32 |
| DetectSt |
168 |
Covered |
T7,T8,T32 |
| IdleSt |
163 |
Covered |
T4,T5,T6 |
| StableSt |
191 |
Covered |
T7,T8,T32 |
| transitions | Line No. | Covered | Tests |
| DebounceSt->DetectSt |
168 |
Covered |
T7,T8,T32 |
| DebounceSt->IdleSt |
163 |
Covered |
T34,T36,T67 |
| DetectSt->IdleSt |
186 |
Covered |
T52,T28,T74 |
| DetectSt->StableSt |
191 |
Covered |
T7,T8,T32 |
| IdleSt->DebounceSt |
148 |
Covered |
T7,T8,T32 |
| StableSt->IdleSt |
206 |
Covered |
T8,T32,T33 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T7,T8,T32 |
| 0 |
1 |
Covered |
T7,T8,T32 |
| 0 |
0 |
Covered |
T4,T5,T6 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T7,T8,T32 |
| 0 |
Covered |
T4,T5,T6 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T7,T8,T32 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T34,T36 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T7,T8,T32 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T51,T67,T116 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T7,T8,T32 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T52,T34,T36 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T7,T8,T32 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T3,T9 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T8,T32,T33 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T7,T8,T32 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T1,T17,T11 |
| 0 |
1 |
Covered |
T1,T17,T11 |
| 0 |
0 |
Covered |
T4,T5,T6 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T17,T11 |
| 0 |
Covered |
T4,T5,T6 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T17,T11 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T5,T6 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T34,T36 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T1,T17,T11 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T28,T34,T36 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T1,T17,T11 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T28,T34,T35 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T1,T17,T11 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T17,T12 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T11,T21,T34 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T1,T17,T11 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T4,T5,T6 |
| 0 |
Covered |
T4,T5,T6 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
16009 |
0 |
0 |
| T1 |
1018 |
4 |
0 |
0 |
| T2 |
1310 |
0 |
0 |
0 |
| T3 |
956 |
2 |
0 |
0 |
| T9 |
0 |
2 |
0 |
0 |
| T10 |
1410 |
2 |
0 |
0 |
| T11 |
3522 |
0 |
0 |
0 |
| T12 |
505 |
4 |
0 |
0 |
| T14 |
848 |
0 |
0 |
0 |
| T15 |
886 |
1 |
0 |
0 |
| T16 |
1002 |
0 |
0 |
0 |
| T17 |
950 |
3 |
0 |
0 |
| T18 |
1044 |
0 |
0 |
0 |
| T19 |
4322 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T32 |
604 |
2 |
0 |
0 |
| T33 |
0 |
4 |
0 |
0 |
| T34 |
5906 |
17 |
0 |
0 |
| T36 |
0 |
18 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
4 |
0 |
0 |
| T62 |
0 |
2 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T65 |
0 |
4 |
0 |
0 |
| T66 |
0 |
4 |
0 |
0 |
| T67 |
0 |
3 |
0 |
0 |
| T76 |
0 |
4 |
0 |
0 |
| T78 |
439 |
0 |
0 |
0 |
| T79 |
403 |
0 |
0 |
0 |
| T80 |
453 |
0 |
0 |
0 |
| T81 |
495 |
0 |
0 |
0 |
| T85 |
753 |
0 |
0 |
0 |
| T91 |
522 |
0 |
0 |
0 |
| T95 |
0 |
2 |
0 |
0 |
| T117 |
0 |
2 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
1724645 |
0 |
0 |
| T1 |
1018 |
46 |
0 |
0 |
| T2 |
1310 |
0 |
0 |
0 |
| T3 |
956 |
25 |
0 |
0 |
| T9 |
0 |
25 |
0 |
0 |
| T10 |
1410 |
25 |
0 |
0 |
| T11 |
3522 |
0 |
0 |
0 |
| T12 |
505 |
46 |
0 |
0 |
| T14 |
848 |
0 |
0 |
0 |
| T15 |
886 |
20 |
0 |
0 |
| T16 |
1002 |
0 |
0 |
0 |
| T17 |
950 |
41 |
0 |
0 |
| T18 |
1044 |
0 |
0 |
0 |
| T19 |
4322 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T32 |
604 |
30 |
0 |
0 |
| T33 |
0 |
95 |
0 |
0 |
| T34 |
5906 |
333 |
0 |
0 |
| T36 |
0 |
418 |
0 |
0 |
| T60 |
0 |
20 |
0 |
0 |
| T61 |
0 |
46 |
0 |
0 |
| T62 |
0 |
25 |
0 |
0 |
| T63 |
0 |
10 |
0 |
0 |
| T65 |
0 |
68 |
0 |
0 |
| T66 |
0 |
110 |
0 |
0 |
| T67 |
0 |
140 |
0 |
0 |
| T76 |
0 |
184 |
0 |
0 |
| T78 |
439 |
0 |
0 |
0 |
| T79 |
403 |
0 |
0 |
0 |
| T80 |
453 |
0 |
0 |
0 |
| T81 |
495 |
0 |
0 |
0 |
| T85 |
753 |
0 |
0 |
0 |
| T91 |
522 |
0 |
0 |
0 |
| T95 |
0 |
21 |
0 |
0 |
| T117 |
0 |
95 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
203774747 |
0 |
0 |
| T1 |
13234 |
2804 |
0 |
0 |
| T2 |
17030 |
6580 |
0 |
0 |
| T4 |
12922 |
2496 |
0 |
0 |
| T5 |
10790 |
364 |
0 |
0 |
| T6 |
10998 |
572 |
0 |
0 |
| T14 |
11024 |
598 |
0 |
0 |
| T15 |
11518 |
1091 |
0 |
0 |
| T16 |
13026 |
2600 |
0 |
0 |
| T17 |
12350 |
1921 |
0 |
0 |
| T23 |
19656 |
104 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
1561 |
0 |
0 |
| T22 |
1545 |
0 |
0 |
0 |
| T34 |
5906 |
1 |
0 |
0 |
| T35 |
24747 |
9 |
0 |
0 |
| T36 |
6770 |
1 |
0 |
0 |
| T46 |
24205 |
6 |
0 |
0 |
| T47 |
5038 |
9 |
0 |
0 |
| T58 |
0 |
18 |
0 |
0 |
| T67 |
737 |
0 |
0 |
0 |
| T71 |
492 |
0 |
0 |
0 |
| T72 |
525 |
0 |
0 |
0 |
| T96 |
0 |
26 |
0 |
0 |
| T98 |
0 |
21 |
0 |
0 |
| T99 |
440 |
0 |
0 |
0 |
| T100 |
502 |
0 |
0 |
0 |
| T101 |
507 |
0 |
0 |
0 |
| T102 |
424 |
0 |
0 |
0 |
| T109 |
0 |
6 |
0 |
0 |
| T118 |
0 |
5 |
0 |
0 |
| T119 |
0 |
1 |
0 |
0 |
| T120 |
0 |
6 |
0 |
0 |
| T121 |
0 |
3 |
0 |
0 |
| T122 |
0 |
4 |
0 |
0 |
| T123 |
0 |
1 |
0 |
0 |
| T124 |
0 |
13 |
0 |
0 |
| T125 |
0 |
4 |
0 |
0 |
| T126 |
0 |
8 |
0 |
0 |
| T127 |
0 |
3 |
0 |
0 |
| T128 |
0 |
5 |
0 |
0 |
| T129 |
0 |
7 |
0 |
0 |
| T130 |
817 |
0 |
0 |
0 |
| T131 |
427 |
0 |
0 |
0 |
| T132 |
1725 |
0 |
0 |
0 |
| T133 |
502 |
0 |
0 |
0 |
| T134 |
421 |
0 |
0 |
0 |
| T135 |
413 |
0 |
0 |
0 |
| T136 |
831 |
0 |
0 |
0 |
| T137 |
402 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
2375786 |
0 |
0 |
| T1 |
1018 |
87 |
0 |
0 |
| T2 |
1310 |
0 |
0 |
0 |
| T3 |
956 |
3 |
0 |
0 |
| T9 |
0 |
3 |
0 |
0 |
| T10 |
1410 |
3 |
0 |
0 |
| T11 |
3522 |
0 |
0 |
0 |
| T12 |
505 |
82 |
0 |
0 |
| T14 |
848 |
0 |
0 |
0 |
| T15 |
886 |
0 |
0 |
0 |
| T16 |
1002 |
0 |
0 |
0 |
| T17 |
950 |
49 |
0 |
0 |
| T18 |
1044 |
0 |
0 |
0 |
| T19 |
4322 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T32 |
604 |
2 |
0 |
0 |
| T33 |
0 |
19 |
0 |
0 |
| T34 |
5906 |
379 |
0 |
0 |
| T36 |
0 |
391 |
0 |
0 |
| T61 |
0 |
80 |
0 |
0 |
| T62 |
0 |
4 |
0 |
0 |
| T63 |
0 |
2 |
0 |
0 |
| T65 |
0 |
9 |
0 |
0 |
| T66 |
0 |
13 |
0 |
0 |
| T67 |
0 |
10 |
0 |
0 |
| T76 |
0 |
12 |
0 |
0 |
| T78 |
439 |
0 |
0 |
0 |
| T79 |
403 |
0 |
0 |
0 |
| T80 |
453 |
0 |
0 |
0 |
| T81 |
495 |
0 |
0 |
0 |
| T85 |
753 |
0 |
0 |
0 |
| T91 |
522 |
0 |
0 |
0 |
| T117 |
0 |
12 |
0 |
0 |
| T138 |
0 |
3 |
0 |
0 |
| T139 |
0 |
8 |
0 |
0 |
| T140 |
0 |
4 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
5401 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
1310 |
0 |
0 |
0 |
| T3 |
956 |
1 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
1410 |
1 |
0 |
0 |
| T11 |
3522 |
0 |
0 |
0 |
| T12 |
505 |
2 |
0 |
0 |
| T14 |
848 |
0 |
0 |
0 |
| T15 |
886 |
0 |
0 |
0 |
| T16 |
1002 |
0 |
0 |
0 |
| T17 |
950 |
1 |
0 |
0 |
| T18 |
1044 |
0 |
0 |
0 |
| T19 |
4322 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T32 |
604 |
1 |
0 |
0 |
| T33 |
0 |
2 |
0 |
0 |
| T34 |
5906 |
6 |
0 |
0 |
| T36 |
0 |
6 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T65 |
0 |
2 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T78 |
439 |
0 |
0 |
0 |
| T79 |
403 |
0 |
0 |
0 |
| T80 |
453 |
0 |
0 |
0 |
| T81 |
495 |
0 |
0 |
0 |
| T85 |
753 |
0 |
0 |
0 |
| T91 |
522 |
0 |
0 |
0 |
| T117 |
0 |
1 |
0 |
0 |
| T138 |
0 |
1 |
0 |
0 |
| T139 |
0 |
1 |
0 |
0 |
| T140 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
192294545 |
0 |
0 |
| T1 |
13234 |
2620 |
0 |
0 |
| T2 |
17030 |
4854 |
0 |
0 |
| T4 |
12922 |
2496 |
0 |
0 |
| T5 |
10790 |
364 |
0 |
0 |
| T6 |
10998 |
572 |
0 |
0 |
| T14 |
11024 |
598 |
0 |
0 |
| T15 |
11518 |
1053 |
0 |
0 |
| T16 |
13026 |
2600 |
0 |
0 |
| T17 |
12350 |
1806 |
0 |
0 |
| T23 |
19656 |
104 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
192340253 |
0 |
0 |
| T1 |
13234 |
2644 |
0 |
0 |
| T2 |
17030 |
4873 |
0 |
0 |
| T4 |
12922 |
2522 |
0 |
0 |
| T5 |
10790 |
390 |
0 |
0 |
| T6 |
10998 |
598 |
0 |
0 |
| T14 |
11024 |
624 |
0 |
0 |
| T15 |
11518 |
1078 |
0 |
0 |
| T16 |
13026 |
2626 |
0 |
0 |
| T17 |
12350 |
1830 |
0 |
0 |
| T23 |
19656 |
208 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
8241 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
1310 |
0 |
0 |
0 |
| T3 |
956 |
1 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
1410 |
1 |
0 |
0 |
| T11 |
3522 |
0 |
0 |
0 |
| T12 |
505 |
2 |
0 |
0 |
| T14 |
848 |
0 |
0 |
0 |
| T15 |
886 |
1 |
0 |
0 |
| T16 |
1002 |
0 |
0 |
0 |
| T17 |
950 |
2 |
0 |
0 |
| T18 |
1044 |
0 |
0 |
0 |
| T19 |
4322 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T32 |
604 |
1 |
0 |
0 |
| T33 |
0 |
2 |
0 |
0 |
| T34 |
5906 |
10 |
0 |
0 |
| T36 |
0 |
11 |
0 |
0 |
| T60 |
0 |
1 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T65 |
0 |
2 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
2 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T78 |
439 |
0 |
0 |
0 |
| T79 |
403 |
0 |
0 |
0 |
| T80 |
453 |
0 |
0 |
0 |
| T81 |
495 |
0 |
0 |
0 |
| T85 |
753 |
0 |
0 |
0 |
| T91 |
522 |
0 |
0 |
0 |
| T95 |
0 |
1 |
0 |
0 |
| T117 |
0 |
2 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
7776 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
1310 |
0 |
0 |
0 |
| T3 |
956 |
1 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
1410 |
1 |
0 |
0 |
| T11 |
3522 |
0 |
0 |
0 |
| T12 |
505 |
2 |
0 |
0 |
| T14 |
848 |
0 |
0 |
0 |
| T15 |
886 |
0 |
0 |
0 |
| T16 |
1002 |
0 |
0 |
0 |
| T17 |
950 |
1 |
0 |
0 |
| T18 |
1044 |
0 |
0 |
0 |
| T19 |
4322 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T32 |
604 |
1 |
0 |
0 |
| T33 |
0 |
2 |
0 |
0 |
| T34 |
5906 |
10 |
0 |
0 |
| T36 |
0 |
10 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T65 |
0 |
2 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T78 |
439 |
0 |
0 |
0 |
| T79 |
403 |
0 |
0 |
0 |
| T80 |
453 |
0 |
0 |
0 |
| T81 |
495 |
0 |
0 |
0 |
| T85 |
753 |
0 |
0 |
0 |
| T91 |
522 |
0 |
0 |
0 |
| T117 |
0 |
1 |
0 |
0 |
| T138 |
0 |
1 |
0 |
0 |
| T139 |
0 |
1 |
0 |
0 |
| T140 |
0 |
1 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
5401 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
1310 |
0 |
0 |
0 |
| T3 |
956 |
1 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
1410 |
1 |
0 |
0 |
| T11 |
3522 |
0 |
0 |
0 |
| T12 |
505 |
2 |
0 |
0 |
| T14 |
848 |
0 |
0 |
0 |
| T15 |
886 |
0 |
0 |
0 |
| T16 |
1002 |
0 |
0 |
0 |
| T17 |
950 |
1 |
0 |
0 |
| T18 |
1044 |
0 |
0 |
0 |
| T19 |
4322 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T32 |
604 |
1 |
0 |
0 |
| T33 |
0 |
2 |
0 |
0 |
| T34 |
5906 |
6 |
0 |
0 |
| T36 |
0 |
6 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T65 |
0 |
2 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T78 |
439 |
0 |
0 |
0 |
| T79 |
403 |
0 |
0 |
0 |
| T80 |
453 |
0 |
0 |
0 |
| T81 |
495 |
0 |
0 |
0 |
| T85 |
753 |
0 |
0 |
0 |
| T91 |
522 |
0 |
0 |
0 |
| T117 |
0 |
1 |
0 |
0 |
| T138 |
0 |
1 |
0 |
0 |
| T139 |
0 |
1 |
0 |
0 |
| T140 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
5401 |
0 |
0 |
| T1 |
1018 |
2 |
0 |
0 |
| T2 |
1310 |
0 |
0 |
0 |
| T3 |
956 |
1 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
1410 |
1 |
0 |
0 |
| T11 |
3522 |
0 |
0 |
0 |
| T12 |
505 |
2 |
0 |
0 |
| T14 |
848 |
0 |
0 |
0 |
| T15 |
886 |
0 |
0 |
0 |
| T16 |
1002 |
0 |
0 |
0 |
| T17 |
950 |
1 |
0 |
0 |
| T18 |
1044 |
0 |
0 |
0 |
| T19 |
4322 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T32 |
604 |
1 |
0 |
0 |
| T33 |
0 |
2 |
0 |
0 |
| T34 |
5906 |
6 |
0 |
0 |
| T36 |
0 |
6 |
0 |
0 |
| T61 |
0 |
2 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T65 |
0 |
2 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T78 |
439 |
0 |
0 |
0 |
| T79 |
403 |
0 |
0 |
0 |
| T80 |
453 |
0 |
0 |
0 |
| T81 |
495 |
0 |
0 |
0 |
| T85 |
753 |
0 |
0 |
0 |
| T91 |
522 |
0 |
0 |
0 |
| T117 |
0 |
1 |
0 |
0 |
| T138 |
0 |
1 |
0 |
0 |
| T139 |
0 |
1 |
0 |
0 |
| T140 |
0 |
1 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
215862426 |
2369718 |
0 |
0 |
| T1 |
1018 |
84 |
0 |
0 |
| T2 |
1310 |
0 |
0 |
0 |
| T3 |
956 |
2 |
0 |
0 |
| T9 |
0 |
2 |
0 |
0 |
| T10 |
1410 |
2 |
0 |
0 |
| T11 |
3522 |
0 |
0 |
0 |
| T12 |
505 |
79 |
0 |
0 |
| T14 |
848 |
0 |
0 |
0 |
| T15 |
886 |
0 |
0 |
0 |
| T16 |
1002 |
0 |
0 |
0 |
| T17 |
950 |
47 |
0 |
0 |
| T18 |
1044 |
0 |
0 |
0 |
| T19 |
4322 |
0 |
0 |
0 |
| T20 |
804 |
0 |
0 |
0 |
| T32 |
604 |
1 |
0 |
0 |
| T33 |
0 |
17 |
0 |
0 |
| T34 |
5906 |
373 |
0 |
0 |
| T36 |
0 |
385 |
0 |
0 |
| T61 |
0 |
77 |
0 |
0 |
| T62 |
0 |
3 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T65 |
0 |
7 |
0 |
0 |
| T66 |
0 |
11 |
0 |
0 |
| T67 |
0 |
9 |
0 |
0 |
| T76 |
0 |
10 |
0 |
0 |
| T78 |
439 |
0 |
0 |
0 |
| T79 |
403 |
0 |
0 |
0 |
| T80 |
453 |
0 |
0 |
0 |
| T81 |
495 |
0 |
0 |
0 |
| T85 |
753 |
0 |
0 |
0 |
| T91 |
522 |
0 |
0 |
0 |
| T117 |
0 |
11 |
0 |
0 |
| T138 |
0 |
2 |
0 |
0 |
| T139 |
0 |
7 |
0 |
0 |
| T140 |
0 |
3 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
74721609 |
40751 |
0 |
0 |
| T1 |
4581 |
3 |
0 |
0 |
| T2 |
5895 |
16 |
0 |
0 |
| T4 |
4473 |
75 |
0 |
0 |
| T5 |
3735 |
9 |
0 |
0 |
| T6 |
3807 |
17 |
0 |
0 |
| T7 |
0 |
2 |
0 |
0 |
| T14 |
3816 |
18 |
0 |
0 |
| T15 |
3987 |
3 |
0 |
0 |
| T16 |
4509 |
42 |
0 |
0 |
| T17 |
4275 |
3 |
0 |
0 |
| T18 |
0 |
35 |
0 |
0 |
| T19 |
0 |
38 |
0 |
0 |
| T23 |
6804 |
0 |
0 |
0 |
| T29 |
0 |
46 |
0 |
0 |
| T31 |
0 |
25 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
41512005 |
39200025 |
0 |
0 |
| T1 |
2545 |
545 |
0 |
0 |
| T2 |
3275 |
1275 |
0 |
0 |
| T4 |
2485 |
485 |
0 |
0 |
| T5 |
2075 |
75 |
0 |
0 |
| T6 |
2115 |
115 |
0 |
0 |
| T14 |
2120 |
120 |
0 |
0 |
| T15 |
2215 |
215 |
0 |
0 |
| T16 |
2505 |
505 |
0 |
0 |
| T17 |
2375 |
375 |
0 |
0 |
| T23 |
3780 |
40 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
141140817 |
133280085 |
0 |
0 |
| T1 |
8653 |
1853 |
0 |
0 |
| T2 |
11135 |
4335 |
0 |
0 |
| T4 |
8449 |
1649 |
0 |
0 |
| T5 |
7055 |
255 |
0 |
0 |
| T6 |
7191 |
391 |
0 |
0 |
| T14 |
7208 |
408 |
0 |
0 |
| T15 |
7531 |
731 |
0 |
0 |
| T16 |
8517 |
1717 |
0 |
0 |
| T17 |
8075 |
1275 |
0 |
0 |
| T23 |
12852 |
136 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
74721609 |
70560045 |
0 |
0 |
| T1 |
4581 |
981 |
0 |
0 |
| T2 |
5895 |
2295 |
0 |
0 |
| T4 |
4473 |
873 |
0 |
0 |
| T5 |
3735 |
135 |
0 |
0 |
| T6 |
3807 |
207 |
0 |
0 |
| T14 |
3816 |
216 |
0 |
0 |
| T15 |
3987 |
387 |
0 |
0 |
| T16 |
4509 |
909 |
0 |
0 |
| T17 |
4275 |
675 |
0 |
0 |
| T23 |
6804 |
72 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
190955223 |
4564 |
0 |
0 |
| T1 |
509 |
1 |
0 |
0 |
| T2 |
655 |
0 |
0 |
0 |
| T3 |
478 |
1 |
0 |
0 |
| T9 |
0 |
1 |
0 |
0 |
| T10 |
1410 |
1 |
0 |
0 |
| T11 |
3522 |
0 |
0 |
0 |
| T12 |
505 |
1 |
0 |
0 |
| T14 |
424 |
0 |
0 |
0 |
| T15 |
443 |
0 |
0 |
0 |
| T16 |
501 |
0 |
0 |
0 |
| T17 |
475 |
0 |
0 |
0 |
| T18 |
522 |
0 |
0 |
0 |
| T19 |
2161 |
0 |
0 |
0 |
| T20 |
402 |
0 |
0 |
0 |
| T32 |
604 |
1 |
0 |
0 |
| T33 |
0 |
2 |
0 |
0 |
| T34 |
5906 |
5 |
0 |
0 |
| T49 |
0 |
1 |
0 |
0 |
| T57 |
0 |
6 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T62 |
0 |
1 |
0 |
0 |
| T63 |
0 |
1 |
0 |
0 |
| T65 |
0 |
2 |
0 |
0 |
| T66 |
0 |
2 |
0 |
0 |
| T67 |
0 |
1 |
0 |
0 |
| T76 |
0 |
2 |
0 |
0 |
| T78 |
439 |
0 |
0 |
0 |
| T79 |
403 |
0 |
0 |
0 |
| T80 |
453 |
0 |
0 |
0 |
| T81 |
495 |
0 |
0 |
0 |
| T85 |
753 |
0 |
0 |
0 |
| T91 |
522 |
0 |
0 |
0 |
| T117 |
0 |
1 |
0 |
0 |
| T138 |
0 |
1 |
0 |
0 |
| T139 |
0 |
1 |
0 |
0 |
| T140 |
0 |
1 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
24907203 |
3042873 |
0 |
0 |
| T11 |
7044 |
791 |
0 |
0 |
| T12 |
1010 |
0 |
0 |
0 |
| T21 |
0 |
132 |
0 |
0 |
| T22 |
1545 |
1155 |
0 |
0 |
| T27 |
40124 |
0 |
0 |
0 |
| T35 |
24747 |
0 |
0 |
0 |
| T36 |
6770 |
0 |
0 |
0 |
| T60 |
882 |
0 |
0 |
0 |
| T73 |
0 |
269 |
0 |
0 |
| T74 |
0 |
301 |
0 |
0 |
| T75 |
0 |
347 |
0 |
0 |
| T76 |
0 |
261 |
0 |
0 |
| T77 |
0 |
907 |
0 |
0 |
| T78 |
878 |
0 |
0 |
0 |
| T79 |
806 |
0 |
0 |
0 |
| T80 |
906 |
0 |
0 |
0 |
| T81 |
990 |
0 |
0 |
0 |
| T82 |
1202 |
0 |
0 |
0 |
| T83 |
6128 |
0 |
0 |
0 |
| T88 |
491 |
0 |
0 |
0 |
| T100 |
502 |
0 |
0 |
0 |
| T101 |
507 |
0 |
0 |
0 |
| T102 |
424 |
0 |
0 |
0 |
| T104 |
0 |
113 |
0 |
0 |
| T107 |
0 |
199 |
0 |
0 |
| T141 |
0 |
1037596 |
0 |
0 |
| T142 |
0 |
772 |
0 |
0 |
| T143 |
0 |
165 |
0 |
0 |
| T144 |
0 |
90550 |
0 |
0 |
| T145 |
502 |
0 |
0 |
0 |
| T146 |
422 |
0 |
0 |
0 |
| T147 |
454 |
0 |
0 |
0 |
