Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T35 T36 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T17 T12 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T15 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T15 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T17 T12 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T17 T12 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T17 T12 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T17 T12 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T17 T12 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T17 T12 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T17 T12 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T17 T12 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T17 T12 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T17 T12 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T17 T12 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T17 T12 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T17 T12 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T17 T12 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T17 T12 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T17 T12 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T36 T108 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T17 T12 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T17 T12 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T17 T12 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T36 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T17 T12 
191        1/1                      state_d = StableSt;
           Tests:       T1 T17 T12 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T17 T12 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T17 T12 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T17 T12 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T17 T12 
206        1/1                    state_d = IdleSt;
           Tests:       T34 T36 T59 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T17 T12 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T17,T12

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T17,T12

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T17,T12

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T1,T17,T12

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T12
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T17,T12
0	1	Covered	T34,T36,T59
1	0	Covered	T36,T227

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T17,T12
1	-	Covered	T34,T36,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T17,T12
DetectSt	168	Covered	T1,T17,T12
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T17,T12

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T17,T12
DebounceSt->IdleSt	163	Covered	T34,T36,T108
DetectSt->IdleSt	186	Covered	T34,T35,T36
DetectSt->StableSt	191	Covered	T1,T17,T12
IdleSt->DebounceSt	148	Covered	T1,T17,T12
StableSt->IdleSt	206	Covered	T34,T36,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T17,T12
0	1	Covered	T1,T17,T12
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T17,T12
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T17,T12
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T17,T12
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T36,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T17,T12
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	0	1	-	Covered	T1,T17,T12
DetectSt	-	-	-	-	0	0	-	Covered	T1,T17,T12
StableSt	-	-	-	-	-	-	1	Covered	T34,T36,T59
StableSt	-	-	-	-	-	-	0	Covered	T1,T17,T12
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	2992	0	0
CntIncr_A	8302401	111099	0	0
CntNoWrap_A	8302401	7835114	0	0
DetectStDropOut_A	8302401	371	0	0
DetectedOut_A	8302401	81349	0	0
DetectedPulseOut_A	8302401	906	0	0
DisabledIdleSt_A	8302401	7352778	0	0
DisabledNoDetection_A	8302401	7354503	0	0
EnterDebounceSt_A	8302401	1503	0	0
EnterDetectSt_A	8302401	1489	0	0
EnterStableSt_A	8302401	906	0	0
PulseIsPulse_A	8302401	906	0	0
StayInStableSt	8302401	80355	0	0
gen_high_event_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_high_level_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_not_sticky_sva.StableStDropOut_A	8302401	806	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	2992	0	0
T1	509	2	0	0
T2	655	0	0	0
T3	478	0	0	0
T12	0	2	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	2	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	16	0	0
T35	0	58	0	0
T36	0	17	0	0
T59	0	34	0	0
T61	0	2	0	0
T95	0	2	0	0
T96	0	52	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	111099	0	0
T1	509	21	0	0
T2	655	0	0	0
T3	478	0	0	0
T12	0	21	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	21	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	326	0	0
T35	0	1786	0	0
T36	0	406	0	0
T59	0	714	0	0
T61	0	21	0	0
T95	0	21	0	0
T96	0	1668	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7835114	0	0
T1	509	106	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	72	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	371	0	0
T22	1545	0	0	0
T34	5906	1	0	0
T35	24747	9	0	0
T36	6770	1	0	0
T58	0	18	0	0
T71	492	0	0	0
T72	525	0	0	0
T96	0	26	0	0
T98	0	21	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T109	0	6	0	0
T122	0	4	0	0
T123	0	1	0	0
T127	0	3	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	81349	0	0
T1	509	84	0	0
T2	655	0	0	0
T3	478	0	0	0
T12	0	79	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	49	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	314	0	0
T36	0	308	0	0
T48	0	2058	0	0
T59	0	604	0	0
T61	0	77	0	0
T95	0	40	0	0
T97	0	70	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	906	0	0
T1	509	1	0	0
T2	655	0	0	0
T3	478	0	0	0
T12	0	1	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	1	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	5	0	0
T36	0	5	0	0
T48	0	19	0	0
T59	0	17	0	0
T61	0	1	0	0
T95	0	1	0	0
T97	0	5	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7352778	0	0
T1	509	3	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	4	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7354503	0	0
T1	509	3	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	4	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1503	0	0
T1	509	1	0	0
T2	655	0	0	0
T3	478	0	0	0
T12	0	1	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	1	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	9	0	0
T35	0	29	0	0
T36	0	10	0	0
T59	0	17	0	0
T61	0	1	0	0
T95	0	1	0	0
T96	0	26	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1489	0	0
T1	509	1	0	0
T2	655	0	0	0
T3	478	0	0	0
T12	0	1	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	1	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	7	0	0
T35	0	29	0	0
T36	0	7	0	0
T59	0	17	0	0
T61	0	1	0	0
T95	0	1	0	0
T96	0	26	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	906	0	0
T1	509	1	0	0
T2	655	0	0	0
T3	478	0	0	0
T12	0	1	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	1	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	5	0	0
T36	0	5	0	0
T48	0	19	0	0
T59	0	17	0	0
T61	0	1	0	0
T95	0	1	0	0
T97	0	5	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	906	0	0
T1	509	1	0	0
T2	655	0	0	0
T3	478	0	0	0
T12	0	1	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	1	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	5	0	0
T36	0	5	0	0
T48	0	19	0	0
T59	0	17	0	0
T61	0	1	0	0
T95	0	1	0	0
T97	0	5	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	80355	0	0
T1	509	82	0	0
T2	655	0	0	0
T3	478	0	0	0
T12	0	77	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	47	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	309	0	0
T36	0	303	0	0
T48	0	2035	0	0
T59	0	587	0	0
T61	0	75	0	0
T95	0	38	0	0
T97	0	65	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	806	0	0
T22	1545	0	0	0
T34	5906	5	0	0
T35	24747	0	0	0
T36	6770	4	0	0
T43	0	13	0	0
T45	0	19	0	0
T48	0	15	0	0
T59	0	17	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	5	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T228	0	2	0	0
T229	0	10	0	0
T230	0	19	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T15 T17 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T15 T17 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T15 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T15 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T15 T17 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T15 T17 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T15 T17 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T15 T17 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T15 T17 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T15 T17 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T15 T17 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T3 T9 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T15 T17 T60 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T3 T9 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T3 T9 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T3 T9 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T36 T46 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 T46 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T3 T9 
191        1/1                      state_d = StableSt;
           Tests:       T1 T3 T9 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T3 T9 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T3 T9 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T3 T9 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T3 T9 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T3 T9 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T3 T9 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T15,T17
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T17
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T15,T17

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T1,T3,T9

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T15,T17
1	0	Covered	T23,T19,T10
1	1	Covered	T1,T15,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T46,T47,T118
1	0	Covered	T34,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T3,T9
0	1	Covered	T1,T3,T9
1	0	Covered	T34,T36

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T3,T9
1	-	Covered	T1,T3,T9

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T15,T17
DetectSt	168	Covered	T1,T3,T9
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T1,T3,T9

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T3,T9
DebounceSt->IdleSt	163	Covered	T15,T17,T60
DetectSt->IdleSt	186	Covered	T34,T36,T46
DetectSt->StableSt	191	Covered	T1,T3,T9
IdleSt->DebounceSt	148	Covered	T1,T15,T17
StableSt->IdleSt	206	Covered	T1,T3,T9

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T15,T17
0	1	Covered	T1,T15,T17
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T3,T9
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T15,T17
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T3,T9
DebounceSt	-	0	1	0	-	-	-	Covered	T15,T17,T60
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T15,T17
DetectSt	-	-	-	-	1	-	-	Covered	T34,T36,T46
DetectSt	-	-	-	-	0	1	-	Covered	T1,T3,T9
DetectSt	-	-	-	-	0	0	-	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	1	Covered	T1,T3,T9
StableSt	-	-	-	-	-	-	0	Covered	T1,T3,T9
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	824	0	0
CntIncr_A	8302401	45700	0	0
CntNoWrap_A	8302401	7837282	0	0
DetectStDropOut_A	8302401	82	0	0
DetectedOut_A	8302401	14980	0	0
DetectedPulseOut_A	8302401	302	0	0
DisabledIdleSt_A	8302401	7482994	0	0
DisabledNoDetection_A	8302401	7484269	0	0
EnterDebounceSt_A	8302401	436	0	0
EnterDetectSt_A	8302401	388	0	0
EnterStableSt_A	8302401	302	0	0
PulseIsPulse_A	8302401	302	0	0
StayInStableSt	8302401	14654	0	0
gen_high_level_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_not_sticky_sva.StableStDropOut_A	8302401	275	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	824	0	0
T1	509	2	0	0
T2	655	0	0	0
T3	478	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	424	0	0	0
T15	443	1	0	0
T16	501	0	0	0
T17	475	1	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T60	0	1	0	0
T61	0	2	0	0
T62	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	45700	0	0
T1	509	25	0	0
T2	655	0	0	0
T3	478	25	0	0
T9	0	25	0	0
T10	0	25	0	0
T12	0	25	0	0
T14	424	0	0	0
T15	443	20	0	0
T16	501	0	0	0
T17	475	20	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T60	0	20	0	0
T61	0	25	0	0
T62	0	25	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7837282	0	0
T1	509	106	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	41	0	0
T16	501	100	0	0
T17	475	73	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	82	0	0
T46	24205	6	0	0
T47	0	2	0	0
T67	737	0	0	0
T118	0	2	0	0
T120	0	6	0	0
T121	0	3	0	0
T124	0	13	0	0
T125	0	2	0	0
T126	0	8	0	0
T128	0	5	0	0
T129	0	7	0	0
T130	817	0	0	0
T131	427	0	0	0
T132	1725	0	0	0
T133	502	0	0	0
T134	421	0	0	0
T135	413	0	0	0
T136	831	0	0	0
T137	402	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	14980	0	0
T1	509	3	0	0
T2	655	0	0	0
T3	478	3	0	0
T9	0	3	0	0
T10	0	3	0	0
T12	0	3	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	65	0	0
T36	0	83	0	0
T61	0	3	0	0
T62	0	4	0	0
T138	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	302	0	0
T1	509	1	0	0
T2	655	0	0	0
T3	478	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T138	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7482994	0	0
T1	509	25	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	3	0	0
T16	501	100	0	0
T17	475	26	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7484269	0	0
T1	509	25	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	3	0	0
T16	501	101	0	0
T17	475	26	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	436	0	0
T1	509	1	0	0
T2	655	0	0	0
T3	478	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	424	0	0	0
T15	443	1	0	0
T16	501	0	0	0
T17	475	1	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	388	0	0
T1	509	1	0	0
T2	655	0	0	0
T3	478	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	3	0	0
T36	0	3	0	0
T61	0	1	0	0
T62	0	1	0	0
T138	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	302	0	0
T1	509	1	0	0
T2	655	0	0	0
T3	478	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T138	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	302	0	0
T1	509	1	0	0
T2	655	0	0	0
T3	478	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	1	0	0
T36	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T138	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	14654	0	0
T1	509	2	0	0
T2	655	0	0	0
T3	478	2	0	0
T9	0	2	0	0
T10	0	2	0	0
T12	0	2	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T34	0	64	0	0
T36	0	82	0	0
T61	0	2	0	0
T62	0	3	0	0
T138	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	275	0	0
T1	509	1	0	0
T2	655	0	0	0
T3	478	1	0	0
T9	0	1	0	0
T10	0	1	0	0
T12	0	1	0	0
T14	424	0	0	0
T15	443	0	0	0
T16	501	0	0	0
T17	475	0	0	0
T18	522	0	0	0
T19	2161	0	0	0
T20	402	0	0	0
T49	0	1	0	0
T57	0	6	0	0
T61	0	1	0	0
T62	0	1	0	0
T138	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T35 T36 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T35 T36 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T15 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T15 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T34 T35 T36 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T34 T35 T36 
129        1/1              cnt_en = 1'b0;
           Tests:       T34 T35 T36 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T34 T35 T36 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T34 T35 T36 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T34 T35 T36 
139                     
140        1/1              unique case (state_q)
           Tests:       T34 T35 T36 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T34 T35 T36 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T35 T36 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T35 T36 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T35 T36 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T35 T36 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T35 T36 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T35 T36 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T36 T108 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T35 T36 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T35 T36 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T36 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T35 T36 
191        1/1                      state_d = StableSt;
           Tests:       T34 T36 T59 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T34 T36 T59 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T34 T36 T59 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T34 T36 T59 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T34 T36 T59 
206        1/1                    state_d = IdleSt;
           Tests:       T34 T36 T59 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T34 T36 T59 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T36,T59
0	1	Covered	T34,T36,T59
1	0	Covered	T34

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T36,T59
1	-	Covered	T34,T36,T59

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T34,T36,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T34,T36,T108
DetectSt->IdleSt	186	Covered	T34,T35,T36
DetectSt->StableSt	191	Covered	T34,T36,T59
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T34,T36,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T36,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	0	1	-	Covered	T34,T36,T59
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	1	Covered	T34,T36,T59
StableSt	-	-	-	-	-	-	0	Covered	T34,T36,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	2681	0	0
CntIncr_A	8302401	101455	0	0
CntNoWrap_A	8302401	7835425	0	0
DetectStDropOut_A	8302401	344	0	0
DetectedOut_A	8302401	68387	0	0
DetectedPulseOut_A	8302401	809	0	0
DisabledIdleSt_A	8302401	7364432	0	0
DisabledNoDetection_A	8302401	7366168	0	0
EnterDebounceSt_A	8302401	1347	0	0
EnterDetectSt_A	8302401	1334	0	0
EnterStableSt_A	8302401	809	0	0
PulseIsPulse_A	8302401	809	0	0
StayInStableSt	8302401	67502	0	0
gen_high_event_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_high_level_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_not_sticky_sva.StableStDropOut_A	8302401	732	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	2681	0	0
T22	1545	0	0	0
T34	5906	17	0	0
T35	24747	38	0	0
T36	6770	16	0	0
T43	0	24	0	0
T48	0	20	0	0
T58	0	46	0	0
T59	0	44	0	0
T71	492	0	0	0
T72	525	0	0	0
T96	0	28	0	0
T97	0	56	0	0
T98	0	22	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	101455	0	0
T22	1545	0	0	0
T34	5906	223	0	0
T35	24747	1178	0	0
T36	6770	431	0	0
T43	0	3132	0	0
T48	0	650	0	0
T58	0	1391	0	0
T59	0	1650	0	0
T71	492	0	0	0
T72	525	0	0	0
T96	0	892	0	0
T97	0	1372	0	0
T98	0	665	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7835425	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	344	0	0
T22	1545	0	0	0
T34	5906	1	0	0
T35	24747	11	0	0
T36	6770	1	0	0
T58	0	17	0	0
T71	492	0	0	0
T72	525	0	0	0
T96	0	14	0	0
T98	0	11	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T108	0	3	0	0
T123	0	1	0	0
T231	0	6	0	0
T232	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	68387	0	0
T22	1545	0	0	0
T34	5906	248	0	0
T35	24747	0	0	0
T36	6770	359	0	0
T43	0	1243	0	0
T45	0	3152	0	0
T48	0	747	0	0
T59	0	755	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	2737	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	266	0	0
T228	0	2457	0	0
T229	0	202	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	809	0	0
T22	1545	0	0	0
T34	5906	5	0	0
T35	24747	0	0	0
T36	6770	5	0	0
T43	0	12	0	0
T45	0	26	0	0
T48	0	10	0	0
T59	0	22	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	28	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	10	0	0
T228	0	20	0	0
T229	0	7	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7364432	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7366168	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1347	0	0
T22	1545	0	0	0
T34	5906	10	0	0
T35	24747	19	0	0
T36	6770	9	0	0
T43	0	12	0	0
T48	0	10	0	0
T58	0	23	0	0
T59	0	22	0	0
T71	492	0	0	0
T72	525	0	0	0
T96	0	14	0	0
T97	0	28	0	0
T98	0	11	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1334	0	0
T22	1545	0	0	0
T34	5906	7	0	0
T35	24747	19	0	0
T36	6770	7	0	0
T43	0	12	0	0
T48	0	10	0	0
T58	0	23	0	0
T59	0	22	0	0
T71	492	0	0	0
T72	525	0	0	0
T96	0	14	0	0
T97	0	28	0	0
T98	0	11	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	809	0	0
T22	1545	0	0	0
T34	5906	5	0	0
T35	24747	0	0	0
T36	6770	5	0	0
T43	0	12	0	0
T45	0	26	0	0
T48	0	10	0	0
T59	0	22	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	28	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	10	0	0
T228	0	20	0	0
T229	0	7	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	809	0	0
T22	1545	0	0	0
T34	5906	5	0	0
T35	24747	0	0	0
T36	6770	5	0	0
T43	0	12	0	0
T45	0	26	0	0
T48	0	10	0	0
T59	0	22	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	28	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	10	0	0
T228	0	20	0	0
T229	0	7	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	67502	0	0
T22	1545	0	0	0
T34	5906	243	0	0
T35	24747	0	0	0
T36	6770	354	0	0
T43	0	1230	0	0
T45	0	3122	0	0
T48	0	736	0	0
T59	0	730	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	2703	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	255	0	0
T228	0	2435	0	0
T229	0	194	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	732	0	0
T22	1545	0	0	0
T34	5906	4	0	0
T35	24747	0	0	0
T36	6770	5	0	0
T43	0	11	0	0
T45	0	22	0	0
T48	0	9	0	0
T59	0	19	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	22	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	9	0	0
T228	0	18	0	0
T229	0	6	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T36 T46 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T15 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T15 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T36 T59 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T36 T59 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T36 T59 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T36 T59 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T36 T59 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 T59 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T36 T59 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T36 T59 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T103 T120 T233 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T36 T59 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T36 T59 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T36 T59 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T36 T47 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 T47 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T36 T59 
191        1/1                      state_d = StableSt;
           Tests:       T34 T36 T59 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T34 T36 T59 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T34 T36 T59 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T34 T36 T59 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T34 T36 T59 
206        1/1                    state_d = IdleSt;
           Tests:       T34 T36 T57 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T34 T36 T59 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T36,T59

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T36,T59

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T36,T59

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T23,T19,T10
1	1	Covered	T34,T36,T59

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T36,T59
0	1	Covered	T47,T118,T119
1	0	Covered	T34,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T36,T59
0	1	Covered	T34,T57,T103
1	0	Covered	T36,T109

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T36,T59
1	-	Covered	T34,T57,T103

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T36,T59
DetectSt	168	Covered	T34,T36,T59
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T34,T36,T59

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T36,T59
DebounceSt->IdleSt	163	Covered	T34,T36,T103
DetectSt->IdleSt	186	Covered	T34,T36,T47
DetectSt->StableSt	191	Covered	T34,T36,T59
IdleSt->DebounceSt	148	Covered	T34,T36,T59
StableSt->IdleSt	206	Covered	T34,T36,T59

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T36,T59
0	1	Covered	T34,T36,T59
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T36,T59
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T36,T59
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T36,T59
DebounceSt	-	0	1	0	-	-	-	Covered	T103,T120,T233
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T36,T59
DetectSt	-	-	-	-	1	-	-	Covered	T34,T36,T47
DetectSt	-	-	-	-	0	1	-	Covered	T34,T36,T59
DetectSt	-	-	-	-	0	0	-	Covered	T34,T36,T59
StableSt	-	-	-	-	-	-	1	Covered	T34,T36,T57
StableSt	-	-	-	-	-	-	0	Covered	T34,T36,T59
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	787	0	0
CntIncr_A	8302401	43447	0	0
CntNoWrap_A	8302401	7837319	0	0
DetectStDropOut_A	8302401	62	0	0
DetectedOut_A	8302401	11813	0	0
DetectedPulseOut_A	8302401	312	0	0
DisabledIdleSt_A	8302401	7491127	0	0
DisabledNoDetection_A	8302401	7492429	0	0
EnterDebounceSt_A	8302401	409	0	0
EnterDetectSt_A	8302401	378	0	0
EnterStableSt_A	8302401	312	0	0
PulseIsPulse_A	8302401	312	0	0
StayInStableSt	8302401	11474	0	0
gen_high_level_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_not_sticky_sva.StableStDropOut_A	8302401	282	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	787	0	0
T22	1545	0	0	0
T34	5906	8	0	0
T35	24747	0	0	0
T36	6770	8	0	0
T43	0	2	0	0
T44	0	14	0	0
T47	0	14	0	0
T57	0	4	0	0
T59	0	6	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	12	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	13	0	0
T118	0	6	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	43447	0	0
T22	1545	0	0	0
T34	5906	115	0	0
T35	24747	0	0	0
T36	6770	207	0	0
T43	0	260	0	0
T44	0	1365	0	0
T47	0	542	0	0
T57	0	176	0	0
T59	0	210	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	384	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	709	0	0
T118	0	279	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7837319	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	62	0	0
T47	5038	7	0	0
T55	2949	0	0	0
T118	0	3	0	0
T119	0	1	0	0
T125	0	2	0	0
T143	1554	0	0	0
T169	0	1	0	0
T175	761	0	0	0
T234	0	3	0	0
T235	0	19	0	0
T236	0	1	0	0
T237	0	3	0	0
T238	0	10	0	0
T239	496	0	0	0
T240	426	0	0	0
T241	4401	0	0	0
T242	452	0	0	0
T243	622	0	0	0
T244	599	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	11813	0	0
T22	1545	0	0	0
T34	5906	66	0	0
T35	24747	0	0	0
T36	6770	83	0	0
T43	0	260	0	0
T44	0	68	0	0
T57	0	108	0	0
T59	0	123	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	376	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	40	0	0
T120	0	50	0	0
T245	0	201	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	312	0	0
T22	1545	0	0	0
T34	5906	1	0	0
T35	24747	0	0	0
T36	6770	1	0	0
T43	0	1	0	0
T44	0	7	0	0
T57	0	2	0	0
T59	0	3	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	6	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	6	0	0
T120	0	8	0	0
T245	0	4	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7491127	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7492429	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	409	0	0
T22	1545	0	0	0
T34	5906	5	0	0
T35	24747	0	0	0
T36	6770	5	0	0
T43	0	1	0	0
T44	0	7	0	0
T47	0	7	0	0
T57	0	2	0	0
T59	0	3	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	6	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	7	0	0
T118	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	378	0	0
T22	1545	0	0	0
T34	5906	3	0	0
T35	24747	0	0	0
T36	6770	3	0	0
T43	0	1	0	0
T44	0	7	0	0
T47	0	7	0	0
T57	0	2	0	0
T59	0	3	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	6	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	6	0	0
T118	0	3	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	312	0	0
T22	1545	0	0	0
T34	5906	1	0	0
T35	24747	0	0	0
T36	6770	1	0	0
T43	0	1	0	0
T44	0	7	0	0
T57	0	2	0	0
T59	0	3	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	6	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	6	0	0
T120	0	8	0	0
T245	0	4	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	312	0	0
T22	1545	0	0	0
T34	5906	1	0	0
T35	24747	0	0	0
T36	6770	1	0	0
T43	0	1	0	0
T44	0	7	0	0
T57	0	2	0	0
T59	0	3	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	6	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	6	0	0
T120	0	8	0	0
T245	0	4	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	11474	0	0
T22	1545	0	0	0
T34	5906	65	0	0
T35	24747	0	0	0
T36	6770	82	0	0
T43	0	259	0	0
T44	0	61	0	0
T57	0	106	0	0
T59	0	117	0	0
T71	492	0	0	0
T72	525	0	0	0
T97	0	364	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	34	0	0
T120	0	42	0	0
T245	0	197	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	282	0	0
T22	1545	0	0	0
T34	5906	1	0	0
T35	24747	0	0	0
T36	6770	0	0	0
T43	0	1	0	0
T44	0	7	0	0
T45	0	4	0	0
T57	0	2	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	6	0	0
T120	0	8	0	0
T121	0	3	0	0
T233	0	5	0	0
T245	0	4	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T34 T35 T36 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T35 T36 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T15 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T15 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T34 T35 T36 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T34 T35 T36 
129        1/1              cnt_en = 1'b0;
           Tests:       T34 T35 T36 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T34 T35 T36 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T34 T35 T36 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T34 T35 T36 
139                     
140        1/1              unique case (state_q)
           Tests:       T34 T35 T36 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T34 T35 T36 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T35 T36 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T35 T36 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T35 T36 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T35 T36 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T35 T36 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T35 T36 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T34 T36 T108 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T35 T36 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T35 T36 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T36 T96 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 T96 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T35 T36 
191        1/1                      state_d = StableSt;
           Tests:       T34 T35 T36 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T34 T35 T36 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T34 T35 T36 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T34 T35 T36 
206        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T36 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T34 T35 T36 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T34,T35,T36
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T34,T36,T96
1	0	Covered	T34,T36,T97

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
1	0	Covered	T113,T246

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T35,T36
1	-	Covered	T34,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T34,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T34,T36,T108
DetectSt->IdleSt	186	Covered	T34,T36,T96
DetectSt->StableSt	191	Covered	T34,T35,T36
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T34,T35,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T34,T35,T36
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T34,T36,T108
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T34,T36,T96
DetectSt	-	-	-	-	0	1	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	1	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T34,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	2907	0	0
CntIncr_A	8302401	109301	0	0
CntNoWrap_A	8302401	7835199	0	0
DetectStDropOut_A	8302401	295	0	0
DetectedOut_A	8302401	88494	0	0
DetectedPulseOut_A	8302401	922	0	0
DisabledIdleSt_A	8302401	7344082	0	0
DisabledNoDetection_A	8302401	7345786	0	0
EnterDebounceSt_A	8302401	1463	0	0
EnterDetectSt_A	8302401	1444	0	0
EnterStableSt_A	8302401	922	0	0
PulseIsPulse_A	8302401	922	0	0
StayInStableSt	8302401	87465	0	0
gen_high_event_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_high_level_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_not_sticky_sva.StableStDropOut_A	8302401	798	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	2907	0	0
T22	1545	0	0	0
T34	5906	16	0	0
T35	24747	40	0	0
T36	6770	16	0	0
T43	0	52	0	0
T48	0	20	0	0
T58	0	28	0	0
T59	0	60	0	0
T71	492	0	0	0
T72	525	0	0	0
T96	0	12	0	0
T97	0	14	0	0
T98	0	12	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	109301	0	0
T22	1545	0	0	0
T34	5906	389	0	0
T35	24747	1180	0	0
T36	6770	502	0	0
T43	0	7072	0	0
T48	0	910	0	0
T58	0	644	0	0
T59	0	1710	0	0
T71	492	0	0	0
T72	525	0	0	0
T96	0	379	0	0
T97	0	494	0	0
T98	0	362	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7835199	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	295	0	0
T22	1545	0	0	0
T34	5906	1	0	0
T35	24747	0	0	0
T36	6770	1	0	0
T71	492	0	0	0
T72	525	0	0	0
T96	0	6	0	0
T98	0	6	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T109	0	14	0	0
T231	0	6	0	0
T247	0	3	0	0
T248	0	10	0	0
T249	0	22	0	0
T250	0	24	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	88494	0	0
T22	1545	0	0	0
T34	5906	251	0	0
T35	24747	2748	0	0
T36	6770	349	0	0
T43	0	4425	0	0
T45	0	582	0	0
T48	0	487	0	0
T58	0	1801	0	0
T59	0	1677	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	1848	0	0
T228	0	410	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	922	0	0
T22	1545	0	0	0
T34	5906	5	0	0
T35	24747	20	0	0
T36	6770	5	0	0
T43	0	26	0	0
T45	0	5	0	0
T48	0	10	0	0
T58	0	14	0	0
T59	0	30	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	22	0	0
T228	0	6	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7344082	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7345786	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1463	0	0
T22	1545	0	0	0
T34	5906	9	0	0
T35	24747	20	0	0
T36	6770	9	0	0
T43	0	26	0	0
T48	0	10	0	0
T58	0	14	0	0
T59	0	30	0	0
T71	492	0	0	0
T72	525	0	0	0
T96	0	6	0	0
T97	0	7	0	0
T98	0	6	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	1444	0	0
T22	1545	0	0	0
T34	5906	7	0	0
T35	24747	20	0	0
T36	6770	7	0	0
T43	0	26	0	0
T48	0	10	0	0
T58	0	14	0	0
T59	0	30	0	0
T71	492	0	0	0
T72	525	0	0	0
T96	0	6	0	0
T97	0	7	0	0
T98	0	6	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	922	0	0
T22	1545	0	0	0
T34	5906	5	0	0
T35	24747	20	0	0
T36	6770	5	0	0
T43	0	26	0	0
T45	0	5	0	0
T48	0	10	0	0
T58	0	14	0	0
T59	0	30	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	22	0	0
T228	0	6	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	922	0	0
T22	1545	0	0	0
T34	5906	5	0	0
T35	24747	20	0	0
T36	6770	5	0	0
T43	0	26	0	0
T45	0	5	0	0
T48	0	10	0	0
T58	0	14	0	0
T59	0	30	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	22	0	0
T228	0	6	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	87465	0	0
T22	1545	0	0	0
T34	5906	246	0	0
T35	24747	2720	0	0
T36	6770	344	0	0
T43	0	4397	0	0
T45	0	576	0	0
T48	0	476	0	0
T58	0	1784	0	0
T59	0	1646	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	1826	0	0
T228	0	403	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	798	0	0
T22	1545	0	0	0
T34	5906	5	0	0
T35	24747	12	0	0
T36	6770	5	0	0
T43	0	24	0	0
T45	0	4	0	0
T48	0	9	0	0
T58	0	11	0	0
T59	0	29	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T122	0	22	0	0
T228	0	5	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T34 T35 T36 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T4 T5 T6 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T4 T5 T6 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T4 T5 T6 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T5 T6 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T34 T35 T36 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T15 T2 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T15 T2 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
105        1/1                cnt_q <= '0;
           Tests:       T4 T5 T6 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T4 T5 T6 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T5 T6 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T5 T6 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T5 T6 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T5 T6 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T5 T6 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T5 T6 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T5 T6 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T5 T6 
148        1/1                    state_d = DebounceSt;
           Tests:       T34 T35 T36 
149        1/1                    cnt_en = 1'b1;
           Tests:       T34 T35 T36 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T34 T35 T36 
163        1/1                    state_d = IdleSt;
           Tests:       T34 T36 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 
165        1/1                  end else if (cnt_done) begin
           Tests:       T34 T35 T36 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
167        1/1                    if (trigger_active) begin
           Tests:       T34 T35 T36 
168        1/1                      state_d = DetectSt;
           Tests:       T34 T35 T36 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T46 T103 T47 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T34 T35 T36 
182        1/1                  cnt_en = 1'b1;
           Tests:       T34 T35 T36 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T34 T35 T36 
186        1/1                    state_d = IdleSt;
           Tests:       T34 T36 T103 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T34 T36 T103 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T34 T35 T36 
191        1/1                      state_d = StableSt;
           Tests:       T34 T35 T36 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T34 T35 T36 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T34 T35 T36 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T34 T35 T36 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T34 T35 T36 
206        1/1                    state_d = IdleSt;
           Tests:       T34 T35 T36 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T34 T35 T36 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T4 T5 T6 
220        1/1                state_q <= IdleSt;
           Tests:       T4 T5 T6 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T4 T5 T6 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T34,T35,T36
1	Covered	T4,T5,T6

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T4,T5,T6
1	1	Covered	T4,T5,T6

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T4,T5,T6
1	Covered	T34,T35,T36

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T34,T35,T36
1	0	Covered	T23,T19,T10
1	1	Covered	T34,T35,T36

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T103,T124,T251
1	0	Covered	T34,T36

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T34,T35,T36
0	1	Covered	T35,T46,T59
1	0	Not Covered

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T34,T35,T36
1	-	Covered	T34,T35,T36

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T34,T35,T36
DetectSt	168	Covered	T34,T35,T36
IdleSt	163	Covered	T4,T5,T6
StableSt	191	Covered	T34,T35,T36

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T34,T35,T36
DebounceSt->IdleSt	163	Covered	T34,T36,T46
DetectSt->IdleSt	186	Covered	T34,T36,T103
DetectSt->StableSt	191	Covered	T34,T35,T36
IdleSt->DebounceSt	148	Covered	T34,T35,T36
StableSt->IdleSt	206	Covered	T34,T35,T36

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T34,T35,T36
0	1	Covered	T34,T35,T36
0	0	Covered	T4,T5,T6

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T34,T35,T36
0	Covered	T4,T5,T6

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T34,T35,T36
IdleSt	0	-	-	-	-	-	-	Covered	T4,T5,T6
DebounceSt	-	1	-	-	-	-	-	Covered	T34,T36
DebounceSt	-	0	1	1	-	-	-	Covered	T34,T35,T36
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T103,T47
DebounceSt	-	0	0	-	-	-	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	1	-	-	Covered	T34,T36,T103
DetectSt	-	-	-	-	0	1	-	Covered	T34,T35,T36
DetectSt	-	-	-	-	0	0	-	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	1	Covered	T34,T35,T36
StableSt	-	-	-	-	-	-	0	Covered	T34,T35,T36
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T4,T5,T6
0	Covered	T4,T5,T6

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	8302401	817	0	0
CntIncr_A	8302401	43607	0	0
CntNoWrap_A	8302401	7837289	0	0
DetectStDropOut_A	8302401	54	0	0
DetectedOut_A	8302401	14871	0	0
DetectedPulseOut_A	8302401	328	0	0
DisabledIdleSt_A	8302401	7467845	0	0
DisabledNoDetection_A	8302401	7469108	0	0
EnterDebounceSt_A	8302401	431	0	0
EnterDetectSt_A	8302401	386	0	0
EnterStableSt_A	8302401	328	0	0
PulseIsPulse_A	8302401	328	0	0
StayInStableSt	8302401	14510	0	0
gen_high_level_sva.HighLevelEvent_A	8302401	7840005	0	0
gen_not_sticky_sva.StableStDropOut_A	8302401	292	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	817	0	0
T22	1545	0	0	0
T34	5906	8	0	0
T35	24747	16	0	0
T36	6770	8	0	0
T46	0	5	0	0
T47	0	7	0	0
T48	0	2	0	0
T57	0	4	0	0
T58	0	6	0	0
T59	0	2	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	21	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	43607	0	0
T22	1545	0	0	0
T34	5906	116	0	0
T35	24747	448	0	0
T36	6770	199	0	0
T46	0	170	0	0
T47	0	151	0	0
T48	0	88	0	0
T57	0	250	0	0
T58	0	213	0	0
T59	0	72	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	1224	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7837289	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	54	0	0
T103	6046	10	0	0
T116	768	0	0	0
T124	0	2	0	0
T129	0	1	0	0
T226	550	0	0	0
T235	0	9	0	0
T237	0	2	0	0
T251	0	3	0	0
T252	0	10	0	0
T253	0	7	0	0
T254	0	2	0	0
T255	0	3	0	0
T256	403	0	0	0
T257	424	0	0	0
T258	934	0	0	0
T259	929	0	0	0
T260	525	0	0	0
T261	505	0	0	0
T262	1304	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	14871	0	0
T22	1545	0	0	0
T34	5906	67	0	0
T35	24747	636	0	0
T36	6770	83	0	0
T46	0	14	0	0
T47	0	112	0	0
T48	0	42	0	0
T57	0	34	0	0
T58	0	139	0	0
T59	0	41	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T118	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	328	0	0
T22	1545	0	0	0
T34	5906	1	0	0
T35	24747	8	0	0
T36	6770	1	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	1	0	0
T57	0	2	0	0
T58	0	3	0	0
T59	0	1	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T118	0	2	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7467845	0	0
T1	509	108	0	0
T2	655	254	0	0
T4	497	96	0	0
T5	415	14	0	0
T6	423	22	0	0
T14	424	23	0	0
T15	443	42	0	0
T16	501	100	0	0
T17	475	74	0	0
T23	756	4	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7469108	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	431	0	0
T22	1545	0	0	0
T34	5906	5	0	0
T35	24747	8	0	0
T36	6770	5	0	0
T46	0	3	0	0
T47	0	4	0	0
T48	0	1	0	0
T57	0	2	0	0
T58	0	3	0	0
T59	0	1	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	11	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	386	0	0
T22	1545	0	0	0
T34	5906	3	0	0
T35	24747	8	0	0
T36	6770	3	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	1	0	0
T57	0	2	0	0
T58	0	3	0	0
T59	0	1	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T103	0	10	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	328	0	0
T22	1545	0	0	0
T34	5906	1	0	0
T35	24747	8	0	0
T36	6770	1	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	1	0	0
T57	0	2	0	0
T58	0	3	0	0
T59	0	1	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T118	0	2	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	328	0	0
T22	1545	0	0	0
T34	5906	1	0	0
T35	24747	8	0	0
T36	6770	1	0	0
T46	0	2	0	0
T47	0	3	0	0
T48	0	1	0	0
T57	0	2	0	0
T58	0	3	0	0
T59	0	1	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T118	0	2	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	14510	0	0
T22	1545	0	0	0
T34	5906	66	0	0
T35	24747	620	0	0
T36	6770	82	0	0
T46	0	12	0	0
T47	0	109	0	0
T48	0	41	0	0
T57	0	32	0	0
T58	0	133	0	0
T59	0	40	0	0
T71	492	0	0	0
T72	525	0	0	0
T99	440	0	0	0
T100	502	0	0	0
T101	507	0	0	0
T102	424	0	0	0
T118	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	7840005	0	0
T1	509	109	0	0
T2	655	255	0	0
T4	497	97	0	0
T5	415	15	0	0
T6	423	23	0	0
T14	424	24	0	0
T15	443	43	0	0
T16	501	101	0	0
T17	475	75	0	0
T23	756	8	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	8302401	292	0	0
T43	0	2	0	0
T44	0	4	0	0
T45	0	1	0	0
T46	24205	2	0	0
T47	0	3	0	0
T48	0	1	0	0
T57	0	2	0	0
T59	0	1	0	0
T67	737	0	0	0
T118	0	2	0	0
T130	817	0	0	0
T131	427	0	0	0
T132	1725	0	0	0
T133	502	0	0	0
T134	421	0	0	0
T135	413	0	0	0
T136	831	0	0	0
T137	402	0	0	0
T245	0	1	0	0