ASSERT | PROPERTIES | SEQUENCES | |
Total | 1028 | 0 | 10 |
Category 0 | 1028 | 0 | 10 |
ASSERT | PROPERTIES | SEQUENCES | |
Total | 1028 | 0 | 10 |
Severity 0 | 1028 | 0 | 10 |
NUMBER | PERCENT | |
Total Number | 1028 | 100.00 |
Uncovered | 8 | 0.78 |
Success | 1020 | 99.22 |
Failure | 0 | 0.00 |
Incomplete | 1 | 0.10 |
Without Attempts | 0 | 0.00 |
NUMBER | PERCENT | |
Total Number | 10 | 100.00 |
Uncovered | 0 | 0.00 |
All Matches | 10 | 100.00 |
First Matches | 10 | 100.00 |
ASSERTIONS | CATEGORY | SEVERITY | ATTEMPTS | REAL SUCCESSES | FAILURES | INCOMPLETE | SRC |
tb.dut.u_reg.u_wkup_status_cdc.u_arb.gen_wr_req.DstUpdateReqCheck_A | 0 | 0 | 6093881 | 668 | 0 | 914 |
COVER SEQUENCES | CATEGORY | SEVERITY | ATTEMPTS | ALL MATCHES | FIRST MATCHES | INCOMPLETE | SRC |
tb.dut.tlul_assert_device.gen_device_cov.aValidNotAccepted_C | 0 | 0 | 1194891410 | 499161 | 499161 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_addressChangedNotAccepted_C | 0 | 0 | 1194891410 | 4924 | 4924 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_dataChangedNotAccepted_C | 0 | 0 | 1194891410 | 12359 | 12359 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_maskChangedNotAccepted_C | 0 | 0 | 1194891410 | 9256 | 9256 | 0 | |
tb.dut.tlul_assert_device.gen_device_cov.a_opcodeChangedNotAccepted_C | 0 | 0 | 1194891410 | 11982 | 11982 | 0 |
0% | 10% | 20% | 30% | 40% | 50% | 60% | 70% | 80% | 90% | 100% |