Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Module Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.09	100.00	95.45		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00			100.00		u_sysrst_ctrl_autoblock

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.95	100.00	94.74		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.75	100.00	93.75		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_ulp

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.87	91.30	90.91		83.33	90.48	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.87	91.30	90.91		83.33	90.48	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T13 T2 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T27 T58 T60 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T16 T26 T27 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T16 T26 T27 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T27 T58 T60 
149        1/1                    cnt_en = 1'b1;
           Tests:       T27 T58 T60 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T27 T58 T60 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T27 T58 T60 
163        1/1                    state_d = IdleSt;
           Tests:       T71 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T71 
165        1/1                  end else if (cnt_done) begin
           Tests:       T27 T58 T60 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T27 T58 T60 
167        1/1                    if (trigger_active) begin
           Tests:       T27 T58 T60 
168        1/1                      state_d = DetectSt;
           Tests:       T27 T58 T60 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T61 T119 T139 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T27 T58 T60 
182        1/1                  cnt_en = 1'b1;
           Tests:       T27 T58 T60 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T27 T58 T60 
186        1/1                    state_d = IdleSt;
           Tests:       T112 T131 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T112 T131 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T27 T58 T60 
191        1/1                      state_d = StableSt;
           Tests:       T27 T58 T60 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T27 T58 T60 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T27 T58 T60 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T27 T58 T60 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T27 T58 T60 
206        1/1                    state_d = IdleSt;
           Tests:       T27 T58 T60 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T27 T58 T60 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T13,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T27,T58,T60

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T27,T58,T60

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T27,T58,T60

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T27,T58,T60
1	0	Covered	T4,T13,T2
1	1	Covered	T27,T58,T60

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T27,T58,T60
0	1	Covered	T112,T131
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T27,T58,T60
0	1	Covered	T27,T58,T60
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T27,T58,T60
1	-	Covered	T27,T58,T60

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T27,T58,T60
DetectSt	168	Covered	T27,T58,T60
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T27,T58,T60

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T27,T58,T60
DebounceSt->IdleSt	163	Covered	T61,T119,T71
DetectSt->IdleSt	186	Covered	T112,T131
DetectSt->StableSt	191	Covered	T27,T58,T60
IdleSt->DebounceSt	148	Covered	T27,T58,T60
StableSt->IdleSt	206	Covered	T27,T58,T60

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T27,T58,T60
0	1	Covered	T27,T58,T60
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T27,T58,T60
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T27,T58,T60
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T71
DebounceSt	-	0	1	1	-	-	-	Covered	T27,T58,T60
DebounceSt	-	0	1	0	-	-	-	Covered	T61,T119,T139
DebounceSt	-	0	0	-	-	-	-	Covered	T27,T58,T60
DetectSt	-	-	-	-	1	-	-	Covered	T112,T131
DetectSt	-	-	-	-	0	1	-	Covered	T27,T58,T60
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T27,T58,T60
StableSt	-	-	-	-	-	-	0	Covered	T27,T58,T60
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_autoblock.u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	162	0	0
CntIncr_A	5849450	51191	0	0
CntNoWrap_A	5849450	5391045	0	0
DetectStDropOut_A	5849450	2	0	0
DetectedOut_A	5849450	479	0	0
DetectedPulseOut_A	5849450	71	0	0
DisabledIdleSt_A	5849450	5336275	0	0
DisabledNoDetection_A	5849450	5338168	0	0
EnterDebounceSt_A	5849450	89	0	0
EnterDetectSt_A	5849450	73	0	0
EnterStableSt_A	5849450	71	0	0
PulseIsPulse_A	5849450	71	0	0
StayInStableSt	5849450	408	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5849450	5568	0	0
gen_low_level_sva.LowLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	70	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	162	0	0
T6	805	0	0	0
T9	2780	0	0	0
T23	499	0	0	0
T27	725	6	0	0
T52	0	2	0	0
T57	434	0	0	0
T58	0	2	0	0
T60	0	6	0	0
T61	0	1	0	0
T64	0	2	0	0
T68	434	0	0	0
T70	0	4	0	0
T78	505	0	0	0
T79	565	0	0	0
T89	522	0	0	0
T118	0	2	0	0
T119	0	1	0	0
T120	0	6	0	0
T121	409	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	51191	0	0
T6	805	0	0	0
T9	2780	0	0	0
T23	499	0	0	0
T27	725	207	0	0
T52	0	19	0	0
T57	434	0	0	0
T58	0	35	0	0
T60	0	158	0	0
T61	0	21	0	0
T64	0	42	0	0
T68	434	0	0	0
T70	0	127	0	0
T78	505	0	0	0
T79	565	0	0	0
T89	522	0	0	0
T118	0	84	0	0
T119	0	33	0	0
T120	0	208	0	0
T121	409	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391045	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	2	0	0
T71	8312	0	0	0
T112	686	1	0	0
T131	0	1	0	0
T135	502	0	0	0
T136	467	0	0	0
T137	1022	0	0	0
T138	2241	0	0	0
T139	721	0	0	0
T140	422	0	0	0
T141	1493	0	0	0
T142	702	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	479	0	0
T6	805	0	0	0
T9	2780	0	0	0
T23	499	0	0	0
T27	725	9	0	0
T52	0	19	0	0
T57	434	0	0	0
T58	0	4	0	0
T60	0	12	0	0
T64	0	8	0	0
T68	434	0	0	0
T70	0	20	0	0
T78	505	0	0	0
T79	565	0	0	0
T89	522	0	0	0
T112	0	10	0	0
T118	0	11	0	0
T120	0	23	0	0
T121	409	0	0	0
T142	0	13	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	71	0	0
T6	805	0	0	0
T9	2780	0	0	0
T23	499	0	0	0
T27	725	3	0	0
T52	0	1	0	0
T57	434	0	0	0
T58	0	1	0	0
T60	0	3	0	0
T64	0	1	0	0
T68	434	0	0	0
T70	0	2	0	0
T78	505	0	0	0
T79	565	0	0	0
T89	522	0	0	0
T112	0	1	0	0
T118	0	1	0	0
T120	0	3	0	0
T121	409	0	0	0
T142	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5336275	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5338168	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	89	0	0
T6	805	0	0	0
T9	2780	0	0	0
T23	499	0	0	0
T27	725	3	0	0
T52	0	1	0	0
T57	434	0	0	0
T58	0	1	0	0
T60	0	3	0	0
T61	0	1	0	0
T64	0	1	0	0
T68	434	0	0	0
T70	0	2	0	0
T78	505	0	0	0
T79	565	0	0	0
T89	522	0	0	0
T118	0	1	0	0
T119	0	1	0	0
T120	0	3	0	0
T121	409	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	73	0	0
T6	805	0	0	0
T9	2780	0	0	0
T23	499	0	0	0
T27	725	3	0	0
T52	0	1	0	0
T57	434	0	0	0
T58	0	1	0	0
T60	0	3	0	0
T64	0	1	0	0
T68	434	0	0	0
T70	0	2	0	0
T78	505	0	0	0
T79	565	0	0	0
T89	522	0	0	0
T112	0	2	0	0
T118	0	1	0	0
T120	0	3	0	0
T121	409	0	0	0
T142	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	71	0	0
T6	805	0	0	0
T9	2780	0	0	0
T23	499	0	0	0
T27	725	3	0	0
T52	0	1	0	0
T57	434	0	0	0
T58	0	1	0	0
T60	0	3	0	0
T64	0	1	0	0
T68	434	0	0	0
T70	0	2	0	0
T78	505	0	0	0
T79	565	0	0	0
T89	522	0	0	0
T112	0	1	0	0
T118	0	1	0	0
T120	0	3	0	0
T121	409	0	0	0
T142	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	71	0	0
T6	805	0	0	0
T9	2780	0	0	0
T23	499	0	0	0
T27	725	3	0	0
T52	0	1	0	0
T57	434	0	0	0
T58	0	1	0	0
T60	0	3	0	0
T64	0	1	0	0
T68	434	0	0	0
T70	0	2	0	0
T78	505	0	0	0
T79	565	0	0	0
T89	522	0	0	0
T112	0	1	0	0
T118	0	1	0	0
T120	0	3	0	0
T121	409	0	0	0
T142	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	408	0	0
T6	805	0	0	0
T9	2780	0	0	0
T23	499	0	0	0
T27	725	6	0	0
T52	0	18	0	0
T57	434	0	0	0
T58	0	3	0	0
T60	0	9	0	0
T64	0	7	0	0
T68	434	0	0	0
T70	0	18	0	0
T78	505	0	0	0
T79	565	0	0	0
T89	522	0	0	0
T112	0	9	0	0
T118	0	10	0	0
T120	0	20	0	0
T121	409	0	0	0
T142	0	12	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5568	0	0
T2	1386	5	0	0
T3	1092	1	0	0
T4	421	2	0	0
T5	471	0	0	0
T7	511	0	0	0
T13	422	4	0	0
T14	497	8	0	0
T15	523	5	0	0
T16	668	3	0	0
T24	508	4	0	0
T26	0	3	0	0
T66	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	70	0	0
T6	805	0	0	0
T9	2780	0	0	0
T23	499	0	0	0
T27	725	3	0	0
T57	434	0	0	0
T58	0	1	0	0
T60	0	3	0	0
T64	0	1	0	0
T68	434	0	0	0
T70	0	2	0	0
T78	505	0	0	0
T79	565	0	0	0
T89	522	0	0	0
T112	0	1	0	0
T118	0	1	0	0
T120	0	3	0	0
T121	409	0	0	0
T142	0	1	0	0
T144	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T13 T2 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T10 T17 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T10 T17 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T10 T17 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T10 T17 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T10 T17 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T10 T17 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T10 T17 
163        1/1                    state_d = IdleSt;
           Tests:       T52 T71 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T52 T71 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T10 T17 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T17 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T10 T17 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T10 T17 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T10 T72 T77 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T10 T17 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T10 T17 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T10 T17 
186        1/1                    state_d = IdleSt;
           Tests:       T10 T110 T116 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T110 T116 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T17 T73 
191        1/1                      state_d = StableSt;
           Tests:       T2 T17 T73 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T17 T73 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T17 T73 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T17 T73 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T17 T73 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T17 T73 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T17 T73 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T13,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T10,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T10,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T10,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T17
1	0	Covered	T4,T13,T2
1	1	Covered	T2,T10,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T17,T73
0	1	Covered	T10,T110,T116
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T17,T73
0	1	Unreachable
1	0	Covered	T2,T17,T73

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T17
DetectSt	168	Covered	T2,T10,T17
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T17,T73

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T17
DebounceSt->IdleSt	163	Covered	T10,T72,T77
DetectSt->IdleSt	186	Covered	T10,T110,T116
DetectSt->StableSt	191	Covered	T2,T17,T73
IdleSt->DebounceSt	148	Covered	T2,T10,T17
StableSt->IdleSt	206	Covered	T2,T17,T73

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T10,T17
0	1	Covered	T2,T10,T17
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T17
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T17
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T10,T72,T77
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T17
DetectSt	-	-	-	-	1	-	-	Covered	T10,T110,T116
DetectSt	-	-	-	-	0	1	-	Covered	T2,T17,T73
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T17,T73
StableSt	-	-	-	-	-	-	0	Covered	T2,T17,T73
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_pwrb

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	117	0	0
CntIncr_A	5849450	86057	0	0
CntNoWrap_A	5849450	5391090	0	0
DetectStDropOut_A	5849450	14	0	0
DetectedOut_A	5849450	179336	0	0
DetectedPulseOut_A	5849450	32	0	0
DisabledIdleSt_A	5849450	4240320	0	0
DisabledNoDetection_A	5849450	4242238	0	0
EnterDebounceSt_A	5849450	73	0	0
EnterDetectSt_A	5849450	46	0	0
EnterStableSt_A	5849450	32	0	0
PulseIsPulse_A	5849450	32	0	0
StayInStableSt	5849450	179304	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5849450	5568	0	0
gen_low_level_sva.LowLevelEvent_A	5849450	5393126	0	0
gen_sticky_sva.StableStDropOut_A	5849450	782034	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	117	0	0
T2	1386	2	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	5	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	2	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	9	0	0
T73	0	2	0	0
T74	0	4	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	2	0	0
T109	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	86057	0	0
T2	1386	70	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	126	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	83	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	396	0	0
T73	0	18250	0	0
T74	0	118	0	0
T75	0	80	0	0
T76	0	49	0	0
T77	0	48	0	0
T109	0	10	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391090	0	0
T1	489	88	0	0
T2	1386	983	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	14	0	0
T10	689	2	0	0
T11	741	0	0	0
T12	510	0	0	0
T58	637	0	0	0
T59	431	0	0	0
T93	502	0	0	0
T110	0	1	0	0
T116	0	2	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T151	0	1	0	0
T152	0	1	0	0
T153	0	3	0	0
T154	0	2	0	0
T155	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	179336	0	0
T2	1386	256	0	0
T3	1092	0	0	0
T7	511	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	121	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T73	0	56233	0	0
T74	0	709	0	0
T75	0	97	0	0
T76	0	1	0	0
T109	0	6	0	0
T110	0	271	0	0
T145	0	52	0	0
T146	0	207	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	32	0	0
T2	1386	1	0	0
T3	1092	0	0	0
T7	511	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4240320	0	0
T1	489	88	0	0
T2	1386	412	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4242238	0	0
T1	489	89	0	0
T2	1386	413	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	73	0	0
T2	1386	1	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	3	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	9	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T109	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	46	0	0
T2	1386	1	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T109	0	1	0	0
T110	0	2	0	0
T145	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	32	0	0
T2	1386	1	0	0
T3	1092	0	0	0
T7	511	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	32	0	0
T2	1386	1	0	0
T3	1092	0	0	0
T7	511	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T109	0	1	0	0
T110	0	1	0	0
T145	0	1	0	0
T146	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	179304	0	0
T2	1386	255	0	0
T3	1092	0	0	0
T7	511	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	120	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T73	0	56232	0	0
T74	0	707	0	0
T75	0	96	0	0
T109	0	5	0	0
T110	0	270	0	0
T111	0	160	0	0
T145	0	51	0	0
T146	0	206	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5568	0	0
T2	1386	5	0	0
T3	1092	1	0	0
T4	421	2	0	0
T5	471	0	0	0
T7	511	0	0	0
T13	422	4	0	0
T14	497	8	0	0
T15	523	5	0	0
T16	668	3	0	0
T24	508	4	0	0
T26	0	3	0	0
T66	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	782034	0	0
T2	1386	227	0	0
T3	1092	0	0	0
T7	511	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	52	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T73	0	80	0	0
T74	0	177	0	0
T75	0	47	0	0
T76	0	82	0	0
T109	0	134	0	0
T110	0	76	0	0
T145	0	453	0	0
T146	0	161	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T13 T2 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T13 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T10 T17 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T10 T17 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T10 T17 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T13 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T13 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T13 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T13 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T13 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T13 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T13 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T13 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T10 T17 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T10 T17 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T10 T17 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T10 T17 
163        1/1                    state_d = IdleSt;
           Tests:       T52 T71 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T52 T71 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T10 T17 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T17 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T10 T17 
168        1/1                      state_d = DetectSt;
           Tests:       T2 T10 T17 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T74 T110 T145 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T2 T10 T17 
182        1/1                  cnt_en = 1'b1;
           Tests:       T2 T10 T17 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T2 T10 T17 
186        1/1                    state_d = IdleSt;
           Tests:       T10 T74 T110 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T10 T74 T110 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T2 T10 T17 
191        1/1                      state_d = StableSt;
           Tests:       T2 T10 T17 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T2 T10 T17 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T2 T10 T17 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T2 T10 T17 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T2 T10 T17 
206        1/1                    state_d = IdleSt;
           Tests:       T2 T10 T17 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T2 T10 T17 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Covered	Percent
Conditions	19	18	94.74
Logical	19	18	94.74
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T13,T2
1	1	Covered	T4,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T10,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T10,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T10,T17

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T17
1	0	Covered	T4,T13,T2
1	1	Covered	T2,T10,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T17
0	1	Covered	T10,T74,T110
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T2,T10,T17
0	1	Unreachable
1	0	Covered	T2,T10,T17

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T17
DetectSt	168	Covered	T2,T10,T17
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T2,T10,T17

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T2,T10,T17
DebounceSt->IdleSt	163	Covered	T74,T52,T110
DetectSt->IdleSt	186	Covered	T10,T74,T110
DetectSt->StableSt	191	Covered	T2,T10,T17
IdleSt->DebounceSt	148	Covered	T2,T10,T17
StableSt->IdleSt	206	Covered	T2,T10,T17

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Line No.	Total	Covered	Percent
Branches		21	21	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T10,T17
0	1	Covered	T2,T10,T17
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T2,T10,T17
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T17
IdleSt	0	-	-	-	-	-	-	Covered	T4,T13,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T2,T10,T17
DebounceSt	-	0	1	0	-	-	-	Covered	T74,T110,T145
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T17
DetectSt	-	-	-	-	1	-	-	Covered	T10,T74,T110
DetectSt	-	-	-	-	0	1	-	Covered	T2,T10,T17
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T2,T10,T17
StableSt	-	-	-	-	-	-	0	Covered	T2,T10,T17
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_lid_open

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	114	0	0
CntIncr_A	5849450	30534	0	0
CntNoWrap_A	5849450	5391093	0	0
DetectStDropOut_A	5849450	7	0	0
DetectedOut_A	5849450	59586	0	0
DetectedPulseOut_A	5849450	34	0	0
DisabledIdleSt_A	5849450	4240320	0	0
DisabledNoDetection_A	5849450	4242238	0	0
EnterDebounceSt_A	5849450	75	0	0
EnterDetectSt_A	5849450	41	0	0
EnterStableSt_A	5849450	34	0	0
PulseIsPulse_A	5849450	34	0	0
StayInStableSt	5849450	59552	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_sticky_sva.StableStDropOut_A	5849450	1057192	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	114	0	0
T2	1386	2	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	4	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	2	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	4	0	0
T73	0	2	0	0
T74	0	9	0	0
T75	0	2	0	0
T76	0	2	0	0
T77	0	2	0	0
T109	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	30534	0	0
T2	1386	100	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	48	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	50	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	76	0	0
T73	0	45	0	0
T74	0	465	0	0
T75	0	21	0	0
T76	0	46	0	0
T77	0	88	0	0
T109	0	71	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391093	0	0
T1	489	88	0	0
T2	1386	983	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	7	0	0
T10	689	1	0	0
T11	741	0	0	0
T12	510	0	0	0
T58	637	0	0	0
T59	431	0	0	0
T74	0	3	0	0
T93	502	0	0	0
T110	0	1	0	0
T145	0	1	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T156	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	59586	0	0
T2	1386	404	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	27	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	121	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	455	0	0
T73	0	207	0	0
T74	0	282	0	0
T75	0	46	0	0
T76	0	24	0	0
T77	0	91	0	0
T109	0	49	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	34	0	0
T2	1386	1	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	1	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T109	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4240320	0	0
T1	489	88	0	0
T2	1386	412	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4242238	0	0
T1	489	89	0	0
T2	1386	413	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	75	0	0
T2	1386	1	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	5	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T109	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	41	0	0
T2	1386	1	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	4	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T109	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	34	0	0
T2	1386	1	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	1	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T109	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	34	0	0
T2	1386	1	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	1	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	1	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T109	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	59552	0	0
T2	1386	403	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	26	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	120	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	453	0	0
T73	0	206	0	0
T74	0	281	0	0
T75	0	45	0	0
T76	0	23	0	0
T77	0	90	0	0
T109	0	48	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1057192	0	0
T2	1386	52	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	64	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	90	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	508	0	0
T73	0	74311	0	0
T74	0	133	0	0
T75	0	158	0	0
T76	0	70	0	0
T77	0	35	0	0
T109	0	29	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T13 T2 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T4 T13 T2 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T2 T10 T17 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T2 T10 T17 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T2 T10 T17 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T13 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T13 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T13 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T13 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T13 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T13 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T13 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T13 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T2 T10 T17 
149        1/1                    cnt_en = 1'b1;
           Tests:       T2 T10 T17 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T2 T10 T17 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T2 T10 T17 
163        1/1                    state_d = IdleSt;
           Tests:       T52 T71 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T52 T71 
165        1/1                  end else if (cnt_done) begin
           Tests:       T2 T10 T17 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T2 T10 T17 
167        1/1                    if (trigger_active) begin
           Tests:       T2 T10 T17 
168        1/1                      state_d = DetectSt;
           Tests:       T10 T72 T73 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T2 T17 T72 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T10 T72 T73 
182        1/1                  cnt_en = 1'b1;
           Tests:       T10 T72 T73 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T10 T72 T73 
186        1/1                    state_d = IdleSt;
           Tests:       T72 T73 T111 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T72 T73 T111 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T10 T72 T73 
191        1/1                      state_d = StableSt;
           Tests:       T10 T72 T73 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T10 T72 T73 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T10 T72 T73 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T10 T72 T73 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T10 T72 T73 
206        1/1                    state_d = IdleSt;
           Tests:       T10 T72 T73 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T10 T72 T73 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Covered	Percent
Conditions	16	15	93.75
Logical	16	15	93.75
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T10,T17

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T2,T10,T17

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T10,T72,T73

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T17
1	0	Covered	T4,T13,T2
1	1	Covered	T2,T10,T17

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T10,T72,T73
0	1	Covered	T72,T73,T111
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
             --------1--------    -----------------2----------------

-1-	-2-	Status	Tests
0	0	Covered	T10,T72,T73
0	1	Unreachable
1	0	Covered	T10,T72,T73

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T2,T10,T17
DetectSt	168	Covered	T10,T72,T73
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T10,T72,T73

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T10,T72,T73
DebounceSt->IdleSt	163	Covered	T2,T17,T72
DetectSt->IdleSt	186	Covered	T72,T73,T111
DetectSt->StableSt	191	Covered	T10,T72,T73
IdleSt->DebounceSt	148	Covered	T2,T10,T17
StableSt->IdleSt	206	Covered	T10,T72,T73

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Line No.	Total	Covered	Percent
Branches		19	19	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	10	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T2,T10,T17
0	1	Covered	T2,T10,T17
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T10,T72,T73
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T2,T10,T17
IdleSt	0	-	-	-	-	-	-	Covered	T4,T13,T2
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T10,T72,T73
DebounceSt	-	0	1	0	-	-	-	Covered	T2,T17,T72
DebounceSt	-	0	0	-	-	-	-	Covered	T2,T10,T17
DetectSt	-	-	-	-	1	-	-	Covered	T72,T73,T111
DetectSt	-	-	-	-	0	1	-	Covered	T10,T72,T73
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T10,T72,T73
StableSt	-	-	-	-	-	-	0	Covered	T10,T72,T73
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_ulp.u_sysrst_ctrl_detect_ac_present

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	129	0	0
CntIncr_A	5849450	374681	0	0
CntNoWrap_A	5849450	5391078	0	0
DetectStDropOut_A	5849450	18	0	0
DetectedOut_A	5849450	430530	0	0
DetectedPulseOut_A	5849450	33	0	0
DisabledIdleSt_A	5849450	4240320	0	0
DisabledNoDetection_A	5849450	4242238	0	0
EnterDebounceSt_A	5849450	80	0	0
EnterDetectSt_A	5849450	51	0	0
EnterStableSt_A	5849450	33	0	0
PulseIsPulse_A	5849450	33	0	0
StayInStableSt	5849450	430497	0	0
gen_high_event_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_sticky_sva.StableStDropOut_A	5849450	22689	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	129	0	0
T2	1386	3	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	4	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	2	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	9	0	0
T73	0	8	0	0
T74	0	4	0	0
T75	0	2	0	0
T76	0	1	0	0
T77	0	2	0	0
T109	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	374681	0	0
T2	1386	78	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	40	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	168	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	410	0	0
T73	0	56	0	0
T74	0	152	0	0
T75	0	29	0	0
T76	0	47	0	0
T77	0	11	0	0
T109	0	35	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391078	0	0
T1	489	88	0	0
T2	1386	982	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	18	0	0
T33	16295	0	0	0
T48	961	0	0	0
T61	624	0	0	0
T72	1529	2	0	0
T73	168253	3	0	0
T111	0	1	0	0
T128	0	4	0	0
T157	0	1	0	0
T158	0	1	0	0
T159	0	2	0	0
T160	0	4	0	0
T161	1823	0	0	0
T162	4405	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	430530	0	0
T10	689	66	0	0
T11	741	0	0	0
T12	510	0	0	0
T58	637	0	0	0
T59	431	0	0	0
T72	0	333	0	0
T73	0	1	0	0
T74	0	564	0	0
T75	0	50	0	0
T77	0	21	0	0
T93	502	0	0	0
T109	0	5	0	0
T110	0	300	0	0
T116	0	57	0	0
T145	0	419	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	33	0	0
T10	689	2	0	0
T11	741	0	0	0
T12	510	0	0	0
T58	637	0	0	0
T59	431	0	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T93	502	0	0	0
T109	0	1	0	0
T110	0	1	0	0
T116	0	1	0	0
T145	0	1	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4240320	0	0
T1	489	88	0	0
T2	1386	412	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4242238	0	0
T1	489	89	0	0
T2	1386	413	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	80	0	0
T2	1386	3	0	0
T3	1092	0	0	0
T7	511	0	0	0
T10	0	2	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	2	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T66	426	0	0	0
T72	0	5	0	0
T73	0	4	0	0
T74	0	2	0	0
T75	0	1	0	0
T76	0	1	0	0
T77	0	1	0	0
T109	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	51	0	0
T10	689	2	0	0
T11	741	0	0	0
T12	510	0	0	0
T58	637	0	0	0
T59	431	0	0	0
T72	0	4	0	0
T73	0	4	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T93	502	0	0	0
T109	0	1	0	0
T110	0	1	0	0
T111	0	1	0	0
T145	0	1	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	33	0	0
T10	689	2	0	0
T11	741	0	0	0
T12	510	0	0	0
T58	637	0	0	0
T59	431	0	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T93	502	0	0	0
T109	0	1	0	0
T110	0	1	0	0
T116	0	1	0	0
T145	0	1	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	33	0	0
T10	689	2	0	0
T11	741	0	0	0
T12	510	0	0	0
T58	637	0	0	0
T59	431	0	0	0
T72	0	2	0	0
T73	0	1	0	0
T74	0	2	0	0
T75	0	1	0	0
T77	0	1	0	0
T93	502	0	0	0
T109	0	1	0	0
T110	0	1	0	0
T116	0	1	0	0
T145	0	1	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	430497	0	0
T10	689	64	0	0
T11	741	0	0	0
T12	510	0	0	0
T58	637	0	0	0
T59	431	0	0	0
T72	0	331	0	0
T74	0	562	0	0
T75	0	49	0	0
T77	0	20	0	0
T93	502	0	0	0
T109	0	4	0	0
T110	0	299	0	0
T116	0	56	0	0
T145	0	418	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T166	0	30	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	22689	0	0
T10	689	109	0	0
T11	741	0	0	0
T12	510	0	0	0
T58	637	0	0	0
T59	431	0	0	0
T72	0	218	0	0
T73	0	18653	0	0
T74	0	298	0	0
T75	0	156	0	0
T77	0	201	0	0
T93	502	0	0	0
T109	0	114	0	0
T110	0	174	0	0
T116	0	139	0	0
T145	0	52	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T4 T5 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T48 T52 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T48 T52 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T48 T52 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T48 T52 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T48 T52 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T48 T52 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T48 T52 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T48 T52 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T48 T52 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T167 T168 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T48 T52 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T48 T52 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T48 T52 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T48 T52 
191        1/1                      state_d = StableSt;
           Tests:       T11 T48 T52 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T48 T52 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T48 T52 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T48 T52 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T48 T52 
206        1/1                    state_d = IdleSt;
           Tests:       T11 T52 T71 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T48 T52 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T48,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T48,T52

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T48,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T11,T48
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T48,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T48,T52
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T48,T52
0	1	Covered	T11,T169,T170
1	0	Covered	T52,T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T48,T52
1	-	Covered	T11,T169,T170

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T48,T52
DetectSt	168	Covered	T11,T48,T52
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T48,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T48,T52
DebounceSt->IdleSt	163	Covered	T167,T168
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T48,T52
IdleSt->DebounceSt	148	Covered	T11,T48,T52
StableSt->IdleSt	206	Covered	T11,T52,T71

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T48,T52
0	1	Covered	T11,T48,T52
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T48,T52
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T48,T52
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T48,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T167,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T48,T52
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T48,T52
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T11,T52,T71
StableSt	-	-	-	-	-	-	0	Covered	T11,T48,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	56	0	0
CntIncr_A	5849450	28312	0	0
CntNoWrap_A	5849450	5391151	0	0
DetectStDropOut_A	5849450	0	0	0
DetectedOut_A	5849450	1938	0	0
DetectedPulseOut_A	5849450	27	0	0
DisabledIdleSt_A	5849450	5250337	0	0
DisabledNoDetection_A	5849450	5252217	0	0
EnterDebounceSt_A	5849450	29	0	0
EnterDetectSt_A	5849450	27	0	0
EnterStableSt_A	5849450	27	0	0
PulseIsPulse_A	5849450	27	0	0
StayInStableSt	5849450	1897	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	56	0	0
T11	741	4	0	0
T12	510	0	0	0
T17	3511	0	0	0
T48	0	2	0	0
T52	0	2	0	0
T54	0	2	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	2	0	0
T93	502	0	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T169	0	2	0	0
T170	0	4	0	0
T171	0	2	0	0
T172	0	2	0	0
T173	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	28312	0	0
T11	741	118	0	0
T12	510	0	0	0
T17	3511	0	0	0
T48	0	96	0	0
T52	0	27	0	0
T54	0	38	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	28	0	0
T93	502	0	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T169	0	60	0	0
T170	0	68	0	0
T171	0	50	0	0
T172	0	57	0	0
T173	0	91	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391151	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1938	0	0
T11	741	77	0	0
T12	510	0	0	0
T17	3511	0	0	0
T48	0	41	0	0
T52	0	18	0	0
T54	0	53	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	14	0	0
T93	502	0	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T169	0	40	0	0
T170	0	87	0	0
T171	0	56	0	0
T172	0	133	0	0
T173	0	19	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	27	0	0
T11	741	2	0	0
T12	510	0	0	0
T17	3511	0	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	1	0	0
T93	502	0	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5250337	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5252217	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	29	0	0
T11	741	2	0	0
T12	510	0	0	0
T17	3511	0	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	1	0	0
T93	502	0	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	27	0	0
T11	741	2	0	0
T12	510	0	0	0
T17	3511	0	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	1	0	0
T93	502	0	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	27	0	0
T11	741	2	0	0
T12	510	0	0	0
T17	3511	0	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	1	0	0
T93	502	0	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	27	0	0
T11	741	2	0	0
T12	510	0	0	0
T17	3511	0	0	0
T48	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	1	0	0
T93	502	0	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T169	0	1	0	0
T170	0	2	0	0
T171	0	1	0	0
T172	0	1	0	0
T173	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1897	0	0
T11	741	74	0	0
T12	510	0	0	0
T17	3511	0	0	0
T48	0	39	0	0
T52	0	17	0	0
T54	0	51	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	13	0	0
T93	502	0	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T169	0	39	0	0
T170	0	85	0	0
T171	0	54	0	0
T172	0	131	0	0
T173	0	18	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	11	0	0
T11	741	1	0	0
T12	510	0	0	0
T17	3511	0	0	0
T59	431	0	0	0
T60	678	0	0	0
T93	502	0	0	0
T113	0	1	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T167	0	1	0	0
T169	0	1	0	0
T170	0	2	0	0
T173	0	1	0	0
T174	0	1	0	0
T175	0	1	0	0
T176	0	1	0	0
T177	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T4 T5 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T6 T50 T49 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T6 T50 T49 
149        1/1                    cnt_en = 1'b1;
           Tests:       T6 T50 T49 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T6 T50 T49 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T6 T50 T49 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T6 T50 T49 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T6 T50 T49 
167        1/1                    if (trigger_active) begin
           Tests:       T6 T50 T49 
168        1/1                      state_d = DetectSt;
           Tests:       T6 T50 T49 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T178 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T6 T50 T49 
182        1/1                  cnt_en = 1'b1;
           Tests:       T6 T50 T49 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T6 T50 T49 
186        1/1                    state_d = IdleSt;
           Tests:       T179 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T179 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T6 T50 T49 
191        1/1                      state_d = StableSt;
           Tests:       T6 T50 T49 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T6 T50 T49 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T6 T50 T49 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T6 T50 T49 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T6 T50 T49 
206        1/1                    state_d = IdleSt;
           Tests:       T49 T45 T52 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T6 T50 T49 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T50,T49

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T50,T49

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T6,T50,T49

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T50,T49
1	0	Covered	T4,T13,T14
1	1	Covered	T6,T50,T49

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T6,T50,T49
0	1	Covered	T179
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T6,T50,T49
0	1	Covered	T49,T45,T180
1	0	Covered	T52,T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T6,T50,T49
1	-	Covered	T49,T45,T180

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T6,T50,T49
DetectSt	168	Covered	T6,T50,T49
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T6,T50,T49

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T6,T50,T49
DebounceSt->IdleSt	163	Covered	T178
DetectSt->IdleSt	186	Covered	T179
DetectSt->StableSt	191	Covered	T6,T50,T49
IdleSt->DebounceSt	148	Covered	T6,T50,T49
StableSt->IdleSt	206	Covered	T49,T45,T117

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T6,T50,T49
0	1	Covered	T6,T50,T49
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T6,T50,T49
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T6,T50,T49
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T6,T50,T49
DebounceSt	-	0	1	0	-	-	-	Covered	T178
DebounceSt	-	0	0	-	-	-	-	Covered	T6,T50,T49
DetectSt	-	-	-	-	1	-	-	Covered	T179
DetectSt	-	-	-	-	0	1	-	Covered	T6,T50,T49
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T49,T45,T52
StableSt	-	-	-	-	-	-	0	Covered	T6,T50,T49
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[0].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	95	0	0
CntIncr_A	5849450	56075	0	0
CntNoWrap_A	5849450	5391112	0	0
DetectStDropOut_A	5849450	1	0	0
DetectedOut_A	5849450	2856	0	0
DetectedPulseOut_A	5849450	46	0	0
DisabledIdleSt_A	5849450	5268898	0	0
DisabledNoDetection_A	5849450	5270783	0	0
EnterDebounceSt_A	5849450	48	0	0
EnterDetectSt_A	5849450	47	0	0
EnterStableSt_A	5849450	46	0	0
PulseIsPulse_A	5849450	46	0	0
StayInStableSt	5849450	2790	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5849450	1520	0	0
gen_low_level_sva.LowLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	24	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	95	0	0
T6	805	2	0	0
T28	455	0	0	0
T45	0	4	0	0
T47	0	2	0	0
T49	0	4	0	0
T50	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T57	434	0	0	0
T71	0	2	0	0
T79	565	0	0	0
T80	913	0	0	0
T90	505	0	0	0
T91	2547	0	0	0
T92	522	0	0	0
T117	0	2	0	0
T180	0	4	0	0
T181	423	0	0	0
T182	411	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	56075	0	0
T6	805	78	0	0
T28	455	0	0	0
T45	0	36	0	0
T47	0	63	0	0
T49	0	138	0	0
T50	0	94	0	0
T52	0	27	0	0
T53	0	31	0	0
T57	434	0	0	0
T71	0	28	0	0
T79	565	0	0	0
T80	913	0	0	0
T90	505	0	0	0
T91	2547	0	0	0
T92	522	0	0	0
T117	0	24	0	0
T180	0	156	0	0
T181	423	0	0	0
T182	411	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391112	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1	0	0
T179	765	1	0	0
T183	11918	0	0	0
T184	496	0	0	0
T185	99989	0	0	0
T186	20354	0	0	0
T187	404	0	0	0
T188	31706	0	0	0
T189	13606	0	0	0
T190	423	0	0	0
T191	525	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	2856	0	0
T6	805	41	0	0
T28	455	0	0	0
T45	0	94	0	0
T47	0	43	0	0
T49	0	183	0	0
T50	0	44	0	0
T52	0	18	0	0
T53	0	154	0	0
T57	434	0	0	0
T71	0	15	0	0
T79	565	0	0	0
T80	913	0	0	0
T90	505	0	0	0
T91	2547	0	0	0
T92	522	0	0	0
T117	0	37	0	0
T180	0	178	0	0
T181	423	0	0	0
T182	411	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	46	0	0
T6	805	1	0	0
T28	455	0	0	0
T45	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	434	0	0	0
T71	0	1	0	0
T79	565	0	0	0
T80	913	0	0	0
T90	505	0	0	0
T91	2547	0	0	0
T92	522	0	0	0
T117	0	1	0	0
T180	0	2	0	0
T181	423	0	0	0
T182	411	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5268898	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5270783	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	48	0	0
T6	805	1	0	0
T28	455	0	0	0
T45	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	434	0	0	0
T71	0	1	0	0
T79	565	0	0	0
T80	913	0	0	0
T90	505	0	0	0
T91	2547	0	0	0
T92	522	0	0	0
T117	0	1	0	0
T180	0	2	0	0
T181	423	0	0	0
T182	411	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	47	0	0
T6	805	1	0	0
T28	455	0	0	0
T45	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	434	0	0	0
T71	0	1	0	0
T79	565	0	0	0
T80	913	0	0	0
T90	505	0	0	0
T91	2547	0	0	0
T92	522	0	0	0
T117	0	1	0	0
T180	0	2	0	0
T181	423	0	0	0
T182	411	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	46	0	0
T6	805	1	0	0
T28	455	0	0	0
T45	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	434	0	0	0
T71	0	1	0	0
T79	565	0	0	0
T80	913	0	0	0
T90	505	0	0	0
T91	2547	0	0	0
T92	522	0	0	0
T117	0	1	0	0
T180	0	2	0	0
T181	423	0	0	0
T182	411	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	46	0	0
T6	805	1	0	0
T28	455	0	0	0
T45	0	2	0	0
T47	0	1	0	0
T49	0	2	0	0
T50	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T57	434	0	0	0
T71	0	1	0	0
T79	565	0	0	0
T80	913	0	0	0
T90	505	0	0	0
T91	2547	0	0	0
T92	522	0	0	0
T117	0	1	0	0
T180	0	2	0	0
T181	423	0	0	0
T182	411	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	2790	0	0
T6	805	39	0	0
T28	455	0	0	0
T45	0	92	0	0
T47	0	41	0	0
T49	0	180	0	0
T50	0	42	0	0
T52	0	17	0	0
T53	0	152	0	0
T57	434	0	0	0
T71	0	14	0	0
T79	565	0	0	0
T80	913	0	0	0
T90	505	0	0	0
T91	2547	0	0	0
T92	522	0	0	0
T117	0	35	0	0
T180	0	175	0	0
T181	423	0	0	0
T182	411	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1520	0	0
T2	1386	0	0	0
T3	1092	2	0	0
T4	421	2	0	0
T5	471	0	0	0
T7	511	0	0	0
T13	422	3	0	0
T14	497	4	0	0
T15	523	7	0	0
T16	668	0	0	0
T22	0	5	0	0
T24	508	3	0	0
T25	0	4	0	0
T66	0	3	0	0
T68	0	4	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	24	0	0
T45	0	2	0	0
T49	963	1	0	0
T65	643	0	0	0
T113	0	1	0	0
T170	0	2	0	0
T172	0	1	0	0
T173	0	1	0	0
T180	0	1	0	0
T192	0	2	0	0
T193	0	1	0	0
T194	0	1	0	0
T195	502	0	0	0
T196	1882	0	0	0
T197	522	0	0	0
T198	403	0	0	0
T199	487	0	0	0
T200	498	0	0	0
T201	418	0	0	0
T202	422	0	0	0