Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
97.27	95.65	95.45		100.00	95.24	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.87	91.30	90.91		83.33	90.48	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.87	91.30	90.91		83.33	90.48	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.87	91.30	90.91		83.33	90.48	93.33

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.87	91.30	90.91		83.33	90.48	93.33

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
89.95	91.30	90.91		83.33	90.48	93.75

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00						u_sysrst_ctrl_keyintr

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	44	95.65
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	30	93.75
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T4 T5 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T43 T45 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T43 T45 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T43 T45 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T43 T45 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T43 T45 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T43 T45 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T43 T45 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T43 T45 
168        1/1                      state_d = DetectSt;
           Tests:       T43 T45 T46 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T3 T212 T176 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T43 T45 T46 
182        1/1                  cnt_en = 1'b1;
           Tests:       T43 T45 T46 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T43 T45 T46 
186        1/1                    state_d = IdleSt;
           Tests:       T46 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T46 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T43 T45 T46 
191        1/1                      state_d = StableSt;
           Tests:       T43 T45 T46 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T43 T45 T46 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T43 T45 T46 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T43 T45 T46 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T43 T45 T46 
206        1/1                    state_d = IdleSt;
           Tests:       T43 T45 T52 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T45 T46 T52 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	21	95.45
Logical	22	21	95.45
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T43,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T43,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T43,T45,T46

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T43,T45
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T43,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T45,T46
0	1	Covered	T46
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T45,T46,T52
0	1	Covered	T43,T45,T53
1	0	Covered	T52,T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T45,T46,T52
1	-	Covered	T43,T45,T53

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T43,T45
DetectSt	168	Covered	T43,T45,T46
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T43,T45,T46

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T45,T46
DebounceSt->IdleSt	163	Covered	T3,T212,T176
DetectSt->IdleSt	186	Covered	T46
DetectSt->StableSt	191	Covered	T43,T45,T46
IdleSt->DebounceSt	148	Covered	T3,T43,T45
StableSt->IdleSt	206	Covered	T43,T45,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	20	95.24
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	9	90.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T43,T45
0	1	Covered	T3,T43,T45
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T43,T45,T46
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T43,T45
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T45,T46
DebounceSt	-	0	1	0	-	-	-	Covered	T3,T212,T176
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T43,T45
DetectSt	-	-	-	-	1	-	-	Covered	T46
DetectSt	-	-	-	-	0	1	-	Covered	T43,T45,T46
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T45,T52
StableSt	-	-	-	-	-	-	0	Covered	T45,T46,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	62	0	0
CntIncr_A	5849450	41183	0	0
CntNoWrap_A	5849450	5391145	0	0
DetectStDropOut_A	5849450	1	0	0
DetectedOut_A	5849450	22340	0	0
DetectedPulseOut_A	5849450	28	0	0
DisabledIdleSt_A	5849450	5265642	0	0
DisabledNoDetection_A	5849450	5267532	0	0
EnterDebounceSt_A	5849450	33	0	0
EnterDetectSt_A	5849450	29	0	0
EnterStableSt_A	5849450	28	0	0
PulseIsPulse_A	5849450	28	0	0
StayInStableSt	5849450	22299	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	62	0	0
T3	1092	1	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T43	0	2	0	0
T45	0	2	0	0
T46	0	4	0	0
T52	0	2	0	0
T53	0	2	0	0
T66	426	0	0	0
T71	0	2	0	0
T171	0	4	0	0
T180	0	4	0	0
T203	0	4	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	41183	0	0
T3	1092	92	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T43	0	12	0	0
T45	0	18	0	0
T46	0	112	0	0
T52	0	27	0	0
T53	0	31	0	0
T66	426	0	0	0
T71	0	28	0	0
T171	0	100	0	0
T180	0	156	0	0
T203	0	38	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391145	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	690	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1	0	0
T46	867	1	0	0
T55	9906	0	0	0
T234	433	0	0	0
T235	739	0	0	0
T236	814	0	0	0
T237	493	0	0	0
T238	422	0	0	0
T239	402	0	0	0
T240	408	0	0	0
T241	522	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	22340	0	0
T43	2561	1	0	0
T44	930	0	0	0
T45	0	59	0	0
T46	0	43	0	0
T52	0	19	0	0
T53	0	72	0	0
T71	0	14	0	0
T81	1512	0	0	0
T171	0	155	0	0
T180	0	49	0	0
T193	0	112	0	0
T203	0	122	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	28	0	0
T43	2561	1	0	0
T44	930	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T71	0	1	0	0
T81	1512	0	0	0
T171	0	2	0	0
T180	0	2	0	0
T193	0	1	0	0
T203	0	2	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5265642	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	3	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5267532	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	3	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	33	0	0
T3	1092	1	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T66	426	0	0	0
T71	0	1	0	0
T171	0	2	0	0
T180	0	2	0	0
T203	0	2	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	29	0	0
T43	2561	1	0	0
T44	930	0	0	0
T45	0	1	0	0
T46	0	2	0	0
T52	0	1	0	0
T53	0	1	0	0
T71	0	1	0	0
T81	1512	0	0	0
T171	0	2	0	0
T180	0	2	0	0
T193	0	1	0	0
T203	0	2	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	28	0	0
T43	2561	1	0	0
T44	930	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T71	0	1	0	0
T81	1512	0	0	0
T171	0	2	0	0
T180	0	2	0	0
T193	0	1	0	0
T203	0	2	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	28	0	0
T43	2561	1	0	0
T44	930	0	0	0
T45	0	1	0	0
T46	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T71	0	1	0	0
T81	1512	0	0	0
T171	0	2	0	0
T180	0	2	0	0
T193	0	1	0	0
T203	0	2	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	22299	0	0
T40	19439	0	0	0
T45	662	58	0	0
T46	0	41	0	0
T52	0	18	0	0
T53	0	71	0	0
T70	719	0	0	0
T71	0	13	0	0
T109	586	0	0	0
T115	0	57	0	0
T171	0	152	0	0
T180	0	46	0	0
T193	0	110	0	0
T203	0	119	0	0
T242	527	0	0	0
T243	495	0	0	0
T244	866	0	0	0
T245	422	0	0	0
T246	556	0	0	0
T247	402	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	13	0	0
T43	2561	1	0	0
T44	930	0	0	0
T45	0	1	0	0
T53	0	1	0	0
T81	1512	0	0	0
T115	0	1	0	0
T171	0	1	0	0
T174	0	1	0	0
T176	0	1	0	0
T180	0	1	0	0
T185	0	1	0	0
T203	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T4 T5 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T11 T48 T43 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T11 T48 T43 
149        1/1                    cnt_en = 1'b1;
           Tests:       T11 T48 T43 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T11 T48 T43 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T11 T48 T43 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T11 T48 T43 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T11 T48 T43 
167        1/1                    if (trigger_active) begin
           Tests:       T11 T48 T43 
168        1/1                      state_d = DetectSt;
           Tests:       T11 T48 T43 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T203 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T11 T48 T43 
182        1/1                  cnt_en = 1'b1;
           Tests:       T11 T48 T43 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T11 T48 T43 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T11 T48 T43 
191        1/1                      state_d = StableSt;
           Tests:       T11 T48 T43 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T11 T48 T43 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T11 T48 T43 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T11 T48 T43 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T11 T48 T43 
206        1/1                    state_d = IdleSt;
           Tests:       T48 T46 T52 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T11 T48 T43 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T48,T43

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T48,T43

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T11,T48,T43

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T11,T48,T43
1	0	Covered	T1,T4,T5
1	1	Covered	T11,T48,T43

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T11,T48,T43
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T11,T48,T43
0	1	Covered	T48,T46,T171
1	0	Covered	T52,T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T11,T48,T43
1	-	Covered	T48,T46,T171

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T11,T48,T43
DetectSt	168	Covered	T11,T48,T43
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T11,T48,T43

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T11,T48,T43
DebounceSt->IdleSt	163	Covered	T203
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T11,T48,T43
IdleSt->DebounceSt	148	Covered	T11,T48,T43
StableSt->IdleSt	206	Covered	T48,T43,T46

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T11,T48,T43
0	1	Covered	T11,T48,T43
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T11,T48,T43
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T11,T48,T43
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T11,T48,T43
DebounceSt	-	0	1	0	-	-	-	Covered	T203
DebounceSt	-	0	0	-	-	-	-	Covered	T11,T48,T43
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T11,T48,T43
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T48,T46,T52
StableSt	-	-	-	-	-	-	0	Covered	T11,T48,T43
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[4].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	47	0	0
CntIncr_A	5849450	70155	0	0
CntNoWrap_A	5849450	5391160	0	0
DetectStDropOut_A	5849450	0	0	0
DetectedOut_A	5849450	2049	0	0
DetectedPulseOut_A	5849450	23	0	0
DisabledIdleSt_A	5849450	5174663	0	0
DisabledNoDetection_A	5849450	5176553	0	0
EnterDebounceSt_A	5849450	24	0	0
EnterDetectSt_A	5849450	23	0	0
EnterStableSt_A	5849450	23	0	0
PulseIsPulse_A	5849450	23	0	0
StayInStableSt	5849450	2015	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5849450	5099	0	0
gen_low_level_sva.LowLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	47	0	0
T11	741	2	0	0
T12	510	0	0	0
T17	3511	0	0	0
T43	0	2	0	0
T45	0	2	0	0
T46	0	2	0	0
T48	0	2	0	0
T52	0	2	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	2	0	0
T93	502	0	0	0
T116	0	2	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T171	0	2	0	0
T203	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	70155	0	0
T11	741	59	0	0
T12	510	0	0	0
T17	3511	0	0	0
T43	0	12	0	0
T45	0	18	0	0
T46	0	56	0	0
T48	0	96	0	0
T52	0	27	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	28	0	0
T93	502	0	0	0
T116	0	40	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T171	0	50	0	0
T203	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391160	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	2049	0	0
T11	741	247	0	0
T12	510	0	0	0
T17	3511	0	0	0
T43	0	114	0	0
T45	0	44	0	0
T46	0	245	0	0
T48	0	43	0	0
T52	0	17	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	14	0	0
T93	502	0	0	0
T116	0	61	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T170	0	172	0	0
T171	0	27	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	23	0	0
T11	741	1	0	0
T12	510	0	0	0
T17	3511	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	1	0	0
T93	502	0	0	0
T116	0	1	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T170	0	1	0	0
T171	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5174663	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5176553	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	24	0	0
T11	741	1	0	0
T12	510	0	0	0
T17	3511	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	1	0	0
T93	502	0	0	0
T116	0	1	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T171	0	1	0	0
T203	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	23	0	0
T11	741	1	0	0
T12	510	0	0	0
T17	3511	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	1	0	0
T93	502	0	0	0
T116	0	1	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T170	0	1	0	0
T171	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	23	0	0
T11	741	1	0	0
T12	510	0	0	0
T17	3511	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	1	0	0
T93	502	0	0	0
T116	0	1	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T170	0	1	0	0
T171	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	23	0	0
T11	741	1	0	0
T12	510	0	0	0
T17	3511	0	0	0
T43	0	1	0	0
T45	0	1	0	0
T46	0	1	0	0
T48	0	1	0	0
T52	0	1	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	1	0	0
T93	502	0	0	0
T116	0	1	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T170	0	1	0	0
T171	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	2015	0	0
T11	741	245	0	0
T12	510	0	0	0
T17	3511	0	0	0
T43	0	112	0	0
T45	0	42	0	0
T46	0	244	0	0
T48	0	42	0	0
T52	0	16	0	0
T59	431	0	0	0
T60	678	0	0	0
T71	0	13	0	0
T93	502	0	0	0
T116	0	59	0	0
T147	420	0	0	0
T148	4410	0	0	0
T149	402	0	0	0
T150	650	0	0	0
T170	0	171	0	0
T171	0	26	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5099	0	0
T1	489	1	0	0
T2	1386	0	0	0
T3	1092	1	0	0
T4	421	1	0	0
T5	471	1	0	0
T7	511	1	0	0
T13	422	3	0	0
T14	497	7	0	0
T15	523	4	0	0
T16	668	0	0	0
T24	0	4	0	0
T66	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	10	0	0
T33	16295	0	0	0
T46	0	1	0	0
T48	961	1	0	0
T73	168253	0	0	0
T161	1823	0	0	0
T162	4405	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T168	0	1	0	0
T170	0	1	0	0
T171	0	1	0	0
T173	0	1	0	0
T192	0	1	0	0
T225	422	0	0	0
T226	556	0	0	0
T248	0	1	0	0
T249	0	1	0	0
T250	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T4 T5 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T43 T49 T45 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T43 T49 T45 
149        1/1                    cnt_en = 1'b1;
           Tests:       T43 T49 T45 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T43 T49 T45 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T43 T49 T45 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T43 T49 T45 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T43 T49 T45 
167        1/1                    if (trigger_active) begin
           Tests:       T43 T49 T45 
168        1/1                      state_d = DetectSt;
           Tests:       T43 T49 T45 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T251 T167 T252 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T43 T49 T45 
182        1/1                  cnt_en = 1'b1;
           Tests:       T43 T49 T45 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T43 T49 T45 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T43 T49 T45 
191        1/1                      state_d = StableSt;
           Tests:       T43 T49 T45 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T43 T49 T45 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T43 T49 T45 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T43 T49 T45 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T43 T49 T45 
206        1/1                    state_d = IdleSt;
           Tests:       T43 T49 T45 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T43 T49 T45 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T43,T49,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T43,T49,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T43,T49,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T6,T43,T49
1	0	Covered	T1,T4,T5
1	1	Covered	T43,T49,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T49,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T49,T45
0	1	Covered	T43,T49,T45
1	0	Covered	T52,T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T49,T45
1	-	Covered	T43,T49,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T43,T49,T45
DetectSt	168	Covered	T43,T49,T45
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T43,T49,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T49,T45
DebounceSt->IdleSt	163	Covered	T251,T167,T252
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T43,T49,T45
IdleSt->DebounceSt	148	Covered	T43,T49,T45
StableSt->IdleSt	206	Covered	T43,T49,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T43,T49,T45
0	1	Covered	T43,T49,T45
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T43,T49,T45
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T43,T49,T45
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T49,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T251,T167,T252
DebounceSt	-	0	0	-	-	-	-	Covered	T43,T49,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T43,T49,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T49,T45
StableSt	-	-	-	-	-	-	0	Covered	T43,T49,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	90	0	0
CntIncr_A	5849450	44506	0	0
CntNoWrap_A	5849450	5391117	0	0
DetectStDropOut_A	5849450	0	0	0
DetectedOut_A	5849450	56883	0	0
DetectedPulseOut_A	5849450	43	0	0
DisabledIdleSt_A	5849450	5284318	0	0
DisabledNoDetection_A	5849450	5286202	0	0
EnterDebounceSt_A	5849450	47	0	0
EnterDetectSt_A	5849450	43	0	0
EnterStableSt_A	5849450	43	0	0
PulseIsPulse_A	5849450	43	0	0
StayInStableSt	5849450	56822	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	23	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	90	0	0
T43	2561	4	0	0
T44	930	0	0	0
T45	0	4	0	0
T49	0	2	0	0
T52	0	2	0	0
T53	0	4	0	0
T71	0	2	0	0
T81	1512	0	0	0
T117	0	2	0	0
T137	0	2	0	0
T180	0	2	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0
T251	0	1	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	44506	0	0
T43	2561	24	0	0
T44	930	0	0	0
T45	0	36	0	0
T49	0	69	0	0
T52	0	27	0	0
T53	0	62	0	0
T71	0	28	0	0
T81	1512	0	0	0
T117	0	24	0	0
T137	0	95	0	0
T180	0	78	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0
T251	0	22	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391117	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	56883	0	0
T43	2561	99	0	0
T44	930	0	0	0
T45	0	92	0	0
T49	0	50	0	0
T52	0	18	0	0
T53	0	112	0	0
T71	0	13	0	0
T81	1512	0	0	0
T117	0	37	0	0
T137	0	216	0	0
T172	0	148	0	0
T180	0	43	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	43	0	0
T43	2561	2	0	0
T44	930	0	0	0
T45	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T71	0	1	0	0
T81	1512	0	0	0
T117	0	1	0	0
T137	0	1	0	0
T172	0	2	0	0
T180	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5284318	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5286202	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	47	0	0
T43	2561	2	0	0
T44	930	0	0	0
T45	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T71	0	1	0	0
T81	1512	0	0	0
T117	0	1	0	0
T137	0	1	0	0
T180	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0
T251	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	43	0	0
T43	2561	2	0	0
T44	930	0	0	0
T45	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T71	0	1	0	0
T81	1512	0	0	0
T117	0	1	0	0
T137	0	1	0	0
T172	0	2	0	0
T180	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	43	0	0
T43	2561	2	0	0
T44	930	0	0	0
T45	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T71	0	1	0	0
T81	1512	0	0	0
T117	0	1	0	0
T137	0	1	0	0
T172	0	2	0	0
T180	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	43	0	0
T43	2561	2	0	0
T44	930	0	0	0
T45	0	2	0	0
T49	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T71	0	1	0	0
T81	1512	0	0	0
T117	0	1	0	0
T137	0	1	0	0
T172	0	2	0	0
T180	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	56822	0	0
T43	2561	96	0	0
T44	930	0	0	0
T45	0	90	0	0
T49	0	49	0	0
T52	0	17	0	0
T53	0	109	0	0
T71	0	12	0	0
T81	1512	0	0	0
T117	0	35	0	0
T137	0	215	0	0
T172	0	145	0	0
T180	0	41	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	23	0	0
T43	2561	1	0	0
T44	930	0	0	0
T45	0	2	0	0
T49	0	1	0	0
T53	0	1	0	0
T81	1512	0	0	0
T115	0	1	0	0
T137	0	1	0	0
T172	0	1	0	0
T173	0	2	0	0
T174	0	2	0	0
T175	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T1 T4 T5 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T3 T46 T47 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T3 T46 T47 
149        1/1                    cnt_en = 1'b1;
           Tests:       T3 T46 T47 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T3 T46 T47 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T3 T46 T47 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T3 T46 T47 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T3 T46 T47 
167        1/1                    if (trigger_active) begin
           Tests:       T3 T46 T47 
168        1/1                      state_d = DetectSt;
           Tests:       T3 T46 T47 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T248 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T3 T46 T47 
182        1/1                  cnt_en = 1'b1;
           Tests:       T3 T46 T47 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T3 T46 T47 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T3 T46 T47 
191        1/1                      state_d = StableSt;
           Tests:       T3 T46 T47 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T3 T46 T47 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T3 T46 T47 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T3 T46 T47 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T3 T46 T47 
206        1/1                    state_d = IdleSt;
           Tests:       T52 T71 T172 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T3 T46 T47 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T46,T47

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T46,T47

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T3,T46,T47

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T3,T6,T11
1	0	Covered	T1,T4,T5
1	1	Covered	T3,T46,T47

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T3,T46,T47
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T3,T46,T47
0	1	Covered	T172,T192,T173
1	0	Covered	T52,T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T3,T46,T47
1	-	Covered	T172,T192,T173

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T3,T46,T47
DetectSt	168	Covered	T3,T46,T47
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T3,T46,T47

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T3,T46,T47
DebounceSt->IdleSt	163	Covered	T248
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T3,T46,T47
IdleSt->DebounceSt	148	Covered	T3,T46,T47
StableSt->IdleSt	206	Covered	T52,T71,T172

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T3,T46,T47
0	1	Covered	T3,T46,T47
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T3,T46,T47
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T3,T46,T47
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T3,T46,T47
DebounceSt	-	0	1	0	-	-	-	Covered	T248
DebounceSt	-	0	0	-	-	-	-	Covered	T3,T46,T47
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T3,T46,T47
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T52,T71,T172
StableSt	-	-	-	-	-	-	0	Covered	T3,T46,T47
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[5].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	59	0	0
CntIncr_A	5849450	28348	0	0
CntNoWrap_A	5849450	5391148	0	0
DetectStDropOut_A	5849450	0	0	0
DetectedOut_A	5849450	2481	0	0
DetectedPulseOut_A	5849450	29	0	0
DisabledIdleSt_A	5849450	5167016	0	0
DisabledNoDetection_A	5849450	5168899	0	0
EnterDebounceSt_A	5849450	30	0	0
EnterDetectSt_A	5849450	29	0	0
EnterStableSt_A	5849450	29	0	0
PulseIsPulse_A	5849450	29	0	0
StayInStableSt	5849450	2435	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5849450	5112	0	0
gen_low_level_sva.LowLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	10	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	59	0	0
T3	1092	2	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T46	0	2	0	0
T47	0	2	0	0
T52	0	2	0	0
T66	426	0	0	0
T71	0	2	0	0
T137	0	2	0	0
T169	0	2	0	0
T172	0	2	0	0
T192	0	2	0	0
T204	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	28348	0	0
T3	1092	92	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T46	0	56	0	0
T47	0	63	0	0
T52	0	27	0	0
T66	426	0	0	0
T71	0	28	0	0
T137	0	95	0	0
T169	0	60	0	0
T172	0	57	0	0
T192	0	45	0	0
T204	0	40	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391148	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	689	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	2481	0	0
T3	1092	46	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T46	0	232	0	0
T47	0	265	0	0
T52	0	18	0	0
T66	426	0	0	0
T71	0	15	0	0
T137	0	206	0	0
T169	0	53	0	0
T172	0	32	0	0
T192	0	27	0	0
T204	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	29	0	0
T3	1092	1	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T66	426	0	0	0
T71	0	1	0	0
T137	0	1	0	0
T169	0	1	0	0
T172	0	1	0	0
T192	0	1	0	0
T204	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5167016	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	3	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5168899	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	3	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	30	0	0
T3	1092	1	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T66	426	0	0	0
T71	0	1	0	0
T137	0	1	0	0
T169	0	1	0	0
T172	0	1	0	0
T192	0	1	0	0
T204	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	29	0	0
T3	1092	1	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T66	426	0	0	0
T71	0	1	0	0
T137	0	1	0	0
T169	0	1	0	0
T172	0	1	0	0
T192	0	1	0	0
T204	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	29	0	0
T3	1092	1	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T66	426	0	0	0
T71	0	1	0	0
T137	0	1	0	0
T169	0	1	0	0
T172	0	1	0	0
T192	0	1	0	0
T204	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	29	0	0
T3	1092	1	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T66	426	0	0	0
T71	0	1	0	0
T137	0	1	0	0
T169	0	1	0	0
T172	0	1	0	0
T192	0	1	0	0
T204	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	2435	0	0
T3	1092	44	0	0
T7	511	0	0	0
T8	484	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T22	496	0	0	0
T24	508	0	0	0
T25	502	0	0	0
T26	1505	0	0	0
T46	0	230	0	0
T47	0	263	0	0
T52	0	17	0	0
T66	426	0	0	0
T71	0	14	0	0
T137	0	204	0	0
T169	0	51	0	0
T172	0	31	0	0
T192	0	26	0	0
T204	0	78	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5112	0	0
T1	489	1	0	0
T2	1386	0	0	0
T3	1092	1	0	0
T4	421	1	0	0
T5	471	1	0	0
T7	511	1	0	0
T13	422	2	0	0
T14	497	5	0	0
T15	523	7	0	0
T16	668	0	0	0
T24	0	4	0	0
T66	0	3	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	10	0	0
T132	0	1	0	0
T167	0	2	0	0
T172	762	1	0	0
T173	0	2	0	0
T174	0	1	0	0
T192	0	1	0	0
T194	0	1	0	0
T253	0	1	0	0
T254	407	0	0	0
T255	690	0	0	0
T256	418	0	0	0
T257	423	0	0	0
T258	453	0	0	0
T259	673	0	0	0
T260	1130	0	0	0
T261	496	0	0	0
T262	521	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T4 T13 T2 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T4 T13 T2 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T49 T51 T52 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T4 T13 T2 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T4 T13 T2 
129        1/1              cnt_en = 1'b0;
           Tests:       T4 T13 T2 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T4 T13 T2 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T4 T13 T2 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T4 T13 T2 
139                     
140        1/1              unique case (state_q)
           Tests:       T4 T13 T2 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T4 T13 T2 
148        1/1                    state_d = DebounceSt;
           Tests:       T49 T51 T52 
149        1/1                    cnt_en = 1'b1;
           Tests:       T49 T51 T52 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T49 T51 T52 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T49 T51 T52 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T49 T51 T52 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T49 T51 T52 
167        1/1                    if (trigger_active) begin
           Tests:       T49 T51 T52 
168        1/1                      state_d = DetectSt;
           Tests:       T49 T51 T52 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T115 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T49 T51 T52 
182        1/1                  cnt_en = 1'b1;
           Tests:       T49 T51 T52 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T49 T51 T52 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T49 T51 T52 
191        1/1                      state_d = StableSt;
           Tests:       T49 T51 T52 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T49 T51 T52 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T49 T51 T52 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T49 T51 T52 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T49 T51 T52 
206        1/1                    state_d = IdleSt;
           Tests:       T52 T180 T137 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T49 T51 T52 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T4,T13,T2

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T4,T5
1	0	Covered	T4,T13,T2
1	1	Covered	T4,T13,T2

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T49,T51,T52

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T49,T51,T52

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T49,T51,T52

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T49,T117,T51
1	0	Covered	T4,T13,T2
1	1	Covered	T49,T51,T52

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T49,T51,T52
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T49,T51,T52
0	1	Covered	T180,T137,T169
1	0	Covered	T52,T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T49,T51,T52
1	-	Covered	T180,T137,T169

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T49,T51,T52
DetectSt	168	Covered	T49,T51,T52
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T49,T51,T52

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T49,T51,T52
DebounceSt->IdleSt	163	Covered	T115,T263
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T49,T51,T52
IdleSt->DebounceSt	148	Covered	T49,T51,T52
StableSt->IdleSt	206	Covered	T52,T180,T137

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T49,T51,T52
0	1	Covered	T49,T51,T52
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T49,T51,T52
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T49,T51,T52
IdleSt	0	-	-	-	-	-	-	Covered	T4,T13,T2
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T49,T51,T52
DebounceSt	-	0	1	0	-	-	-	Covered	T115
DebounceSt	-	0	0	-	-	-	-	Covered	T49,T51,T52
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T49,T51,T52
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T52,T180,T137
StableSt	-	-	-	-	-	-	0	Covered	T49,T51,T52
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_l2h

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	14	93.33
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	14	93.33

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	73	0	0
CntIncr_A	5849450	114248	0	0
CntNoWrap_A	5849450	5391134	0	0
DetectStDropOut_A	5849450	0	0	0
DetectedOut_A	5849450	46320	0	0
DetectedPulseOut_A	5849450	36	0	0
DisabledIdleSt_A	5849450	5156628	0	0
DisabledNoDetection_A	5849450	5158515	0	0
EnterDebounceSt_A	5849450	38	0	0
EnterDetectSt_A	5849450	36	0	0
EnterStableSt_A	5849450	36	0	0
PulseIsPulse_A	5849450	36	0	0
StayInStableSt	5849450	46263	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	13	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	73	0	0
T49	963	2	0	0
T51	0	2	0	0
T52	0	2	0	0
T53	0	2	0	0
T54	0	2	0	0
T65	643	0	0	0
T71	0	2	0	0
T137	0	2	0	0
T180	0	4	0	0
T195	502	0	0	0
T196	1882	0	0	0
T197	522	0	0	0
T198	403	0	0	0
T199	487	0	0	0
T200	498	0	0	0
T201	418	0	0	0
T202	422	0	0	0
T212	0	2	0	0
T215	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	114248	0	0
T49	963	69	0	0
T51	0	97	0	0
T52	0	27	0	0
T53	0	31	0	0
T54	0	38	0	0
T65	643	0	0	0
T71	0	28	0	0
T137	0	95	0	0
T180	0	156	0	0
T195	502	0	0	0
T196	1882	0	0	0
T197	522	0	0	0
T198	403	0	0	0
T199	487	0	0	0
T200	498	0	0	0
T201	418	0	0	0
T202	422	0	0	0
T212	0	72	0	0
T215	0	16394	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391134	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	46320	0	0
T49	963	41	0	0
T51	0	141	0	0
T52	0	18	0	0
T53	0	154	0	0
T54	0	54	0	0
T65	643	0	0	0
T71	0	15	0	0
T137	0	67	0	0
T180	0	49	0	0
T195	502	0	0	0
T196	1882	0	0	0
T197	522	0	0	0
T198	403	0	0	0
T199	487	0	0	0
T200	498	0	0	0
T201	418	0	0	0
T202	422	0	0	0
T212	0	284	0	0
T215	0	44	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	36	0	0
T49	963	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T65	643	0	0	0
T71	0	1	0	0
T137	0	1	0	0
T180	0	2	0	0
T195	502	0	0	0
T196	1882	0	0	0
T197	522	0	0	0
T198	403	0	0	0
T199	487	0	0	0
T200	498	0	0	0
T201	418	0	0	0
T202	422	0	0	0
T212	0	1	0	0
T215	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5156628	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5158515	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	38	0	0
T49	963	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T65	643	0	0	0
T71	0	1	0	0
T137	0	1	0	0
T180	0	2	0	0
T195	502	0	0	0
T196	1882	0	0	0
T197	522	0	0	0
T198	403	0	0	0
T199	487	0	0	0
T200	498	0	0	0
T201	418	0	0	0
T202	422	0	0	0
T212	0	1	0	0
T215	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	36	0	0
T49	963	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T65	643	0	0	0
T71	0	1	0	0
T137	0	1	0	0
T180	0	2	0	0
T195	502	0	0	0
T196	1882	0	0	0
T197	522	0	0	0
T198	403	0	0	0
T199	487	0	0	0
T200	498	0	0	0
T201	418	0	0	0
T202	422	0	0	0
T212	0	1	0	0
T215	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	36	0	0
T49	963	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T65	643	0	0	0
T71	0	1	0	0
T137	0	1	0	0
T180	0	2	0	0
T195	502	0	0	0
T196	1882	0	0	0
T197	522	0	0	0
T198	403	0	0	0
T199	487	0	0	0
T200	498	0	0	0
T201	418	0	0	0
T202	422	0	0	0
T212	0	1	0	0
T215	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	36	0	0
T49	963	1	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	1	0	0
T54	0	1	0	0
T65	643	0	0	0
T71	0	1	0	0
T137	0	1	0	0
T180	0	2	0	0
T195	502	0	0	0
T196	1882	0	0	0
T197	522	0	0	0
T198	403	0	0	0
T199	487	0	0	0
T200	498	0	0	0
T201	418	0	0	0
T202	422	0	0	0
T212	0	1	0	0
T215	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	46263	0	0
T49	963	39	0	0
T51	0	139	0	0
T52	0	17	0	0
T53	0	152	0	0
T54	0	52	0	0
T65	643	0	0	0
T71	0	14	0	0
T137	0	66	0	0
T180	0	46	0	0
T195	502	0	0	0
T196	1882	0	0	0
T197	522	0	0	0
T198	403	0	0	0
T199	487	0	0	0
T200	498	0	0	0
T201	418	0	0	0
T202	422	0	0	0
T212	0	282	0	0
T215	0	42	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	13	0	0
T54	540	0	0	0
T96	10455	0	0	0
T115	0	1	0	0
T137	0	1	0	0
T146	1799	0	0	0
T169	0	1	0	0
T179	0	1	0	0
T180	863	1	0	0
T227	423	0	0	0
T228	12973	0	0	0
T229	427	0	0	0
T249	0	1	0	0
T253	0	1	0	0
T264	0	1	0	0
T265	0	1	0	0
T266	0	1	0	0
T267	437	0	0	0
T268	30921	0	0	0
T269	495	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
TOTAL		46	42	91.30
CONT_ASSIGN	58	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	28	87.50
ALWAYS	219	3	3	100.00

57                        if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58         1/1              assign trigger_active = (trigger_i == 1'b0);
           Tests:       T4 T13 T2 
59                        end else begin : gen_trigger_active_high
60                          assign trigger_active = (trigger_i == 1'b1);
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T43 T44 T45 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T43 T44 T45 
149        1/1                    cnt_en = 1'b1;
           Tests:       T43 T44 T45 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T43 T44 T45 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T43 T44 T45 
163        0/1     ==>            state_d = IdleSt;
164        0/1     ==>            cnt_clr = 1'b1;
165        1/1                  end else if (cnt_done) begin
           Tests:       T43 T44 T45 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T43 T44 T45 
167        1/1                    if (trigger_active) begin
           Tests:       T43 T44 T45 
168        1/1                      state_d = DetectSt;
           Tests:       T43 T44 T45 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T46 T167 T168 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T43 T44 T45 
182        1/1                  cnt_en = 1'b1;
           Tests:       T43 T44 T45 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T43 T44 T45 
186        0/1     ==>            state_d = IdleSt;
187        0/1     ==>            cnt_clr = 1'b1;
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T43 T44 T45 
191        1/1                      state_d = StableSt;
           Tests:       T43 T44 T45 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T43 T44 T45 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T43 T44 T45 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T43 T44 T45 
195                               end
                   ==>  MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T43 T44 T45 
206        1/1                    state_d = IdleSt;
           Tests:       T43 T44 T45 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T43 T44 T45 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Covered	Percent
Conditions	22	20	90.91
Logical	22	20	90.91
Non-Logical	0	0
Event	0	0

 LINE       58
 EXPRESSION (trigger_i == 1'b0)
            ---------1---------

-1-	Status	Tests
0	Covered	T4,T13,T2
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T4,T13,T2
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T43,T44,T45

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T43,T44,T45

 LINE       99
 EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T43,T44,T45

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T50,T43,T44
1	0	Covered	T4,T13,T2
1	1	Covered	T43,T44,T45

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T45
0	1	Not Covered
1	0	Not Covered

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T43,T44,T45
0	1	Covered	T43,T44,T45
1	0	Covered	T52,T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T43,T44,T45
1	-	Covered	T43,T44,T45

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	5	83.33
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T43,T44,T45
DetectSt	168	Covered	T43,T44,T45
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T43,T44,T45

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T43,T44,T45
DebounceSt->IdleSt	163	Covered	T46,T167,T168
DetectSt->IdleSt	186	Not Covered
DetectSt->StableSt	191	Covered	T43,T44,T45
IdleSt->DebounceSt	148	Covered	T43,T44,T45
StableSt->IdleSt	206	Covered	T43,T44,T45

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Line No.	Total	Covered	Percent
Branches		21	19	90.48
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	10	8	80.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T43,T44,T45
0	1	Covered	T43,T44,T45
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T43,T44,T45
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==> (Excluded)
Exclude Annotation: VC_COV_UNR
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T43,T44,T45
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Not Covered
DebounceSt	-	0	1	1	-	-	-	Covered	T43,T44,T45
DebounceSt	-	0	1	0	-	-	-	Covered	T46,T167,T168
DebounceSt	-	0	0	-	-	-	-	Covered	T43,T44,T45
DetectSt	-	-	-	-	1	-	-	Not Covered
DetectSt	-	-	-	-	0	1	-	Covered	T43,T44,T45
DetectSt	-	-	-	-	0	0	-	Excluded		VC_COV_UNR
StableSt	-	-	-	-	-	-	1	Covered	T43,T44,T45
StableSt	-	-	-	-	-	-	0	Covered	T43,T44,T45
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_keyintr.gen_keyfsm[6].u_sysrst_ctrl_detect_h2l

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	15	93.75
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	15	93.75

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	53	0	0
CntIncr_A	5849450	70239	0	0
CntNoWrap_A	5849450	5391154	0	0
DetectStDropOut_A	5849450	0	0	0
DetectedOut_A	5849450	1498	0	0
DetectedPulseOut_A	5849450	25	0	0
DisabledIdleSt_A	5849450	5072052	0	0
DisabledNoDetection_A	5849450	5073933	0	0
EnterDebounceSt_A	5849450	28	0	0
EnterDetectSt_A	5849450	25	0	0
EnterStableSt_A	5849450	25	0	0
PulseIsPulse_A	5849450	25	0	0
StayInStableSt	5849450	1461	0	0
gen_edge_to_low_event_sva.EdgeToLowEvent_A	5849450	5568	0	0
gen_low_level_sva.LowLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	11	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	53	0	0
T43	2561	2	0	0
T44	930	2	0	0
T45	0	4	0	0
T46	0	3	0	0
T47	0	2	0	0
T52	0	2	0	0
T71	0	2	0	0
T81	1512	0	0	0
T137	0	2	0	0
T170	0	4	0	0
T180	0	2	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	70239	0	0
T43	2561	12	0	0
T44	930	92	0	0
T45	0	36	0	0
T46	0	112	0	0
T47	0	63	0	0
T52	0	27	0	0
T71	0	28	0	0
T81	1512	0	0	0
T137	0	95	0	0
T170	0	68	0	0
T180	0	78	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5391154	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	0	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1498	0	0
T43	2561	59	0	0
T44	930	40	0	0
T45	0	160	0	0
T46	0	132	0	0
T47	0	43	0	0
T52	0	18	0	0
T71	0	15	0	0
T81	1512	0	0	0
T137	0	42	0	0
T170	0	84	0	0
T180	0	169	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	25	0	0
T43	2561	1	0	0
T44	930	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T71	0	1	0	0
T81	1512	0	0	0
T137	0	1	0	0
T170	0	2	0	0
T180	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5072052	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5073933	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	28	0	0
T43	2561	1	0	0
T44	930	1	0	0
T45	0	2	0	0
T46	0	2	0	0
T47	0	1	0	0
T52	0	1	0	0
T71	0	1	0	0
T81	1512	0	0	0
T137	0	1	0	0
T170	0	2	0	0
T180	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	25	0	0
T43	2561	1	0	0
T44	930	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T71	0	1	0	0
T81	1512	0	0	0
T137	0	1	0	0
T170	0	2	0	0
T180	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	25	0	0
T43	2561	1	0	0
T44	930	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T71	0	1	0	0
T81	1512	0	0	0
T137	0	1	0	0
T170	0	2	0	0
T180	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	25	0	0
T43	2561	1	0	0
T44	930	1	0	0
T45	0	2	0	0
T46	0	1	0	0
T47	0	1	0	0
T52	0	1	0	0
T71	0	1	0	0
T81	1512	0	0	0
T137	0	1	0	0
T170	0	2	0	0
T180	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1461	0	0
T43	2561	58	0	0
T44	930	39	0	0
T45	0	157	0	0
T46	0	130	0	0
T47	0	41	0	0
T52	0	17	0	0
T71	0	14	0	0
T81	1512	0	0	0
T137	0	40	0	0
T170	0	81	0	0
T180	0	168	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0

gen_edge_to_low_event_sva.EdgeToLowEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5568	0	0
T2	1386	5	0	0
T3	1092	1	0	0
T4	421	2	0	0
T5	471	0	0	0
T7	511	0	0	0
T13	422	4	0	0
T14	497	8	0	0
T15	523	5	0	0
T16	668	3	0	0
T24	508	4	0	0
T26	0	3	0	0
T66	0	1	0	0

gen_low_level_sva.LowLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	11	0	0
T43	2561	1	0	0
T44	930	1	0	0
T45	0	1	0	0
T81	1512	0	0	0
T167	0	1	0	0
T170	0	1	0	0
T175	0	1	0	0
T179	0	1	0	0
T180	0	1	0	0
T192	0	1	0	0
T194	0	1	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T209	407	0	0	0
T210	719	0	0	0
T211	523	0	0	0