Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 58 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
57 if (EventType inside {LowLevel, EdgeToLow}) begin : gen_trigger_active_low
58 1/1 assign trigger_active = (trigger_i == 1'b0);
Tests: T1 T4 T5
59 end else begin : gen_trigger_active_high
60 assign trigger_active = (trigger_i == 1'b1);
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T4 T5
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T4 T5
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T4 T5
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T27 T6
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T2 T16
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T2 T16
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
105 1/1 cnt_q <= '0;
Tests: T1 T4 T5
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T5
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T4 T5
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T4 T5
129 1/1 cnt_en = 1'b0;
Tests: T1 T4 T5
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T4 T5
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T4 T5
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T4 T5
139
140 1/1 unique case (state_q)
Tests: T1 T4 T5
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T4 T5
148 1/1 state_d = DebounceSt;
Tests: T2 T27 T6
149 1/1 cnt_en = 1'b1;
Tests: T2 T27 T6
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T27 T6
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T27 T6
163 1/1 state_d = IdleSt;
Tests: T52 T71
164 1/1 cnt_clr = 1'b1;
Tests: T52 T71
165 1/1 end else if (cnt_done) begin
Tests: T2 T27 T6
166 1/1 cnt_clr = 1'b1;
Tests: T2 T27 T6
167 1/1 if (trigger_active) begin
Tests: T2 T27 T6
168 1/1 state_d = DetectSt;
Tests: T2 T27 T6
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T10 T72 T61
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T27 T6
182 1/1 cnt_en = 1'b1;
Tests: T2 T27 T6
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T27 T6
186 1/1 state_d = IdleSt;
Tests: T10 T44 T110
187 1/1 cnt_clr = 1'b1;
Tests: T10 T44 T110
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T27 T6
191 1/1 state_d = StableSt;
Tests: T2 T27 T6
192 1/1 cnt_clr = 1'b1;
Tests: T2 T27 T6
193 1/1 event_detected_o = 1'b1;
Tests: T2 T27 T6
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T27 T6
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T27 T6
206 1/1 state_d = IdleSt;
Tests: T2 T27 T58
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T27 T6
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T5
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T5
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T1 T4 T5
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T4 T5
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T4 T5
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T4 T5
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T10 T11
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T5 T2
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T5 T2
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
105 1/1 cnt_q <= '0;
Tests: T1 T4 T5
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T5
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T4 T5
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T4 T5
129 1/1 cnt_en = 1'b0;
Tests: T1 T4 T5
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T4 T5
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T4 T5
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T4 T5
139
140 1/1 unique case (state_q)
Tests: T1 T4 T5
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T4 T5
148 1/1 state_d = DebounceSt;
Tests: T2 T10 T11
149 1/1 cnt_en = 1'b1;
Tests: T2 T10 T11
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T10 T11
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T10 T11
163 1/1 state_d = IdleSt;
Tests: T52 T71
164 1/1 cnt_clr = 1'b1;
Tests: T52 T71
165 1/1 end else if (cnt_done) begin
Tests: T2 T10 T11
166 1/1 cnt_clr = 1'b1;
Tests: T2 T10 T11
167 1/1 if (trigger_active) begin
Tests: T2 T10 T11
168 1/1 state_d = DetectSt;
Tests: T2 T10 T11
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T3 T6 T11
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T2 T10 T11
182 1/1 cnt_en = 1'b1;
Tests: T2 T10 T11
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T2 T10 T11
186 1/1 state_d = IdleSt;
Tests: T10 T74 T46
187 1/1 cnt_clr = 1'b1;
Tests: T10 T74 T46
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T2 T10 T11
191 1/1 state_d = StableSt;
Tests: T2 T10 T11
192 1/1 cnt_clr = 1'b1;
Tests: T2 T10 T11
193 1/1 event_detected_o = 1'b1;
Tests: T2 T10 T11
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T2 T10 T11
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T2 T10 T11
206 1/1 state_d = IdleSt;
Tests: T2 T10 T11
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T2 T10 T11
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T5
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T5
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T4 T13 T2
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T4 T13 T2
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T2 T10 T17
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T2 T10 T17
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T2 T10 T17
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
105 1/1 cnt_q <= '0;
Tests: T1 T4 T5
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T5
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T4 T13 T2
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T4 T13 T2
129 1/1 cnt_en = 1'b0;
Tests: T4 T13 T2
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T4 T13 T2
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T4 T13 T2
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T4 T13 T2
139
140 1/1 unique case (state_q)
Tests: T4 T13 T2
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T4 T13 T2
148 1/1 state_d = DebounceSt;
Tests: T2 T10 T17
149 1/1 cnt_en = 1'b1;
Tests: T2 T10 T17
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T2 T10 T17
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T2 T10 T17
163 1/1 state_d = IdleSt;
Tests: T52 T71
164 1/1 cnt_clr = 1'b1;
Tests: T52 T71
165 1/1 end else if (cnt_done) begin
Tests: T2 T10 T17
166 1/1 cnt_clr = 1'b1;
Tests: T2 T10 T17
167 1/1 if (trigger_active) begin
Tests: T2 T10 T17
168 1/1 state_d = DetectSt;
Tests: T10 T72 T73
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T2 T17 T72
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T10 T72 T73
182 1/1 cnt_en = 1'b1;
Tests: T10 T72 T73
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T10 T72 T73
186 1/1 state_d = IdleSt;
Tests: T72 T73 T111
187 1/1 cnt_clr = 1'b1;
Tests: T72 T73 T111
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T10 T72 T73
191 1/1 state_d = StableSt;
Tests: T10 T72 T73
192 1/1 cnt_clr = 1'b1;
Tests: T10 T72 T73
193 1/1 event_detected_o = 1'b1;
Tests: T10 T72 T73
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T10 T72 T73
195 end
==> MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T10 T72 T73
206 1/1 state_d = IdleSt;
Tests: T10 T72 T73
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T10 T72 T73
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T5
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T5
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 43 | 43 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 79 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T29 T30 T31
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 if (!rst_ni) begin
70 trigger_active_q <= 1'b0;
71 end else begin
72 trigger_active_q <= trigger_active;
73 end
74 end
75
76 assign trigger_event = trigger_active & ~trigger_active_q;
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 1/1 assign trigger_event = trigger_active;
Tests: T29 T30 T31
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T5 T7 T28
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T5 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T5 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
105 1/1 cnt_q <= '0;
Tests: T1 T4 T5
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T5
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T5 T7 T28
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T5 T7 T28
129 1/1 cnt_en = 1'b0;
Tests: T5 T7 T28
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T5 T7 T28
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T5 T7 T28
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T5 T7 T28
139
140 1/1 unique case (state_q)
Tests: T5 T7 T28
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T5 T7 T28
148 1/1 state_d = DebounceSt;
Tests: T5 T7 T28
149 1/1 cnt_en = 1'b1;
Tests: T5 T7 T28
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T5 T7 T28
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T5 T7 T28
163 1/1 state_d = IdleSt;
Tests: T52 T71
164 1/1 cnt_clr = 1'b1;
Tests: T52 T71
165 1/1 end else if (cnt_done) begin
Tests: T5 T7 T28
166 1/1 cnt_clr = 1'b1;
Tests: T5 T7 T28
167 1/1 if (trigger_active) begin
Tests: T5 T7 T28
168 1/1 state_d = DetectSt;
Tests: T5 T7 T28
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T52 T95 T71
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T5 T7 T28
182 1/1 cnt_en = 1'b1;
Tests: T5 T7 T28
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T5 T7 T28
186 1/1 state_d = IdleSt;
Tests: T29 T30 T31
187 1/1 cnt_clr = 1'b1;
Tests: T29 T30 T31
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T5 T7 T28
191 1/1 state_d = StableSt;
Tests: T5 T7 T28
192 1/1 cnt_clr = 1'b1;
Tests: T5 T7 T28
193 1/1 event_detected_o = 1'b1;
Tests: T5 T7 T28
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T5 T7 T28
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T5 T7 T28
206 1/1 state_d = IdleSt;
Tests: T30 T31 T41
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T5 T7 T28
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T5
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T5
Line Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Line Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
|---|
| TOTAL | | 46 | 46 | 100.00 |
| CONT_ASSIGN | 60 | 1 | 1 | 100.00 |
| ALWAYS | 69 | 3 | 3 | 100.00 |
| CONT_ASSIGN | 76 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 92 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 99 | 1 | 1 | 100.00 |
| CONT_ASSIGN | 101 | 1 | 1 | 100.00 |
| ALWAYS | 104 | 3 | 3 | 100.00 |
| ALWAYS | 125 | 32 | 32 | 100.00 |
| ALWAYS | 219 | 3 | 3 | 100.00 |
59 end else begin : gen_trigger_active_high
60 1/1 assign trigger_active = (trigger_i == 1'b1);
Tests: T1 T5 T7
61 end
62
63 // In case of edge events, we also need to detect the transition.
64 logic trigger_event;
65 if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66 // This flop is always active, no matter the enable state.
67 logic trigger_active_q;
68 always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
70 1/1 trigger_active_q <= 1'b0;
Tests: T1 T4 T5
71 end else begin
72 1/1 trigger_active_q <= trigger_active;
Tests: T1 T4 T5
73 end
74 end
75
76 1/1 assign trigger_event = trigger_active & ~trigger_active_q;
Tests: T1 T4 T5
77 // In case of level events, the event is equal to the level being active.
78 end else begin : gen_trigger_event_level
79 assign trigger_event = trigger_active;
80 end
81
82 /////////////////
83 // Timer Logic //
84 /////////////////
85
86 // Take the maximum width of both timer values.
87 localparam int unsigned TimerWidth =
88 (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89
90 logic cnt_en, cnt_clr;
91 logic [TimerWidth-1:0] cnt_d, cnt_q;
92 1/1 assign cnt_d = (cnt_clr) ? '0 :
Tests: T1 T5 T7
93 (cnt_en) ? cnt_q + 1'b1 :
94 cnt_q;
95
96
97 logic cnt_done, thresh_sel;
98 logic [TimerWidth-1:0] thresh;
99 1/1 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
Tests: T1 T5 T3
100 TimerWidth'(cfg_debounce_timer_i);
101 1/1 assign cnt_done = (cnt_q >= thresh);
Tests: T1 T5 T3
102
103 always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
105 1/1 cnt_q <= '0;
Tests: T1 T4 T5
106 end else begin
107 1/1 cnt_q <= cnt_d;
Tests: T1 T4 T5
108 end
109 end
110
111 /////////
112 // FSM //
113 /////////
114
115 typedef enum logic [1:0] {
116 IdleSt,
117 DebounceSt,
118 DetectSt,
119 StableSt
120 } state_t;
121
122 state_t state_d, state_q;
123
124 always_comb begin : p_fsm
125 1/1 state_d = state_q;
Tests: T1 T4 T5
126
127 // Counter controls (clear has priority).
128 1/1 cnt_clr = 1'b0;
Tests: T1 T4 T5
129 1/1 cnt_en = 1'b0;
Tests: T1 T4 T5
130
131 // Detected outputs
132 1/1 event_detected_o = 1'b0;
Tests: T1 T4 T5
133 1/1 event_detected_pulse_o = 1'b0;
Tests: T1 T4 T5
134
135 // Threshold select
136 // 0: debounce
137 // 1: detect
138 1/1 thresh_sel = 1'b0;
Tests: T1 T4 T5
139
140 1/1 unique case (state_q)
Tests: T1 T4 T5
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 1/1 if (trigger_event && cfg_enable_i) begin
Tests: T1 T4 T5
148 1/1 state_d = DebounceSt;
Tests: T1 T5 T7
149 1/1 cnt_en = 1'b1;
Tests: T1 T5 T7
150 end
MISSING_ELSE
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 1/1 cnt_en = 1'b1;
Tests: T1 T5 T7
161 // Unconditionally go back to idle if the detector is disabled.
162 1/1 if (!cfg_enable_i) begin
Tests: T1 T5 T7
163 1/1 state_d = IdleSt;
Tests: T52 T71
164 1/1 cnt_clr = 1'b1;
Tests: T52 T71
165 1/1 end else if (cnt_done) begin
Tests: T1 T5 T7
166 1/1 cnt_clr = 1'b1;
Tests: T1 T5 T7
167 1/1 if (trigger_active) begin
Tests: T1 T5 T7
168 1/1 state_d = DetectSt;
Tests: T1 T7 T8
169 end else begin
170 1/1 state_d = IdleSt;
Tests: T5 T28 T59
171 end
172 end
MISSING_ELSE
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 1/1 thresh_sel = 1'b1;
Tests: T1 T7 T8
182 1/1 cnt_en = 1'b1;
Tests: T1 T7 T8
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 1/1 if (!cfg_enable_i || !trigger_active) begin
Tests: T1 T7 T8
186 1/1 state_d = IdleSt;
Tests: T32 T33 T55
187 1/1 cnt_clr = 1'b1;
Tests: T32 T33 T55
188 // If the trigger is active, count up.
189 end else begin
190 1/1 if (cnt_done) begin
Tests: T1 T7 T8
191 1/1 state_d = StableSt;
Tests: T1 T7 T8
192 1/1 cnt_clr = 1'b1;
Tests: T1 T7 T8
193 1/1 event_detected_o = 1'b1;
Tests: T1 T7 T8
194 1/1 event_detected_pulse_o = 1'b1;
Tests: T1 T7 T8
195 end
MISSING_ELSE
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 1/1 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
Tests: T1 T7 T8
206 1/1 state_d = IdleSt;
Tests: T1 T7 T8
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 1/1 event_detected_o = 1'b1;
Tests: T1 T7 T8
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
215 endcase // state_q
216 end
217
218 always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219 1/1 if (!rst_ni) begin
Tests: T1 T4 T5
220 1/1 state_q <= IdleSt;
Tests: T1 T4 T5
221 end else begin
222 1/1 state_q <= state_d;
Tests: T1 T4 T5
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 22 | 100.00 |
| Logical | 22 | 22 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T5,T7 |
| 1 | Covered | T1,T4,T5 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T5,T7 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T5,T7 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T5,T7 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T7,T8 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T5,T7 |
| 1 | 0 | Covered | T26,T9,T91 |
| 1 | 1 | Covered | T1,T5,T7 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T7,T8 |
| 0 | 1 | Covered | T32,T33,T55 |
| 1 | 0 | Covered | T52,T71 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T1,T7,T8 |
| 0 | 1 | Covered | T1,T7,T8 |
| 1 | 0 | Covered | T30,T52,T71 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T1,T7,T8 |
| 1 | - | Covered | T1,T7,T8 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T4,T5 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T27,T6,T58 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T27,T6,T58 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T27,T6,T58 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T27,T6,T58 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T27,T6,T58 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T6,T58 |
| 0 | 1 | Covered | T44,T112,T113 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T27,T6,T58 |
| 0 | 1 | Covered | T27,T58,T60 |
| 1 | 0 | Covered | T52,T71 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T27,T6,T58 |
| 1 | - | Covered | T27,T58,T60 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 19 | 100.00 |
| Logical | 19 | 19 | 100.00 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T29,T30,T31 |
| 1 | Covered | T1,T4,T5 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T5,T7,T28 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T5,T7,T28 |
LINE 99
EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T5,T7,T28 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T29,T30,T31 |
| 1 | 0 | Covered | T30,T31,T41 |
| 1 | 1 | Covered | T5,T7,T28 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T7,T28 |
| 0 | 1 | Covered | T29,T30,T31 |
| 1 | 0 | Covered | T30,T31,T52 |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T5,T7,T28 |
| 0 | 1 | Covered | T30,T31,T41 |
| 1 | 0 | Covered | T52,T71,T114 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T5,T7,T28 |
| 1 | - | Covered | T30,T31,T41 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 16 | 15 | 93.75 |
| Logical | 16 | 15 | 93.75 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T4,T13,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T2,T10,T17 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T2,T10,T17 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T10,T72,T73 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T10,T17 |
| 1 | 0 | Covered | T4,T13,T2 |
| 1 | 1 | Covered | T2,T10,T17 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T10,T72,T73 |
| 0 | 1 | Covered | T72,T73,T111 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T10,T72,T73 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T10,T72,T73 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 22 | 21 | 95.45 |
| Logical | 22 | 21 | 95.45 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T1,T4,T5 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T3,T6,T11 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T3,T6,T11 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T3,T6,T11 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T3,T6,T11 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T3,T6,T11 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T6,T11 |
| 0 | 1 | Covered | T46,T54,T115 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
--------1-------- ------------------2-----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T3,T6,T11 |
| 0 | 1 | Covered | T11,T48,T43 |
| 1 | 0 | Covered | T52,T71 |
LINE 205
SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
---------1--------- -----2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | - | Covered | T3,T6,T11 |
| 1 | - | Covered | T11,T48,T43 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 60
EXPRESSION (trigger_i == 1'b1)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T4,T13,T2 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T1,T4,T5 |
| 1 | 0 | Covered | T4,T13,T2 |
| 1 | 1 | Covered | T4,T13,T2 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T2,T10,T17 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T2,T10,T17 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T2,T10,T17 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T10,T17 |
| 1 | 0 | Covered | T4,T13,T2 |
| 1 | 1 | Covered | T2,T10,T17 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T10,T17 |
| 0 | 1 | Covered | T10,T74,T110 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T10,T17 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T10,T17 |
Cond Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 )
Cond Coverage for Module self-instances :
| Total | Covered | Percent |
|---|
| Conditions | 19 | 18 | 94.74 |
| Logical | 19 | 18 | 94.74 |
| Non-Logical | 0 | 0 | |
| Event | 0 | 0 | |
LINE 58
EXPRESSION (trigger_i == 1'b0)
---------1---------
| -1- | Status | Tests |
|---|
| 0 | Covered | T4,T13,T2 |
| 1 | Covered | T1,T4,T5 |
LINE 76
EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
-------1------ ----------------------2---------------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T4,T13,T2 |
| 1 | 0 | Covered | T1,T4,T5 |
| 1 | 1 | Covered | T1,T4,T5 |
LINE 92
EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
---1---
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T2,T10,T17 |
LINE 92
SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
---1--
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T2,T10,T17 |
LINE 99
EXPRESSION (thresh_sel ? (16'(cfg_detect_timer_i)) : (16'(cfg_debounce_timer_i)))
-----1----
| -1- | Status | Tests |
|---|
| 0 | Covered | T1,T4,T5 |
| 1 | Covered | T2,T10,T17 |
LINE 147
EXPRESSION (trigger_event && cfg_enable_i)
------1------ ------2-----
| -1- | -2- | Status | Tests |
|---|
| 0 | 1 | Covered | T2,T10,T17 |
| 1 | 0 | Covered | T4,T13,T2 |
| 1 | 1 | Covered | T2,T10,T17 |
LINE 185
EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
--------1-------- ---------2---------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T17,T73 |
| 0 | 1 | Covered | T10,T110,T116 |
| 1 | 0 | Not Covered | |
LINE 205
EXPRESSION (((!cfg_enable_i)) || (((!trigger_active) && (!Sticky))))
--------1-------- -----------------2----------------
| -1- | -2- | Status | Tests |
|---|
| 0 | 0 | Covered | T2,T17,T73 |
| 0 | 1 | Unreachable | |
| 1 | 0 | Covered | T2,T17,T73 |
FSM Coverage for Module :
sysrst_ctrl_detect
Summary for FSM :: state_q
| Total | Covered | Percent | |
| States |
4 |
4 |
100.00 |
(Not included in score) |
| Transitions |
6 |
6 |
100.00 |
|
| Sequences |
0 |
0 |
|
|
State, Transition and Sequence Details for FSM :: state_q
| states | Line No. | Covered | Tests |
| DebounceSt |
148 |
Covered |
T27,T6,T58 |
| DetectSt |
168 |
Covered |
T27,T6,T58 |
| IdleSt |
163 |
Covered |
T1,T4,T5 |
| StableSt |
191 |
Covered |
T27,T6,T58 |
| transitions | Line No. | Covered | Tests |
| DebounceSt->DetectSt |
168 |
Covered |
T27,T6,T58 |
| DebounceSt->IdleSt |
163 |
Covered |
T61,T46,T117 |
| DetectSt->IdleSt |
186 |
Covered |
T10,T72,T73 |
| DetectSt->StableSt |
191 |
Covered |
T27,T6,T58 |
| IdleSt->DebounceSt |
148 |
Covered |
T27,T6,T58 |
| StableSt->IdleSt |
206 |
Covered |
T27,T58,T60 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=2,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=1,EventType=3,Sticky=0,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=3,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
23 |
22 |
95.65 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
| IF |
69 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T27,T6,T58 |
| 0 |
1 |
Covered |
T27,T6,T58 |
| 0 |
0 |
Covered |
T1,T4,T5 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T27,T6,T58 |
| 0 |
Covered |
T1,T4,T5 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T4,T5 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T27,T6,T58 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T1,T4,T5 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T52,T71 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T27,T6,T58 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T61,T46,T117 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T27,T6,T58 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T10,T32,T33 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T27,T6,T58 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T1,T7,T8 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T27,T58,T60 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T27,T6,T58 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T4,T5 |
69 if (!rst_ni) begin
-1-
70 trigger_active_q <= 1'b0;
==>
71 end else begin
72 trigger_active_q <= trigger_active;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T4,T5 |
Branch Coverage for Module :
sysrst_ctrl_detect ( parameter DebounceTimerWidth=16,DetectTimerWidth=1,EventType=1,Sticky=1,TimerWidth=16 + DebounceTimerWidth=16,DetectTimerWidth=32,EventType=1,Sticky=0,TimerWidth=32 )
Branch Coverage for Module self-instances :
| Line No. | Total | Covered | Percent |
| Branches |
|
21 |
20 |
95.24 |
| TERNARY |
92 |
3 |
3 |
100.00 |
| TERNARY |
99 |
2 |
2 |
100.00 |
| IF |
104 |
2 |
2 |
100.00 |
| CASE |
140 |
12 |
11 |
91.67 |
| IF |
219 |
2 |
2 |
100.00 |
92 assign cnt_d = (cnt_clr) ? '0 :
-1-
==>
93 (cnt_en) ? cnt_q + 1'b1 :
-2-
==>
==>
Branches:
| -1- | -2- | Status | Tests |
| 1 |
- |
Covered |
T5,T2,T7 |
| 0 |
1 |
Covered |
T5,T2,T7 |
| 0 |
0 |
Covered |
T1,T4,T5 |
99 assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
-1-
==>
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T5,T7,T28 |
| 0 |
Covered |
T1,T4,T5 |
104 if (!rst_ni) begin
-1-
105 cnt_q <= '0;
==>
106 end else begin
107 cnt_q <= cnt_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T4,T5 |
140 unique case (state_q)
-1-
141 ////////////////////////////////////////////
142 // We are waiting for the event to occur.
143 // This can be either a specific level or edge,
144 // depending on the configuration.
145 IdleSt: begin
146 // Stay here if the detector is disabled.
147 if (trigger_event && cfg_enable_i) begin
-2-
148 state_d = DebounceSt;
==>
149 cnt_en = 1'b1;
150 end
MISSING_ELSE
==>
151 end
152 ////////////////////////////////////////////
153 // If an event has occurred, we back off for
154 // the amount of debounce cycles configured.
155 // Once the timer has expired, we sample the
156 // signal again and check whether it has the
157 // correct level. If so, we move on to the
158 // detection stage, otherwise we fall back.
159 DebounceSt: begin
160 cnt_en = 1'b1;
161 // Unconditionally go back to idle if the detector is disabled.
162 if (!cfg_enable_i) begin
-3-
163 state_d = IdleSt;
==>
164 cnt_clr = 1'b1;
165 end else if (cnt_done) begin
-4-
166 cnt_clr = 1'b1;
167 if (trigger_active) begin
-5-
168 state_d = DetectSt;
==>
169 end else begin
170 state_d = IdleSt;
==>
171 end
172 end
MISSING_ELSE
==>
173 end
174 ////////////////////////////////////////////
175 // Once the debounce period has passed, we
176 // check whether the signal remains stable
177 // throughout the entire detection period.
178 // If it is not stable at any cycle, we fall
179 // back to idle.
180 DetectSt: begin
181 thresh_sel = 1'b1;
182 cnt_en = 1'b1;
183 // Go back to idle if either the trigger level is not active anymore, or if the
184 // detector is disabled.
185 if (!cfg_enable_i || !trigger_active) begin
-6-
186 state_d = IdleSt;
==>
187 cnt_clr = 1'b1;
188 // If the trigger is active, count up.
189 end else begin
190 if (cnt_done) begin
-7-
191 state_d = StableSt;
==>
192 cnt_clr = 1'b1;
193 event_detected_o = 1'b1;
194 event_detected_pulse_o = 1'b1;
195 end
MISSING_ELSE
==>
196 end
197 end
198 ////////////////////////////////////////////
199 // At this point we have detected the event
200 // and monitor whether the signal remains stable.
201 StableSt: begin
202 // Go back to idle if either the trigger level is not active anymore, or if the detector is
203 // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204 // to go back to the idle state.
205 if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
-8-
206 state_d = IdleSt;
==>
207 // Otherwise keep the event detected output signal high.
208 end else begin
209 event_detected_o = 1'b1;
==>
210 end
211 end
212 ////////////////////////////////////////////
213 // This is a full case statement
214 default: ;
==>
Branches:
| -1- | -2- | -3- | -4- | -5- | -6- | -7- | -8- | Status | Tests |
| IdleSt |
1 |
- |
- |
- |
- |
- |
- |
Covered |
T5,T2,T7 |
| IdleSt |
0 |
- |
- |
- |
- |
- |
- |
Covered |
T4,T13,T2 |
| DebounceSt |
- |
1 |
- |
- |
- |
- |
- |
Covered |
T52,T71 |
| DebounceSt |
- |
0 |
1 |
1 |
- |
- |
- |
Covered |
T5,T7,T28 |
| DebounceSt |
- |
0 |
1 |
0 |
- |
- |
- |
Covered |
T2,T17,T72 |
| DebounceSt |
- |
0 |
0 |
- |
- |
- |
- |
Covered |
T5,T2,T7 |
| DetectSt |
- |
- |
- |
- |
1 |
- |
- |
Covered |
T72,T73,T29 |
| DetectSt |
- |
- |
- |
- |
0 |
1 |
- |
Covered |
T5,T7,T28 |
| DetectSt |
- |
- |
- |
- |
0 |
0 |
- |
Covered |
T5,T7,T28 |
| StableSt |
- |
- |
- |
- |
- |
- |
1 |
Covered |
T10,T72,T73 |
| StableSt |
- |
- |
- |
- |
- |
- |
0 |
Covered |
T5,T7,T28 |
| default |
- |
- |
- |
- |
- |
- |
- |
Not Covered |
|
219 if (!rst_ni) begin
-1-
220 state_q <= IdleSt;
==>
221 end else begin
222 state_q <= state_d;
==>
Branches:
| -1- | Status | Tests |
| 1 |
Covered |
T1,T4,T5 |
| 0 |
Covered |
T1,T4,T5 |
Assert Coverage for Module :
sysrst_ctrl_detect
Assertion Details
CntClr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
17578 |
0 |
0 |
| T1 |
489 |
2 |
0 |
0 |
| T2 |
2772 |
0 |
0 |
0 |
| T3 |
2184 |
0 |
0 |
0 |
| T4 |
421 |
0 |
0 |
0 |
| T5 |
942 |
3 |
0 |
0 |
| T6 |
805 |
0 |
0 |
0 |
| T7 |
1022 |
4 |
0 |
0 |
| T8 |
0 |
2 |
0 |
0 |
| T9 |
2780 |
2 |
0 |
0 |
| T12 |
0 |
4 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
994 |
0 |
0 |
0 |
| T15 |
1046 |
0 |
0 |
0 |
| T16 |
1336 |
0 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T23 |
499 |
0 |
0 |
0 |
| T24 |
508 |
0 |
0 |
0 |
| T27 |
725 |
6 |
0 |
0 |
| T28 |
0 |
3 |
0 |
0 |
| T29 |
0 |
22 |
0 |
0 |
| T32 |
0 |
14 |
0 |
0 |
| T52 |
0 |
18 |
0 |
0 |
| T57 |
434 |
0 |
0 |
0 |
| T58 |
0 |
2 |
0 |
0 |
| T60 |
0 |
6 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T64 |
0 |
2 |
0 |
0 |
| T68 |
434 |
0 |
0 |
0 |
| T69 |
0 |
4 |
0 |
0 |
| T70 |
0 |
4 |
0 |
0 |
| T78 |
505 |
0 |
0 |
0 |
| T79 |
565 |
0 |
0 |
0 |
| T89 |
522 |
0 |
0 |
0 |
| T118 |
0 |
2 |
0 |
0 |
| T119 |
0 |
1 |
0 |
0 |
| T120 |
0 |
6 |
0 |
0 |
| T121 |
409 |
0 |
0 |
0 |
CntIncr_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
1844457 |
0 |
0 |
| T1 |
489 |
25 |
0 |
0 |
| T2 |
2772 |
0 |
0 |
0 |
| T3 |
2184 |
0 |
0 |
0 |
| T4 |
421 |
0 |
0 |
0 |
| T5 |
942 |
41 |
0 |
0 |
| T6 |
805 |
0 |
0 |
0 |
| T7 |
1022 |
46 |
0 |
0 |
| T8 |
0 |
25 |
0 |
0 |
| T9 |
2780 |
25 |
0 |
0 |
| T12 |
0 |
46 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
994 |
0 |
0 |
0 |
| T15 |
1046 |
0 |
0 |
0 |
| T16 |
1336 |
0 |
0 |
0 |
| T17 |
0 |
20 |
0 |
0 |
| T23 |
499 |
0 |
0 |
0 |
| T24 |
508 |
0 |
0 |
0 |
| T27 |
725 |
207 |
0 |
0 |
| T28 |
0 |
41 |
0 |
0 |
| T32 |
0 |
1008 |
0 |
0 |
| T52 |
0 |
725 |
0 |
0 |
| T57 |
434 |
0 |
0 |
0 |
| T58 |
0 |
35 |
0 |
0 |
| T59 |
0 |
19 |
0 |
0 |
| T60 |
0 |
158 |
0 |
0 |
| T61 |
0 |
21 |
0 |
0 |
| T64 |
0 |
42 |
0 |
0 |
| T68 |
434 |
0 |
0 |
0 |
| T69 |
0 |
21 |
0 |
0 |
| T70 |
0 |
127 |
0 |
0 |
| T78 |
505 |
0 |
0 |
0 |
| T79 |
565 |
0 |
0 |
0 |
| T89 |
522 |
0 |
0 |
0 |
| T118 |
0 |
84 |
0 |
0 |
| T119 |
0 |
33 |
0 |
0 |
| T120 |
0 |
208 |
0 |
0 |
| T121 |
409 |
0 |
0 |
0 |
CntNoWrap_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
140153804 |
0 |
0 |
| T1 |
12714 |
2286 |
0 |
0 |
| T2 |
36036 |
25603 |
0 |
0 |
| T3 |
28392 |
17959 |
0 |
0 |
| T4 |
10946 |
520 |
0 |
0 |
| T5 |
12246 |
1817 |
0 |
0 |
| T7 |
13286 |
2856 |
0 |
0 |
| T13 |
10972 |
546 |
0 |
0 |
| T14 |
12922 |
2496 |
0 |
0 |
| T15 |
13598 |
3172 |
0 |
0 |
| T16 |
17368 |
6942 |
0 |
0 |
DetectStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
1999 |
0 |
0 |
| T29 |
12219 |
11 |
0 |
0 |
| T30 |
0 |
5 |
0 |
0 |
| T32 |
7578 |
7 |
0 |
0 |
| T33 |
0 |
2 |
0 |
0 |
| T52 |
0 |
1 |
0 |
0 |
| T69 |
505 |
0 |
0 |
0 |
| T71 |
8312 |
1 |
0 |
0 |
| T72 |
1529 |
0 |
0 |
0 |
| T83 |
1342 |
0 |
0 |
0 |
| T84 |
491 |
0 |
0 |
0 |
| T97 |
0 |
2 |
0 |
0 |
| T104 |
423 |
0 |
0 |
0 |
| T105 |
512 |
0 |
0 |
0 |
| T106 |
421 |
0 |
0 |
0 |
| T107 |
525 |
0 |
0 |
0 |
| T108 |
402 |
0 |
0 |
0 |
| T112 |
686 |
1 |
0 |
0 |
| T122 |
0 |
7 |
0 |
0 |
| T123 |
0 |
7 |
0 |
0 |
| T124 |
0 |
5 |
0 |
0 |
| T125 |
0 |
22 |
0 |
0 |
| T126 |
0 |
4 |
0 |
0 |
| T127 |
0 |
4 |
0 |
0 |
| T128 |
0 |
1 |
0 |
0 |
| T129 |
0 |
4 |
0 |
0 |
| T130 |
0 |
1 |
0 |
0 |
| T131 |
0 |
1 |
0 |
0 |
| T132 |
0 |
1 |
0 |
0 |
| T133 |
0 |
5 |
0 |
0 |
| T134 |
0 |
5 |
0 |
0 |
| T135 |
502 |
0 |
0 |
0 |
| T136 |
467 |
0 |
0 |
0 |
| T137 |
1022 |
0 |
0 |
0 |
| T138 |
2241 |
0 |
0 |
0 |
| T139 |
721 |
0 |
0 |
0 |
| T140 |
422 |
0 |
0 |
0 |
| T141 |
1493 |
0 |
0 |
0 |
| T142 |
702 |
0 |
0 |
0 |
DetectedOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
1271442 |
0 |
0 |
| T1 |
489 |
3 |
0 |
0 |
| T2 |
2772 |
0 |
0 |
0 |
| T3 |
2184 |
0 |
0 |
0 |
| T4 |
421 |
0 |
0 |
0 |
| T5 |
942 |
46 |
0 |
0 |
| T6 |
805 |
0 |
0 |
0 |
| T7 |
1022 |
89 |
0 |
0 |
| T8 |
0 |
3 |
0 |
0 |
| T9 |
2780 |
3 |
0 |
0 |
| T12 |
0 |
87 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
994 |
0 |
0 |
0 |
| T15 |
1046 |
0 |
0 |
0 |
| T16 |
1336 |
0 |
0 |
0 |
| T23 |
499 |
0 |
0 |
0 |
| T24 |
508 |
0 |
0 |
0 |
| T27 |
725 |
9 |
0 |
0 |
| T40 |
0 |
132 |
0 |
0 |
| T52 |
0 |
501 |
0 |
0 |
| T55 |
0 |
52 |
0 |
0 |
| T57 |
434 |
0 |
0 |
0 |
| T58 |
0 |
4 |
0 |
0 |
| T60 |
0 |
12 |
0 |
0 |
| T64 |
0 |
8 |
0 |
0 |
| T68 |
434 |
0 |
0 |
0 |
| T69 |
0 |
82 |
0 |
0 |
| T70 |
0 |
20 |
0 |
0 |
| T78 |
505 |
0 |
0 |
0 |
| T79 |
565 |
0 |
0 |
0 |
| T89 |
522 |
0 |
0 |
0 |
| T103 |
0 |
26 |
0 |
0 |
| T112 |
0 |
10 |
0 |
0 |
| T118 |
0 |
11 |
0 |
0 |
| T120 |
0 |
23 |
0 |
0 |
| T121 |
409 |
0 |
0 |
0 |
| T142 |
0 |
13 |
0 |
0 |
| T143 |
0 |
3 |
0 |
0 |
DetectedPulseOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
5430 |
0 |
0 |
| T1 |
489 |
1 |
0 |
0 |
| T2 |
2772 |
0 |
0 |
0 |
| T3 |
2184 |
0 |
0 |
0 |
| T4 |
421 |
0 |
0 |
0 |
| T5 |
942 |
1 |
0 |
0 |
| T6 |
805 |
0 |
0 |
0 |
| T7 |
1022 |
2 |
0 |
0 |
| T8 |
0 |
1 |
0 |
0 |
| T9 |
2780 |
1 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
994 |
0 |
0 |
0 |
| T15 |
1046 |
0 |
0 |
0 |
| T16 |
1336 |
0 |
0 |
0 |
| T23 |
499 |
0 |
0 |
0 |
| T24 |
508 |
0 |
0 |
0 |
| T27 |
725 |
3 |
0 |
0 |
| T40 |
0 |
3 |
0 |
0 |
| T52 |
0 |
6 |
0 |
0 |
| T55 |
0 |
3 |
0 |
0 |
| T57 |
434 |
0 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T60 |
0 |
3 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T68 |
434 |
0 |
0 |
0 |
| T69 |
0 |
2 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T78 |
505 |
0 |
0 |
0 |
| T79 |
565 |
0 |
0 |
0 |
| T89 |
522 |
0 |
0 |
0 |
| T103 |
0 |
1 |
0 |
0 |
| T112 |
0 |
1 |
0 |
0 |
| T118 |
0 |
1 |
0 |
0 |
| T120 |
0 |
3 |
0 |
0 |
| T121 |
409 |
0 |
0 |
0 |
| T142 |
0 |
1 |
0 |
0 |
| T143 |
0 |
1 |
0 |
0 |
DisabledIdleSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
130848350 |
0 |
0 |
| T1 |
12714 |
2204 |
0 |
0 |
| T2 |
36036 |
23891 |
0 |
0 |
| T3 |
28392 |
14526 |
0 |
0 |
| T4 |
10946 |
520 |
0 |
0 |
| T5 |
12246 |
1708 |
0 |
0 |
| T7 |
13286 |
2670 |
0 |
0 |
| T13 |
10972 |
546 |
0 |
0 |
| T14 |
12922 |
2496 |
0 |
0 |
| T15 |
13598 |
3172 |
0 |
0 |
| T16 |
17368 |
6942 |
0 |
0 |
DisabledNoDetection_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
130894391 |
0 |
0 |
| T1 |
12714 |
2229 |
0 |
0 |
| T2 |
36036 |
23917 |
0 |
0 |
| T3 |
28392 |
14547 |
0 |
0 |
| T4 |
10946 |
546 |
0 |
0 |
| T5 |
12246 |
1732 |
0 |
0 |
| T7 |
13286 |
2694 |
0 |
0 |
| T13 |
10972 |
572 |
0 |
0 |
| T14 |
12922 |
2522 |
0 |
0 |
| T15 |
13598 |
3198 |
0 |
0 |
| T16 |
17368 |
6968 |
0 |
0 |
EnterDebounceSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
9062 |
0 |
0 |
| T1 |
489 |
1 |
0 |
0 |
| T2 |
2772 |
0 |
0 |
0 |
| T3 |
2184 |
0 |
0 |
0 |
| T4 |
421 |
0 |
0 |
0 |
| T5 |
942 |
2 |
0 |
0 |
| T6 |
805 |
0 |
0 |
0 |
| T7 |
1022 |
2 |
0 |
0 |
| T8 |
0 |
1 |
0 |
0 |
| T9 |
2780 |
1 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
994 |
0 |
0 |
0 |
| T15 |
1046 |
0 |
0 |
0 |
| T16 |
1336 |
0 |
0 |
0 |
| T17 |
0 |
1 |
0 |
0 |
| T23 |
499 |
0 |
0 |
0 |
| T24 |
508 |
0 |
0 |
0 |
| T27 |
725 |
3 |
0 |
0 |
| T28 |
0 |
2 |
0 |
0 |
| T32 |
0 |
7 |
0 |
0 |
| T52 |
0 |
10 |
0 |
0 |
| T57 |
434 |
0 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T59 |
0 |
1 |
0 |
0 |
| T60 |
0 |
3 |
0 |
0 |
| T61 |
0 |
1 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T68 |
434 |
0 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T78 |
505 |
0 |
0 |
0 |
| T79 |
565 |
0 |
0 |
0 |
| T89 |
522 |
0 |
0 |
0 |
| T118 |
0 |
1 |
0 |
0 |
| T119 |
0 |
1 |
0 |
0 |
| T120 |
0 |
3 |
0 |
0 |
| T121 |
409 |
0 |
0 |
0 |
EnterDetectSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
8537 |
0 |
0 |
| T1 |
489 |
1 |
0 |
0 |
| T2 |
2772 |
0 |
0 |
0 |
| T3 |
2184 |
0 |
0 |
0 |
| T4 |
421 |
0 |
0 |
0 |
| T5 |
942 |
1 |
0 |
0 |
| T6 |
805 |
0 |
0 |
0 |
| T7 |
1022 |
2 |
0 |
0 |
| T8 |
0 |
1 |
0 |
0 |
| T9 |
2780 |
1 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
994 |
0 |
0 |
0 |
| T15 |
1046 |
0 |
0 |
0 |
| T16 |
1336 |
0 |
0 |
0 |
| T23 |
499 |
0 |
0 |
0 |
| T24 |
508 |
0 |
0 |
0 |
| T27 |
725 |
3 |
0 |
0 |
| T32 |
0 |
7 |
0 |
0 |
| T33 |
0 |
2 |
0 |
0 |
| T40 |
0 |
3 |
0 |
0 |
| T52 |
0 |
8 |
0 |
0 |
| T57 |
434 |
0 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T60 |
0 |
3 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T68 |
434 |
0 |
0 |
0 |
| T69 |
0 |
2 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T78 |
505 |
0 |
0 |
0 |
| T79 |
565 |
0 |
0 |
0 |
| T89 |
522 |
0 |
0 |
0 |
| T112 |
0 |
2 |
0 |
0 |
| T118 |
0 |
1 |
0 |
0 |
| T120 |
0 |
3 |
0 |
0 |
| T121 |
409 |
0 |
0 |
0 |
| T142 |
0 |
1 |
0 |
0 |
| T143 |
0 |
1 |
0 |
0 |
EnterStableSt_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
5430 |
0 |
0 |
| T1 |
489 |
1 |
0 |
0 |
| T2 |
2772 |
0 |
0 |
0 |
| T3 |
2184 |
0 |
0 |
0 |
| T4 |
421 |
0 |
0 |
0 |
| T5 |
942 |
1 |
0 |
0 |
| T6 |
805 |
0 |
0 |
0 |
| T7 |
1022 |
2 |
0 |
0 |
| T8 |
0 |
1 |
0 |
0 |
| T9 |
2780 |
1 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
994 |
0 |
0 |
0 |
| T15 |
1046 |
0 |
0 |
0 |
| T16 |
1336 |
0 |
0 |
0 |
| T23 |
499 |
0 |
0 |
0 |
| T24 |
508 |
0 |
0 |
0 |
| T27 |
725 |
3 |
0 |
0 |
| T40 |
0 |
3 |
0 |
0 |
| T52 |
0 |
6 |
0 |
0 |
| T55 |
0 |
3 |
0 |
0 |
| T57 |
434 |
0 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T60 |
0 |
3 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T68 |
434 |
0 |
0 |
0 |
| T69 |
0 |
2 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T78 |
505 |
0 |
0 |
0 |
| T79 |
565 |
0 |
0 |
0 |
| T89 |
522 |
0 |
0 |
0 |
| T103 |
0 |
1 |
0 |
0 |
| T112 |
0 |
1 |
0 |
0 |
| T118 |
0 |
1 |
0 |
0 |
| T120 |
0 |
3 |
0 |
0 |
| T121 |
409 |
0 |
0 |
0 |
| T142 |
0 |
1 |
0 |
0 |
| T143 |
0 |
1 |
0 |
0 |
PulseIsPulse_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
5430 |
0 |
0 |
| T1 |
489 |
1 |
0 |
0 |
| T2 |
2772 |
0 |
0 |
0 |
| T3 |
2184 |
0 |
0 |
0 |
| T4 |
421 |
0 |
0 |
0 |
| T5 |
942 |
1 |
0 |
0 |
| T6 |
805 |
0 |
0 |
0 |
| T7 |
1022 |
2 |
0 |
0 |
| T8 |
0 |
1 |
0 |
0 |
| T9 |
2780 |
1 |
0 |
0 |
| T12 |
0 |
2 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
994 |
0 |
0 |
0 |
| T15 |
1046 |
0 |
0 |
0 |
| T16 |
1336 |
0 |
0 |
0 |
| T23 |
499 |
0 |
0 |
0 |
| T24 |
508 |
0 |
0 |
0 |
| T27 |
725 |
3 |
0 |
0 |
| T40 |
0 |
3 |
0 |
0 |
| T52 |
0 |
6 |
0 |
0 |
| T55 |
0 |
3 |
0 |
0 |
| T57 |
434 |
0 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T60 |
0 |
3 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T68 |
434 |
0 |
0 |
0 |
| T69 |
0 |
2 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T78 |
505 |
0 |
0 |
0 |
| T79 |
565 |
0 |
0 |
0 |
| T89 |
522 |
0 |
0 |
0 |
| T103 |
0 |
1 |
0 |
0 |
| T112 |
0 |
1 |
0 |
0 |
| T118 |
0 |
1 |
0 |
0 |
| T120 |
0 |
3 |
0 |
0 |
| T121 |
409 |
0 |
0 |
0 |
| T142 |
0 |
1 |
0 |
0 |
| T143 |
0 |
1 |
0 |
0 |
StayInStableSt
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
152085700 |
1265235 |
0 |
0 |
| T1 |
489 |
2 |
0 |
0 |
| T2 |
2772 |
0 |
0 |
0 |
| T3 |
2184 |
0 |
0 |
0 |
| T4 |
421 |
0 |
0 |
0 |
| T5 |
942 |
44 |
0 |
0 |
| T6 |
805 |
0 |
0 |
0 |
| T7 |
1022 |
86 |
0 |
0 |
| T8 |
0 |
2 |
0 |
0 |
| T9 |
2780 |
2 |
0 |
0 |
| T12 |
0 |
84 |
0 |
0 |
| T13 |
844 |
0 |
0 |
0 |
| T14 |
994 |
0 |
0 |
0 |
| T15 |
1046 |
0 |
0 |
0 |
| T16 |
1336 |
0 |
0 |
0 |
| T23 |
499 |
0 |
0 |
0 |
| T24 |
508 |
0 |
0 |
0 |
| T27 |
725 |
6 |
0 |
0 |
| T40 |
0 |
129 |
0 |
0 |
| T52 |
0 |
495 |
0 |
0 |
| T55 |
0 |
49 |
0 |
0 |
| T57 |
434 |
0 |
0 |
0 |
| T58 |
0 |
3 |
0 |
0 |
| T60 |
0 |
9 |
0 |
0 |
| T64 |
0 |
7 |
0 |
0 |
| T68 |
434 |
0 |
0 |
0 |
| T69 |
0 |
79 |
0 |
0 |
| T70 |
0 |
18 |
0 |
0 |
| T78 |
505 |
0 |
0 |
0 |
| T79 |
565 |
0 |
0 |
0 |
| T89 |
522 |
0 |
0 |
0 |
| T103 |
0 |
25 |
0 |
0 |
| T112 |
0 |
9 |
0 |
0 |
| T118 |
0 |
10 |
0 |
0 |
| T120 |
0 |
20 |
0 |
0 |
| T121 |
409 |
0 |
0 |
0 |
| T142 |
0 |
12 |
0 |
0 |
| T143 |
0 |
2 |
0 |
0 |
gen_edge_to_low_event_sva.EdgeToLowEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
52645050 |
40704 |
0 |
0 |
| T1 |
1467 |
3 |
0 |
0 |
| T2 |
12474 |
20 |
0 |
0 |
| T3 |
9828 |
10 |
0 |
0 |
| T4 |
3789 |
14 |
0 |
0 |
| T5 |
4239 |
3 |
0 |
0 |
| T7 |
4599 |
3 |
0 |
0 |
| T13 |
3798 |
28 |
0 |
0 |
| T14 |
4473 |
62 |
0 |
0 |
| T15 |
4707 |
50 |
0 |
0 |
| T16 |
6012 |
9 |
0 |
0 |
| T22 |
0 |
14 |
0 |
0 |
| T24 |
3048 |
39 |
0 |
0 |
| T25 |
0 |
15 |
0 |
0 |
| T26 |
0 |
9 |
0 |
0 |
| T66 |
0 |
20 |
0 |
0 |
| T68 |
0 |
14 |
0 |
0 |
gen_high_event_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
29247250 |
26965630 |
0 |
0 |
| T1 |
2445 |
445 |
0 |
0 |
| T2 |
6930 |
4930 |
0 |
0 |
| T3 |
5460 |
3460 |
0 |
0 |
| T4 |
2105 |
105 |
0 |
0 |
| T5 |
2355 |
355 |
0 |
0 |
| T7 |
2555 |
555 |
0 |
0 |
| T13 |
2110 |
110 |
0 |
0 |
| T14 |
2485 |
485 |
0 |
0 |
| T15 |
2615 |
615 |
0 |
0 |
| T16 |
3340 |
1340 |
0 |
0 |
gen_high_level_sva.HighLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
99440650 |
91683142 |
0 |
0 |
| T1 |
8313 |
1513 |
0 |
0 |
| T2 |
23562 |
16762 |
0 |
0 |
| T3 |
18564 |
11764 |
0 |
0 |
| T4 |
7157 |
357 |
0 |
0 |
| T5 |
8007 |
1207 |
0 |
0 |
| T7 |
8687 |
1887 |
0 |
0 |
| T13 |
7174 |
374 |
0 |
0 |
| T14 |
8449 |
1649 |
0 |
0 |
| T15 |
8891 |
2091 |
0 |
0 |
| T16 |
11356 |
4556 |
0 |
0 |
gen_low_level_sva.LowLevelEvent_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
52645050 |
48538134 |
0 |
0 |
| T1 |
4401 |
801 |
0 |
0 |
| T2 |
12474 |
8874 |
0 |
0 |
| T3 |
9828 |
6228 |
0 |
0 |
| T4 |
3789 |
189 |
0 |
0 |
| T5 |
4239 |
639 |
0 |
0 |
| T7 |
4599 |
999 |
0 |
0 |
| T13 |
3798 |
198 |
0 |
0 |
| T14 |
4473 |
873 |
0 |
0 |
| T15 |
4707 |
1107 |
0 |
0 |
| T16 |
6012 |
2412 |
0 |
0 |
gen_not_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
134537350 |
4492 |
0 |
0 |
| T1 |
489 |
1 |
0 |
0 |
| T2 |
1386 |
0 |
0 |
0 |
| T3 |
1092 |
0 |
0 |
0 |
| T4 |
421 |
0 |
0 |
0 |
| T5 |
471 |
0 |
0 |
0 |
| T6 |
805 |
0 |
0 |
0 |
| T7 |
511 |
1 |
0 |
0 |
| T8 |
0 |
1 |
0 |
0 |
| T9 |
2780 |
1 |
0 |
0 |
| T12 |
0 |
1 |
0 |
0 |
| T13 |
422 |
0 |
0 |
0 |
| T14 |
497 |
0 |
0 |
0 |
| T15 |
523 |
0 |
0 |
0 |
| T16 |
668 |
0 |
0 |
0 |
| T23 |
499 |
0 |
0 |
0 |
| T27 |
725 |
3 |
0 |
0 |
| T31 |
6576 |
10 |
0 |
0 |
| T40 |
0 |
3 |
0 |
0 |
| T55 |
0 |
3 |
0 |
0 |
| T57 |
434 |
0 |
0 |
0 |
| T58 |
0 |
1 |
0 |
0 |
| T60 |
0 |
3 |
0 |
0 |
| T64 |
0 |
1 |
0 |
0 |
| T68 |
434 |
0 |
0 |
0 |
| T69 |
0 |
1 |
0 |
0 |
| T70 |
0 |
2 |
0 |
0 |
| T78 |
505 |
0 |
0 |
0 |
| T79 |
565 |
0 |
0 |
0 |
| T89 |
522 |
0 |
0 |
0 |
| T103 |
0 |
1 |
0 |
0 |
| T112 |
0 |
1 |
0 |
0 |
| T118 |
0 |
1 |
0 |
0 |
| T120 |
0 |
3 |
0 |
0 |
| T121 |
409 |
0 |
0 |
0 |
| T142 |
0 |
1 |
0 |
0 |
| T143 |
0 |
1 |
0 |
0 |
| T144 |
0 |
1 |
0 |
0 |
gen_sticky_sva.StableStDropOut_A
| Name | Attempts | Real Successes | Failures | Incomplete |
| Total |
17548350 |
1861915 |
0 |
0 |
| T2 |
2772 |
279 |
0 |
0 |
| T3 |
2184 |
0 |
0 |
0 |
| T7 |
1022 |
0 |
0 |
0 |
| T10 |
689 |
173 |
0 |
0 |
| T11 |
741 |
0 |
0 |
0 |
| T12 |
510 |
0 |
0 |
0 |
| T14 |
994 |
0 |
0 |
0 |
| T15 |
1046 |
0 |
0 |
0 |
| T16 |
1336 |
0 |
0 |
0 |
| T17 |
0 |
142 |
0 |
0 |
| T24 |
1016 |
0 |
0 |
0 |
| T25 |
1004 |
0 |
0 |
0 |
| T26 |
3010 |
0 |
0 |
0 |
| T58 |
637 |
0 |
0 |
0 |
| T59 |
431 |
0 |
0 |
0 |
| T66 |
852 |
0 |
0 |
0 |
| T72 |
0 |
726 |
0 |
0 |
| T73 |
0 |
93044 |
0 |
0 |
| T74 |
0 |
608 |
0 |
0 |
| T75 |
0 |
361 |
0 |
0 |
| T76 |
0 |
152 |
0 |
0 |
| T77 |
0 |
236 |
0 |
0 |
| T93 |
502 |
0 |
0 |
0 |
| T109 |
0 |
277 |
0 |
0 |
| T110 |
0 |
250 |
0 |
0 |
| T116 |
0 |
139 |
0 |
0 |
| T145 |
0 |
505 |
0 |
0 |
| T146 |
0 |
161 |
0 |
0 |
| T147 |
420 |
0 |
0 |
0 |
| T148 |
4410 |
0 |
0 |
0 |
| T149 |
402 |
0 |
0 |
0 |
| T150 |
650 |
0 |
0 |
0 |
