Unified Coverage Report :: Module Instance :: tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Module Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00		100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00	100.00					u_sysrst_ctrl_combo

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
no children

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T29 T30 T31 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T29 T30 T31 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T5 T7 T28 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T5 T7 T28 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T5 T7 T28 
129        1/1              cnt_en = 1'b0;
           Tests:       T5 T7 T28 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T5 T7 T28 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T5 T7 T28 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T5 T7 T28 
139                     
140        1/1              unique case (state_q)
           Tests:       T5 T7 T28 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T5 T7 T28 
148        1/1                    state_d = DebounceSt;
           Tests:       T5 T7 T28 
149        1/1                    cnt_en = 1'b1;
           Tests:       T5 T7 T28 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T5 T7 T28 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T5 T7 T28 
163        1/1                    state_d = IdleSt;
           Tests:       T52 T71 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T52 T71 
165        1/1                  end else if (cnt_done) begin
           Tests:       T5 T7 T28 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T5 T7 T28 
167        1/1                    if (trigger_active) begin
           Tests:       T5 T7 T28 
168        1/1                      state_d = DetectSt;
           Tests:       T5 T7 T28 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T52 T95 T71 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T5 T7 T28 
182        1/1                  cnt_en = 1'b1;
           Tests:       T5 T7 T28 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T5 T7 T28 
186        1/1                    state_d = IdleSt;
           Tests:       T29 T30 T52 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T30 T52 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T5 T7 T28 
191        1/1                      state_d = StableSt;
           Tests:       T5 T7 T28 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T5 T7 T28 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T5 T7 T28 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T5 T7 T28 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T5 T7 T28 
206        1/1                    state_d = IdleSt;
           Tests:       T31 T41 T52 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T5 T7 T28 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T29,T30,T31
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T7,T28

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T7,T28

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T5,T7,T28

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T30,T31,T41
1	1	Covered	T5,T7,T28

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T28
0	1	Covered	T29,T30,T52
1	0	Covered	T30,T52,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T5,T7,T28
0	1	Covered	T31,T41,T52
1	0	Covered	T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T5,T7,T28
1	-	Covered	T31,T41,T52

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T5,T7,T28
DetectSt	168	Covered	T5,T7,T28
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T5,T7,T28

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T5,T7,T28
DebounceSt->IdleSt	163	Covered	T52,T95,T71
DetectSt->IdleSt	186	Covered	T29,T30,T52
DetectSt->StableSt	191	Covered	T5,T7,T28
IdleSt->DebounceSt	148	Covered	T5,T7,T28
StableSt->IdleSt	206	Covered	T31,T41,T52

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T5,T7,T28
0	1	Covered	T5,T7,T28
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T5,T7,T28
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T5,T7,T28
IdleSt	0	-	-	-	-	-	-	Covered	T29,T30,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T5,T7,T28
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T95,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T5,T7,T28
DetectSt	-	-	-	-	1	-	-	Covered	T29,T30,T52
DetectSt	-	-	-	-	0	1	-	Covered	T5,T7,T28
DetectSt	-	-	-	-	0	0	-	Covered	T5,T7,T28
StableSt	-	-	-	-	-	-	1	Covered	T31,T41,T52
StableSt	-	-	-	-	-	-	0	Covered	T5,T7,T28
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	3256	0	0
CntIncr_A	5849450	116033	0	0
CntNoWrap_A	5849450	5387951	0	0
DetectStDropOut_A	5849450	449	0	0
DetectedOut_A	5849450	69854	0	0
DetectedPulseOut_A	5849450	889	0	0
DisabledIdleSt_A	5849450	4945035	0	0
DisabledNoDetection_A	5849450	4946758	0	0
EnterDebounceSt_A	5849450	1652	0	0
EnterDetectSt_A	5849450	1607	0	0
EnterStableSt_A	5849450	889	0	0
PulseIsPulse_A	5849450	889	0	0
StayInStableSt	5849450	68865	0	0
gen_high_event_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	788	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	3256	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T5	471	2	0	0
T7	511	2	0	0
T12	0	2	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T24	508	0	0	0
T26	1505	0	0	0
T28	0	2	0	0
T29	0	22	0	0
T30	0	16	0	0
T31	0	20	0	0
T41	0	26	0	0
T52	0	16	0	0
T69	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	116033	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T5	471	21	0	0
T7	511	21	0	0
T12	0	21	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T24	508	0	0	0
T26	1505	0	0	0
T28	0	21	0	0
T29	0	2107	0	0
T30	0	519	0	0
T31	0	430	0	0
T41	0	728	0	0
T52	0	706	0	0
T69	0	21	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5387951	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	68	0	0
T7	511	108	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	449	0	0
T29	12219	11	0	0
T30	0	5	0	0
T52	0	1	0	0
T71	0	1	0	0
T75	2552	0	0	0
T86	1412	0	0	0
T87	496	0	0	0
T88	511	0	0	0
T97	0	2	0	0
T98	502	0	0	0
T99	525	0	0	0
T100	872	0	0	0
T101	407	0	0	0
T102	402	0	0	0
T122	0	7	0	0
T123	0	7	0	0
T125	0	22	0	0
T126	0	4	0	0
T270	0	2	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	69854	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T5	471	46	0	0
T7	511	85	0	0
T12	0	84	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T24	508	0	0	0
T26	1505	0	0	0
T28	0	29	0	0
T31	0	240	0	0
T41	0	164	0	0
T52	0	482	0	0
T56	0	1615	0	0
T69	0	79	0	0
T95	0	80	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	889	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T5	471	1	0	0
T7	511	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T24	508	0	0	0
T26	1505	0	0	0
T28	0	1	0	0
T31	0	10	0	0
T41	0	13	0	0
T52	0	5	0	0
T56	0	27	0	0
T69	0	1	0	0
T95	0	10	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4945035	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	3	0	0
T7	511	4	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4946758	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	3	0	0
T7	511	4	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1652	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T5	471	1	0	0
T7	511	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T24	508	0	0	0
T26	1505	0	0	0
T28	0	1	0	0
T29	0	11	0	0
T30	0	8	0	0
T31	0	10	0	0
T41	0	13	0	0
T52	0	9	0	0
T69	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1607	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T5	471	1	0	0
T7	511	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T24	508	0	0	0
T26	1505	0	0	0
T28	0	1	0	0
T29	0	11	0	0
T30	0	8	0	0
T31	0	10	0	0
T41	0	13	0	0
T52	0	7	0	0
T69	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	889	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T5	471	1	0	0
T7	511	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T24	508	0	0	0
T26	1505	0	0	0
T28	0	1	0	0
T31	0	10	0	0
T41	0	13	0	0
T52	0	5	0	0
T56	0	27	0	0
T69	0	1	0	0
T95	0	10	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	889	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T5	471	1	0	0
T7	511	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T24	508	0	0	0
T26	1505	0	0	0
T28	0	1	0	0
T31	0	10	0	0
T41	0	13	0	0
T52	0	5	0	0
T56	0	27	0	0
T69	0	1	0	0
T95	0	10	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	68865	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T5	471	44	0	0
T7	511	83	0	0
T12	0	82	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T24	508	0	0	0
T26	1505	0	0	0
T28	0	27	0	0
T31	0	230	0	0
T41	0	151	0	0
T52	0	477	0	0
T56	0	1588	0	0
T69	0	77	0	0
T95	0	70	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	788	0	0
T31	6576	10	0	0
T40	19439	0	0	0
T41	0	13	0	0
T45	662	0	0	0
T52	0	5	0	0
T56	0	27	0	0
T70	719	0	0	0
T71	0	4	0	0
T95	0	10	0	0
T96	0	4	0	0
T109	586	0	0	0
T242	527	0	0	0
T243	495	0	0	0
T271	0	12	0	0
T272	0	12	0	0
T273	0	24	0	0
T274	1974	0	0	0
T275	503	0	0	0
T276	515	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T1 T5 T7 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T1 T5 T7 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T1 T5 T7 
149        1/1                    cnt_en = 1'b1;
           Tests:       T1 T5 T7 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T1 T5 T7 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T1 T5 T7 
163        1/1                    state_d = IdleSt;
           Tests:       T52 T71 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T52 T71 
165        1/1                  end else if (cnt_done) begin
           Tests:       T1 T5 T7 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T1 T5 T7 
167        1/1                    if (trigger_active) begin
           Tests:       T1 T5 T7 
168        1/1                      state_d = DetectSt;
           Tests:       T1 T7 T8 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T5 T28 T59 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T1 T7 T8 
182        1/1                  cnt_en = 1'b1;
           Tests:       T1 T7 T8 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T1 T7 T8 
186        1/1                    state_d = IdleSt;
           Tests:       T32 T33 T52 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T52 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T1 T7 T8 
191        1/1                      state_d = StableSt;
           Tests:       T1 T7 T8 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T1 T7 T8 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T1 T7 T8 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T1 T7 T8 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T1 T7 T8 
206        1/1                    state_d = IdleSt;
           Tests:       T1 T7 T8 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T1 T7 T8 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T1,T5,T7
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T5,T7

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T1,T7,T8

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T1,T5,T7
1	0	Covered	T26,T9,T91
1	1	Covered	T1,T5,T7

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T32,T33,T124
1	0	Covered	T52,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T1,T7,T8
0	1	Covered	T1,T7,T8
1	0	Covered	T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T1,T7,T8
1	-	Covered	T1,T7,T8

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T1,T5,T7
DetectSt	168	Covered	T1,T7,T8
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T1,T7,T8

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T1,T7,T8
DebounceSt->IdleSt	163	Covered	T5,T28,T17
DetectSt->IdleSt	186	Covered	T32,T33,T52
DetectSt->StableSt	191	Covered	T1,T7,T8
IdleSt->DebounceSt	148	Covered	T1,T5,T7
StableSt->IdleSt	206	Covered	T1,T7,T8

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T1,T5,T7
0	1	Covered	T1,T5,T7
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T1,T7,T8
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T1,T5,T7
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T1,T7,T8
DebounceSt	-	0	1	0	-	-	-	Covered	T5,T28,T59
DebounceSt	-	0	0	-	-	-	-	Covered	T1,T5,T7
DetectSt	-	-	-	-	1	-	-	Covered	T32,T33,T52
DetectSt	-	-	-	-	0	1	-	Covered	T1,T7,T8
DetectSt	-	-	-	-	0	0	-	Covered	T1,T7,T8
StableSt	-	-	-	-	-	-	1	Covered	T1,T7,T8
StableSt	-	-	-	-	-	-	0	Covered	T1,T7,T8
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[0].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	787	0	0
CntIncr_A	5849450	41115	0	0
CntNoWrap_A	5849450	5390420	0	0
DetectStDropOut_A	5849450	47	0	0
DetectedOut_A	5849450	13825	0	0
DetectedPulseOut_A	5849450	320	0	0
DisabledIdleSt_A	5849450	5051093	0	0
DisabledNoDetection_A	5849450	5052360	0	0
EnterDebounceSt_A	5849450	417	0	0
EnterDetectSt_A	5849450	371	0	0
EnterStableSt_A	5849450	320	0	0
PulseIsPulse_A	5849450	320	0	0
StayInStableSt	5849450	13480	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	294	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	787	0	0
T1	489	2	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T4	421	0	0	0
T5	471	1	0	0
T7	511	2	0	0
T8	0	2	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T28	0	1	0	0
T32	0	14	0	0
T69	0	2	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	41115	0	0
T1	489	25	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T4	421	0	0	0
T5	471	20	0	0
T7	511	25	0	0
T8	0	25	0	0
T9	0	25	0	0
T12	0	25	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	20	0	0
T28	0	20	0	0
T32	0	1008	0	0
T59	0	19	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5390420	0	0
T1	489	86	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	69	0	0
T7	511	108	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	47	0	0
T32	7578	7	0	0
T33	0	2	0	0
T69	505	0	0	0
T72	1529	0	0	0
T83	1342	0	0	0
T84	491	0	0	0
T104	423	0	0	0
T105	512	0	0	0
T106	421	0	0	0
T107	525	0	0	0
T108	402	0	0	0
T124	0	5	0	0
T127	0	4	0	0
T128	0	1	0	0
T129	0	4	0	0
T130	0	1	0	0
T132	0	1	0	0
T133	0	5	0	0
T134	0	5	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	13825	0	0
T1	489	3	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T4	421	0	0	0
T5	471	0	0	0
T7	511	4	0	0
T8	0	3	0	0
T9	0	3	0	0
T12	0	3	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T40	0	132	0	0
T55	0	52	0	0
T69	0	3	0	0
T103	0	26	0	0
T143	0	3	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	320	0	0
T1	489	1	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T4	421	0	0	0
T5	471	0	0	0
T7	511	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T40	0	3	0	0
T55	0	3	0	0
T69	0	1	0	0
T103	0	1	0	0
T143	0	1	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5051093	0	0
T1	489	4	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	25	0	0
T7	511	26	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5052360	0	0
T1	489	4	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	25	0	0
T7	511	26	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	417	0	0
T1	489	1	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T4	421	0	0	0
T5	471	1	0	0
T7	511	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T17	0	1	0	0
T28	0	1	0	0
T32	0	7	0	0
T59	0	1	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	371	0	0
T1	489	1	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T4	421	0	0	0
T5	471	0	0	0
T7	511	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T32	0	7	0	0
T33	0	2	0	0
T40	0	3	0	0
T69	0	1	0	0
T143	0	1	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	320	0	0
T1	489	1	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T4	421	0	0	0
T5	471	0	0	0
T7	511	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T40	0	3	0	0
T55	0	3	0	0
T69	0	1	0	0
T103	0	1	0	0
T143	0	1	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	320	0	0
T1	489	1	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T4	421	0	0	0
T5	471	0	0	0
T7	511	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T40	0	3	0	0
T55	0	3	0	0
T69	0	1	0	0
T103	0	1	0	0
T143	0	1	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	13480	0	0
T1	489	2	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T4	421	0	0	0
T5	471	0	0	0
T7	511	3	0	0
T8	0	2	0	0
T9	0	2	0	0
T12	0	2	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T40	0	129	0	0
T55	0	49	0	0
T69	0	2	0	0
T103	0	25	0	0
T143	0	2	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	294	0	0
T1	489	1	0	0
T2	1386	0	0	0
T3	1092	0	0	0
T4	421	0	0	0
T5	471	0	0	0
T7	511	1	0	0
T8	0	1	0	0
T9	0	1	0	0
T12	0	1	0	0
T13	422	0	0	0
T14	497	0	0	0
T15	523	0	0	0
T16	668	0	0	0
T40	0	3	0	0
T55	0	3	0	0
T69	0	1	0	0
T103	0	1	0	0
T143	0	1	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T29 T30 T31 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T29 T30 T31 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T29 T30 T31 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T29 T30 T31 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T29 T30 T31 
129        1/1              cnt_en = 1'b0;
           Tests:       T29 T30 T31 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T29 T30 T31 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T29 T30 T31 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T29 T30 T31 
139                     
140        1/1              unique case (state_q)
           Tests:       T29 T30 T31 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T29 T30 T31 
148        1/1                    state_d = DebounceSt;
           Tests:       T29 T30 T31 
149        1/1                    cnt_en = 1'b1;
           Tests:       T29 T30 T31 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T29 T30 T31 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T29 T30 T31 
163        1/1                    state_d = IdleSt;
           Tests:       T52 T71 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T52 T71 
165        1/1                  end else if (cnt_done) begin
           Tests:       T29 T30 T31 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T30 T31 
167        1/1                    if (trigger_active) begin
           Tests:       T29 T30 T31 
168        1/1                      state_d = DetectSt;
           Tests:       T29 T30 T31 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T52 T95 T71 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T29 T30 T31 
182        1/1                  cnt_en = 1'b1;
           Tests:       T29 T30 T31 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T29 T30 T31 
186        1/1                    state_d = IdleSt;
           Tests:       T29 T30 T31 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T30 T31 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T29 T30 T31 
191        1/1                      state_d = StableSt;
           Tests:       T41 T52 T56 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T41 T52 T56 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T41 T52 T56 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T41 T52 T56 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T41 T52 T56 
206        1/1                    state_d = IdleSt;
           Tests:       T41 T52 T56 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T41 T52 T56 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T29,T30,T31
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T29,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T29,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T29,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T30,T31,T41
1	1	Covered	T29,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T29,T30,T31
1	0	Covered	T30,T31,T52

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T41,T52,T56
0	1	Covered	T41,T52,T56
1	0	Covered	T71,T277

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T41,T52,T56
1	-	Covered	T41,T52,T56

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T30,T31
DetectSt	168	Covered	T29,T30,T31
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T41,T52,T56

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T30,T31
DebounceSt->IdleSt	163	Covered	T52,T95,T71
DetectSt->IdleSt	186	Covered	T29,T30,T31
DetectSt->StableSt	191	Covered	T41,T52,T56
IdleSt->DebounceSt	148	Covered	T29,T30,T31
StableSt->IdleSt	206	Covered	T41,T52,T56

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T30,T31
0	1	Covered	T29,T30,T31
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T29,T30,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T95,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T29,T30,T31
DetectSt	-	-	-	-	0	1	-	Covered	T41,T52,T56
DetectSt	-	-	-	-	0	0	-	Covered	T29,T30,T31
StableSt	-	-	-	-	-	-	1	Covered	T41,T52,T56
StableSt	-	-	-	-	-	-	0	Covered	T41,T52,T56
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	3335	0	0
CntIncr_A	5849450	114458	0	0
CntNoWrap_A	5849450	5387872	0	0
DetectStDropOut_A	5849450	492	0	0
DetectedOut_A	5849450	66258	0	0
DetectedPulseOut_A	5849450	799	0	0
DisabledIdleSt_A	5849450	4945033	0	0
DisabledNoDetection_A	5849450	4946734	0	0
EnterDebounceSt_A	5849450	1697	0	0
EnterDetectSt_A	5849450	1641	0	0
EnterStableSt_A	5849450	799	0	0
PulseIsPulse_A	5849450	799	0	0
StayInStableSt	5849450	65336	0	0
gen_high_event_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	668	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	3335	0	0
T29	12219	4	0	0
T30	0	26	0	0
T31	0	46	0	0
T41	0	18	0	0
T52	0	16	0	0
T56	0	20	0	0
T71	0	17	0	0
T75	2552	0	0	0
T86	1412	0	0	0
T87	496	0	0	0
T88	511	0	0	0
T95	0	27	0	0
T96	0	30	0	0
T97	0	52	0	0
T98	502	0	0	0
T99	525	0	0	0
T100	872	0	0	0
T101	407	0	0	0
T102	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	114458	0	0
T29	12219	382	0	0
T30	0	850	0	0
T31	0	1231	0	0
T41	0	567	0	0
T52	0	517	0	0
T56	0	690	0	0
T71	0	727	0	0
T75	2552	0	0	0
T86	1412	0	0	0
T87	496	0	0	0
T88	511	0	0	0
T95	0	1007	0	0
T96	0	818	0	0
T97	0	2092	0	0
T98	502	0	0	0
T99	525	0	0	0
T100	872	0	0	0
T101	407	0	0	0
T102	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5387872	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	492	0	0
T29	12219	2	0	0
T30	0	5	0	0
T31	0	5	0	0
T52	0	1	0	0
T71	0	1	0	0
T75	2552	0	0	0
T86	1412	0	0	0
T87	496	0	0	0
T88	511	0	0	0
T95	0	10	0	0
T96	0	14	0	0
T97	0	12	0	0
T98	502	0	0	0
T99	525	0	0	0
T100	872	0	0	0
T101	407	0	0	0
T102	402	0	0	0
T122	0	4	0	0
T123	0	13	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	66258	0	0
T41	11908	212	0	0
T52	8259	421	0	0
T56	0	187	0	0
T71	0	430	0	0
T119	628	0	0	0
T125	0	1967	0	0
T271	0	1249	0	0
T272	0	1511	0	0
T273	0	967	0	0
T278	0	389	0	0
T279	0	1964	0	0
T280	403	0	0	0
T281	432	0	0	0
T282	446	0	0	0
T283	845	0	0	0
T284	495	0	0	0
T285	521	0	0	0
T286	641	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	799	0	0
T41	11908	9	0	0
T52	8259	5	0	0
T56	0	10	0	0
T71	0	5	0	0
T119	628	0	0	0
T125	0	8	0	0
T271	0	23	0	0
T272	0	22	0	0
T273	0	24	0	0
T278	0	7	0	0
T279	0	27	0	0
T280	403	0	0	0
T281	432	0	0	0
T282	446	0	0	0
T283	845	0	0	0
T284	495	0	0	0
T285	521	0	0	0
T286	641	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4945033	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4946734	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1697	0	0
T29	12219	2	0	0
T30	0	13	0	0
T31	0	23	0	0
T41	0	9	0	0
T52	0	9	0	0
T56	0	10	0	0
T71	0	10	0	0
T75	2552	0	0	0
T86	1412	0	0	0
T87	496	0	0	0
T88	511	0	0	0
T95	0	17	0	0
T96	0	15	0	0
T97	0	26	0	0
T98	502	0	0	0
T99	525	0	0	0
T100	872	0	0	0
T101	407	0	0	0
T102	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1641	0	0
T29	12219	2	0	0
T30	0	13	0	0
T31	0	23	0	0
T41	0	9	0	0
T52	0	7	0	0
T56	0	10	0	0
T71	0	7	0	0
T75	2552	0	0	0
T86	1412	0	0	0
T87	496	0	0	0
T88	511	0	0	0
T95	0	10	0	0
T96	0	15	0	0
T97	0	26	0	0
T98	502	0	0	0
T99	525	0	0	0
T100	872	0	0	0
T101	407	0	0	0
T102	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	799	0	0
T41	11908	9	0	0
T52	8259	5	0	0
T56	0	10	0	0
T71	0	5	0	0
T119	628	0	0	0
T125	0	8	0	0
T271	0	23	0	0
T272	0	22	0	0
T273	0	24	0	0
T278	0	7	0	0
T279	0	27	0	0
T280	403	0	0	0
T281	432	0	0	0
T282	446	0	0	0
T283	845	0	0	0
T284	495	0	0	0
T285	521	0	0	0
T286	641	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	799	0	0
T41	11908	9	0	0
T52	8259	5	0	0
T56	0	10	0	0
T71	0	5	0	0
T119	628	0	0	0
T125	0	8	0	0
T271	0	23	0	0
T272	0	22	0	0
T273	0	24	0	0
T278	0	7	0	0
T279	0	27	0	0
T280	403	0	0	0
T281	432	0	0	0
T282	446	0	0	0
T283	845	0	0	0
T284	495	0	0	0
T285	521	0	0	0
T286	641	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	65336	0	0
T41	11908	202	0	0
T52	8259	416	0	0
T56	0	177	0	0
T71	0	425	0	0
T119	628	0	0	0
T125	0	1959	0	0
T271	0	1225	0	0
T272	0	1487	0	0
T273	0	942	0	0
T278	0	382	0	0
T279	0	1934	0	0
T280	403	0	0	0
T281	432	0	0	0
T282	446	0	0	0
T283	845	0	0	0
T284	495	0	0	0
T285	521	0	0	0
T286	641	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	668	0	0
T41	11908	8	0	0
T52	8259	5	0	0
T56	0	10	0	0
T71	0	4	0	0
T119	628	0	0	0
T125	0	8	0	0
T271	0	22	0	0
T272	0	20	0	0
T273	0	23	0	0
T278	0	7	0	0
T279	0	24	0	0
T280	403	0	0	0
T281	432	0	0	0
T282	446	0	0	0
T283	845	0	0	0
T284	495	0	0	0
T285	521	0	0	0
T286	641	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T32 T33 T29 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T32 T33 T40 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T32 T33 T40 
149        1/1                    cnt_en = 1'b1;
           Tests:       T32 T33 T40 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T40 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T32 T33 T40 
163        1/1                    state_d = IdleSt;
           Tests:       T52 T71 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T52 T71 
165        1/1                  end else if (cnt_done) begin
           Tests:       T32 T33 T40 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T40 
167        1/1                    if (trigger_active) begin
           Tests:       T32 T33 T40 
168        1/1                      state_d = DetectSt;
           Tests:       T32 T33 T40 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T42 T287 T288 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T32 T33 T40 
182        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T40 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T32 T33 T40 
186        1/1                    state_d = IdleSt;
           Tests:       T32 T52 T289 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T52 T289 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T32 T33 T40 
191        1/1                      state_d = StableSt;
           Tests:       T33 T40 T55 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T33 T40 T55 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T33 T40 T55 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T33 T40 T55 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T33 T40 T55 
206        1/1                    state_d = IdleSt;
           Tests:       T33 T40 T55 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T33 T40 T55 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T32,T33,T29
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T29
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T32,T33,T40

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T32,T33,T40

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T32,T33,T40

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T40
1	0	Covered	T26,T9,T91
1	1	Covered	T32,T33,T40

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T40
0	1	Covered	T32,T289,T71
1	0	Covered	T52,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T40,T55
0	1	Covered	T33,T40,T55
1	0	Covered	T52,T71

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T40,T55
1	-	Covered	T33,T40,T55

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T33,T40
DetectSt	168	Covered	T32,T33,T40
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T33,T40,T55

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T33,T40
DebounceSt->IdleSt	163	Covered	T42,T52,T71
DetectSt->IdleSt	186	Covered	T32,T52,T289
DetectSt->StableSt	191	Covered	T33,T40,T55
IdleSt->DebounceSt	148	Covered	T32,T33,T40
StableSt->IdleSt	206	Covered	T33,T40,T55

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T32,T33,T40
0	1	Covered	T32,T33,T40
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T40
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T33,T40
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T33,T40
DebounceSt	-	0	1	0	-	-	-	Covered	T42,T287,T288
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T33,T40
DetectSt	-	-	-	-	1	-	-	Covered	T32,T52,T289
DetectSt	-	-	-	-	0	1	-	Covered	T33,T40,T55
DetectSt	-	-	-	-	0	0	-	Covered	T32,T33,T40
StableSt	-	-	-	-	-	-	1	Covered	T33,T40,T55
StableSt	-	-	-	-	-	-	0	Covered	T33,T40,T55
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[1].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	797	0	0
CntIncr_A	5849450	41949	0	0
CntNoWrap_A	5849450	5390410	0	0
DetectStDropOut_A	5849450	61	0	0
DetectedOut_A	5849450	14661	0	0
DetectedPulseOut_A	5849450	316	0	0
DisabledIdleSt_A	5849450	5068584	0	0
DisabledNoDetection_A	5849450	5069873	0	0
EnterDebounceSt_A	5849450	417	0	0
EnterDetectSt_A	5849450	381	0	0
EnterStableSt_A	5849450	316	0	0
PulseIsPulse_A	5849450	316	0	0
StayInStableSt	5849450	14309	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	277	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	797	0	0
T32	7578	12	0	0
T33	0	2	0	0
T40	0	12	0	0
T41	0	2	0	0
T42	0	30	0	0
T52	0	8	0	0
T55	0	4	0	0
T69	505	0	0	0
T71	0	8	0	0
T72	1529	0	0	0
T83	1342	0	0	0
T84	491	0	0	0
T104	423	0	0	0
T105	512	0	0	0
T106	421	0	0	0
T107	525	0	0	0
T108	402	0	0	0
T268	0	12	0	0
T289	0	12	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	41949	0	0
T32	7578	860	0	0
T33	0	33	0	0
T40	0	708	0	0
T41	0	73	0	0
T42	0	2044	0	0
T52	0	290	0	0
T55	0	256	0	0
T69	505	0	0	0
T71	0	272	0	0
T72	1529	0	0	0
T83	1342	0	0	0
T84	491	0	0	0
T104	423	0	0	0
T105	512	0	0	0
T106	421	0	0	0
T107	525	0	0	0
T108	402	0	0	0
T268	0	720	0	0
T289	0	1073	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5390410	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	61	0	0
T32	7578	6	0	0
T69	505	0	0	0
T71	0	1	0	0
T72	1529	0	0	0
T83	1342	0	0	0
T84	491	0	0	0
T104	423	0	0	0
T105	512	0	0	0
T106	421	0	0	0
T107	525	0	0	0
T108	402	0	0	0
T127	0	3	0	0
T129	0	1	0	0
T218	0	3	0	0
T289	0	6	0	0
T290	0	1	0	0
T291	0	2	0	0
T292	0	2	0	0
T293	0	1	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	14661	0	0
T33	16295	16	0	0
T40	0	416	0	0
T41	0	77	0	0
T42	0	258	0	0
T52	0	63	0	0
T55	0	23	0	0
T71	0	85	0	0
T74	1485	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	212	0	0
T271	0	55	0	0
T294	0	269	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	316	0	0
T33	16295	1	0	0
T40	0	6	0	0
T41	0	1	0	0
T42	0	14	0	0
T52	0	1	0	0
T55	0	2	0	0
T71	0	1	0	0
T74	1485	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	6	0	0
T271	0	1	0	0
T294	0	5	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5068584	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5069873	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	417	0	0
T32	7578	6	0	0
T33	0	1	0	0
T40	0	6	0	0
T41	0	1	0	0
T42	0	16	0	0
T52	0	5	0	0
T55	0	2	0	0
T69	505	0	0	0
T71	0	5	0	0
T72	1529	0	0	0
T83	1342	0	0	0
T84	491	0	0	0
T104	423	0	0	0
T105	512	0	0	0
T106	421	0	0	0
T107	525	0	0	0
T108	402	0	0	0
T268	0	6	0	0
T289	0	6	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	381	0	0
T32	7578	6	0	0
T33	0	1	0	0
T40	0	6	0	0
T41	0	1	0	0
T42	0	14	0	0
T52	0	3	0	0
T55	0	2	0	0
T69	505	0	0	0
T71	0	3	0	0
T72	1529	0	0	0
T83	1342	0	0	0
T84	491	0	0	0
T104	423	0	0	0
T105	512	0	0	0
T106	421	0	0	0
T107	525	0	0	0
T108	402	0	0	0
T268	0	6	0	0
T289	0	6	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	316	0	0
T33	16295	1	0	0
T40	0	6	0	0
T41	0	1	0	0
T42	0	14	0	0
T52	0	1	0	0
T55	0	2	0	0
T71	0	1	0	0
T74	1485	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	6	0	0
T271	0	1	0	0
T294	0	5	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	316	0	0
T33	16295	1	0	0
T40	0	6	0	0
T41	0	1	0	0
T42	0	14	0	0
T52	0	1	0	0
T55	0	2	0	0
T71	0	1	0	0
T74	1485	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	6	0	0
T271	0	1	0	0
T294	0	5	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	14309	0	0
T33	16295	15	0	0
T40	0	410	0	0
T41	0	76	0	0
T42	0	244	0	0
T52	0	62	0	0
T55	0	21	0	0
T71	0	84	0	0
T74	1485	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	206	0	0
T271	0	54	0	0
T294	0	264	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	277	0	0
T33	16295	1	0	0
T40	0	6	0	0
T41	0	1	0	0
T42	0	14	0	0
T55	0	2	0	0
T74	1485	0	0	0
T124	0	4	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	6	0	0
T271	0	1	0	0
T272	0	1	0	0
T294	0	5	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
TOTAL		43	43	100.00
CONT_ASSIGN	60	1	1	100.00
CONT_ASSIGN	79	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T29 T30 T31 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69                            if (!rst_ni) begin
70                              trigger_active_q <= 1'b0;
71                            end else begin
72                              trigger_active_q <= trigger_active;
73                            end
74                          end
75                      
76                          assign trigger_event = trigger_active & ~trigger_active_q;
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79         1/1              assign trigger_event = trigger_active;
           Tests:       T29 T30 T31 
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T29 T30 T31 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T29 T30 T31 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T29 T30 T31 
129        1/1              cnt_en = 1'b0;
           Tests:       T29 T30 T31 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T29 T30 T31 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T29 T30 T31 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T29 T30 T31 
139                     
140        1/1              unique case (state_q)
           Tests:       T29 T30 T31 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T29 T30 T31 
148        1/1                    state_d = DebounceSt;
           Tests:       T29 T30 T31 
149        1/1                    cnt_en = 1'b1;
           Tests:       T29 T30 T31 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T29 T30 T31 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T29 T30 T31 
163        1/1                    state_d = IdleSt;
           Tests:       T52 T71 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T52 T71 
165        1/1                  end else if (cnt_done) begin
           Tests:       T29 T30 T31 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T30 T31 
167        1/1                    if (trigger_active) begin
           Tests:       T29 T30 T31 
168        1/1                      state_d = DetectSt;
           Tests:       T29 T30 T31 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T52 T95 T71 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T29 T30 T31 
182        1/1                  cnt_en = 1'b1;
           Tests:       T29 T30 T31 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T29 T30 T31 
186        1/1                    state_d = IdleSt;
           Tests:       T29 T52 T96 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T29 T52 T96 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T29 T30 T31 
191        1/1                      state_d = StableSt;
           Tests:       T30 T31 T41 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T30 T31 T41 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T30 T31 T41 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T30 T31 T41 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T30 T31 T41 
206        1/1                    state_d = IdleSt;
           Tests:       T30 T31 T41 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T30 T31 T41 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Covered	Percent
Conditions	19	19	100.00
Logical	19	19	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T29,T30,T31
1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T29,T30,T31

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T29,T30,T31

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T29,T30,T31

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T29,T30,T31
1	0	Covered	T41,T52,T56
1	1	Covered	T29,T30,T31

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T29,T30,T31
0	1	Covered	T29,T52,T96
1	0	Covered	T52,T96,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T30,T31,T41
0	1	Covered	T30,T31,T41
1	0	Covered	T298

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T30,T31,T41
1	-	Covered	T30,T31,T41

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T29,T30,T31
DetectSt	168	Covered	T29,T30,T31
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T30,T31,T41

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T29,T30,T31
DebounceSt->IdleSt	163	Covered	T52,T95,T71
DetectSt->IdleSt	186	Covered	T29,T52,T96
DetectSt->StableSt	191	Covered	T30,T31,T41
IdleSt->DebounceSt	148	Covered	T29,T30,T31
StableSt->IdleSt	206	Covered	T30,T31,T41

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Line No.	Total	Covered	Percent
Branches		20	20	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T29,T30,T31
0	1	Covered	T29,T30,T31
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T29,T30,T31
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T29,T30,T31
IdleSt	0	-	-	-	-	-	-	Covered	T29,T30,T31
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T29,T30,T31
DebounceSt	-	0	1	0	-	-	-	Covered	T52,T95,T71
DebounceSt	-	0	0	-	-	-	-	Covered	T29,T30,T31
DetectSt	-	-	-	-	1	-	-	Covered	T29,T52,T96
DetectSt	-	-	-	-	0	1	-	Covered	T30,T31,T41
DetectSt	-	-	-	-	0	0	-	Covered	T29,T30,T31
StableSt	-	-	-	-	-	-	1	Covered	T30,T31,T41
StableSt	-	-	-	-	-	-	0	Covered	T30,T31,T41
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect_pre

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	16	16	100.00	16	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	16	16	100.00	16	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	3122	0	0
CntIncr_A	5849450	108058	0	0
CntNoWrap_A	5849450	5388085	0	0
DetectStDropOut_A	5849450	394	0	0
DetectedOut_A	5849450	69248	0	0
DetectedPulseOut_A	5849450	864	0	0
DisabledIdleSt_A	5849450	4945042	0	0
DisabledNoDetection_A	5849450	4946761	0	0
EnterDebounceSt_A	5849450	1587	0	0
EnterDetectSt_A	5849450	1538	0	0
EnterStableSt_A	5849450	864	0	0
PulseIsPulse_A	5849450	864	0	0
StayInStableSt	5849450	68279	0	0
gen_high_event_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	752	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	3122	0	0
T29	12219	50	0	0
T30	0	24	0	0
T31	0	62	0	0
T41	0	18	0	0
T52	0	16	0	0
T56	0	46	0	0
T71	0	16	0	0
T75	2552	0	0	0
T86	1412	0	0	0
T87	496	0	0	0
T88	511	0	0	0
T95	0	30	0	0
T96	0	10	0	0
T97	0	18	0	0
T98	502	0	0	0
T99	525	0	0	0
T100	872	0	0	0
T101	407	0	0	0
T102	402	0	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	108058	0	0
T29	12219	4798	0	0
T30	0	636	0	0
T31	0	1426	0	0
T41	0	522	0	0
T52	0	672	0	0
T56	0	1495	0	0
T71	0	661	0	0
T75	2552	0	0	0
T86	1412	0	0	0
T87	496	0	0	0
T88	511	0	0	0
T95	0	1060	0	0
T96	0	272	0	0
T97	0	715	0	0
T98	502	0	0	0
T99	525	0	0	0
T100	872	0	0	0
T101	407	0	0	0
T102	402	0	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5388085	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	394	0	0
T29	12219	25	0	0
T52	0	1	0	0
T71	0	1	0	0
T75	2552	0	0	0
T86	1412	0	0	0
T87	496	0	0	0
T88	511	0	0	0
T96	0	4	0	0
T97	0	7	0	0
T98	502	0	0	0
T99	525	0	0	0
T100	872	0	0	0
T101	407	0	0	0
T102	402	0	0	0
T122	0	1	0	0
T123	0	3	0	0
T125	0	6	0	0
T279	0	5	0	0
T299	0	21	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	69248	0	0
T30	7163	1425	0	0
T31	0	1493	0	0
T41	0	409	0	0
T43	2561	0	0	0
T52	0	430	0	0
T56	0	937	0	0
T64	700	0	0	0
T71	0	415	0	0
T76	577	0	0	0
T95	0	90	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T271	0	719	0	0
T272	0	1379	0	0
T273	0	511	0	0
T300	443	0	0	0
T301	865	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	864	0	0
T30	7163	12	0	0
T31	0	31	0	0
T41	0	9	0	0
T43	2561	0	0	0
T52	0	5	0	0
T56	0	23	0	0
T64	700	0	0	0
T71	0	5	0	0
T76	577	0	0	0
T95	0	10	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T271	0	17	0	0
T272	0	22	0	0
T273	0	24	0	0
T300	443	0	0	0
T301	865	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4945042	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	4946761	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1587	0	0
T29	12219	25	0	0
T30	0	12	0	0
T31	0	31	0	0
T41	0	9	0	0
T52	0	9	0	0
T56	0	23	0	0
T71	0	9	0	0
T75	2552	0	0	0
T86	1412	0	0	0
T87	496	0	0	0
T88	511	0	0	0
T95	0	20	0	0
T96	0	5	0	0
T97	0	9	0	0
T98	502	0	0	0
T99	525	0	0	0
T100	872	0	0	0
T101	407	0	0	0
T102	402	0	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	1538	0	0
T29	12219	25	0	0
T30	0	12	0	0
T31	0	31	0	0
T41	0	9	0	0
T52	0	7	0	0
T56	0	23	0	0
T71	0	7	0	0
T75	2552	0	0	0
T86	1412	0	0	0
T87	496	0	0	0
T88	511	0	0	0
T95	0	10	0	0
T96	0	5	0	0
T97	0	9	0	0
T98	502	0	0	0
T99	525	0	0	0
T100	872	0	0	0
T101	407	0	0	0
T102	402	0	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	864	0	0
T30	7163	12	0	0
T31	0	31	0	0
T41	0	9	0	0
T43	2561	0	0	0
T52	0	5	0	0
T56	0	23	0	0
T64	700	0	0	0
T71	0	5	0	0
T76	577	0	0	0
T95	0	10	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T271	0	17	0	0
T272	0	22	0	0
T273	0	24	0	0
T300	443	0	0	0
T301	865	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	864	0	0
T30	7163	12	0	0
T31	0	31	0	0
T41	0	9	0	0
T43	2561	0	0	0
T52	0	5	0	0
T56	0	23	0	0
T64	700	0	0	0
T71	0	5	0	0
T76	577	0	0	0
T95	0	10	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T271	0	17	0	0
T272	0	22	0	0
T273	0	24	0	0
T300	443	0	0	0
T301	865	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	68279	0	0
T30	7163	1413	0	0
T31	0	1462	0	0
T41	0	399	0	0
T43	2561	0	0	0
T52	0	425	0	0
T56	0	913	0	0
T64	700	0	0	0
T71	0	410	0	0
T76	577	0	0	0
T95	0	80	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T271	0	701	0	0
T272	0	1355	0	0
T273	0	486	0	0
T300	443	0	0	0
T301	865	0	0	0

gen_high_event_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	752	0	0
T30	7163	12	0	0
T31	0	31	0	0
T41	0	8	0	0
T43	2561	0	0	0
T52	0	5	0	0
T56	0	22	0	0
T64	700	0	0	0
T71	0	5	0	0
T76	577	0	0	0
T95	0	10	0	0
T205	426	0	0	0
T206	502	0	0	0
T207	406	0	0	0
T208	421	0	0	0
T271	0	16	0	0
T272	0	20	0	0
T273	0	23	0	0
T300	443	0	0	0
T301	865	0	0	0

Line Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
TOTAL		46	46	100.00
CONT_ASSIGN	60	1	1	100.00
ALWAYS	69	3	3	100.00
CONT_ASSIGN	76	1	1	100.00
CONT_ASSIGN	92	1	1	100.00
CONT_ASSIGN	99	1	1	100.00
CONT_ASSIGN	101	1	1	100.00
ALWAYS	104	3	3	100.00
ALWAYS	125	32	32	100.00
ALWAYS	219	3	3	100.00

59                        end else begin : gen_trigger_active_high
60         1/1              assign trigger_active = (trigger_i == 1'b1);
           Tests:       T32 T33 T29 
61                        end
62                      
63                        // In case of edge events, we also need to detect the transition.
64                        logic trigger_event;
65                        if (EventType inside {EdgeToLow, EdgeToHigh}) begin : gen_trigger_event_edge
66                          // This flop is always active, no matter the enable state.
67                          logic trigger_active_q;
68                          always_ff @(posedge clk_i or negedge rst_ni) begin : p_trigger_reg
69         1/1                if (!rst_ni) begin
           Tests:       T1 T4 T5 
70         1/1                  trigger_active_q <= 1'b0;
           Tests:       T1 T4 T5 
71                            end else begin
72         1/1                  trigger_active_q <= trigger_active;
           Tests:       T1 T4 T5 
73                            end
74                          end
75                      
76         1/1              assign trigger_event = trigger_active & ~trigger_active_q;
           Tests:       T1 T4 T5 
77                        // In case of level events, the event is equal to the level being active.
78                        end else begin : gen_trigger_event_level
79                          assign trigger_event = trigger_active;
80                        end
81                      
82                        /////////////////
83                        // Timer Logic //
84                        /////////////////
85                      
86                        // Take the maximum width of both timer values.
87                        localparam int unsigned TimerWidth =
88                            (DetectTimerWidth > DebounceTimerWidth) ? DetectTimerWidth : DebounceTimerWidth;
89                      
90                        logic cnt_en, cnt_clr;
91                        logic [TimerWidth-1:0] cnt_d, cnt_q;
92         1/1            assign cnt_d = (cnt_clr) ? '0           :
           Tests:       T32 T33 T30 
93                                       (cnt_en)  ? cnt_q + 1'b1 :
94                                                   cnt_q;
95                      
96                      
97                        logic cnt_done, thresh_sel;
98                        logic [TimerWidth-1:0] thresh;
99         1/1            assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
           Tests:       T1 T5 T3 
100                                                      TimerWidth'(cfg_debounce_timer_i);
101        1/1            assign cnt_done = (cnt_q >= thresh);
           Tests:       T1 T5 T3 
102                     
103                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_cnt_reg
104        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
105        1/1                cnt_q <= '0;
           Tests:       T1 T4 T5 
106                         end else begin
107        1/1                cnt_q <= cnt_d;
           Tests:       T1 T4 T5 
108                         end
109                       end
110                     
111                       /////////
112                       // FSM //
113                       /////////
114                     
115                       typedef enum logic [1:0] {
116                         IdleSt,
117                         DebounceSt,
118                         DetectSt,
119                         StableSt
120                       } state_t;
121                     
122                       state_t state_d, state_q;
123                     
124                       always_comb begin : p_fsm
125        1/1              state_d = state_q;
           Tests:       T1 T4 T5 
126                     
127                         // Counter controls (clear has priority).
128        1/1              cnt_clr = 1'b0;
           Tests:       T1 T4 T5 
129        1/1              cnt_en = 1'b0;
           Tests:       T1 T4 T5 
130                     
131                         // Detected outputs
132        1/1              event_detected_o = 1'b0;
           Tests:       T1 T4 T5 
133        1/1              event_detected_pulse_o = 1'b0;
           Tests:       T1 T4 T5 
134                     
135                         // Threshold select
136                         // 0: debounce
137                         // 1: detect
138        1/1              thresh_sel = 1'b0;
           Tests:       T1 T4 T5 
139                     
140        1/1              unique case (state_q)
           Tests:       T1 T4 T5 
141                           ////////////////////////////////////////////
142                           // We are waiting for the event to occur.
143                           // This can be either a specific level or edge,
144                           // depending on the configuration.
145                           IdleSt: begin
146                             // Stay here if the detector is disabled.
147        1/1                  if (trigger_event && cfg_enable_i) begin
           Tests:       T1 T4 T5 
148        1/1                    state_d = DebounceSt;
           Tests:       T32 T33 T30 
149        1/1                    cnt_en = 1'b1;
           Tests:       T32 T33 T30 
150                             end
                        MISSING_ELSE
151                           end
152                           ////////////////////////////////////////////
153                           // If an event has occurred, we back off for
154                           // the amount of debounce cycles configured.
155                           // Once the timer has expired, we sample the
156                           // signal again and check whether it has the
157                           // correct level. If so, we move on to the
158                           // detection stage, otherwise we fall back.
159                           DebounceSt: begin
160        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T30 
161                             // Unconditionally go back to idle if the detector is disabled.
162        1/1                  if (!cfg_enable_i) begin
           Tests:       T32 T33 T30 
163        1/1                    state_d = IdleSt;
           Tests:       T52 T71 
164        1/1                    cnt_clr = 1'b1;
           Tests:       T52 T71 
165        1/1                  end else if (cnt_done) begin
           Tests:       T32 T33 T30 
166        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T33 T30 
167        1/1                    if (trigger_active) begin
           Tests:       T32 T33 T30 
168        1/1                      state_d = DetectSt;
           Tests:       T32 T33 T30 
169                               end else begin
170        1/1                      state_d = IdleSt;
           Tests:       T33 T40 T42 
171                               end
172                             end
                        MISSING_ELSE
173                           end
174                           ////////////////////////////////////////////
175                           // Once the debounce period has passed, we
176                           // check whether the signal remains stable
177                           // throughout the entire detection period.
178                           // If it is not stable at any cycle, we fall
179                           // back to idle.
180                           DetectSt: begin
181        1/1                  thresh_sel = 1'b1;
           Tests:       T32 T33 T30 
182        1/1                  cnt_en = 1'b1;
           Tests:       T32 T33 T30 
183                             // Go back to idle if either the trigger level is not active anymore, or if the
184                             // detector is disabled.
185        1/1                  if (!cfg_enable_i || !trigger_active) begin
           Tests:       T32 T33 T30 
186        1/1                    state_d = IdleSt;
           Tests:       T32 T55 T103 
187        1/1                    cnt_clr = 1'b1;
           Tests:       T32 T55 T103 
188                             // If the trigger is active, count up.
189                             end else begin
190        1/1                    if (cnt_done) begin
           Tests:       T32 T33 T30 
191        1/1                      state_d = StableSt;
           Tests:       T33 T30 T40 
192        1/1                      cnt_clr = 1'b1;
           Tests:       T33 T30 T40 
193        1/1                      event_detected_o = 1'b1;
           Tests:       T33 T30 T40 
194        1/1                      event_detected_pulse_o = 1'b1;
           Tests:       T33 T30 T40 
195                               end
                        MISSING_ELSE
196                             end
197                           end
198                           ////////////////////////////////////////////
199                           // At this point we have detected the event
200                           // and monitor whether the signal remains stable.
201                           StableSt: begin
202                             // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                             // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                             // to go back to the idle state.
205        1/1                  if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
           Tests:       T33 T30 T40 
206        1/1                    state_d = IdleSt;
           Tests:       T33 T30 T40 
207                             // Otherwise keep the event detected output signal high.
208                             end else begin
209        1/1                    event_detected_o = 1'b1;
           Tests:       T33 T30 T40 
210                             end
211                           end
212                           ////////////////////////////////////////////
213                           // This is a full case statement
214                           default: ;
Exclude Annotation: VC_COV_UNR
215                         endcase // state_q
216                       end
217                     
218                       always_ff @(posedge clk_i or negedge rst_ni) begin : p_fsm_reg
219        1/1              if (!rst_ni) begin
           Tests:       T1 T4 T5 
220        1/1                state_q <= IdleSt;
           Tests:       T1 T4 T5 
221                         end else begin
222        1/1                state_q <= state_d;
           Tests:       T1 T4 T5 

---

Cond Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Covered	Percent
Conditions	22	22	100.00
Logical	22	22	100.00
Non-Logical	0	0
Event	0	0

 LINE       60
 EXPRESSION (trigger_i == 1'b1)
            ---------1---------

-1-	Status	Tests
0	Covered	T32,T33,T29
1	Covered	T1,T4,T5

 LINE       76
 EXPRESSION (trigger_active & ((~gen_trigger_event_edge.trigger_active_q)))
             -------1------   ----------------------2---------------------

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T29
1	0	Covered	T1,T4,T5
1	1	Covered	T1,T4,T5

 LINE       92
 EXPRESSION (cnt_clr ? '0 : (cnt_en ? ((cnt_q + 1'b1)) : cnt_q))
             ---1---

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T32,T33,T30

 LINE       92
 SUB-EXPRESSION (cnt_en ? ((cnt_q + 1'b1)) : cnt_q)
                 ---1--

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T32,T33,T30

 LINE       99
 EXPRESSION (thresh_sel ? (32'(cfg_detect_timer_i)) : (32'(cfg_debounce_timer_i)))
             -----1----

-1-	Status	Tests
0	Covered	T1,T4,T5
1	Covered	T32,T33,T30

 LINE       147
 EXPRESSION (trigger_event && cfg_enable_i)
             ------1------    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T32,T33,T30
1	0	Covered	T26,T9,T91
1	1	Covered	T32,T33,T30

 LINE       185
 EXPRESSION (((!cfg_enable_i)) || ((!trigger_active)))
             --------1--------    ---------2---------

-1-	-2-	Status	Tests
0	0	Covered	T32,T33,T30
0	1	Covered	T32,T55,T103
1	0	Covered	T52,T71

 LINE       205
 EXPRESSION (((!cfg_enable_i)) || (((!trigger_active)) && ((!Sticky))))
             --------1--------    ------------------2-----------------

-1-	-2-	Status	Tests
0	0	Covered	T33,T30,T40
0	1	Covered	T33,T30,T40
1	0	Covered	T30,T52

 LINE       205
 SUB-EXPRESSION (((!trigger_active)) && ((!Sticky)))
                 ---------1---------    -----2-----

-1-	-2-	Status	Tests
0	-	Covered	T33,T30,T40
1	-	Covered	T33,T30,T40

---

FSM Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

Summary for FSM :: state_q

	Total	Covered	Percent
States	4	4	100.00	(Not included in score)
Transitions	6	6	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
DebounceSt	148	Covered	T32,T33,T30
DetectSt	168	Covered	T32,T33,T30
IdleSt	163	Covered	T1,T4,T5
StableSt	191	Covered	T33,T30,T40

transitions	Line No.	Covered	Tests
DebounceSt->DetectSt	168	Covered	T32,T33,T30
DebounceSt->IdleSt	163	Covered	T33,T40,T42
DetectSt->IdleSt	186	Covered	T32,T55,T103
DetectSt->StableSt	191	Covered	T33,T30,T40
IdleSt->DebounceSt	148	Covered	T32,T33,T30
StableSt->IdleSt	206	Covered	T33,T30,T40

---

Branch Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Line No.	Total	Covered	Percent
Branches		22	22	100.00
TERNARY	92	3	3	100.00
TERNARY	99	2	2	100.00
IF	104	2	2	100.00
CASE	140	11	11	100.00
IF	219	2	2	100.00
IF	69	2	2	100.00

92           assign cnt_d = (cnt_clr) ? '0           :
                                      -1-  
                                      ==>  
93                          (cnt_en)  ? cnt_q + 1'b1 :
                                      -2-  
                                      ==>  
                                      ==>  

Branches:

-1-	-2-	Status	Tests
1	-	Covered	T32,T33,T30
0	1	Covered	T32,T33,T30
0	0	Covered	T1,T4,T5

99           assign thresh = (thresh_sel) ? TimerWidth'(cfg_detect_timer_i) :
                                          -1-  
                                          ==>  
                                          ==>  

Branches:

-1-	Status	Tests
1	Covered	T32,T33,T30
0	Covered	T1,T4,T5

104            if (!rst_ni) begin
               -1-  
105              cnt_q <= '0;
                 ==>
106            end else begin
107              cnt_q <= cnt_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

140            unique case (state_q)
                      -1-  
141              ////////////////////////////////////////////
142              // We are waiting for the event to occur.
143              // This can be either a specific level or edge,
144              // depending on the configuration.
145              IdleSt: begin
146                // Stay here if the detector is disabled.
147                if (trigger_event && cfg_enable_i) begin
                   -2-  
148                  state_d = DebounceSt;
                     ==>
149                  cnt_en = 1'b1;
150                end
                   MISSING_ELSE
                   ==>
151              end
152              ////////////////////////////////////////////
153              // If an event has occurred, we back off for
154              // the amount of debounce cycles configured.
155              // Once the timer has expired, we sample the
156              // signal again and check whether it has the
157              // correct level. If so, we move on to the
158              // detection stage, otherwise we fall back.
159              DebounceSt: begin
160                cnt_en = 1'b1;
161                // Unconditionally go back to idle if the detector is disabled.
162                if (!cfg_enable_i) begin
                   -3-  
163                  state_d = IdleSt;
                     ==>
164                  cnt_clr = 1'b1;
165                end else if (cnt_done) begin
                            -4-  
166                  cnt_clr = 1'b1;
167                  if (trigger_active) begin
                     -5-  
168                    state_d = DetectSt;
                       ==>
169                  end else begin
170                    state_d = IdleSt;
                       ==>
171                  end
172                end
                   MISSING_ELSE
                   ==>
173              end
174              ////////////////////////////////////////////
175              // Once the debounce period has passed, we
176              // check whether the signal remains stable
177              // throughout the entire detection period.
178              // If it is not stable at any cycle, we fall
179              // back to idle.
180              DetectSt: begin
181                thresh_sel = 1'b1;
182                cnt_en = 1'b1;
183                // Go back to idle if either the trigger level is not active anymore, or if the
184                // detector is disabled.
185                if (!cfg_enable_i || !trigger_active) begin
                   -6-  
186                  state_d = IdleSt;
                     ==>
187                  cnt_clr = 1'b1;
188                // If the trigger is active, count up.
189                end else begin
190                  if (cnt_done) begin
                     -7-  
191                    state_d = StableSt;
                       ==>
192                    cnt_clr = 1'b1;
193                    event_detected_o = 1'b1;
194                    event_detected_pulse_o = 1'b1;
195                  end
                     MISSING_ELSE
                     ==>
196                end
197              end
198              ////////////////////////////////////////////
199              // At this point we have detected the event
200              // and monitor whether the signal remains stable.
201              StableSt: begin
202                // Go back to idle if either the trigger level is not active anymore, or if the detector is
203                // disabled. Note that if the detector is sticky, it has to be explicitly disabled in order
204                // to go back to the idle state.
205                if (!cfg_enable_i || (!trigger_active && !Sticky)) begin
                   -8-  
206                  state_d = IdleSt;
                     ==>
207                // Otherwise keep the event detected output signal high.
208                end else begin
209                  event_detected_o = 1'b1;
                     ==>
210                end
211              end
212              ////////////////////////////////////////////
213              // This is a full case statement
214              default: ;
                 ==> (Excluded)
Exclude Annotation: VC_COV_UNR

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	Status	Tests	Exclude Annotation
IdleSt	1	-	-	-	-	-	-	Covered	T32,T33,T30
IdleSt	0	-	-	-	-	-	-	Covered	T1,T4,T5
DebounceSt	-	1	-	-	-	-	-	Covered	T52,T71
DebounceSt	-	0	1	1	-	-	-	Covered	T32,T33,T30
DebounceSt	-	0	1	0	-	-	-	Covered	T33,T40,T42
DebounceSt	-	0	0	-	-	-	-	Covered	T32,T33,T30
DetectSt	-	-	-	-	1	-	-	Covered	T32,T55,T103
DetectSt	-	-	-	-	0	1	-	Covered	T33,T30,T40
DetectSt	-	-	-	-	0	0	-	Covered	T32,T33,T30
StableSt	-	-	-	-	-	-	1	Covered	T33,T30,T40
StableSt	-	-	-	-	-	-	0	Covered	T33,T30,T40
default	-	-	-	-	-	-	-	Excluded		VC_COV_UNR

219            if (!rst_ni) begin
               -1-  
220              state_q <= IdleSt;
                 ==>
221            end else begin
222              state_q <= state_d;
                 ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

69               if (!rst_ni) begin
                 -1-  
70                 trigger_active_q <= 1'b0;
                   ==>
71               end else begin
72                 trigger_active_q <= trigger_active;
                   ==>

Branches:

-1-	Status	Tests
1	Covered	T1,T4,T5
0	Covered	T1,T4,T5

---

Assert Coverage for Instance : tb.dut.u_sysrst_ctrl_combo.gen_combo_trigger[2].u_sysrst_ctrl_detect

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	15	15	100.00	15	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	15	15	100.00	15	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CntClr_A	5849450	835	0	0
CntIncr_A	5849450	43611	0	0
CntNoWrap_A	5849450	5390372	0	0
DetectStDropOut_A	5849450	52	0	0
DetectedOut_A	5849450	13103	0	0
DetectedPulseOut_A	5849450	339	0	0
DisabledIdleSt_A	5849450	5053147	0	0
DisabledNoDetection_A	5849450	5054434	0	0
EnterDebounceSt_A	5849450	440	0	0
EnterDetectSt_A	5849450	395	0	0
EnterStableSt_A	5849450	339	0	0
PulseIsPulse_A	5849450	339	0	0
StayInStableSt	5849450	12731	0	0
gen_high_level_sva.HighLevelEvent_A	5849450	5393126	0	0
gen_not_sticky_sva.StableStDropOut_A	5849450	299	0	0

CntClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	835	0	0
T30	0	8	0	0
T32	7578	26	0	0
T33	0	11	0	0
T40	0	10	0	0
T41	0	2	0	0
T42	0	28	0	0
T52	0	8	0	0
T55	0	2	0	0
T69	505	0	0	0
T72	1529	0	0	0
T83	1342	0	0	0
T84	491	0	0	0
T103	0	4	0	0
T104	423	0	0	0
T105	512	0	0	0
T106	421	0	0	0
T107	525	0	0	0
T108	402	0	0	0
T289	0	5	0	0

CntIncr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	43611	0	0
T30	0	320	0	0
T32	7578	1877	0	0
T33	0	237	0	0
T40	0	864	0	0
T41	0	95	0	0
T42	0	1140	0	0
T52	0	300	0	0
T55	0	139	0	0
T69	505	0	0	0
T72	1529	0	0	0
T83	1342	0	0	0
T84	491	0	0	0
T103	0	181	0	0
T104	423	0	0	0
T105	512	0	0	0
T106	421	0	0	0
T107	525	0	0	0
T108	402	0	0	0
T289	0	420	0	0

CntNoWrap_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5390372	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DetectStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	52	0	0
T32	7578	13	0	0
T55	0	1	0	0
T69	505	0	0	0
T72	1529	0	0	0
T83	1342	0	0	0
T84	491	0	0	0
T103	0	2	0	0
T104	423	0	0	0
T105	512	0	0	0
T106	421	0	0	0
T107	525	0	0	0
T108	402	0	0	0
T127	0	4	0	0
T133	0	1	0	0
T287	0	13	0	0
T288	0	6	0	0
T302	0	1	0	0
T303	0	4	0	0
T304	0	7	0	0

DetectedOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	13103	0	0
T30	0	171	0	0
T33	16295	27	0	0
T40	0	47	0	0
T41	0	56	0	0
T42	0	1002	0	0
T52	0	63	0	0
T56	0	43	0	0
T71	0	84	0	0
T74	1485	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	500	0	0
T289	0	9	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0

DetectedPulseOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	339	0	0
T30	0	4	0	0
T33	16295	5	0	0
T40	0	4	0	0
T41	0	1	0	0
T42	0	13	0	0
T52	0	1	0	0
T56	0	1	0	0
T71	0	1	0	0
T74	1485	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	11	0	0
T289	0	2	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0

DisabledIdleSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5053147	0	0
T1	489	88	0	0
T2	1386	985	0	0
T3	1092	691	0	0
T4	421	20	0	0
T5	471	70	0	0
T7	511	110	0	0
T13	422	21	0	0
T14	497	96	0	0
T15	523	122	0	0
T16	668	267	0	0

DisabledNoDetection_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5054434	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

EnterDebounceSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	440	0	0
T30	0	4	0	0
T32	7578	13	0	0
T33	0	6	0	0
T40	0	6	0	0
T41	0	1	0	0
T42	0	15	0	0
T52	0	5	0	0
T55	0	1	0	0
T69	505	0	0	0
T72	1529	0	0	0
T83	1342	0	0	0
T84	491	0	0	0
T103	0	2	0	0
T104	423	0	0	0
T105	512	0	0	0
T106	421	0	0	0
T107	525	0	0	0
T108	402	0	0	0
T289	0	3	0	0

EnterDetectSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	395	0	0
T30	0	4	0	0
T32	7578	13	0	0
T33	0	5	0	0
T40	0	4	0	0
T41	0	1	0	0
T42	0	13	0	0
T52	0	3	0	0
T55	0	1	0	0
T69	505	0	0	0
T72	1529	0	0	0
T83	1342	0	0	0
T84	491	0	0	0
T103	0	2	0	0
T104	423	0	0	0
T105	512	0	0	0
T106	421	0	0	0
T107	525	0	0	0
T108	402	0	0	0
T289	0	2	0	0

EnterStableSt_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	339	0	0
T30	0	4	0	0
T33	16295	5	0	0
T40	0	4	0	0
T41	0	1	0	0
T42	0	13	0	0
T52	0	1	0	0
T56	0	1	0	0
T71	0	1	0	0
T74	1485	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	11	0	0
T289	0	2	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0

PulseIsPulse_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	339	0	0
T30	0	4	0	0
T33	16295	5	0	0
T40	0	4	0	0
T41	0	1	0	0
T42	0	13	0	0
T52	0	1	0	0
T56	0	1	0	0
T71	0	1	0	0
T74	1485	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	11	0	0
T289	0	2	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0

StayInStableSt

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	12731	0	0
T30	0	167	0	0
T33	16295	22	0	0
T40	0	43	0	0
T41	0	55	0	0
T42	0	989	0	0
T52	0	62	0	0
T56	0	41	0	0
T71	0	83	0	0
T74	1485	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	489	0	0
T289	0	7	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0

gen_high_level_sva.HighLevelEvent_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	5393126	0	0
T1	489	89	0	0
T2	1386	986	0	0
T3	1092	692	0	0
T4	421	21	0	0
T5	471	71	0	0
T7	511	111	0	0
T13	422	22	0	0
T14	497	97	0	0
T15	523	123	0	0
T16	668	268	0	0

gen_not_sticky_sva.StableStDropOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	5849450	299	0	0
T30	0	1	0	0
T33	16295	5	0	0
T40	0	4	0	0
T41	0	1	0	0
T42	0	13	0	0
T74	1485	0	0	0
T163	402	0	0	0
T164	2891	0	0	0
T165	524	0	0	0
T225	422	0	0	0
T226	556	0	0	0
T268	0	11	0	0
T271	0	1	0	0
T272	0	1	0	0
T289	0	2	0	0
T294	0	13	0	0
T295	504	0	0	0
T296	440	0	0	0
T297	586	0	0	0