| T111 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_ultra_low_pwr.2665080401 |
|
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Sep 04 02:15:19 AM UTC 24 |
Sep 04 02:15:27 AM UTC 24 |
3648188367 ps |
| T271 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/13.sysrst_ctrl_combo_detect_with_pre_cond.1040697372 |
|
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Sep 04 02:14:48 AM UTC 24 |
Sep 04 02:15:27 AM UTC 24 |
46507561773 ps |
| T493 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_flash_wr_prot_out.3299586972 |
|
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Sep 04 02:15:18 AM UTC 24 |
Sep 04 02:15:28 AM UTC 24 |
2609285989 ps |
| T116 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_stress_all.1177776106 |
|
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Sep 04 02:15:16 AM UTC 24 |
Sep 04 02:15:28 AM UTC 24 |
8897624499 ps |
| T144 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_auto_blk_key_output.1137944151 |
|
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Sep 04 02:15:18 AM UTC 24 |
Sep 04 02:15:29 AM UTC 24 |
3439047503 ps |
| T494 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_auto_blk_key_output.2982421277 |
|
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Sep 04 02:15:23 AM UTC 24 |
Sep 04 02:15:29 AM UTC 24 |
3379167761 ps |
| T342 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_stress_all_with_rand_reset.2614616354 |
|
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Sep 04 02:15:03 AM UTC 24 |
Sep 04 02:15:29 AM UTC 24 |
7843984690 ps |
| T352 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ec_pwr_on_rst.3008050073 |
|
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Sep 04 02:15:22 AM UTC 24 |
Sep 04 02:15:30 AM UTC 24 |
3220485344 ps |
| T353 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_pin_override_test.3761780554 |
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Sep 04 02:15:22 AM UTC 24 |
Sep 04 02:15:30 AM UTC 24 |
2520847604 ps |
| T354 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_in_out_inverted.1008912850 |
|
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Sep 04 02:15:22 AM UTC 24 |
Sep 04 02:15:31 AM UTC 24 |
2461455153 ps |
| T212 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_edge_detect.4093550668 |
|
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Sep 04 02:15:25 AM UTC 24 |
Sep 04 02:15:31 AM UTC 24 |
3835578494 ps |
| T355 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_in_out_inverted.1039507763 |
|
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Sep 04 02:15:18 AM UTC 24 |
Sep 04 02:15:32 AM UTC 24 |
2469464937 ps |
| T356 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_smoke.224247821 |
|
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Sep 04 02:15:21 AM UTC 24 |
Sep 04 02:15:32 AM UTC 24 |
2110311580 ps |
| T357 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_stress_all.3547941309 |
|
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Sep 04 02:15:10 AM UTC 24 |
Sep 04 02:15:32 AM UTC 24 |
7086620034 ps |
| T358 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_flash_wr_prot_out.3856308078 |
|
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Sep 04 02:15:22 AM UTC 24 |
Sep 04 02:15:32 AM UTC 24 |
2608278833 ps |
| T359 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_alert_test.1222725630 |
|
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Sep 04 02:15:28 AM UTC 24 |
Sep 04 02:15:33 AM UTC 24 |
2038741457 ps |
| T251 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all.4117288736 |
|
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Sep 04 02:15:42 AM UTC 24 |
Sep 04 02:15:47 AM UTC 24 |
11180694801 ps |
| T495 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_smoke.2023157407 |
|
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Sep 04 02:15:29 AM UTC 24 |
Sep 04 02:15:33 AM UTC 24 |
2135366694 ps |
| T496 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_access_test.1413207284 |
|
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Sep 04 02:15:30 AM UTC 24 |
Sep 04 02:15:34 AM UTC 24 |
2094083959 ps |
| T497 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_alert_test.53817233 |
|
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Sep 04 02:15:21 AM UTC 24 |
Sep 04 02:15:34 AM UTC 24 |
2012843508 ps |
| T498 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_auto_blk_key_output.1110514291 |
|
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Sep 04 02:15:31 AM UTC 24 |
Sep 04 02:15:35 AM UTC 24 |
3136218586 ps |
| T499 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_pin_override_test.2071837467 |
|
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Sep 04 02:15:30 AM UTC 24 |
Sep 04 02:15:36 AM UTC 24 |
2519971474 ps |
| T169 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_edge_detect.2779591687 |
|
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Sep 04 02:15:33 AM UTC 24 |
Sep 04 02:15:36 AM UTC 24 |
4791040216 ps |
| T500 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_smoke.506459292 |
|
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Sep 04 02:15:34 AM UTC 24 |
Sep 04 02:15:37 AM UTC 24 |
2122158999 ps |
| T340 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ultra_low_pwr.1535932031 |
|
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Sep 04 02:15:32 AM UTC 24 |
Sep 04 02:15:38 AM UTC 24 |
2863578895 ps |
| T501 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_alert_test.3783497405 |
|
|
Sep 04 02:15:34 AM UTC 24 |
Sep 04 02:15:38 AM UTC 24 |
2027111781 ps |
| T502 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_in_out_inverted.701933308 |
|
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Sep 04 02:15:29 AM UTC 24 |
Sep 04 02:15:38 AM UTC 24 |
2436279267 ps |
| T336 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_stress_all_with_rand_reset.3410252702 |
|
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Sep 04 02:15:28 AM UTC 24 |
Sep 04 02:15:40 AM UTC 24 |
5325048332 ps |
| T503 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_flash_wr_prot_out.3553096219 |
|
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Sep 04 02:15:30 AM UTC 24 |
Sep 04 02:15:41 AM UTC 24 |
2607875094 ps |
| T504 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_override_test.47888888 |
|
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Sep 04 02:15:36 AM UTC 24 |
Sep 04 02:15:41 AM UTC 24 |
2529392839 ps |
| T505 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_auto_blk_key_output.2374655234 |
|
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Sep 04 02:15:37 AM UTC 24 |
Sep 04 02:15:42 AM UTC 24 |
3482366930 ps |
| T506 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_flash_wr_prot_out.1978980048 |
|
|
Sep 04 02:15:36 AM UTC 24 |
Sep 04 02:15:42 AM UTC 24 |
2625778015 ps |
| T448 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_ultra_low_pwr.3475781442 |
|
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Sep 04 02:15:23 AM UTC 24 |
Sep 04 02:15:42 AM UTC 24 |
158142161449 ps |
| T294 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect.464841805 |
|
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Sep 04 02:13:55 AM UTC 24 |
Sep 04 02:15:42 AM UTC 24 |
179151270078 ps |
| T166 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ultra_low_pwr.2639236990 |
|
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Sep 04 02:15:39 AM UTC 24 |
Sep 04 02:15:43 AM UTC 24 |
3395607426 ps |
| T507 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_ec_pwr_on_rst.2015337069 |
|
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Sep 04 02:15:30 AM UTC 24 |
Sep 04 02:15:44 AM UTC 24 |
3845730307 ps |
| T272 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/0.sysrst_ctrl_combo_detect_with_pre_cond.110627966 |
|
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Sep 04 02:13:07 AM UTC 24 |
Sep 04 02:15:44 AM UTC 24 |
54108613319 ps |
| T151 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all.3933850313 |
|
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Sep 04 02:15:33 AM UTC 24 |
Sep 04 02:15:46 AM UTC 24 |
11069713645 ps |
| T508 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_pin_access_test.2144482862 |
|
|
Sep 04 02:15:35 AM UTC 24 |
Sep 04 02:15:47 AM UTC 24 |
2223457686 ps |
| T509 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_in_out_inverted.3320643282 |
|
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Sep 04 02:15:34 AM UTC 24 |
Sep 04 02:15:46 AM UTC 24 |
2444651315 ps |
| T510 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_alert_test.847778806 |
|
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Sep 04 02:15:42 AM UTC 24 |
Sep 04 02:15:48 AM UTC 24 |
2026619277 ps |
| T337 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all_with_rand_reset.1304222484 |
|
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Sep 04 02:15:21 AM UTC 24 |
Sep 04 02:15:46 AM UTC 24 |
6416852601 ps |
| T122 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect_with_pre_cond.1425774092 |
|
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Sep 04 02:15:33 AM UTC 24 |
Sep 04 02:15:48 AM UTC 24 |
79340906833 ps |
| T511 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_auto_blk_key_output.2232805879 |
|
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Sep 04 02:15:46 AM UTC 24 |
Sep 04 02:15:49 AM UTC 24 |
3626184255 ps |
| T512 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_override_test.2995188969 |
|
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Sep 04 02:15:43 AM UTC 24 |
Sep 04 02:15:50 AM UTC 24 |
2517699982 ps |
| T123 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect_with_pre_cond.2371683004 |
|
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Sep 04 02:15:08 AM UTC 24 |
Sep 04 02:15:50 AM UTC 24 |
26087953958 ps |
| T513 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_smoke.3798600274 |
|
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Sep 04 02:15:42 AM UTC 24 |
Sep 04 02:15:51 AM UTC 24 |
2109774541 ps |
| T514 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_in_out_inverted.102501364 |
|
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Sep 04 02:15:42 AM UTC 24 |
Sep 04 02:15:51 AM UTC 24 |
2460626924 ps |
| T170 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_edge_detect.1514945166 |
|
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Sep 04 02:15:39 AM UTC 24 |
Sep 04 02:15:53 AM UTC 24 |
3972394723 ps |
| T172 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_edge_detect.1384434971 |
|
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Sep 04 02:15:48 AM UTC 24 |
Sep 04 02:15:53 AM UTC 24 |
3815655299 ps |
| T254 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_alert_test.1897343796 |
|
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Sep 04 02:15:49 AM UTC 24 |
Sep 04 02:15:53 AM UTC 24 |
2040921516 ps |
| T255 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_stress_all_with_rand_reset.2598217881 |
|
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Sep 04 02:15:41 AM UTC 24 |
Sep 04 02:15:53 AM UTC 24 |
3453112943 ps |
| T256 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_pin_access_test.1335615636 |
|
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Sep 04 02:15:43 AM UTC 24 |
Sep 04 02:15:53 AM UTC 24 |
2094232722 ps |
| T257 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_smoke.2369294124 |
|
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Sep 04 02:15:49 AM UTC 24 |
Sep 04 02:15:54 AM UTC 24 |
2118012238 ps |
| T258 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_access_test.3330787938 |
|
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Sep 04 02:15:50 AM UTC 24 |
Sep 04 02:15:54 AM UTC 24 |
2267159883 ps |
| T259 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_ultra_low_pwr.4177823845 |
|
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Sep 04 02:15:47 AM UTC 24 |
Sep 04 02:15:55 AM UTC 24 |
3363819423 ps |
| T260 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_stress_all_with_rand_reset.1594690286 |
|
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Sep 04 02:15:33 AM UTC 24 |
Sep 04 02:15:55 AM UTC 24 |
5652871520 ps |
| T261 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_in_out_inverted.1297902426 |
|
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Sep 04 02:15:49 AM UTC 24 |
Sep 04 02:15:55 AM UTC 24 |
2484578299 ps |
| T262 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_flash_wr_prot_out.3501365199 |
|
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Sep 04 02:15:44 AM UTC 24 |
Sep 04 02:15:57 AM UTC 24 |
2611466974 ps |
| T515 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_flash_wr_prot_out.628723010 |
|
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Sep 04 02:15:52 AM UTC 24 |
Sep 04 02:15:58 AM UTC 24 |
2619652263 ps |
| T192 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_edge_detect.2835014367 |
|
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Sep 04 02:15:54 AM UTC 24 |
Sep 04 02:15:58 AM UTC 24 |
4416108118 ps |
| T516 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_access_test.4195573724 |
|
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Sep 04 02:16:19 AM UTC 24 |
Sep 04 02:16:26 AM UTC 24 |
2229338649 ps |
| T517 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_alert_test.2890834431 |
|
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Sep 04 02:15:55 AM UTC 24 |
Sep 04 02:15:58 AM UTC 24 |
2092545394 ps |
| T124 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect.1196736299 |
|
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Sep 04 02:15:02 AM UTC 24 |
Sep 04 02:15:59 AM UTC 24 |
99289827609 ps |
| T125 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect_with_pre_cond.2993227809 |
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Sep 04 02:15:21 AM UTC 24 |
Sep 04 02:15:59 AM UTC 24 |
53045662865 ps |
| T518 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_override_test.1933037666 |
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Sep 04 02:15:57 AM UTC 24 |
Sep 04 02:16:00 AM UTC 24 |
2533078211 ps |
| T519 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_in_out_inverted.1159569251 |
|
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Sep 04 02:15:55 AM UTC 24 |
Sep 04 02:16:01 AM UTC 24 |
2467269964 ps |
| T520 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_pin_access_test.4134971968 |
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Sep 04 02:15:57 AM UTC 24 |
Sep 04 02:16:01 AM UTC 24 |
2048251297 ps |
| T156 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ultra_low_pwr.267944525 |
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Sep 04 02:15:54 AM UTC 24 |
Sep 04 02:16:01 AM UTC 24 |
2685872273 ps |
| T521 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_ec_pwr_on_rst.1192746337 |
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Sep 04 02:15:52 AM UTC 24 |
Sep 04 02:16:02 AM UTC 24 |
4300547854 ps |
| T522 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_smoke.3278465329 |
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Sep 04 02:15:55 AM UTC 24 |
Sep 04 02:16:02 AM UTC 24 |
2112261687 ps |
| T523 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_auto_blk_key_output.2869420961 |
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Sep 04 02:15:59 AM UTC 24 |
Sep 04 02:16:02 AM UTC 24 |
3441061525 ps |
| T524 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_pin_override_test.2511944295 |
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Sep 04 02:15:52 AM UTC 24 |
Sep 04 02:16:02 AM UTC 24 |
2512933731 ps |
| T525 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ultra_low_pwr.3461296564 |
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Sep 04 02:15:59 AM UTC 24 |
Sep 04 02:16:06 AM UTC 24 |
2888198538 ps |
| T526 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_access_test.1449537453 |
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Sep 04 02:16:03 AM UTC 24 |
Sep 04 02:16:06 AM UTC 24 |
2144810596 ps |
| T273 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect_with_pre_cond.2504430699 |
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Sep 04 02:15:26 AM UTC 24 |
Sep 04 02:16:07 AM UTC 24 |
60731865362 ps |
| T527 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_flash_wr_prot_out.3769116097 |
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Sep 04 02:16:03 AM UTC 24 |
Sep 04 02:16:07 AM UTC 24 |
2638209573 ps |
| T528 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ec_pwr_on_rst.2200976489 |
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Sep 04 02:16:04 AM UTC 24 |
Sep 04 02:16:07 AM UTC 24 |
3457621711 ps |
| T529 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all.1762936693 |
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Sep 04 02:15:55 AM UTC 24 |
Sep 04 02:16:07 AM UTC 24 |
7923035846 ps |
| T126 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/5.sysrst_ctrl_combo_detect_with_pre_cond.1321855258 |
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Sep 04 02:13:56 AM UTC 24 |
Sep 04 02:16:07 AM UTC 24 |
53686782220 ps |
| T530 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_pin_override_test.2638394947 |
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Sep 04 02:16:03 AM UTC 24 |
Sep 04 02:16:08 AM UTC 24 |
2527017536 ps |
| T531 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_flash_wr_prot_out.2538072384 |
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Sep 04 02:15:58 AM UTC 24 |
Sep 04 02:16:08 AM UTC 24 |
2612943426 ps |
| T532 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_alert_test.2136420684 |
|
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Sep 04 02:16:03 AM UTC 24 |
Sep 04 02:16:08 AM UTC 24 |
2020270678 ps |
| T533 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_ec_pwr_on_rst.4065191959 |
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Sep 04 02:15:58 AM UTC 24 |
Sep 04 02:16:09 AM UTC 24 |
3910669627 ps |
| T534 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_in_out_inverted.4152335347 |
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Sep 04 02:16:03 AM UTC 24 |
Sep 04 02:16:10 AM UTC 24 |
2469930921 ps |
| T535 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_smoke.2827848713 |
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Sep 04 02:16:03 AM UTC 24 |
Sep 04 02:16:10 AM UTC 24 |
2117554709 ps |
| T536 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_access_test.586836032 |
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Sep 04 02:16:10 AM UTC 24 |
Sep 04 02:16:12 AM UTC 24 |
2084997431 ps |
| T173 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_edge_detect.1031128810 |
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Sep 04 02:16:07 AM UTC 24 |
Sep 04 02:16:13 AM UTC 24 |
5718706123 ps |
| T537 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_alert_test.450974388 |
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Sep 04 02:16:09 AM UTC 24 |
Sep 04 02:16:13 AM UTC 24 |
2015794023 ps |
| T538 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_edge_detect.2068947658 |
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Sep 04 02:16:00 AM UTC 24 |
Sep 04 02:16:13 AM UTC 24 |
2884878940 ps |
| T539 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all.1905326112 |
|
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Sep 04 02:16:01 AM UTC 24 |
Sep 04 02:16:13 AM UTC 24 |
12183554195 ps |
| T540 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_in_out_inverted.2163613543 |
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Sep 04 02:16:10 AM UTC 24 |
Sep 04 02:16:14 AM UTC 24 |
2462444168 ps |
| T541 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_stress_all_with_rand_reset.3628768945 |
|
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Sep 04 02:16:01 AM UTC 24 |
Sep 04 02:16:14 AM UTC 24 |
6194952030 ps |
| T542 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_stress_all_with_rand_reset.2027211569 |
|
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Sep 04 02:15:55 AM UTC 24 |
Sep 04 02:16:15 AM UTC 24 |
6258701845 ps |
| T315 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/15.sysrst_ctrl_combo_detect.1032025532 |
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Sep 04 02:14:57 AM UTC 24 |
Sep 04 02:16:16 AM UTC 24 |
156059140051 ps |
| T543 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ultra_low_pwr.2429099738 |
|
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Sep 04 02:16:14 AM UTC 24 |
Sep 04 02:16:18 AM UTC 24 |
3554556644 ps |
| T544 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_smoke.80275510 |
|
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Sep 04 02:16:26 AM UTC 24 |
Sep 04 02:16:29 AM UTC 24 |
2123692316 ps |
| T545 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_pin_override_test.4147573108 |
|
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Sep 04 02:16:10 AM UTC 24 |
Sep 04 02:16:18 AM UTC 24 |
2514300158 ps |
| T287 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect.2190571933 |
|
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Sep 04 02:13:46 AM UTC 24 |
Sep 04 02:16:18 AM UTC 24 |
103098600557 ps |
| T546 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_ec_pwr_on_rst.3182524089 |
|
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Sep 04 02:16:13 AM UTC 24 |
Sep 04 02:16:19 AM UTC 24 |
3715574564 ps |
| T547 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_ultra_low_pwr.754652522 |
|
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Sep 04 02:16:07 AM UTC 24 |
Sep 04 02:16:19 AM UTC 24 |
3035004244 ps |
| T548 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_flash_wr_prot_out.813018827 |
|
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Sep 04 02:16:11 AM UTC 24 |
Sep 04 02:16:19 AM UTC 24 |
2614411377 ps |
| T549 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_auto_blk_key_output.2168092786 |
|
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Sep 04 02:16:13 AM UTC 24 |
Sep 04 02:16:20 AM UTC 24 |
3281853219 ps |
| T550 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_smoke.2142560453 |
|
|
Sep 04 02:16:09 AM UTC 24 |
Sep 04 02:16:20 AM UTC 24 |
2114971185 ps |
| T551 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_auto_blk_key_output.3456626976 |
|
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Sep 04 02:16:06 AM UTC 24 |
Sep 04 02:16:20 AM UTC 24 |
3353867389 ps |
| T193 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_edge_detect.345060730 |
|
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Sep 04 02:16:14 AM UTC 24 |
Sep 04 02:16:20 AM UTC 24 |
3591514799 ps |
| T552 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_smoke.2485752439 |
|
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Sep 04 02:16:19 AM UTC 24 |
Sep 04 02:16:22 AM UTC 24 |
2123583226 ps |
| T194 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_stress_all.3376853738 |
|
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Sep 04 02:15:48 AM UTC 24 |
Sep 04 02:16:28 AM UTC 24 |
12971582904 ps |
| T553 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_flash_wr_prot_out.2992863798 |
|
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Sep 04 02:16:20 AM UTC 24 |
Sep 04 02:16:23 AM UTC 24 |
2656296548 ps |
| T554 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_alert_test.1627659930 |
|
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Sep 04 02:16:17 AM UTC 24 |
Sep 04 02:16:24 AM UTC 24 |
2015514140 ps |
| T555 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_in_out_inverted.2156500428 |
|
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Sep 04 02:16:19 AM UTC 24 |
Sep 04 02:16:25 AM UTC 24 |
2456420279 ps |
| T278 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect_with_pre_cond.618154276 |
|
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Sep 04 02:15:15 AM UTC 24 |
Sep 04 02:16:25 AM UTC 24 |
57803247038 ps |
| T113 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_edge_detect.1361162717 |
|
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Sep 04 02:16:21 AM UTC 24 |
Sep 04 02:16:28 AM UTC 24 |
5094795290 ps |
| T115 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all_with_rand_reset.1128574318 |
|
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Sep 04 02:16:09 AM UTC 24 |
Sep 04 02:16:28 AM UTC 24 |
50101933182 ps |
| T216 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all_with_rand_reset.3544984147 |
|
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Sep 04 02:16:16 AM UTC 24 |
Sep 04 02:16:30 AM UTC 24 |
4591194935 ps |
| T217 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_pin_override_test.2810107587 |
|
|
Sep 04 02:16:20 AM UTC 24 |
Sep 04 02:16:30 AM UTC 24 |
2512717009 ps |
| T218 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_combo_detect.1423264262 |
|
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Sep 04 02:15:19 AM UTC 24 |
Sep 04 02:17:12 AM UTC 24 |
146367495179 ps |
| T219 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_ultra_low_pwr.2139667558 |
|
|
Sep 04 02:16:20 AM UTC 24 |
Sep 04 02:16:31 AM UTC 24 |
4401591563 ps |
| T220 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_override_test.298236653 |
|
|
Sep 04 02:16:28 AM UTC 24 |
Sep 04 02:16:33 AM UTC 24 |
2532549048 ps |
| T221 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_in_out_inverted.3286679941 |
|
|
Sep 04 02:16:26 AM UTC 24 |
Sep 04 02:16:33 AM UTC 24 |
2464792037 ps |
| T222 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_alert_test.2646872677 |
|
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Sep 04 02:16:25 AM UTC 24 |
Sep 04 02:16:34 AM UTC 24 |
2013134089 ps |
| T223 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_pin_access_test.3354609850 |
|
|
Sep 04 02:16:27 AM UTC 24 |
Sep 04 02:16:34 AM UTC 24 |
2032333685 ps |
| T224 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_flash_wr_prot_out.2657607622 |
|
|
Sep 04 02:16:29 AM UTC 24 |
Sep 04 02:16:36 AM UTC 24 |
2620520771 ps |
| T556 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ec_pwr_on_rst.4012850110 |
|
|
Sep 04 02:16:29 AM UTC 24 |
Sep 04 02:16:38 AM UTC 24 |
2548352802 ps |
| T377 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/17.sysrst_ctrl_combo_detect.2527162037 |
|
|
Sep 04 02:15:07 AM UTC 24 |
Sep 04 02:16:39 AM UTC 24 |
74989114114 ps |
| T557 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_stress_all_with_rand_reset.3149083108 |
|
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Sep 04 02:16:24 AM UTC 24 |
Sep 04 02:16:39 AM UTC 24 |
8518972899 ps |
| T558 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_alert_test.744134978 |
|
|
Sep 04 02:16:35 AM UTC 24 |
Sep 04 02:16:39 AM UTC 24 |
2039470658 ps |
| T559 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_stress_all.1532918791 |
|
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Sep 04 02:16:09 AM UTC 24 |
Sep 04 02:16:40 AM UTC 24 |
11121961772 ps |
| T152 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_ultra_low_pwr.2284202886 |
|
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Sep 04 02:16:30 AM UTC 24 |
Sep 04 02:16:40 AM UTC 24 |
817991519536 ps |
| T279 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/2.sysrst_ctrl_combo_detect_with_pre_cond.1712009633 |
|
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Sep 04 02:13:25 AM UTC 24 |
Sep 04 02:16:40 AM UTC 24 |
65594797645 ps |
| T560 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all.619576782 |
|
|
Sep 04 02:16:34 AM UTC 24 |
Sep 04 02:16:41 AM UTC 24 |
9131928803 ps |
| T561 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_smoke.1188864637 |
|
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Sep 04 02:16:35 AM UTC 24 |
Sep 04 02:16:42 AM UTC 24 |
2118223448 ps |
| T562 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_edge_detect.1488781956 |
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Sep 04 02:16:32 AM UTC 24 |
Sep 04 02:16:42 AM UTC 24 |
3233352693 ps |
| T563 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_auto_blk_key_output.2410609835 |
|
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Sep 04 02:16:30 AM UTC 24 |
Sep 04 02:16:42 AM UTC 24 |
3682438662 ps |
| T564 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_in_out_inverted.2071814933 |
|
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Sep 04 02:16:36 AM UTC 24 |
Sep 04 02:16:43 AM UTC 24 |
2473468124 ps |
| T565 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_access_test.516207087 |
|
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Sep 04 02:16:38 AM UTC 24 |
Sep 04 02:16:43 AM UTC 24 |
2270006778 ps |
| T566 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_flash_wr_prot_out.1410966798 |
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Sep 04 02:16:39 AM UTC 24 |
Sep 04 02:16:44 AM UTC 24 |
2620913599 ps |
| T567 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_pin_override_test.3453423413 |
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Sep 04 02:16:39 AM UTC 24 |
Sep 04 02:16:44 AM UTC 24 |
2535943334 ps |
| T568 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ec_pwr_on_rst.3663329919 |
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Sep 04 02:16:39 AM UTC 24 |
Sep 04 02:16:45 AM UTC 24 |
2544544716 ps |
| T380 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect.51974649 |
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Sep 04 02:14:00 AM UTC 24 |
Sep 04 02:16:46 AM UTC 24 |
61462948318 ps |
| T569 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_smoke.2411557182 |
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Sep 04 02:16:44 AM UTC 24 |
Sep 04 02:16:47 AM UTC 24 |
2144346679 ps |
| T157 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_ultra_low_pwr.2206287660 |
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Sep 04 02:16:42 AM UTC 24 |
Sep 04 02:16:48 AM UTC 24 |
4388884135 ps |
| T570 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_alert_test.2695840192 |
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Sep 04 02:16:44 AM UTC 24 |
Sep 04 02:16:48 AM UTC 24 |
2029237368 ps |
| T174 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_edge_detect.3573701829 |
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Sep 04 02:16:42 AM UTC 24 |
Sep 04 02:16:48 AM UTC 24 |
3225555281 ps |
| T288 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/18.sysrst_ctrl_combo_detect.3419147377 |
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Sep 04 02:15:13 AM UTC 24 |
Sep 04 02:16:49 AM UTC 24 |
64960405890 ps |
| T127 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect.3179013618 |
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Sep 04 02:15:54 AM UTC 24 |
Sep 04 02:16:49 AM UTC 24 |
19548177635 ps |
| T270 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect_with_pre_cond.760661730 |
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Sep 04 02:16:07 AM UTC 24 |
Sep 04 02:16:50 AM UTC 24 |
54669055502 ps |
| T571 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/8.sysrst_ctrl_auto_blk_key_output.806397456 |
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Sep 04 02:14:10 AM UTC 24 |
Sep 04 02:16:50 AM UTC 24 |
241130190991 ps |
| T572 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_flash_wr_prot_out.731011188 |
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Sep 04 02:16:46 AM UTC 24 |
Sep 04 02:16:50 AM UTC 24 |
2643010797 ps |
| T573 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_access_test.1743984302 |
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Sep 04 02:16:45 AM UTC 24 |
Sep 04 02:16:50 AM UTC 24 |
2101631370 ps |
| T290 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_combo_detect.1385776641 |
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Sep 04 02:16:31 AM UTC 24 |
Sep 04 02:16:51 AM UTC 24 |
24919835927 ps |
| T574 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/29.sysrst_ctrl_stress_all_with_rand_reset.2553541221 |
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Sep 04 02:16:34 AM UTC 24 |
Sep 04 02:16:51 AM UTC 24 |
4413011863 ps |
| T575 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ultra_low_pwr.710751181 |
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Sep 04 02:16:49 AM UTC 24 |
Sep 04 02:16:52 AM UTC 24 |
6246412614 ps |
| T576 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_auto_blk_key_output.3283672839 |
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Sep 04 02:16:49 AM UTC 24 |
Sep 04 02:16:52 AM UTC 24 |
3191689317 ps |
| T299 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_combo_detect_with_pre_cond.2022178759 |
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Sep 04 02:15:54 AM UTC 24 |
Sep 04 02:16:53 AM UTC 24 |
25089395736 ps |
| T577 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_in_out_inverted.4288287363 |
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Sep 04 02:16:45 AM UTC 24 |
Sep 04 02:16:55 AM UTC 24 |
2452346864 ps |
| T578 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_pin_override_test.1356664776 |
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Sep 04 02:16:45 AM UTC 24 |
Sep 04 02:16:55 AM UTC 24 |
2510361742 ps |
| T579 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_access_test.574189008 |
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Sep 04 02:16:52 AM UTC 24 |
Sep 04 02:16:57 AM UTC 24 |
2117916989 ps |
| T580 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_in_out_inverted.3044844632 |
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Sep 04 02:16:52 AM UTC 24 |
Sep 04 02:16:57 AM UTC 24 |
2466456882 ps |
| T581 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_pin_override_test.2272065040 |
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Sep 04 02:16:52 AM UTC 24 |
Sep 04 02:16:58 AM UTC 24 |
2519099902 ps |
| T381 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/4.sysrst_ctrl_combo_detect_with_pre_cond.373042047 |
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Sep 04 02:13:47 AM UTC 24 |
Sep 04 02:16:58 AM UTC 24 |
55881386323 ps |
| T582 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_smoke.2087896478 |
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Sep 04 02:16:51 AM UTC 24 |
Sep 04 02:16:58 AM UTC 24 |
2112036643 ps |
| T583 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all_with_rand_reset.126899163 |
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Sep 04 02:16:43 AM UTC 24 |
Sep 04 02:16:59 AM UTC 24 |
4668355069 ps |
| T584 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_ec_pwr_on_rst.1951873671 |
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Sep 04 02:16:55 AM UTC 24 |
Sep 04 02:16:59 AM UTC 24 |
3602610891 ps |
| T585 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all_with_rand_reset.484521759 |
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Sep 04 02:16:51 AM UTC 24 |
Sep 04 02:16:59 AM UTC 24 |
2100262131 ps |
| T586 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_flash_wr_prot_out.3303009224 |
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Sep 04 02:16:54 AM UTC 24 |
Sep 04 02:16:59 AM UTC 24 |
2631346412 ps |
| T378 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/20.sysrst_ctrl_combo_detect.290143161 |
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Sep 04 02:15:24 AM UTC 24 |
Sep 04 02:17:00 AM UTC 24 |
156857854474 ps |
| T587 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_auto_blk_key_output.318768834 |
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Sep 04 02:16:41 AM UTC 24 |
Sep 04 02:17:00 AM UTC 24 |
4018143688 ps |
| T588 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_edge_detect.11414137 |
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Sep 04 02:16:58 AM UTC 24 |
Sep 04 02:17:01 AM UTC 24 |
2620626106 ps |
| T589 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_alert_test.3037853688 |
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Sep 04 02:16:51 AM UTC 24 |
Sep 04 02:17:02 AM UTC 24 |
2011268066 ps |
| T175 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_edge_detect.3551227211 |
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Sep 04 02:16:50 AM UTC 24 |
Sep 04 02:17:03 AM UTC 24 |
3852129867 ps |
| T590 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_smoke.1792392451 |
|
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Sep 04 02:16:59 AM UTC 24 |
Sep 04 02:17:04 AM UTC 24 |
2118988641 ps |
| T591 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_ec_pwr_on_rst.4179713365 |
|
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Sep 04 02:16:48 AM UTC 24 |
Sep 04 02:17:04 AM UTC 24 |
3238777587 ps |
| T382 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/14.sysrst_ctrl_combo_detect.41115178 |
|
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Sep 04 02:14:52 AM UTC 24 |
Sep 04 02:17:05 AM UTC 24 |
109448488454 ps |
| T592 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ultra_low_pwr.1299811985 |
|
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Sep 04 02:17:04 AM UTC 24 |
Sep 04 02:17:08 AM UTC 24 |
3111968733 ps |
| T593 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_access_test.2037938328 |
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Sep 04 02:17:01 AM UTC 24 |
Sep 04 02:17:08 AM UTC 24 |
2209566916 ps |
| T594 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_alert_test.807778202 |
|
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Sep 04 02:16:59 AM UTC 24 |
Sep 04 02:17:08 AM UTC 24 |
2012850737 ps |
| T595 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_in_out_inverted.2647405812 |
|
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Sep 04 02:17:00 AM UTC 24 |
Sep 04 02:17:09 AM UTC 24 |
2456504076 ps |
| T596 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_auto_blk_key_output.477235980 |
|
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Sep 04 02:17:03 AM UTC 24 |
Sep 04 02:17:10 AM UTC 24 |
9026183988 ps |
| T597 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_ec_pwr_on_rst.3757785642 |
|
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Sep 04 02:17:02 AM UTC 24 |
Sep 04 02:17:10 AM UTC 24 |
3562237301 ps |
| T302 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/25.sysrst_ctrl_combo_detect.1784283779 |
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Sep 04 02:15:59 AM UTC 24 |
Sep 04 02:17:11 AM UTC 24 |
100407140352 ps |
| T598 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_auto_blk_key_output.528033657 |
|
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Sep 04 02:16:56 AM UTC 24 |
Sep 04 02:17:11 AM UTC 24 |
3498552573 ps |
| T599 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_flash_wr_prot_out.1845870894 |
|
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Sep 04 02:17:01 AM UTC 24 |
Sep 04 02:17:11 AM UTC 24 |
2612999173 ps |
| T379 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/26.sysrst_ctrl_combo_detect.3271221664 |
|
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Sep 04 02:16:07 AM UTC 24 |
Sep 04 02:17:12 AM UTC 24 |
108380392983 ps |
| T441 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_combo_detect_with_pre_cond.1441161116 |
|
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Sep 04 02:15:03 AM UTC 24 |
Sep 04 02:17:13 AM UTC 24 |
39877925910 ps |
| T600 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_pin_override_test.1628540428 |
|
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Sep 04 02:17:01 AM UTC 24 |
Sep 04 02:17:13 AM UTC 24 |
2510729564 ps |
| T601 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_stress_all_with_rand_reset.3767930556 |
|
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Sep 04 02:16:59 AM UTC 24 |
Sep 04 02:17:14 AM UTC 24 |
5182092180 ps |
| T602 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_smoke.2582246418 |
|
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Sep 04 02:17:09 AM UTC 24 |
Sep 04 02:17:14 AM UTC 24 |
2130130455 ps |
| T603 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_access_test.2870419598 |
|
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Sep 04 02:17:11 AM UTC 24 |
Sep 04 02:17:15 AM UTC 24 |
2096751915 ps |
| T406 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_combo_detect_with_pre_cond.2874754117 |
|
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Sep 04 02:16:15 AM UTC 24 |
Sep 04 02:17:16 AM UTC 24 |
82692176800 ps |
| T604 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_flash_wr_prot_out.773657294 |
|
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Sep 04 02:17:12 AM UTC 24 |
Sep 04 02:17:17 AM UTC 24 |
2631238940 ps |
| T605 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_edge_detect.551414979 |
|
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Sep 04 02:17:05 AM UTC 24 |
Sep 04 02:17:17 AM UTC 24 |
2362883423 ps |
| T320 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all_with_rand_reset.2655586020 |
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Sep 04 02:17:08 AM UTC 24 |
Sep 04 02:17:18 AM UTC 24 |
10934147964 ps |
| T606 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_pin_override_test.1701656073 |
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Sep 04 02:17:11 AM UTC 24 |
Sep 04 02:17:19 AM UTC 24 |
2510774755 ps |
| T607 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_alert_test.3952882767 |
|
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Sep 04 02:17:15 AM UTC 24 |
Sep 04 02:17:19 AM UTC 24 |
2029896827 ps |
| T608 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_smoke.2303516607 |
|
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Sep 04 02:17:16 AM UTC 24 |
Sep 04 02:17:19 AM UTC 24 |
2160489837 ps |
| T609 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_alert_test.676696188 |
|
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Sep 04 02:17:09 AM UTC 24 |
Sep 04 02:17:20 AM UTC 24 |
2014636732 ps |
| T424 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect_with_pre_cond.4124645373 |
|
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Sep 04 02:16:50 AM UTC 24 |
Sep 04 02:17:20 AM UTC 24 |
65969654151 ps |
| T610 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ultra_low_pwr.1804410572 |
|
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Sep 04 02:17:13 AM UTC 24 |
Sep 04 02:17:20 AM UTC 24 |
4894372087 ps |
| T611 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_in_out_inverted.1530246406 |
|
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Sep 04 02:17:18 AM UTC 24 |
Sep 04 02:17:21 AM UTC 24 |
2503164298 ps |
| T248 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_edge_detect.1702032031 |
|
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Sep 04 02:17:14 AM UTC 24 |
Sep 04 02:17:22 AM UTC 24 |
4474115785 ps |
| T612 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_stress_all.1549530073 |
|
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Sep 04 02:16:43 AM UTC 24 |
Sep 04 02:17:22 AM UTC 24 |
11379907366 ps |
| T613 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_auto_blk_key_output.968945355 |
|
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Sep 04 02:17:13 AM UTC 24 |
Sep 04 02:17:23 AM UTC 24 |
3516885070 ps |
| T444 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/6.sysrst_ctrl_combo_detect_with_pre_cond.2948248488 |
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Sep 04 02:14:01 AM UTC 24 |
Sep 04 02:17:23 AM UTC 24 |
74331203130 ps |
| T614 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_in_out_inverted.4215266151 |
|
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Sep 04 02:17:09 AM UTC 24 |
Sep 04 02:17:24 AM UTC 24 |
2440252145 ps |
| T615 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_access_test.3722732601 |
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Sep 04 02:17:19 AM UTC 24 |
Sep 04 02:17:24 AM UTC 24 |
2160441264 ps |
| T616 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_pin_override_test.2129945646 |
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Sep 04 02:17:19 AM UTC 24 |
Sep 04 02:17:24 AM UTC 24 |
2521849071 ps |
| T383 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/23.sysrst_ctrl_combo_detect.3238389784 |
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Sep 04 02:15:47 AM UTC 24 |
Sep 04 02:17:24 AM UTC 24 |
102814772013 ps |
| T617 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_ec_pwr_on_rst.2516956418 |
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Sep 04 02:17:13 AM UTC 24 |
Sep 04 02:17:26 AM UTC 24 |
3634024975 ps |
| T291 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/21.sysrst_ctrl_combo_detect.653754021 |
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Sep 04 02:15:33 AM UTC 24 |
Sep 04 02:17:28 AM UTC 24 |
121554121922 ps |
| T618 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_smoke.1943402005 |
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Sep 04 02:17:25 AM UTC 24 |
Sep 04 02:17:28 AM UTC 24 |
2146347608 ps |
| T619 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_flash_wr_prot_out.2811222072 |
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Sep 04 02:17:20 AM UTC 24 |
Sep 04 02:17:28 AM UTC 24 |
2610066754 ps |
| T620 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_access_test.1941302009 |
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Sep 04 02:17:25 AM UTC 24 |
Sep 04 02:17:28 AM UTC 24 |
2178649376 ps |
| T621 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_alert_test.2552086243 |
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Sep 04 02:17:24 AM UTC 24 |
Sep 04 02:17:30 AM UTC 24 |
2016376118 ps |
| T128 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all_with_rand_reset.1396431360 |
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Sep 04 02:17:14 AM UTC 24 |
Sep 04 02:17:30 AM UTC 24 |
18569572546 ps |
| T213 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_edge_detect.3665638663 |
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Sep 04 02:17:21 AM UTC 24 |
Sep 04 02:17:30 AM UTC 24 |
3793482565 ps |
| T622 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ec_pwr_on_rst.2810055868 |
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Sep 04 02:17:20 AM UTC 24 |
Sep 04 02:17:31 AM UTC 24 |
3331283880 ps |
| T623 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_flash_wr_prot_out.2278094584 |
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Sep 04 02:17:26 AM UTC 24 |
Sep 04 02:17:31 AM UTC 24 |
2622825663 ps |
| T624 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_in_out_inverted.3744335047 |
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Sep 04 02:17:25 AM UTC 24 |
Sep 04 02:17:32 AM UTC 24 |
2486322300 ps |
| T158 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ultra_low_pwr.2769123409 |
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Sep 04 02:17:29 AM UTC 24 |
Sep 04 02:17:33 AM UTC 24 |
7359170315 ps |
| T625 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_auto_blk_key_output.770836737 |
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Sep 04 02:17:20 AM UTC 24 |
Sep 04 02:17:33 AM UTC 24 |
3538078900 ps |
| T626 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_alert_test.2235601412 |
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Sep 04 02:17:32 AM UTC 24 |
Sep 04 02:17:35 AM UTC 24 |
2032345360 ps |
| T627 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_auto_blk_key_output.3219687656 |
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Sep 04 02:17:29 AM UTC 24 |
Sep 04 02:17:35 AM UTC 24 |
3198290474 ps |
| T628 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_ec_pwr_on_rst.2283837805 |
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Sep 04 02:17:27 AM UTC 24 |
Sep 04 02:17:37 AM UTC 24 |
2787072178 ps |
| T629 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_pin_override_test.764052710 |
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Sep 04 02:17:25 AM UTC 24 |
Sep 04 02:17:38 AM UTC 24 |
2512727020 ps |
| T214 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/34.sysrst_ctrl_stress_all.750595122 |
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Sep 04 02:17:15 AM UTC 24 |
Sep 04 02:17:38 AM UTC 24 |
14564167519 ps |
| T343 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all_with_rand_reset.1213875384 |
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Sep 04 02:17:22 AM UTC 24 |
Sep 04 02:17:39 AM UTC 24 |
16971779102 ps |
| T630 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_in_out_inverted.4183206629 |
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Sep 04 02:17:33 AM UTC 24 |
Sep 04 02:17:40 AM UTC 24 |
2461723434 ps |
| T631 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_override_test.2964258760 |
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Sep 04 02:17:34 AM UTC 24 |
Sep 04 02:17:41 AM UTC 24 |
2517463997 ps |
| T344 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_stress_all_with_rand_reset.1762180162 |
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Sep 04 02:17:31 AM UTC 24 |
Sep 04 02:17:43 AM UTC 24 |
3699649408 ps |
| T632 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_smoke.1725543170 |
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Sep 04 02:17:32 AM UTC 24 |
Sep 04 02:17:43 AM UTC 24 |
2108776079 ps |
| T450 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_ultra_low_pwr.3853506714 |
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Sep 04 02:17:21 AM UTC 24 |
Sep 04 02:17:43 AM UTC 24 |
509098624835 ps |
| T633 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ec_pwr_on_rst.2963301509 |
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Sep 04 02:17:36 AM UTC 24 |
Sep 04 02:17:44 AM UTC 24 |
2986467648 ps |
| T634 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_flash_wr_prot_out.4212331662 |
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Sep 04 02:17:36 AM UTC 24 |
Sep 04 02:17:45 AM UTC 24 |
2607766208 ps |
| T635 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_pin_access_test.968003854 |
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Sep 04 02:17:34 AM UTC 24 |
Sep 04 02:17:45 AM UTC 24 |
2188244713 ps |
| T636 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_auto_blk_key_output.2070048923 |
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Sep 04 02:17:38 AM UTC 24 |
Sep 04 02:17:47 AM UTC 24 |
3513994668 ps |
| T179 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_edge_detect.4130898885 |
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Sep 04 02:17:39 AM UTC 24 |
Sep 04 02:17:48 AM UTC 24 |
3829113922 ps |
| T183 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/32.sysrst_ctrl_combo_detect_with_pre_cond.2865780819 |
|
|
Sep 04 02:16:58 AM UTC 24 |
Sep 04 02:17:49 AM UTC 24 |
59592404182 ps |
| T184 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_in_out_inverted.2552764632 |
|
|
Sep 04 02:17:45 AM UTC 24 |
Sep 04 02:17:49 AM UTC 24 |
2480363536 ps |
| T185 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_edge_detect.3737118246 |
|
|
Sep 04 02:17:29 AM UTC 24 |
Sep 04 02:17:50 AM UTC 24 |
499949219084 ps |
| T186 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_stress_all.4107136832 |
|
|
Sep 04 02:17:23 AM UTC 24 |
Sep 04 02:17:50 AM UTC 24 |
101775989758 ps |
| T187 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_alert_test.1351960911 |
|
|
Sep 04 02:17:44 AM UTC 24 |
Sep 04 02:17:50 AM UTC 24 |
2019068706 ps |
| T188 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_combo_detect.2296084470 |
|
|
Sep 04 02:15:39 AM UTC 24 |
Sep 04 02:17:50 AM UTC 24 |
158533440424 ps |
| T189 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_combo_detect_with_pre_cond.80690343 |
|
|
Sep 04 02:17:06 AM UTC 24 |
Sep 04 02:17:51 AM UTC 24 |
68029919828 ps |
| T190 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_smoke.1682575568 |
|
|
Sep 04 02:17:45 AM UTC 24 |
Sep 04 02:17:52 AM UTC 24 |
2114646567 ps |
| T191 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_flash_wr_prot_out.608529502 |
|
|
Sep 04 02:17:48 AM UTC 24 |
Sep 04 02:17:52 AM UTC 24 |
2631068399 ps |
| T637 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_ultra_low_pwr.2043332891 |
|
|
Sep 04 02:17:38 AM UTC 24 |
Sep 04 02:17:53 AM UTC 24 |
10233550078 ps |
| T432 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect.1964914873 |
|
|
Sep 04 02:16:42 AM UTC 24 |
Sep 04 02:17:54 AM UTC 24 |
107710808188 ps |
| T638 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_pin_override_test.2362898627 |
|
|
Sep 04 02:17:46 AM UTC 24 |
Sep 04 02:17:55 AM UTC 24 |
2509936698 ps |
| T153 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_ultra_low_pwr.2832827473 |
|
|
Sep 04 02:17:50 AM UTC 24 |
Sep 04 02:17:56 AM UTC 24 |
6920869903 ps |