| T639 |
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Sep 04 02:17:53 AM UTC 24 |
Sep 04 02:17:57 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_alert_test.637287960 |
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Sep 04 02:17:53 AM UTC 24 |
Sep 04 02:17:57 AM UTC 24 |
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Sep 04 02:17:49 AM UTC 24 |
Sep 04 02:17:57 AM UTC 24 |
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Sep 04 02:17:46 AM UTC 24 |
Sep 04 02:17:58 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_auto_blk_key_output.1652920212 |
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Sep 04 02:17:50 AM UTC 24 |
Sep 04 02:18:00 AM UTC 24 |
3653085112 ps |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_pin_override_test.26085618 |
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Sep 04 02:17:55 AM UTC 24 |
Sep 04 02:18:00 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_flash_wr_prot_out.639254690 |
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Sep 04 02:17:56 AM UTC 24 |
Sep 04 02:18:01 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_in_out_inverted.1001115944 |
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Sep 04 02:17:54 AM UTC 24 |
Sep 04 02:18:01 AM UTC 24 |
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Sep 04 02:17:50 AM UTC 24 |
Sep 04 02:18:02 AM UTC 24 |
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Sep 04 02:17:57 AM UTC 24 |
Sep 04 02:18:03 AM UTC 24 |
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Sep 04 02:17:41 AM UTC 24 |
Sep 04 02:18:03 AM UTC 24 |
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Sep 04 02:16:00 AM UTC 24 |
Sep 04 02:18:04 AM UTC 24 |
34000940939 ps |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_auto_blk_key_output.1979115727 |
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Sep 04 02:17:58 AM UTC 24 |
Sep 04 02:18:04 AM UTC 24 |
3325024214 ps |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_ultra_low_pwr.2285413833 |
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Sep 04 02:17:58 AM UTC 24 |
Sep 04 02:18:04 AM UTC 24 |
3119971980 ps |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/35.sysrst_ctrl_combo_detect.2081789108 |
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Sep 04 02:17:21 AM UTC 24 |
Sep 04 02:18:06 AM UTC 24 |
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Sep 04 02:17:52 AM UTC 24 |
Sep 04 02:18:06 AM UTC 24 |
15234754885 ps |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_alert_test.2043101959 |
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Sep 04 02:18:03 AM UTC 24 |
Sep 04 02:18:07 AM UTC 24 |
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Sep 04 02:17:55 AM UTC 24 |
Sep 04 02:18:07 AM UTC 24 |
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Sep 04 02:18:05 AM UTC 24 |
Sep 04 02:18:10 AM UTC 24 |
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Sep 04 02:17:31 AM UTC 24 |
Sep 04 02:18:10 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_stress_all.3558430994 |
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Sep 04 02:17:44 AM UTC 24 |
Sep 04 02:18:10 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_flash_wr_prot_out.43851743 |
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Sep 04 02:18:05 AM UTC 24 |
Sep 04 02:18:10 AM UTC 24 |
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Sep 04 02:18:08 AM UTC 24 |
Sep 04 02:18:12 AM UTC 24 |
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Sep 04 02:14:54 AM UTC 24 |
Sep 04 02:18:14 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/39.sysrst_ctrl_edge_detect.2667669758 |
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Sep 04 02:18:01 AM UTC 24 |
Sep 04 02:18:14 AM UTC 24 |
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Sep 04 02:18:11 AM UTC 24 |
Sep 04 02:18:15 AM UTC 24 |
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Sep 04 02:18:04 AM UTC 24 |
Sep 04 02:18:15 AM UTC 24 |
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Sep 04 02:18:05 AM UTC 24 |
Sep 04 02:18:16 AM UTC 24 |
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Sep 04 02:18:02 AM UTC 24 |
Sep 04 02:18:16 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_in_out_inverted.2452919146 |
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Sep 04 02:18:04 AM UTC 24 |
Sep 04 02:18:17 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/28.sysrst_ctrl_combo_detect.1719322873 |
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Sep 04 02:16:21 AM UTC 24 |
Sep 04 02:18:18 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_ec_pwr_on_rst.747115805 |
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Sep 04 02:18:06 AM UTC 24 |
Sep 04 02:18:19 AM UTC 24 |
2658207108 ps |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_alert_test.1268025578 |
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Sep 04 02:18:12 AM UTC 24 |
Sep 04 02:18:19 AM UTC 24 |
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/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_in_out_inverted.182308181 |
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Sep 04 02:18:15 AM UTC 24 |
Sep 04 02:18:19 AM UTC 24 |
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Sep 04 02:13:25 AM UTC 24 |
Sep 04 02:18:20 AM UTC 24 |
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Sep 04 02:16:23 AM UTC 24 |
Sep 04 02:18:20 AM UTC 24 |
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Sep 04 02:18:16 AM UTC 24 |
Sep 04 02:18:21 AM UTC 24 |
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Sep 04 02:18:16 AM UTC 24 |
Sep 04 02:18:21 AM UTC 24 |
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Sep 04 02:18:18 AM UTC 24 |
Sep 04 02:18:22 AM UTC 24 |
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Sep 04 02:18:11 AM UTC 24 |
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Sep 04 02:18:16 AM UTC 24 |
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Sep 04 02:18:15 AM UTC 24 |
Sep 04 02:18:25 AM UTC 24 |
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Sep 04 02:17:40 AM UTC 24 |
Sep 04 02:18:25 AM UTC 24 |
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Sep 04 02:18:17 AM UTC 24 |
Sep 04 02:18:27 AM UTC 24 |
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Sep 04 02:18:21 AM UTC 24 |
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Sep 04 02:18:11 AM UTC 24 |
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Sep 04 02:16:59 AM UTC 24 |
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Sep 04 02:18:21 AM UTC 24 |
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Sep 04 02:18:16 AM UTC 24 |
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Sep 04 02:18:28 AM UTC 24 |
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Sep 04 02:18:22 AM UTC 24 |
Sep 04 02:18:32 AM UTC 24 |
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Sep 04 02:18:22 AM UTC 24 |
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Sep 04 02:18:20 AM UTC 24 |
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Sep 04 02:18:08 AM UTC 24 |
Sep 04 02:18:33 AM UTC 24 |
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Sep 04 02:18:29 AM UTC 24 |
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Sep 04 02:18:26 AM UTC 24 |
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Sep 04 02:18:26 AM UTC 24 |
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Sep 04 02:18:23 AM UTC 24 |
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Sep 04 02:18:32 AM UTC 24 |
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Sep 04 02:17:59 AM UTC 24 |
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Sep 04 02:15:28 AM UTC 24 |
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Sep 04 02:18:32 AM UTC 24 |
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Sep 04 02:18:02 AM UTC 24 |
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Sep 04 02:18:34 AM UTC 24 |
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Sep 04 02:18:27 AM UTC 24 |
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Sep 04 02:18:31 AM UTC 24 |
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Sep 04 02:17:21 AM UTC 24 |
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Sep 04 02:18:35 AM UTC 24 |
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Sep 04 02:18:37 AM UTC 24 |
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Sep 04 02:18:37 AM UTC 24 |
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Sep 04 02:18:34 AM UTC 24 |
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Sep 04 02:18:41 AM UTC 24 |
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Sep 04 02:18:35 AM UTC 24 |
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Sep 04 02:17:13 AM UTC 24 |
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31615048646 ps |
| T697 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ultra_low_pwr.3159076333 |
|
|
Sep 04 02:18:42 AM UTC 24 |
Sep 04 02:18:46 AM UTC 24 |
11974535893 ps |
| T698 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_override_test.3723119902 |
|
|
Sep 04 02:18:41 AM UTC 24 |
Sep 04 02:18:47 AM UTC 24 |
2520003682 ps |
| T699 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_ec_pwr_on_rst.504886944 |
|
|
Sep 04 02:18:41 AM UTC 24 |
Sep 04 02:18:47 AM UTC 24 |
3549201652 ps |
| T250 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_edge_detect.462808317 |
|
|
Sep 04 02:18:44 AM UTC 24 |
Sep 04 02:18:49 AM UTC 24 |
3969383643 ps |
| T700 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_override_test.2972047372 |
|
|
Sep 04 02:18:48 AM UTC 24 |
Sep 04 02:18:50 AM UTC 24 |
2569686989 ps |
| T701 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_pin_access_test.3165034237 |
|
|
Sep 04 02:18:48 AM UTC 24 |
Sep 04 02:18:51 AM UTC 24 |
2112747750 ps |
| T702 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_pin_access_test.3384301928 |
|
|
Sep 04 02:18:41 AM UTC 24 |
Sep 04 02:18:51 AM UTC 24 |
2184600284 ps |
| T703 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/11.sysrst_ctrl_combo_detect.939753352 |
|
|
Sep 04 02:14:29 AM UTC 24 |
Sep 04 02:18:51 AM UTC 24 |
141805582563 ps |
| T704 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_edge_detect.1190108681 |
|
|
Sep 04 02:18:38 AM UTC 24 |
Sep 04 02:18:51 AM UTC 24 |
2769814758 ps |
| T705 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_in_out_inverted.2488591786 |
|
|
Sep 04 02:18:39 AM UTC 24 |
Sep 04 02:18:52 AM UTC 24 |
2463400764 ps |
| T387 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/30.sysrst_ctrl_combo_detect_with_pre_cond.1006462459 |
|
|
Sep 04 02:16:43 AM UTC 24 |
Sep 04 02:18:53 AM UTC 24 |
47916489162 ps |
| T706 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_stress_all_with_rand_reset.1210220137 |
|
|
Sep 04 02:18:45 AM UTC 24 |
Sep 04 02:18:54 AM UTC 24 |
2126209396 ps |
| T707 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_smoke.1493032138 |
|
|
Sep 04 02:18:46 AM UTC 24 |
Sep 04 02:18:55 AM UTC 24 |
2112554163 ps |
| T708 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_alert_test.639470445 |
|
|
Sep 04 02:18:46 AM UTC 24 |
Sep 04 02:18:55 AM UTC 24 |
2013182399 ps |
| T709 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/36.sysrst_ctrl_combo_detect_with_pre_cond.4236254121 |
|
|
Sep 04 02:17:30 AM UTC 24 |
Sep 04 02:18:55 AM UTC 24 |
116617875893 ps |
| T710 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ec_pwr_on_rst.3641856959 |
|
|
Sep 04 02:18:51 AM UTC 24 |
Sep 04 02:18:56 AM UTC 24 |
3211683737 ps |
| T711 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/44.sysrst_ctrl_auto_blk_key_output.276960100 |
|
|
Sep 04 02:18:41 AM UTC 24 |
Sep 04 02:18:57 AM UTC 24 |
3249190795 ps |
| T347 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_stress_all_with_rand_reset.3076757883 |
|
|
Sep 04 02:18:38 AM UTC 24 |
Sep 04 02:18:57 AM UTC 24 |
16666796125 ps |
| T712 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_in_out_inverted.1375507113 |
|
|
Sep 04 02:18:46 AM UTC 24 |
Sep 04 02:18:58 AM UTC 24 |
2470080249 ps |
| T713 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_auto_blk_key_output.3964378683 |
|
|
Sep 04 02:18:52 AM UTC 24 |
Sep 04 02:18:58 AM UTC 24 |
3713583570 ps |
| T714 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/24.sysrst_ctrl_auto_blk_key_output.2881262845 |
|
|
Sep 04 02:15:54 AM UTC 24 |
Sep 04 02:18:59 AM UTC 24 |
235488575635 ps |
| T715 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_alert_test.2286346765 |
|
|
Sep 04 02:18:55 AM UTC 24 |
Sep 04 02:19:00 AM UTC 24 |
2029234770 ps |
| T306 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_combo_detect.851898876 |
|
|
Sep 04 02:18:08 AM UTC 24 |
Sep 04 02:19:00 AM UTC 24 |
185061280794 ps |
| T154 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_ultra_low_pwr.453294066 |
|
|
Sep 04 02:18:52 AM UTC 24 |
Sep 04 02:19:00 AM UTC 24 |
8381561281 ps |
| T114 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_combo_detect_with_pre_cond.1982689176 |
|
|
Sep 04 02:17:51 AM UTC 24 |
Sep 04 02:19:00 AM UTC 24 |
111045545058 ps |
| T716 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all.4167992321 |
|
|
Sep 04 02:18:54 AM UTC 24 |
Sep 04 02:19:00 AM UTC 24 |
6721780354 ps |
| T717 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_access_test.3495215299 |
|
|
Sep 04 02:18:57 AM UTC 24 |
Sep 04 02:19:01 AM UTC 24 |
2045935784 ps |
| T435 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/19.sysrst_ctrl_stress_all.3905565604 |
|
|
Sep 04 02:15:21 AM UTC 24 |
Sep 04 02:19:01 AM UTC 24 |
78080050426 ps |
| T718 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_flash_wr_prot_out.2361390658 |
|
|
Sep 04 02:18:50 AM UTC 24 |
Sep 04 02:19:01 AM UTC 24 |
2611258162 ps |
| T719 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_flash_wr_prot_out.4102192090 |
|
|
Sep 04 02:18:58 AM UTC 24 |
Sep 04 02:19:01 AM UTC 24 |
2633751900 ps |
| T720 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all_with_rand_reset.3372664038 |
|
|
Sep 04 02:19:01 AM UTC 24 |
Sep 04 02:19:22 AM UTC 24 |
6274819690 ps |
| T721 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/22.sysrst_ctrl_ec_pwr_on_rst.92847508 |
|
|
Sep 04 02:15:37 AM UTC 24 |
Sep 04 02:19:02 AM UTC 24 |
90152431520 ps |
| T722 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_in_out_inverted.2176344195 |
|
|
Sep 04 02:18:57 AM UTC 24 |
Sep 04 02:19:02 AM UTC 24 |
2473400440 ps |
| T723 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_edge_detect.2297156866 |
|
|
Sep 04 02:18:52 AM UTC 24 |
Sep 04 02:19:03 AM UTC 24 |
2415244114 ps |
| T724 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_ec_pwr_on_rst.154791334 |
|
|
Sep 04 02:18:59 AM UTC 24 |
Sep 04 02:19:04 AM UTC 24 |
4728756881 ps |
| T725 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_smoke.2609014286 |
|
|
Sep 04 02:18:57 AM UTC 24 |
Sep 04 02:19:04 AM UTC 24 |
2113736810 ps |
| T252 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_edge_detect.2035479984 |
|
|
Sep 04 02:19:01 AM UTC 24 |
Sep 04 02:19:05 AM UTC 24 |
3061411394 ps |
| T726 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_smoke.1684889782 |
|
|
Sep 04 02:19:02 AM UTC 24 |
Sep 04 02:19:05 AM UTC 24 |
2133863007 ps |
| T178 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_stress_all_with_rand_reset.3070226194 |
|
|
Sep 04 02:18:53 AM UTC 24 |
Sep 04 02:19:05 AM UTC 24 |
35363800260 ps |
| T727 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_pin_override_test.3833211005 |
|
|
Sep 04 02:18:58 AM UTC 24 |
Sep 04 02:19:07 AM UTC 24 |
2510932431 ps |
| T728 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_access_test.3131368247 |
|
|
Sep 04 02:19:03 AM UTC 24 |
Sep 04 02:19:08 AM UTC 24 |
2234544973 ps |
| T729 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_auto_blk_key_output.368913002 |
|
|
Sep 04 02:18:59 AM UTC 24 |
Sep 04 02:19:08 AM UTC 24 |
3451589091 ps |
| T730 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_flash_wr_prot_out.3244409269 |
|
|
Sep 04 02:19:03 AM UTC 24 |
Sep 04 02:19:08 AM UTC 24 |
2617824241 ps |
| T731 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_in_out_inverted.625384799 |
|
|
Sep 04 02:19:03 AM UTC 24 |
Sep 04 02:19:09 AM UTC 24 |
2454601733 ps |
| T384 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/38.sysrst_ctrl_stress_all.366108566 |
|
|
Sep 04 02:17:52 AM UTC 24 |
Sep 04 02:19:09 AM UTC 24 |
93521921448 ps |
| T155 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ultra_low_pwr.1082256426 |
|
|
Sep 04 02:19:04 AM UTC 24 |
Sep 04 02:19:09 AM UTC 24 |
11761046027 ps |
| T177 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_edge_detect.2957356313 |
|
|
Sep 04 02:19:05 AM UTC 24 |
Sep 04 02:19:10 AM UTC 24 |
2849946830 ps |
| T732 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_stress_all.2945752422 |
|
|
Sep 04 02:16:51 AM UTC 24 |
Sep 04 02:19:10 AM UTC 24 |
153996556393 ps |
| T131 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_auto_blk_key_output.1967760127 |
|
|
Sep 04 02:19:04 AM UTC 24 |
Sep 04 02:19:11 AM UTC 24 |
3173071287 ps |
| T733 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_alert_test.1137958220 |
|
|
Sep 04 02:19:02 AM UTC 24 |
Sep 04 02:19:11 AM UTC 24 |
2014158781 ps |
| T433 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect.1363887140 |
|
|
Sep 04 02:18:19 AM UTC 24 |
Sep 04 02:19:11 AM UTC 24 |
80136082319 ps |
| T734 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_pin_override_test.2895469030 |
|
|
Sep 04 02:19:03 AM UTC 24 |
Sep 04 02:19:12 AM UTC 24 |
2510188752 ps |
| T735 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_access_test.734081495 |
|
|
Sep 04 02:19:09 AM UTC 24 |
Sep 04 02:19:12 AM UTC 24 |
2055049700 ps |
| T736 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_alert_test.777036214 |
|
|
Sep 04 02:19:08 AM UTC 24 |
Sep 04 02:19:13 AM UTC 24 |
2020341100 ps |
| T737 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_ec_pwr_on_rst.3773242003 |
|
|
Sep 04 02:19:04 AM UTC 24 |
Sep 04 02:19:13 AM UTC 24 |
2752371247 ps |
| T738 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ultra_low_pwr.3883523261 |
|
|
Sep 04 02:19:11 AM UTC 24 |
Sep 04 02:19:15 AM UTC 24 |
9003240511 ps |
| T739 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_auto_blk_key_output.1332423991 |
|
|
Sep 04 02:19:11 AM UTC 24 |
Sep 04 02:19:15 AM UTC 24 |
3695184048 ps |
| T740 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_flash_wr_prot_out.793724915 |
|
|
Sep 04 02:19:10 AM UTC 24 |
Sep 04 02:19:15 AM UTC 24 |
2622896391 ps |
| T741 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_smoke.3773017824 |
|
|
Sep 04 02:19:09 AM UTC 24 |
Sep 04 02:19:16 AM UTC 24 |
2110777279 ps |
| T742 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/47.sysrst_ctrl_stress_all_with_rand_reset.37952585 |
|
|
Sep 04 02:19:05 AM UTC 24 |
Sep 04 02:19:18 AM UTC 24 |
3759987745 ps |
| T743 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_smoke.3601904942 |
|
|
Sep 04 02:19:14 AM UTC 24 |
Sep 04 02:19:18 AM UTC 24 |
2132778252 ps |
| T744 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/46.sysrst_ctrl_stress_all.3966174000 |
|
|
Sep 04 02:19:01 AM UTC 24 |
Sep 04 02:19:18 AM UTC 24 |
6252425905 ps |
| T745 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_in_out_inverted.3772438175 |
|
|
Sep 04 02:19:09 AM UTC 24 |
Sep 04 02:19:18 AM UTC 24 |
2450756672 ps |
| T253 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_edge_detect.470893819 |
|
|
Sep 04 02:19:12 AM UTC 24 |
Sep 04 02:19:18 AM UTC 24 |
4048929863 ps |
| T746 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_in_out_inverted.401441926 |
|
|
Sep 04 02:19:16 AM UTC 24 |
Sep 04 02:19:19 AM UTC 24 |
2503282473 ps |
| T304 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/37.sysrst_ctrl_combo_detect.2131050496 |
|
|
Sep 04 02:17:39 AM UTC 24 |
Sep 04 02:19:19 AM UTC 24 |
56653002739 ps |
| T747 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_ec_pwr_on_rst.143961469 |
|
|
Sep 04 02:19:10 AM UTC 24 |
Sep 04 02:19:20 AM UTC 24 |
3582615745 ps |
| T748 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_override_test.1822361201 |
|
|
Sep 04 02:19:16 AM UTC 24 |
Sep 04 02:19:20 AM UTC 24 |
2530060879 ps |
| T749 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_pin_override_test.3472507775 |
|
|
Sep 04 02:19:10 AM UTC 24 |
Sep 04 02:19:20 AM UTC 24 |
2514899382 ps |
| T307 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/42.sysrst_ctrl_combo_detect.122550202 |
|
|
Sep 04 02:18:29 AM UTC 24 |
Sep 04 02:19:21 AM UTC 24 |
75813168668 ps |
| T750 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_auto_blk_key_output.2156252597 |
|
|
Sep 04 02:19:19 AM UTC 24 |
Sep 04 02:19:22 AM UTC 24 |
3263623039 ps |
| T751 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_alert_test.535144205 |
|
|
Sep 04 02:19:14 AM UTC 24 |
Sep 04 02:19:22 AM UTC 24 |
2010640861 ps |
| T266 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_edge_detect.4253192196 |
|
|
Sep 04 02:19:19 AM UTC 24 |
Sep 04 02:19:22 AM UTC 24 |
3928026876 ps |
| T752 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_alert_test.2141365033 |
|
|
Sep 04 02:19:21 AM UTC 24 |
Sep 04 02:19:24 AM UTC 24 |
2032321576 ps |
| T753 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_pin_access_test.506333321 |
|
|
Sep 04 02:19:16 AM UTC 24 |
Sep 04 02:19:25 AM UTC 24 |
2037017892 ps |
| T754 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_flash_wr_prot_out.314012405 |
|
|
Sep 04 02:19:17 AM UTC 24 |
Sep 04 02:19:31 AM UTC 24 |
2612490023 ps |
| T386 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/12.sysrst_ctrl_combo_detect.2515106577 |
|
|
Sep 04 02:14:37 AM UTC 24 |
Sep 04 02:19:31 AM UTC 24 |
97353084399 ps |
| T755 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all_with_rand_reset.2826165218 |
|
|
Sep 04 02:19:12 AM UTC 24 |
Sep 04 02:19:31 AM UTC 24 |
9128214458 ps |
| T416 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/41.sysrst_ctrl_combo_detect_with_pre_cond.2041681060 |
|
|
Sep 04 02:18:20 AM UTC 24 |
Sep 04 02:19:36 AM UTC 24 |
93847360654 ps |
| T756 |
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Sep 04 02:19:20 AM UTC 24 |
Sep 04 02:19:37 AM UTC 24 |
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Sep 04 02:19:20 AM UTC 24 |
Sep 04 02:19:39 AM UTC 24 |
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Sep 04 02:18:46 AM UTC 24 |
Sep 04 02:19:43 AM UTC 24 |
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Sep 04 02:19:23 AM UTC 24 |
Sep 04 02:19:46 AM UTC 24 |
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Sep 04 02:18:53 AM UTC 24 |
Sep 04 02:19:58 AM UTC 24 |
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Sep 04 02:19:23 AM UTC 24 |
Sep 04 02:19:59 AM UTC 24 |
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Sep 04 02:18:01 AM UTC 24 |
Sep 04 02:20:04 AM UTC 24 |
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Sep 04 02:19:32 AM UTC 24 |
Sep 04 02:20:05 AM UTC 24 |
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Sep 04 02:19:22 AM UTC 24 |
Sep 04 02:20:06 AM UTC 24 |
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Sep 04 02:14:15 AM UTC 24 |
Sep 04 02:20:14 AM UTC 24 |
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Sep 04 02:19:06 AM UTC 24 |
Sep 04 02:20:17 AM UTC 24 |
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Sep 04 02:16:56 AM UTC 24 |
Sep 04 02:20:19 AM UTC 24 |
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Sep 04 02:20:30 AM UTC 24 |
Sep 04 02:22:20 AM UTC 24 |
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Sep 04 02:19:40 AM UTC 24 |
Sep 04 02:20:21 AM UTC 24 |
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Sep 04 02:19:23 AM UTC 24 |
Sep 04 02:20:21 AM UTC 24 |
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Sep 04 02:16:24 AM UTC 24 |
Sep 04 02:20:23 AM UTC 24 |
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Sep 04 02:19:42 AM UTC 24 |
Sep 04 02:20:24 AM UTC 24 |
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Sep 04 02:16:14 AM UTC 24 |
Sep 04 02:20:28 AM UTC 24 |
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Sep 04 02:15:39 AM UTC 24 |
Sep 04 02:20:34 AM UTC 24 |
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Sep 04 02:19:24 AM UTC 24 |
Sep 04 02:20:39 AM UTC 24 |
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Sep 04 02:14:46 AM UTC 24 |
Sep 04 02:20:40 AM UTC 24 |
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Sep 04 02:20:24 AM UTC 24 |
Sep 04 02:20:40 AM UTC 24 |
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Sep 04 02:19:23 AM UTC 24 |
Sep 04 02:20:43 AM UTC 24 |
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Sep 04 02:19:05 AM UTC 24 |
Sep 04 02:20:43 AM UTC 24 |
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Sep 04 02:19:52 AM UTC 24 |
Sep 04 02:20:45 AM UTC 24 |
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Sep 04 02:17:50 AM UTC 24 |
Sep 04 02:20:48 AM UTC 24 |
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Sep 04 02:19:21 AM UTC 24 |
Sep 04 02:20:51 AM UTC 24 |
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Sep 04 02:19:47 AM UTC 24 |
Sep 04 02:20:54 AM UTC 24 |
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Sep 04 02:14:59 AM UTC 24 |
Sep 04 02:20:54 AM UTC 24 |
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Sep 04 02:20:29 AM UTC 24 |
Sep 04 02:20:58 AM UTC 24 |
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Sep 04 02:18:31 AM UTC 24 |
Sep 04 02:20:59 AM UTC 24 |
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Sep 04 02:20:25 AM UTC 24 |
Sep 04 02:21:05 AM UTC 24 |
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Sep 04 02:19:25 AM UTC 24 |
Sep 04 02:21:08 AM UTC 24 |
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Sep 04 02:20:39 AM UTC 24 |
Sep 04 02:21:08 AM UTC 24 |
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Sep 04 02:20:07 AM UTC 24 |
Sep 04 02:21:14 AM UTC 24 |
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Sep 04 02:20:41 AM UTC 24 |
Sep 04 02:21:14 AM UTC 24 |
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Sep 04 02:19:37 AM UTC 24 |
Sep 04 02:21:17 AM UTC 24 |
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Sep 04 02:20:52 AM UTC 24 |
Sep 04 02:21:23 AM UTC 24 |
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Sep 04 02:18:21 AM UTC 24 |
Sep 04 02:21:24 AM UTC 24 |
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Sep 04 02:20:00 AM UTC 24 |
Sep 04 02:21:25 AM UTC 24 |
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Sep 04 02:17:14 AM UTC 24 |
Sep 04 02:21:28 AM UTC 24 |
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Sep 04 02:20:59 AM UTC 24 |
Sep 04 02:21:29 AM UTC 24 |
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Sep 04 02:19:59 AM UTC 24 |
Sep 04 02:21:36 AM UTC 24 |
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Sep 04 02:20:54 AM UTC 24 |
Sep 04 02:21:38 AM UTC 24 |
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Sep 04 02:21:09 AM UTC 24 |
Sep 04 02:21:42 AM UTC 24 |
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Sep 04 02:20:19 AM UTC 24 |
Sep 04 02:21:47 AM UTC 24 |
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Sep 04 02:20:55 AM UTC 24 |
Sep 04 02:21:48 AM UTC 24 |
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Sep 04 02:16:32 AM UTC 24 |
Sep 04 02:21:50 AM UTC 24 |
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Sep 04 02:20:49 AM UTC 24 |
Sep 04 02:21:54 AM UTC 24 |
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Sep 04 02:20:40 AM UTC 24 |
Sep 04 02:22:00 AM UTC 24 |
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Sep 04 02:19:40 AM UTC 24 |
Sep 04 02:22:01 AM UTC 24 |
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Sep 04 02:19:01 AM UTC 24 |
Sep 04 02:22:04 AM UTC 24 |
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Sep 04 02:15:07 AM UTC 24 |
Sep 04 02:22:06 AM UTC 24 |
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Sep 04 02:20:23 AM UTC 24 |
Sep 04 02:22:06 AM UTC 24 |
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Sep 04 02:20:43 AM UTC 24 |
Sep 04 02:22:07 AM UTC 24 |
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Sep 04 02:18:38 AM UTC 24 |
Sep 04 02:22:10 AM UTC 24 |
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Sep 04 02:20:46 AM UTC 24 |
Sep 04 02:22:15 AM UTC 24 |
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Sep 04 02:21:08 AM UTC 24 |
Sep 04 02:22:30 AM UTC 24 |
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Sep 04 02:21:00 AM UTC 24 |
Sep 04 02:22:32 AM UTC 24 |
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Sep 04 02:19:05 AM UTC 24 |
Sep 04 02:22:35 AM UTC 24 |
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Sep 04 02:21:06 AM UTC 24 |
Sep 04 02:22:38 AM UTC 24 |
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Sep 04 02:20:04 AM UTC 24 |
Sep 04 02:22:51 AM UTC 24 |
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Sep 04 02:19:00 AM UTC 24 |
Sep 04 02:22:53 AM UTC 24 |
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Sep 04 02:20:22 AM UTC 24 |
Sep 04 02:22:55 AM UTC 24 |
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Sep 04 02:20:35 AM UTC 24 |
Sep 04 02:22:58 AM UTC 24 |
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Sep 04 02:19:43 AM UTC 24 |
Sep 04 02:23:03 AM UTC 24 |
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Sep 04 02:20:14 AM UTC 24 |
Sep 04 02:23:04 AM UTC 24 |
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Sep 04 02:19:11 AM UTC 24 |
Sep 04 02:23:09 AM UTC 24 |
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Sep 04 02:17:05 AM UTC 24 |
Sep 04 02:23:21 AM UTC 24 |
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Sep 04 02:19:37 AM UTC 24 |
Sep 04 02:23:33 AM UTC 24 |
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Sep 04 02:19:12 AM UTC 24 |
Sep 04 02:23:36 AM UTC 24 |
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Sep 04 02:20:44 AM UTC 24 |
Sep 04 02:23:38 AM UTC 24 |
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Sep 04 02:16:58 AM UTC 24 |
Sep 04 02:23:45 AM UTC 24 |
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Sep 04 02:17:29 AM UTC 24 |
Sep 04 02:23:53 AM UTC 24 |
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Sep 04 02:18:42 AM UTC 24 |
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Sep 04 02:14:40 AM UTC 24 |
Sep 04 02:24:06 AM UTC 24 |
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Sep 04 02:19:22 AM UTC 24 |
Sep 04 02:24:16 AM UTC 24 |
79920332615 ps |
| T793 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/16.sysrst_ctrl_ec_pwr_on_rst.1283377951 |
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Sep 04 02:15:01 AM UTC 24 |
Sep 04 02:24:17 AM UTC 24 |
903355923668 ps |
| T794 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/43.sysrst_ctrl_combo_detect.37482598 |
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Sep 04 02:18:38 AM UTC 24 |
Sep 04 02:24:24 AM UTC 24 |
121063710518 ps |
| T795 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_combo_detect.513406378 |
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Sep 04 02:19:19 AM UTC 24 |
Sep 04 02:24:33 AM UTC 24 |
104599583729 ps |
| T434 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/31.sysrst_ctrl_combo_detect.3231613143 |
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Sep 04 02:16:50 AM UTC 24 |
Sep 04 02:24:41 AM UTC 24 |
182513023562 ps |
| T399 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/76.sysrst_ctrl_combo_detect_with_pre_cond.1534155698 |
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Sep 04 02:20:18 AM UTC 24 |
Sep 04 02:25:03 AM UTC 24 |
96204520058 ps |
| T420 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/61.sysrst_ctrl_combo_detect_with_pre_cond.1818956905 |
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Sep 04 02:19:32 AM UTC 24 |
Sep 04 02:25:15 AM UTC 24 |
119854786700 ps |
| T796 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/45.sysrst_ctrl_combo_detect.986974350 |
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Sep 04 02:18:52 AM UTC 24 |
Sep 04 02:25:44 AM UTC 24 |
194241952393 ps |
| T797 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/33.sysrst_ctrl_stress_all.1941162295 |
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Sep 04 02:17:08 AM UTC 24 |
Sep 04 02:25:44 AM UTC 24 |
156833661235 ps |
| T446 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/27.sysrst_ctrl_stress_all.804466718 |
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Sep 04 02:16:17 AM UTC 24 |
Sep 04 02:26:21 AM UTC 24 |
221793153736 ps |
| T398 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/58.sysrst_ctrl_combo_detect_with_pre_cond.1570642321 |
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Sep 04 02:19:32 AM UTC 24 |
Sep 04 02:27:22 AM UTC 24 |
189305127717 ps |
| T443 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/73.sysrst_ctrl_combo_detect_with_pre_cond.734995200 |
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Sep 04 02:20:06 AM UTC 24 |
Sep 04 02:27:59 AM UTC 24 |
173608428656 ps |
| T798 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/3.sysrst_ctrl_edge_detect.656999671 |
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Sep 04 02:13:36 AM UTC 24 |
Sep 04 02:35:56 AM UTC 24 |
483387703401 ps |
| T799 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/49.sysrst_ctrl_ec_pwr_on_rst.210123522 |
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Sep 04 02:19:18 AM UTC 24 |
Sep 04 02:49:18 AM UTC 24 |
563173094321 ps |
| T168 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/40.sysrst_ctrl_stress_all.899706296 |
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Sep 04 02:18:11 AM UTC 24 |
Sep 04 02:51:54 AM UTC 24 |
681225288165 ps |
| T438 |
/workspaces/repo/scratch/os_regression_2024_09_03/sysrst_ctrl-sim-vcs/coverage/default/48.sysrst_ctrl_stress_all.397210225 |
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Sep 04 02:19:12 AM UTC 24 |
Sep 04 02:52:38 AM UTC 24 |
1763243818948 ps |